Image sensing device

Abstract

To acquire further range depth information and to improve accuracy.SOLUTION: An active imaging system includes a laser to illuminate a scene, and an imaging device to receive returns reflected from the scene. The imaging device includes an array of pixel circuits. Each pixel circuit includes a photodiode connected to multiple track and hold circuits, and a timing circuit adapted to operate the track and hold circuits in quick succession such that each track and hold circuit captures an information signal indicative of returns arriving during different successive time periods during a gate period and thus provides 3D image data based on the arrival times of returns from the scene during the gate period.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to image sensing devices for use in active imaging systems. [Background technology]

[0002] Several different technologies and approaches for sensing or sampling reflected laser light are currently used in active imaging systems. Four exemplary technologies are detailed below.

[0003] i) 2D burst illumination (BIL) detectors use a single gate period, typically 10 ns to 100 ns, to capture a snapshot of a laser light pulse or a portion of a laser light pulse reflected from a scene of interest. The image is flat and contains little or no 3D context information. To improve depth perception, a narrower gate time can be selected. The gate time can be delayed until after the arrival of the reflected light from the target object, allowing the background to be imaged and the object's silhouette to be revealed. Additional images can be acquired across the target range to provide context for the scene of interest. Multiple frames can be acquired to improve image quality. The gate duration affects and ultimately limits the range-depth resolution and accuracy that can be achieved. Creating shorter gate times presents technical challenges and is ultimately limited by jitter effects, which limit the achievable range-depth accuracy. Early devices had limited sensitivity due to avalanche photodiode (APD) gain limitations.

[0004] ii) Swept 2D detectors are similar to (i), but vary the phase of the acquisition to take several snapshots that "sweep" through the depth of the target to build a 3D model of the target. Again, similar limitations on gate timing and APD gain exist.

[0005] iii) 3D (BIL) detectors operate similarly to 2D BIL detectors, except that each acquired frame may be further processed on-chip by using timer circuits in each pixel to determine signal depth (closer and more distant signals produce different signal levels within the gate period), but the processing is sensitive to intensity fluctuations, which can distort the 3D image, although post-processing corrections can be applied. Again, similar limitations on gate timing and APD gain exist.

[0006] iv) Geiger-mode detectors measure the arrival time of the first detected photon and are insensitive to the arrival of all other subsequent photons until the detector array is reset. A Geiger-mode detection event creates an avalanche effect that requires the detector to be reset or quenched to restore its detection threshold before it can sense again. In the photon-starved regime, due to Poisson statistics, the arrival of the first or even second photon may not be detected, allowing the arrival of subsequent photons from more distant surfaces to be occasionally detected.

[0007] Multiple frames can be acquired to derive information in the form of a point cloud data cube that characterizes the target's 3D profile. The pixel pitch of Geiger-mode detector arrays is limited to relatively large sizes, ranging from 25 μm to 100 μm. Current array sizes are relatively small: 32 × 32 and 128 × 32, primarily limited by the silicon process node that sets track density. The required ROIC pixel array tracking connects the pixels to the timing circuitry, which is generally located outside the pixel array due to its size.

[0008] Multiple acquisition cycles are required to obtain additional range depth information and improve accuracy. Increasing imaging time can affect or limit how images are acquired and their quality, taking into account any associated motion between the imager and the target.

[0009] A further example of the prior art is US2006158542 which illustrates an image sensing device that is capable of capturing samples of an optical signal at different times during a shutter period.

[0010] US10422890B2 describes an imaging device for radiation detection that includes three sample-and-hold circuits operated in sequence. Two of the sample-and-hold circuits provide different sensitivities to the optical signal, while the third sample-and-hold circuit provides a pixel offset. This configuration relies on a signal that does not appreciably change during the sequential time that the three circuits are operated, even across the entire scan. The use of a sample-and-hold circuit is necessary to provide the pixel offset.

[0011] US2008 / 0049128 describes an imaging device that uses multiple sample and hold circuits to capture successive images. Neither US10422890B2 nor US2008 / 0049128 is adapted to take successive images at a rate suitable for use in an active imaging system that can provide 3D image data based on the arrival times of photons from a scene. Summary of the Invention

[0012] According to a first aspect of the present invention there is provided an image sensing device for use in an active imaging system, the image sensing device comprising a pixel circuit; Each pixel circuit is a) a photodetection circuit comprising a photodetector element configured to output a time-varying optical signal during a gating period; b) a plurality of storage circuits each configured to receive and store the optical signals from the photodetector circuit; c) a separate switch through which each storage circuit is connectable to the photodetector circuit; the image sensing device comprising a timing controller circuit that sequentially operates the switches to capture samples of the time-varying light signal at different times over a gate period; Each pixel circuit is characterized by a buffer amplifier connected between the photodetector circuit and the storage circuit to substantially isolate the photodetector circuit from variations in the capacitive load of the plurality of storage circuits.

[0013] In an active imaging system application, targets in a scene at different distances from the device will cause returns at different times during the gate period. This also applies to different surfaces of the same target at different distances from the device. The different signals stored in each storage circuit thereby provide 3D image information of the target and / or targets. In other words, the image sensing device can provide 3D image data based on the arrival times of returns from the scene during the gate period.

[0014] For each storage circuit to capture image information for targets at different distances from the sensing device, i.e., to distinguish between pictures arriving at different times during the gate period, the timing controller circuit and pixel circuit must be capable of operating the switches in very rapid succession. For the distances expected in terrestrial active image sensing applications, a time interval between operating two successive switches of 30 ns or less is typically required, and <200 ps when different surfaces of the target are to be distinguished.

[0015] Connecting the photodetector directly to the storage circuit exposes the photodetector to the changing capacitive load of the storage circuit, reducing the size of the time-varying optical signal and therefore reducing photosensitivity, which means it may not be possible to resolve potentially important small signals. By using a buffer amplifier to isolate the photodetector circuit from the capacitive load of the storage circuit, the photosensitivity of the photodetector circuit can be maintained.

[0016] In a preferred implementation, the buffer amplifier comprises a source follower transistor and a current source load. This implementation provides a simple, low-component solution. Additionally or alternatively, the buffer amplifier may include an operational amplifier, but this is less preferred because it requires significantly more transistors and has less favorable characteristics with respect to signal dynamics, slew rate, noise, and power usage.

[0017] The source follower transistor may be a MOSFET, but any dielectrically isolated transistor may provide the inherent capacitive load isolation function.

[0018] Preferably, each storage circuit includes a track and hold circuit. It is possible to use a sample and hold circuit instead, although this is less preferred as to achieve signal settling with shorter gate times, a proportionately higher current is required to charge the storage capacitor, increasing power consumption and negating the speed and power advantages gained by the present invention.

[0019] In a preferred configuration, the timing controller circuit is configured to operate the switches so that all of the storage circuits capture the time-varying signal simultaneously and then disconnect one by one from the photodetector circuits at different times during the gate period.

[0020] To resolve the small optical signal voltage within the gate period, the source follower transistor gain must be set high enough by operating at a high transistor drain current. If the gain is insufficient, the transistor output settling time will exceed the shorter gate period, or for smaller voltages, the correct value will not be resolvable.

[0021] Higher transistor drain current corresponds to higher power consumption per pixel, which places constraints on the actual size that can be manipulated.

[0022] The solution is to include a bias controller configured to switch the bias state of the source follower transistor current so that it is operable in a quiescent (low current) state outside the gate period and in a high bias state during the gate period. Because the gate period is typically a relatively small portion of the total period for taking a frame, this solution allows the desired source follower transistor current, speed, and settling performance of the transistor to be achieved with only a small increase in root mean square (rms) power dissipation and, as a result, without significant perturbations in the operating temperature of the sensing device.

[0023] The timing controller circuit and the plurality of storage circuits may be mounted on a single integrated semiconductor die. This configuration reduces jitter in the switching times of the storage circuits. The bias controller may be mounted on the same single integrated semiconductor die as the timing controller circuit and / or the plurality of storage circuits.

[0024] The timing circuit may include a chain of delay stages implemented using inverters. Each delay stage may include at least two inverters. This configuration can provide very short delays, e.g., <200 ps, ​​thereby enabling very short intervals between operating switches of different storage circuits, e.g., track-and-hold circuits, of the pixel circuit. Similarly, this configuration also allows for longer interval lengths, e.g., up to 30 ns, providing significant flexibility in the interval time that can be selected.

[0025] The timing circuit may comprise means for controlling the timing of operation of the switches of the storage circuits in the pixel circuits. In this way, the timing can be selected to suit the relative distances of different objects of interest from the device, thus avoiding looking for returns at distances where there are no expected objects of interest.

[0026] for example, to select the length of the delay before the first track and hold circuit is activated after the gate is opened; and / or A timing circuit may be used to allow independent control of the timing of each switch in each track of the hold circuit.

[0027] When the separation distance between two objects in a scene is large, with a first object being relatively close to the image sensing device and a second object being relatively far from the image sensing device, the timing circuit may be configured to operate one or more of the track and hold circuits during a time when a return from the first object is expected to provide information about the first object (e.g., 3D information), and the remaining track and hold circuits are configured to operate when a return from the second object is expected to provide information about the second object (e.g., 3D information).

[0028] The photodetector may comprise an avalanche photodetector. Avalanche photodiodes are advantageous because they output a signal photocurrent that is larger than the detected photocurrent.

[0029] To provide the desired performance for many applications, the circuit is preferably implemented on a high-speed mixed-signal silicon process that offers low parasitic circuit elements and supports signal slew rates on the order of volts per nanosecond (V / ns). The slew rate is compatible with small optical signal voltages within the gate time range of interest. This can be achieved by fabricating the pixel circuit on a compatible silicon process. Typical processes include 0.18 μm, i.e., the transistors have a gate length of 0.18 μm.

[0030] The image sensing device may be part of an active imaging system that also includes a laser for illuminating the scene with light pulses, the image sensing device being adapted to image light from the laser reflected from the scene.

[0031] The invention will now be described, by way of example only, with reference to the following drawings: [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 1 is a schematic diagram of an active imaging system. [Figure 2] FIG. 2 is a schematic diagram of a pixel circuit of a detector of an active imaging system. [Figure 3] FIG. 3 is a schematic diagram of a timing controller of the detector for controlling the timing of the operation of the switches of the track and hold circuit. [Figure 4] FIG. 4 is a schematic diagram of a detector bias controller for controlling the bias point of the source follower transistor of the pixel circuit of FIG. [Figure 5] FIG. 5 is a timing diagram illustrating an exemplary timing regime for operation of the system. DETAILED DESCRIPTION OF THE INVENTION

[0033] Figure 1 is a schematic diagram of an active imaging system. The active imaging system comprises a laser 1 for illuminating a scene with narrow pulses of light, e.g., short wavelength infrared light, a time base controller 2, and a detector 3 including a photodetector array 4, a timing controller 5, and a bias controller 6. The photodetector array 4 comprises pixel circuits 7 (Figure 2), each of which includes a separate photodetector element 8, e.g., an avalanche photodiode, and circuitry for recording the output of each photodetector element 8.

[0034] 2 is a schematic diagram of one of the pixel circuits 7. Each pixel circuit 7 comprises a photodetector circuit and "n" track and hold circuits 9, where n>1. In one example, n=5.

[0035] In addition to the photodetector element 8, the photodetector circuit comprises an input reset transistor M2 and a reset current limiting transistor M1 operable to bias the photodetector element 8.

[0036] The outputs of the photodetector elements 8 are connected to each of the track and hold circuits 9 through a buffer amplifier implemented by a source follower transistor M4 and a current source VDD. The source follower transistor M4 acts to isolate the photodetector circuits from the variations in the capacitive load of the multiplexed track and hold circuits 9. The parasitic capacitances normally associated with transistor circuits are not considered significant compared to the input and output load capacitances and can therefore be ignored.

[0037] Each track and hold circuit 9 comprises a storage capacitor C1 to Cn, a switch S1 to Sn (typically implemented by a transistor) connecting each storage capacitor C1 to Cn to the drain terminal of a source follower transistor M4, and a readout circuit M5, M6, of which only the readout circuit for track and hold circuit n is shown.

[0038] The pixel circuit 7 further comprises a transistor M3 connected between a current source VDD and the drain terminal of a source follower transistor M4, which operates via a control signal VG3 from a bias controller 6 to control the bias point of the source follower transistor M4.

[0039] Photodetector elements 8 responsive to the wavelength emitted by laser 1 are arranged in an array on a first semiconductor die. Source follower transistor M4 and track and hold circuit 9 are formed on a second semiconductor die. The first and second dies are bump bonded to electrically connect each photodetector element 8 to its respective pixel circuit 7.

[0040] Referring back to Figure 1, in use, laser 1 illuminates a scene. Laser light reflected from the scene is imaged onto array 4 of photodetecting elements 8 of detector 3. Trigger signals from base controller 2 to laser 1 and detector 3 are used to coordinate their operation.

[0041] A trigger signal from the base controller 2 is used by the timing controller 5 to in turn time the switching of the track and hold circuit 9 to capture the time varying signal from the photodiode 8 over a gate period. The different values ​​held on the track and hold circuit 9 provide information of targets in the scene at different distances from the detector 3 and / or three dimensional information of the target.

[0042] The circuitry of the timing controller 5 is provided on the same die as the track and hold circuit 9 in order to reduce jitter in the switching times of the switches S1 to Sn of the track and hold circuit 9.

[0043] 3 is a schematic diagram of an exemplary implementation of a circuit of a timing controller 5 adapted to output control signals for controlling switches S1 to Sn. The timing controller 5 comprises a chain of delay stages 5A[1] to 5A[N], each having an adjustable propagation delay. Each delay stage 5A[1] to 5A[N] is implemented by a pair of inverters (although there may be more). The output of each delay stage 5A is connected to a different one of the switches (S1 to Sn). That is, the output of the first buffer 5A(1) is connected to switch S1 of the first track-and-hold circuit 9 of each pixel circuit 7 and to the input of delay stage 5A(2), the output of delay stage 5A(2) is connected to switch S2 of the second track-and-hold circuit 9 of each pixel circuit 7 and to the input of third buffer 5A(3), and so on.

[0044] In this configuration, in response to a trigger signal received at the input of the first delay stage 5A of the chain, the timing controller 5 outputs a sequence of control signals that sequentially operate each of the track and hold circuits 9. In this embodiment, as shown in Figure 5, the output signal from the chain operates switches S1 to Sn to sequentially disconnect capacitors C1 to Cn of the track and hold circuit 9 from the photodetector element 8.

[0045] The output of the timing controller 5 is connected to all pixel circuits 7 of the array 4 using a conventional balanced clock tree network to maintain timing uniformity between pixel circuits 7 across the photodetector array 4.

[0046] Depending on the application requirements, the timing controller 5 can be configured to independently control the time interval TBIN (see FIG. 5) between operating each of the track-and-hold circuits, i.e., the propagation delay of each delay stage. Depending on the application, interval lengths in the range of <200 ps to 30 ns are likely to be appropriate.

[0047] This is achieved by providing multiple bias generators 5B, a separate one of which is connected to one of the inverters in each delay stage 5A[1] to 5A[N], so that the propagation delay of each delay stage 5A[1] to 5A[N] in the chain can be set independently of the others by data in a control register (BIAS DATA), thereby allowing the interval between operating each of the track and hold circuits 9 to be set individually.

[0048] The timing interval TBIN between operations of each track-and-hold circuit is common to all pixel circuits 7 of the array 4, ie the interval between operations S1 and S2 is the same for each pixel circuit 7 of the array 4.

[0049] The number of track and hold circuits 9 operating during the gate period can be configured from the control register to be less than the total number n by retarding the bias generator signal to the associated inverter (using a delay enable function) to allow flexibility in the image acquisition mode.

[0050] The timing controller 5 also includes a bias control signal generator, which in this example is implemented by a latch (see the top of Figure 3) configured to output a bias control signal BIAS CONTROL in response to receiving a trigger (TRIGGER).

[0051] FIG. 4 is a circuit schematic of the bias controller 6 used to control the bias point of the source follower transistor M4 of each pixel circuit 7 via transistor M3.

[0052] The bias controller 6 is adapted to switch the bias point of the source follower transistor M4 of the pixel circuit 7 between a low current value and a high current value in response to a bias control (BIAS CONTROL) signal (and thus indirectly from a trigger (TRIGGER) from the time base controller 2). The switching is timed to operate such that the source follower transistor M4 is biased in a low bias state (quiescent state) most of the time, but is biased in a high current state during the entire gate period, i.e., the period of a frame during which the light signal is being collected by the photodetector element 8 and captured on the track and hold circuit 9. Because the gate period is significantly shorter than the frame period, this leads to a significant reduction in power usage.

[0053] The bias controller 6 includes a programmable current mirror circuit configured by a control register.

[0054] The programmable current mirror circuit includes two mirror stages each controlled by a different control register data bit.

[0055] The quiescent and pulsed high current values ​​are set by switching mirror stages in and out of the current mirror circuit. Switching additional stages into the current mirror circuit increases VG3 and therefore increases the bias current values ​​of all connected pixel source follower transistors M4 across the array.

[0056] Alternatively, bias controller 6 may be adapted to receive an externally generated control signal (this configuration is also shown in FIG. 3) to directly configure the current mirror drain voltage to control the VG3 signal. However, this approach is less preferable than using a trigger signal because it requires an additional waveform, is generated outside the die, and is more susceptible to external timing accuracy and jitter.

[0057] In one example, the mirror circuit may be configured so that the quiescent bias current has a value of a few microamps, ie, less than 10 microamps, and the high bias current has a value in the range of 10 microamps to 100 microamps.

[0058] The following describes an exemplary configuration sequence for an active imaging system at start-up.

[0059] i. The system is initialized.

[0060] ii. The system is configured and held in a reset state prior to operation.

[0061] iii. The photodetector bias voltages are configured to operate the array of photodetectors 8 at the required gain.

[0062] iv. The timing controller 5 is configured with the required track and hold interval value TBIN (or multiple TBIN values ​​where different timing intervals are used while operating different track and hold circuits).

[0063] v. The bias controller 6 is configured with a quiescent (low) current value and a pulsed (high) operating current value.

[0064] vi. The photodiode array 4 is held in a reset state by the pixel circuit array. In reset, the photodiode array output does not respond to light signals, and the track and hold capacitor voltage increases to a reset voltage level. Alternatively, the track and hold capacitor may be reset to an alternate value using a reset transistor. If this voltage differs significantly from the transistor source voltage value, excessive current may be expected to flow.

[0065] vii. The pixel array is ready to be triggered.

[0066] viii. Activate the system.

[0067] FIG. 5 shows an exemplary timing diagram and operation sequence for an active imaging system in which each pixel circuit 7 comprises five storage circuits.

[0068] The photodiode array 4 is held in a reset state. All track and hold (T&H) circuits 9 are in a reset state from the previous frame (A).

[0069] In response to a trigger signal from the time base controller 2 to the laser 1, the laser 1 fires (B).

[0070] The trigger (TRIGGER) input from the time base controller 2 to the detector 3 goes backward (falling edge) (C). In response, the bias controller 6 changes the bias state of the source follower transistor M4 from its quiescent current value to a higher current value. This is done before the T&H circuit 9 is initiated to allow time for the bias current to stabilize.

[0071] The trigger (TRIGGER) input from the time base controller 2 is asserted (rising edge) (D). In response, the timing controller 5 initiates a T&H circuit control timing sequence, retarding the photodiode 8 array reset signal (RESET) (E). The photoarray 4 responds to the light signal. As the light signal increases, the gate and source voltages of source follower transistor M4 decrease. The voltages on T&H capacitors C1 through Cn decrease proportionally as capacitors C1 through Cn are discharged by source follower transistor M4.

[0072] The timing controller 5 sequentially delays each of the T&H control signals at a time defined by the configured timing interval (iv) (FG). As each gate closes, the accumulated optical signal is captured. The difference between the signal stored in the T&H circuit and the previous T&H circuit in the sequence represents the signal acquired within that track-and-hold bin time TBIN within the gate period. For example, the signal acquired during the third gate period corresponds to the voltage value held in C3 minus the value held in C2. Optical signal acquisition is complete (G). Each pixel circuit 7 holds multiple samples of optical signal information at different times or range depths. Each sample represents the optical signal from a more distant portion of the target or range depth.

[0073] In the example of FIG. 5, the interval TBIN between switching each track and hold circuit 9 in sequence (except the first) is the same, but in other embodiments it may be different.

[0074] After 1 to n samples have been taken, the timing controller 5 asserts the photodetector 8 array reset (RESET) signal (H) causing the photodetectors 8 of the array to return to the reset state.

[0075] Next, the bias controller 6 operates from the completion of the last T&H control signal Sn to switch the bias state of the source follower transistor M4 from a high value to a quiescent value (I).

[0076] The system operates to read out signal information. The frame request (FDEM) and clock (CK) signals operate conventionally to address and read out the track and hold circuits 9 in sequence (J). This is conventional and therefore will not be described in further detail.

[0077] The track and hold gate control signals S1 to Sn are stored to reset the voltages on the capacitors C1 to Cn, ready for the next signal acquisition event (L).

[0078] In alternative embodiments, the timing controller 5 may be implemented by means other than a chain of inverters, for example a linear amplifier with a delay stage, or a comparator stage that triggers at a variable point on the lamp.

Claims

1. 1. An image sensing device for use in an active imaging system, comprising: the image sensing device comprises a pixel circuit; Each pixel circuit is a) a photodetection circuit comprising a photodetector element configured to output a time-varying optical signal during a gating period; b) a plurality of storage circuits, each configured to receive and store the optical signals from the photodetector circuits; c) a separate switch, each storage circuit being connectable to the photodetector circuit through a separate switch associated with each storage circuit; the image sensing device comprising a timing controller circuit that sequences the switches to capture samples of the time-varying light signal at different times over the gate period; 1. An image sensing device comprising: a pixel circuit including a plurality of track-and-hold circuits, each storage circuit including a track-and-hold circuit, and each pixel circuit including a buffer amplifier connected between the photodetector circuit and the plurality of track-and-hold circuits, the buffer amplifier adapted to isolate the photodetector circuit from changes in capacitive loading of the plurality of storage circuits.

2. 2. The image sensing device of claim 1, wherein the timing controller circuit is configured to operate the separate switches such that the time-varying light signal is stored by each of a plurality of track-and-hold circuits for a period within the gate period of a different duration than other track-and-hold circuits, the periods being simultaneous.

3. 3. The image sensing device of claim 1, wherein the buffer amplifier comprises a source follower transistor and a current source load, and the active imaging system comprises a bias controller for configuring the source follower transistor between a low current value bias state and a high current value bias state, and switching is timed so that the source follower transistor operates in a high bias state during the gating period.

4. The image sensing device of claim 1 , wherein the timing controller circuit and the plurality of track-and-hold circuits are mounted on a single IC die.

5. The image sensing device of claim 1 , wherein the timing controller circuit comprises a chain of inverters.

6. The image sensing device of claim 1 , wherein the timing circuit is configurable to vary the interval at which the switch is operated.

7. The image sensing device of claim 1 , wherein the photodetector comprises an avalanche photodetector.

8. 1. A method of operating an image sensing device having a focal plane array, comprising: the image sensing device comprises a pixel circuit; Each pixel circuit is a photodetection circuit comprising a photodetector element configured to output a time-varying optical signal during a gating period; a plurality of track and hold circuits, each configured to receive and store the optical signal from the optical detection circuit, each track and hold circuit comprising a switch through which each track and hold circuit is connectable to the optical detection circuit; each pixel circuit comprising a buffer amplifier connected between the photodetector circuit and the plurality of track-and-hold circuits, the buffer amplifier adapted to isolate the photodetector circuit from changes in capacitive loading of the plurality of storage circuits; The method includes using a timing circuit to operate the switch to capture samples of the time-varying optical signal at different times over the gate period.

9. 9. The method of claim 8, including individually controlling the timing of the switches of each track and hold circuit.

10. changing the bias state of the source follower transistor from a quiescent bias state to a high bias state; activating the switch of the track and hold circuit; configuring the photodetector to respond to the laser return optical signal; 10. The method of claim 8 or 9, comprising using a common trigger signal configured to be received by a bias controller, a timing circuit, and the photodetector circuit.

11. 11. The method of claim 8, including means for configuring the pixel circuit between a first mode of operation in which each of the track and hold circuits is operative during the gate period, and a second mode of operation in which all but one of the track and hold circuits is inoperative for the entire gate period.

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