Semiconductor device

Abstract

To provide a semiconductor device in which a warp can be reduced.SOLUTION: A semiconductor device comprises: a first electrode; a second electrode; a semiconductor layer that has a plurality of mesa parts arranged in a first direction; a gate electrode that is adjacent to the mesa part in the first direction, and extends in a second direction; a conductive member that is adjacent to the mesa part in the first direction, and extends in the second direction; a first connection part that electrically connects the first electrode and the mesa part; and a second connection part that electrically connects the first electrode and the conductive member. The first electrode has a first opening that is positioned above the conductive member. Above the conductive member, the first opening and the second connection part are arranged along the second direction.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] In a vertical power device having a trench gate structure, there is a configuration in which a dummy trench that does not function as a gate electrode is provided. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-164851 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiment provides a semiconductor device capable of reducing warpage. [Means for solving the problem]

[0005] According to an embodiment, a semiconductor device includes a first electrode, a second electrode, a semiconductor layer provided between the first electrode and the second electrode, the semiconductor layer having a plurality of mesas aligned in a first direction, an insulating layer provided between the first electrode and the semiconductor layer, a gate electrode adjacent to the mesa in the first direction and extending in a second direction perpendicular to the first direction, a first insulating film provided between the gate electrode and the mesa, a conductive member adjacent to the mesa in the first direction and extending in the second direction, a second insulating film provided between the conductive member and the mesa, a first connecting portion provided between the first electrode and the mesa and electrically connecting the first electrode to the mesa, and a second connecting portion provided between the first electrode and the conductive member and electrically connecting the first electrode to the conductive member. The first electrode has a first opening located above the conductive member. The first opening and the second connecting portion are aligned above the conductive member along the second direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 10 is a schematic plan view of a semiconductor device according to a second embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line BB in FIG. [Figure 5] 10 is a graph showing a simulation result of the amount of warpage of a wafer. DETAILED DESCRIPTION OF THE INVENTION

[0007] [First embodiment] A semiconductor device 1 according to a first embodiment will be described with reference to Figures 1 and 2. The semiconductor device 1 has a first electrode 20, a second electrode 30, and a semiconductor layer .

[0008] The semiconductor device 1 has, for example, an IGBT (Insulated Gate Bipolar Transistor) structure. The first electrode 20 is an emitter electrode of the IGBT, and the second electrode 30 is a collector electrode of the IGBT. For example, a positive potential is applied to the second electrode 30, and a ground potential is applied to the first electrode 20. In an on-state in which the gate voltage of a gate electrode 51 (described later) is made higher than a threshold voltage, a current flows vertically (third direction Z) between the first electrode 20 and the second electrode 30 through the semiconductor layer 10. In the third direction Z, the direction from the second electrode 30 to the first electrode 20 is defined as up or upward, and the direction from the first electrode 20 to the second electrode 30 is defined as down or downward.

[0009] The semiconductor layer 10 is located between the first electrode 20 and the second electrode 30 in the third direction Z. The semiconductor layer 10 has a plurality of mesa portions 10A aligned in the first direction X and extending in the second direction Y. The first direction X and the second direction Y are orthogonal to each other in a plane perpendicular to the third direction Z. The semiconductor layer 10 is, for example, a silicon layer. The semiconductor layer 10 may be a silicon carbide layer or a gallium nitride layer. In this specification, the first conductivity type is described as n-type and the second conductivity type is described as p-type in terms of the conductivity type of the semiconductor layer 10, but the first conductivity type may be described as p-type and the second conductivity type may be described as n-type.

[0010] The semiconductor layer 10 has an n-type first semiconductor layer 11, a p-type second semiconductor layer 12 provided on the first semiconductor layer 11, and an n-type third semiconductor layer 13 provided on the second semiconductor layer 12. The n-type impurity concentration of the third semiconductor layer 13 is higher than the n-type impurity concentration of the first semiconductor layer 11. The semiconductor layer 10 also has a p-type fifth semiconductor layer 15 provided between the second electrode 30 and the first semiconductor layer 11. The p-type impurity concentration of the fifth semiconductor layer 15 is higher than the p-type impurity concentration of the second semiconductor layer 12. The fifth semiconductor layer 15 is in contact with the second electrode 30 and is electrically connected to the second electrode 30.

[0011] The first semiconductor layer 11, the second semiconductor layer 12, the third semiconductor layer 13, and the fifth semiconductor layer 15 are the drift layer, the base layer, the emitter layer, and the collector layer, respectively, of the IGBT.

[0012] The mesa portion 10A has a part of the first semiconductor layer 11, a second semiconductor layer 12 provided on a part of the first semiconductor layer 11, and a third semiconductor layer 13 provided on the second semiconductor layer 12.

[0013] The semiconductor device 1 further includes a gate electrode 51, a conductive member 52, a first insulating film 71, and a second insulating film 72. The gate electrode 51 and the conductive member 52 are adjacent to the mesa portion 10A in the first direction X and extend in the second direction Y. The first insulating film 71 is provided between the gate electrode 51 and the mesa portion 10A and between a lower end of the gate electrode 51 and the first semiconductor layer 11. The second insulating film 72 is provided between the conductive member 52 and the mesa portion 10A and between a lower end of the conductive member 52 and the first semiconductor layer 11. The gate electrode 51 is embedded in a trench formed in the semiconductor layer 10 with the first insulating film 71 interposed therebetween. The conductive member 52 is embedded in a trench formed in the semiconductor layer 10 with the second insulating film 72 interposed therebetween. The gate electrode 51 and the conductive member 52 can be simultaneously formed of the same material. For example, polycrystalline silicon can be used as the material for the gate electrode 51 and the conductive member 52.

[0014] A side surface of the gate electrode 51 faces the second semiconductor layer 12 (base layer) of the mesa portion 10A in the first direction X via the first insulating film 71. In an on-state where the gate voltage of the gate electrode 51 is made higher than the threshold voltage, an n-channel (inversion layer) is formed in a region of the second semiconductor layer 12 (base layer) facing the gate electrode 51.

[0015] The mesa portion 10A located between adjacent conductive members 52 in the first direction X is not adjacent to the gate electrode 51. Such a mesa portion 10A may not have the third semiconductor layer 13. Furthermore, the mesa portion 10A not adjacent to the gate electrode 51 may include a p-type fourth semiconductor layer 14 provided on the second semiconductor layer 12. The p-type impurity concentration of the fourth semiconductor layer 14 is higher than the p-type impurity concentration of the second semiconductor layer 12. The fourth semiconductor layer 14 is not provided in a region of the mesa portion 10A facing the gate electrode 51.

[0016] The semiconductor device 1 further includes an insulating layer 73, a plurality of first connecting portions 61, and a plurality of second connecting portions 62.

[0017] The insulating layer 73 is provided in the third direction Z between the semiconductor layer 10 (mesa portion 10A) and the first electrode 20, between the gate electrode 51 and the first electrode 20, and between the conductive member 52 and the first electrode 20.

[0018] The first connection portion 61 penetrates the insulating layer 73 and is provided between the mesa portion 10A and the first electrode 20. The first connection portion 61 is conductive and electrically connects the mesa portion 10A and the first electrode 20. In the mesa portion 10A including the third semiconductor layer 13, the first connection portion 61 contacts the third semiconductor layer 13 (emitter layer). The third semiconductor layer 13 is electrically connected to the first electrode 20 via the first connection portion 61. In the mesa portion 10A not including the third semiconductor layer 13 but including the fourth semiconductor layer 14, the first connection portion 61 contacts the fourth semiconductor layer 14. The fourth semiconductor layer 14 is electrically connected to the first electrode 20 via the first connection portion 61. Holes in the first semiconductor layer 11 can be discharged to the first electrode 20 via the second semiconductor layer 12, the fourth semiconductor layer 14, and the first connection portion 61.

[0019] The second connection portion 62 penetrates the insulating layer 73 and is provided between the conductive member 52 and the first electrode 20. The second connection portion 62 is conductive and electrically connects the conductive member 52 and the first electrode 20. The conductive member 52 is supplied with the potential of the first electrode 20 (emitter potential).

[0020] The first connecting portion 61 and the second connecting portion 62 can be simultaneously formed of the same material. The first connecting portion 61 and the second connecting portion 62 can be made of, for example, tungsten.

[0021] 1, the first connection portion 61 extends continuously in the second direction Y. Above one conductive member 52, multiple second connection portions 62 are arranged apart from each other in the second direction Y. The gate electrode 51 is connected to a gate wiring (not shown) at an end portion in the second direction Y.

[0022] 2 includes, for example, one gate electrode 51 and three conductive members 52. The cross-sectional area shown in FIG. 2 is repeated multiple times in the first direction X. Therefore, the semiconductor device 1 has multiple gate electrodes 51 and multiple conductive members 52. For example, the number of conductive members 52 is greater than the number of gate electrodes 51.

[0023] In the semiconductor device 1 having a trench gate structure, the gate capacitance can be reduced by providing a conductive member 52 to which an emitter potential is applied in addition to the gate electrode 51. Furthermore, by providing the conductive member 52, the emitter component (gate-emitter capacitance) and collector component (gate-collector capacitance) of the gate capacitance can be adjusted. Furthermore, by providing the conductive member 52, the channel density can be reduced.

[0024] The first electrode 20 has a first opening 20A located above the conductive member 52. The first opening 20A penetrates the first electrode 20 in the third direction Z and reaches the insulating layer 73. In the first opening 20A, the insulating layer 73 is exposed from the first electrode 20. In the third direction Z, the second connection portion 62 is not provided between the first opening 20A and the conductive member 52.

[0025] As shown in FIG. 1, above the conductive member 52 extending in the second direction Y, the first opening 20A and the second connection portion 62 are aligned in the second direction Y.

[0026] For example, the first electrode 20 made of a metal such as AlCu is likely to have a large tensile stress, and warpage is likely to occur in the wafer before it is separated into individual semiconductor devices 1. Wafer warpage affects wafer transportation and processing.

[0027] According to this embodiment, the volume of the first electrode 20 can be reduced by forming the first opening 20A in the first electrode 20. This reduces the tensile stress generated in the first electrode 20, and reduces warpage of the wafer.

[0028] The length in the second direction Y of one first opening 20A is shorter than the length in the second direction Y of the conductive member 52 and the length in the second direction Y of the first electrode 20, and the first opening 20A does not divide the first electrode 20 in the first direction X. Each conductive member 52 extending in the second direction Y is electrically connected to the first electrode 20 via a second connection portion 62 at a position where no first opening 20A is formed. A wire can be bonded to the first electrode 20 at a position where no first opening 20A is formed, thereby electrically connecting the first electrode 20 to an external circuit.

[0029] 1, a plurality of first openings 20A and a plurality of second connection portions 62 are arranged above one conductive member 52 extending in the second direction Y. The first openings 20A and the second connection portions 62 are arranged alternately in the second direction Y above one conductive member 52. In the region between adjacent first openings 20A in the second direction Y, the conductive member 52 is electrically connected to the first electrode 20 via the second connection portions 62.

[0030] The position in the second direction Y of a first opening 20A of one conductive member 52A (the conductive member 52A at the left end in FIG. 1 ) of two adjacent conductive members 52 in the first direction X is offset from the position in the second direction Y of a first opening 20A of the other conductive member 52B of the two adjacent conductive members 52. Furthermore, the position in the second direction Y of a second connection portion 62 of one conductive member 52A is offset from the position in the second direction Y of the second connection portion 62 of the other conductive member 52B. Note that the position in the second direction Y of the first opening 20A represents the center position of the first opening 20A in the second direction Y, and the position in the second direction Y of the second connection portion 62 represents the center position of the second connection portion 62 in the second direction Y.

[0031] Between the conductive member 52B and the conductive member 52C (the conductive member 52C on the far right in FIG. 1) adjacent to each other across the gate electrode 51 in the first direction X, the first openings 20A and the second connection portions 62 are aligned in the first direction X.

[0032] 1, the first electrode 20 may further have a second opening 20B located above the gate electrode 51. The second opening 20B penetrates the first electrode 20 in the third direction Z and reaches the insulating layer 73. In the second opening 20B, the insulating layer 73 is exposed from the first electrode 20. For example, a plurality of second openings 20B are lined up in the second direction Y above the gate electrode 51.

[0033] By forming the second opening 20B in the first electrode 20, the volume of the first electrode 20 can be further reduced, and warpage of the wafer can be easily reduced.

[0034] FIG. 5 is a graph showing the results of a simulation of the amount of warpage of a wafer. The diameter of the wafer is 200 mm, and the horizontal axis represents the position along one direction of the wafer. The vertical axis represents the ratio of the amount of warp at a position of 100 mm to the amount of warp at a position of 1.

[0035] The amount of warpage was calculated for each of the models a to e. In a, no opening is formed in the first electrode 20. In b, the area ratio of the openings to the non-openings in the first electrode 20 was set to 3:7. In c, the area ratio of the openings to the non-openings in the first electrode 20 was set to 5:5. In d, the area ratio of the openings to the non-openings in the first electrode 20 was set to 7:3. In e, the area ratio of the openings to the non-openings in the first electrode 20 was set to 9:1.

[0036] From the results of FIG. 5, it can be seen that the larger the area ratio of the opening in the first electrode 20, the smaller the amount of warpage.

[0037] [Second embodiment] A semiconductor device 2 of the second embodiment will be described with reference to Figures 3 and 4. In the semiconductor device 2 of the second embodiment, the same components as those in the semiconductor device 1 of the first embodiment are denoted by the same reference numerals. In the semiconductor device 2 of the second embodiment, components different from those in the semiconductor device 1 of the first embodiment will be mainly described.

[0038] The first electrode 20 has a first layer 21 provided on the insulating layer 73 and a second layer 22 provided on the first layer 21. The first connection portion 61 penetrates the insulating layer 73, is provided between the mesa portion 10A and the first layer 21, and is in contact with the mesa portion 10A and the first layer 21. The second connection portion 62 penetrates the insulating layer 73, is provided between the conductive member 52 and the first layer 21, and is in contact with the conductive member 52 and the first layer 21. The first layer 21 can be made of, for example, aluminum or copper. The second layer 22 can be made of, for example, nickel.

[0039] The first layer 21 has a first portion 21A and a second portion 21B. The thickness (thickness in the third direction Z) of the second portion 21B is thinner than the thickness (thickness in the third direction Z) of the first portion 21A. The second portion 21B is located above the conductive member 52. The upper surface of the first layer 21 has irregularities. The second layer 22 is provided on the first layer 21 along the irregularities of the upper surface of the first layer 21. As a result, the second layer 22 has a recess 22A located above the second portion 21B of the first layer 21. As shown in FIG. 1 , for example, the second portion 21B and the recess 22A extend in the second direction Y. A wire can be bonded to a position of the first electrode 20 where the recess 22A is not formed, thereby electrically connecting the first electrode 20 to an external circuit.

[0040] The presence of the recess 22A in the second layer 22 makes it possible to reduce the volume of the first electrode 20. This reduces the tensile stress generated in the first electrode 20, and reduces the warpage of the wafer.

[0041] The second layer 22 is formed by a plating method. For example, when a through-hole is formed in the first layer 21 to reduce the volume of the first electrode 20, the insulating layer 73 is exposed at the through-hole, and there is a concern that ions in the plating solution may pass through the insulating layer 73 during the plating process and migrate to the cell portion where the mesa portion 10A and the gate electrode 51 are formed. This may reduce the reliability of the semiconductor device.

[0042] According to this embodiment, by leaving a thin second portion 21B on the first layer 21, the insulating layer 73 is not exposed during the plating process for forming the second layer 22. This prevents ions in the plating solution from migrating to the cell portion side through the insulating layer 73.

[0043] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0044] REFERENCE SIGNS LIST 1, 2...semiconductor device, 10...semiconductor layer, 10A...mesa portion, 11...first semiconductor layer, 12...second semiconductor layer, 13...third semiconductor layer, 14...fourth semiconductor layer, 15...fifth semiconductor layer, 20...first electrode, 20A...first opening, 20B...second opening, 21...first layer, 21A...first portion, 21B...second portion, 22...second layer, 22A...recess, 30...second electrode, 51...gate electrode, 52...conductive member, 61...first connecting portion, 62...second connecting portion, 71...first insulating film, 72...second insulating film, 73...insulating layer

Claims

1. A first electrode; A second electrode; a semiconductor layer provided between the first electrode and the second electrode, the semiconductor layer having a plurality of mesa portions aligned in a first direction; an insulating layer provided between the first electrode and the semiconductor layer; a gate electrode adjacent to the mesa portion in the first direction and extending in a second direction perpendicular to the first direction; a first insulating film provided between the gate electrode and the mesa portion; a conductive member adjacent to the mesa portion in the first direction and extending in the second direction; a second insulating film provided between the conductive member and the mesa portion; a first connection portion provided between the first electrode and the mesa portion and electrically connecting the first electrode and the mesa portion; a second connection portion provided between the first electrode and the conductive member and electrically connecting the first electrode and the conductive member; Equipped with the first electrode has a first opening located above the conductive member; The semiconductor device, wherein the first opening and the second connection portion are aligned along the second direction above the conductive member.

2. a plurality of the first openings and a plurality of the second connection portions are disposed above one of the conductive members; the first openings and the second connection portions are alternately arranged in the second direction above the one conductive member, 2. The semiconductor device according to claim 1, wherein the position in the second direction of the first opening of one of two conductive members adjacent to each other in the first direction is offset from the position in the second direction of the first opening of the other of the two conductive members.

3. 3. The semiconductor device according to claim 1, wherein said first electrode is located above said gate electrode and has a second opening that reaches said insulating layer.

4. The semiconductor device according to claim 3 , wherein a plurality of said second openings are aligned in said second direction above said gate electrode.

5. A first electrode; A second electrode; a semiconductor layer provided between the first electrode and the second electrode, the semiconductor layer having a plurality of mesa portions aligned in a first direction; an insulating layer provided between the first electrode and the semiconductor layer; a gate electrode adjacent to the mesa portion in the first direction and extending in a second direction perpendicular to the first direction; a first insulating film provided between the gate electrode and the mesa portion; a conductive member adjacent to the mesa portion in the first direction and extending in the second direction; a second insulating film provided between the conductive member and the mesa portion; a first connection portion provided between the first electrode and the mesa portion and electrically connecting the first electrode and the mesa portion; a second connection portion provided between the first electrode and the conductive member and electrically connecting the first electrode and the conductive member; Equipped with the first electrode has a first layer provided on the insulating layer and a second layer provided on the first layer; the first layer has a first portion and a second portion that is thinner than the first portion and located above the conductive member; The second layer has a recess located above the second portion.

6. The semiconductor device according to claim 5 , wherein the second portion and the recess extend in the second direction.

7. The mesa portion is a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided on the second semiconductor layer and having a higher first conductivity type impurity concentration than the first semiconductor layer; and the first connection portion is in contact with the third semiconductor layer; The semiconductor device according to claim 1 , wherein a side surface of the gate electrode faces the second semiconductor layer in the first direction, with the first insulating film interposed therebetween.

8. the mesa portion further includes a fourth semiconductor layer of a second conductivity type provided on the second semiconductor layer and having a second conductivity type impurity concentration higher than that of the second semiconductor layer; The semiconductor device according to claim 7 , wherein the first connection portion is in contact with the fourth semiconductor layer.

9. 8. The semiconductor device according to claim 7, wherein the semiconductor layer further includes a fifth semiconductor layer of the second conductivity type provided between the second electrode and the first semiconductor layer.

10. The semiconductor device according to claim 1 , wherein the first opening of the first electrode reaches the insulating layer.

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