Display device and electronic apparatus

Abstract

To provide a display device capable of preventing or reducing deterioration in the visibility of an image displayed in a display area by external light.SOLUTION: A display device comprises: a substrate including a display area and a non-display area; a pad area disposed in the non-display area of the substrate; first and second cluster pads that are attached in the pad area; and routing lines arranged on the substrate and electrically connected from the display area to the first and second cluster pads. The routing lines include first and second routing lines extending to the first and second cluster pads, and the first routing line and the second routing line are arranged adjacent to each other. The first routing line includes a first middle portion extending in a second direction crossing a first direction that is a horizontal direction, and the second routing line includes a second middle portion adjacent to and parallel to the first middle portion. The first middle portion and the second middle portion are arranged between the first cluster pad and the second cluster pad.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a display device and an electronic device. [Background technology]

[0002] With the development of an information society, the demands for display devices for displaying images are becoming increasingly diverse. For example, display devices are applied to a variety of electronic devices such as smartphones, digital cameras, notebook computers, navigation systems, and smart TVs.

[0003] Recently, display devices have been minimizing bezel areas or non-display areas outside the display area in order to expand the display area where pixels that display images are arranged. Various signal wiring is arranged in the bezel area or non-display area, and resistance differences occur depending on the length and width of the signal wiring, which can degrade display quality. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Chinese Patent No. 117037674 [Patent Document 2] Korean Patent Registration No. 2529077 [Patent Document 3] Korean Patent No. 2256854 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device capable of improving display quality by reducing the difference in resistance between wirings in the non-display area.

[0006] The objectives of the present invention are not limited to those mentioned above, and other technical objectives not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] According to one embodiment of the present invention, there is provided a display device including a substrate having a display area and a non-display area, a pad area disposed in the non-display area of ​​the substrate, first cluster pads and second cluster pads attached to the pad area, and routing wiring disposed on the substrate and electrically connected from the display area to the first cluster pads and the second cluster pads, the routing wiring being disposed adjacent to each other and including a first routing wiring extending to the first cluster pads and a second routing wiring extending to the second cluster pads, the first routing wiring and the second routing wiring being disposed adjacent to each other, the first routing wiring including a first middle portion extending in a second direction intersecting a first direction which is horizontal, and the second routing wiring including a second middle portion aligned adjacent to the first middle portion, the first middle portion and the second middle portion being disposed between the first cluster pads and the second cluster pads.

[0008] The first routing wiring may include a first front portion extending from the display area, a first connecting portion bent and extending from the first front portion, a first extension portion bent and extending from the first middle portion, and a first rear portion bent from the first extension portion and extending to the first cluster pad, and the first middle portion may be bent and extending from the first connecting portion.

[0009] The first front section, the first middle section, and the first rear section may extend in a second direction and be aligned with one another.

[0010] The display device may further include a power supply wiring disposed on the non-display area, extending in the first direction, and overlapping with the routing wiring.

[0011] The first front portion and the first middle portion may not overlap the power supply wiring, and the first extension portion may overlap the power supply wiring.

[0012] The second routing wiring may include a second front portion extending from the display area, a second connecting portion bent and extending from the second front portion, a second extension portion bent and extending from the second middle portion, and a second rear portion bent from the second extension portion and extending to the second cluster pad, and the second middle portion may be bent and extending from the second connecting portion.

[0013] The second front section, the second middle section, and the second rear section may extend in a second direction and be aligned with one another, and the first front section and the second front section, the first middle section and the second middle section, and the first rear section and the second rear section may be aligned with one another, respectively.

[0014] The display device may further include a power wiring arranged on the non-display area, extending in the first direction, and overlapping with the routing wiring, wherein the second front stage and the second middle stage do not overlap with the power wiring, and the second extension stage overlaps with the power wiring.

[0015] The first routing wiring may include a first front bend portion disposed between the first front portion and the first connecting portion, a first middle bend portion disposed between the first connecting portion and the first middle portion, a first extended bend portion disposed between the first middle portion and the first extended portion, and a first rear bend portion disposed between the first extended portion and the first rear portion.

[0016] The second routing wiring may include a second front bend portion disposed between the second front portion and the second connecting portion, a second middle bend portion disposed between the second connecting portion and the second middle portion, a second extended bend portion disposed between the second middle portion and the second extended portion, and a second rear bend portion disposed between the second extended portion and the second rear portion.

[0017] The distance between the first front section and the second front section may be greater than the distance between the first middle section and the second middle section, and the distance between the first rear section and the second rear section may be greater than the distance between the first front section and the second front section.

[0018] The first routing wiring may include other adjacent first routing wirings, and the spacing between the first front stages of the adjacent first routing wirings may be greater than the spacing between the first middle stages, and the spacing between the first middle stages may be greater than the spacing between the first rear stages.

[0019] The second routing wiring may include other adjacent second routing wiring, and the spacing between the second front stages of the adjacent second routing wiring may be greater than the spacing between the second middle stages, and the spacing between the second middle stages may be greater than the spacing between the second rear stages.

[0020] The width and length of the routing wires may be the same, and "same" also includes "approximately the same."

[0021] Moreover, a display device according to one embodiment includes a display panel, a plurality of pixels arranged in a display area of ​​the display panel, a pad area arranged in a non-display area of ​​the display panel and including first cluster pads and second cluster pads, data routing wiring extending from the display area to the pad area, and power wiring arranged in the non-display area and intersecting the data routing wiring, wherein the data routing wiring includes a first data routing wiring extending to the first cluster pad and a second data routing wiring extending to the second cluster pad, and the first data routing wiring and the second data routing wiring each may include a plurality of bent portions in a planar view.

[0022] The first data routing wiring may include a first front portion extending from the display area, a first connecting portion bent and extending from the first front portion, a first middle portion bent and extending from the first connecting portion, a first extension portion bent and extending from the first middle portion, and a first rear portion bent from the first extension portion to extend to the first cluster pad, and the second data routing wiring may include a second front portion extending from the display area, a second connecting portion bent and extending from the second front portion, a second middle portion bent and extending from the second connecting portion, a second extension portion bent and extending from the second middle portion, and a second rear portion bent from the second extension portion to extend to the second cluster pad.

[0023] The first data routing wiring may include a first front bend disposed between the first front portion and the first connecting portion, a first middle bend disposed between the first connecting portion and the first middle portion, a first extended bend disposed between the first middle portion and the first extended portion, and a first rear bend disposed between the first extended portion and the first rear portion, and the second data routing wiring may include a second front bend disposed between the second front portion and the second connecting portion, a second middle bend disposed between the second connecting portion and the second middle portion, a second extended bend disposed between the second middle portion and the second extended portion, and a second rear bend disposed between the second extended portion and the second rear portion.

[0024] In the first data routing wiring and the second data routing wiring, which are arranged adjacent to each other, the first front bend portion and the first rear bend portion of the first data routing wiring may overlap with the first cluster pad in a second direction intersecting a first direction that is horizontal on a plane.

[0025] The first middle bend and the first extended bend of the first data routing wiring and the second middle bend and the second extended bend of the second data routing wiring may overlap between the first cluster pad and the second cluster pad in the second direction on a plane.

[0026] The first data routing line and the second data routing line may have the same width and length.

[0027] Further, according to one embodiment, a display device includes a substrate including a non-display area including a pad area and a display area, first cluster pads and second cluster pads arranged on the pad area of ​​the substrate, a first data routing wiring arranged on the non-display area of ​​the substrate and extending from the display area to the first cluster pads, a second data routing wiring arranged on the non-display area of ​​the substrate and extending from the display area to the second cluster pads, and a first insulating layer arranged on the non-display area of ​​the substrate, wherein the first data routing wiring includes a 1-1 routing wiring arranged below the first insulating layer and a 1-2 routing wiring arranged above the first insulating layer, and the second data routing wiring includes a 2-1 routing wiring arranged below the first insulating layer and a 2-2 routing wiring arranged above the first insulating layer, and the 1-2 routing wiring and the 2-1 routing wiring are adjacent to each other and each may include a plurality of bent portions in a planar view.

[0028] The 1-1 routing wiring and the 1-2 routing wiring may be alternately and repeatedly arranged with the first insulating layer therebetween, and the 2-1 routing wiring and the 2-2 routing wiring may be alternately and repeatedly arranged with the first insulating layer therebetween.

[0029] The circuit may further include a voltage wiring disposed on the first-second routing wiring and the second-first routing wiring, and the first data routing wiring and the second data routing wiring may overlap with the voltage wiring.

[0030] The first data routing line and the second data routing line may have the same width and length.

[0031] According to an embodiment, an electronic device includes a display device for providing an image, a processor for providing an image data signal to the display device, a memory for storing data information for driving the display device, and a power supply module for generating power. The display device may include: a substrate including a display area and a non-display area; a pad area disposed in the non-display area of ​​the substrate; first cluster pads and second cluster pads attached to the pad area; and routing wiring disposed on the substrate and electrically connected from the display area to the first cluster pads and the second cluster pads, the routing wiring being disposed adjacent to each other and including a first routing wiring extending to the first cluster pad and a second routing wiring extending to the second cluster pad, the first routing wiring and the second routing wiring being disposed adjacent to each other, the first routing wiring including a first middle portion extending in a second direction intersecting a first direction, which is horizontal, and the second routing wiring including a second middle portion adjacent to and aligned with the first middle portion, the first middle portion and the second middle portion being disposed between the first cluster pads and the second cluster pads.

[0032] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0033] In a display device according to an embodiment, the wiring resistance between the routing lines can be made uniform by adjusting the extension shape of the routing lines to make the width and length of the routing lines uniform, thereby preventing RC delay, thereby improving the brightness difference of the display device and improving display quality.

[0034] The effects of the embodiments are not limited to the above-mentioned examples, and a wider variety of effects are included in this specification. [Brief explanation of the drawings]

[0035] [Figure 1] 1 is a perspective view illustrating a display device according to an embodiment. [Figure 2] 1 is a plan view showing a display device according to an embodiment. [Figure 3] FIG. 3 is a plan view showing the display panel of FIG. 2. [Figure 4] 1 is a circuit diagram of a pixel of a display device according to an embodiment; [Figure 5] 1 is a cross-sectional view showing a display device according to an embodiment. [Figure 6] FIG. 2 is a plan view showing a non-display area of ​​a display device according to an embodiment. [Figure 7] FIG. 7 is an enlarged plan view of region A in FIG. 6. [Figure 8] FIG. 2 is a plan view schematically showing a first routing wiring. [Figure 9] FIG. 10 is a plan view schematically showing a second routing wiring. [Figure 10] FIG. 8 is a cross-sectional view taken along the line Q1-Q1′ in FIG. 7. [Figure 11] FIG. 8 is an enlarged plan view of region B in FIG. 7. [Figure 12] 8A and 8B are cross-sectional views taken along lines Q2-Q2', Q3-Q3', and Q4-Q4' in FIG. 7. [Figure 13] FIG. 1 is a block diagram of an electronic device according to one embodiment. [Figure 14] 1 is a schematic diagram of an electronic device according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0036] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided merely to complete the disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0037] When an element or layer is referred to as being "on" another element or layer, this includes the case where it is directly on top of or has other layers or elements interposed therebetween. Similarly, when references are made to "below," "left," and "right," this includes the case where it is directly adjacent to or has other layers or materials interposed therebetween. The same reference numerals refer to the same elements throughout the specification. In embodiments, "same" also includes "substantially the same."

[0038] Although terms such as "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that a "first" component referred to below may be a "second" component within the technical concept of the present invention.

[0039] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0040] FIG. 1 is a perspective view showing a display device according to an embodiment.

[0041] Referring to FIG. 1, the display device 100 is a device for displaying moving or still images, and can be used as a display screen for a variety of products, including portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, and Ultra Mobile PCs (UMPCs), as well as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT).

[0042] The display device 100 may be an emissive display device such as an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, and a micro- or nano-light emitting display device using a micro- or nano-light emitting diode (micro LED or nano LED). Although the following description focuses on the case where the display device 100 is an organic light emitting display device, the present invention is not limited thereto.

[0043] The display device 100 may include a display panel 110 and a circuit board 200 .

[0044] The display panel 110 may be formed as a rectangular plane having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1. The corner where the long side in the first direction DR1 and the short side in the second direction DR2 intersect may be rounded or squared to have a predetermined curvature.

[0045] The planar shape of the display panel 110 is not limited to a rectangle, but may be other polygonal, circular, or elliptical shapes. The display panel 110 may be formed flat, but is not limited thereto. For example, the display panel 110 may include curved portions formed at the left and right ends, having a constant or variable curvature. In addition, the display panel 110 may be formed flexible so that it can be bent, warped, bent, folded, or rolled.

[0046] The display panel 110 may include a display area DA that displays an image and a non-display area NDA that is arranged around the display area DA. Alternatively, the substrate of the display panel 110 ("SUB" in FIG. 5) may include the display area DA and the non-display area NDA.

[0047] The display area DA occupies most of the area of ​​the display panel 110. The display area DA may be disposed in the center of the display panel 110. Pixels may be disposed in the display area DA to display an image.

[0048] The non-display area NDA may be disposed adjacent to the display area DA, may be an outer area of ​​the display area DA, may be disposed so as to surround the display area DA, or may be an edge area of ​​the display panel 110.

[0049] Pads ("PD" in FIG. 3) may be arranged in the non-display area NDA to be connected to the circuit board 200. The pads may be arranged on one side edge of the display panel 110. For example, the pads may be arranged on the bottom edge of the display panel 110.

[0050] The circuit board 200 may be disposed on a pad area PA disposed on one side edge of the display panel 110. The circuit board 200 may be attached to the display pad DP using a low-resistance, highly reliable material such as anisotropic conductive film or SAP (Self-Assembly Anisotropic Conductive Paste). This allows the circuit board 200 to be electrically connected to the signal wiring of the display panel 110.

[0051] The display panel 110 may receive inputs such as a data voltage, a power supply voltage, and a scan timing signal via a circuit board 200. The circuit board 200 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0052] The circuit board 200 may include a data driver DD. The data driver DD may generate a data voltage, a power supply voltage, a scan timing signal, etc. The data driver DD may supply the data voltage, the power supply voltage, the scan timing signal, etc. to the display panel 110 via the circuit board 200.

[0053] The data driver DD may be formed as an integrated circuit (IC) and mounted on the circuit board 200. Alternatively, the data driver DD may be mounted on the display panel 110 using a chip on glass (COG) method, a chip on plastic (COP) method, or ultrasonic bonding method.

[0054] Fig. 2 is a plan view of a display device according to an embodiment, Fig. 3 is a plan view of a display panel of Fig. 2, Fig. 3 is a diagram showing the remaining components of Fig. 2 except for a data driver.

[0055] 2 and 3, the display device 100 may include a plurality of pixels PX arranged on a display panel 110, a gate driver that supplies driving signals to the pixels PX, an emission driver, and a data driver. Here, the pixels PX may be arranged in a display area DA of the display panel 110, the gate driver and the emission driver may be arranged in a non-display area NDA of the display panel 110, and the data driver may be connected to the non-display area NDA of the display panel 110 via a circuit board 200.

[0056] The display device 100 may further include a power supply and a timing control unit. The power supply may supply power voltages to the pixels PX, the gate drivers, the light emitting drivers, and the data drivers. The timing control unit may control the operations of the first gate driver GD1, the second gate driver GD2, the first light emitting driver ED1, the second light emitting driver ED2, and the data driver.

[0057] A plurality of pixels PX may be arranged in a display area DA. The plurality of pixels PX may display an image. The plurality of pixels PX may be connected to gate lines GL, emission control lines EML, data lines DL, and power lines. The gate lines GL and emission control lines EML may extend along a first direction DR1, and the data lines DL may extend along a second direction DR2.

[0058] 3, the non-display area NDA may include a pad area PA in which a plurality of pads PD are arranged. For example, the pad area PA may be arranged in a non-display area (NDA; e.g., a lower non-display area) located below the display area. The plurality of pads PD may be arranged along a first direction DR1.

[0059] A gate driver GD and a light-emitting driver ED may be arranged in the non-display area NDA. For example, the gate driver GD may include a first gate driver GD1 and a second gate driver GD2. The light-emitting driver ED may include a first light-emitting driver ED1 and a second light-emitting driver ED2. Here, the first gate driver GD1 and the first light-emitting driver ED1 may be arranged in the non-display area (NDA; e.g., the left non-display area) located on the left side of the display area DA, and the second gate driver GD2 and the second light-emitting driver ED2 may be arranged in the non-display area (NDA; e.g., the right non-display area) located on the right side of the display area DA.

[0060] The gate driver GD may drive the gate lines GL. For example, the first gate driver GD1 and the second gate driver GD2 may respectively supply gate signals to the gate lines GL. The gate lines GL may be connected to the first gate driver GD1 and the second gate driver GD2. For example, one side of each gate line GL may be electrically connected to the first gate driver GD1, and the other side of each gate line GL may be electrically connected to the second gate driver GD2.

[0061] The light-emitting driver ED may drive the light-emitting control line EML. For example, the first light-emitting driver ED1 and the second light-emitting driver ED2 may each supply a light-emitting control signal to the light-emitting control line EML, and the light-emitting control line EML may be connected to the first light-emitting driver ED1 and the second light-emitting driver ED2. For example, one side of each light-emitting control line EML may be electrically connected to the first light-emitting driver ED1, and the other side of each light-emitting control line EML may be electrically connected to the second light-emitting driver ED2.

[0062] The circuit board 200 may be electrically connected to the display panel 110 via pads PD. The circuit board 200 may include a first circuit board CB1, a second circuit board CB2, a third circuit board CB3, a fourth circuit board CB4, and a fifth circuit board CB5. In one embodiment, the first to fifth circuit boards CB1-CB5 may be connected to at least one of a timing control unit and a power supply unit via another circuit board or a connector.

[0063] Each circuit board CB1-CB5 may include a cluster terminal (or cluster bump). For example, the first circuit board CB1 may include a first cluster terminal BP1, the second circuit board CB2 may include a second cluster terminal BP2, the third circuit board CB3 may include a third cluster terminal BP3, the fourth circuit board CB4 may include a fourth cluster terminal BP4, and the fifth circuit board CB5 may include a fifth cluster terminal BP5.

[0064] The first cluster terminal BP1 may include a plurality of first terminals (or bumps; C1, P1, D1) arranged adjacently on the first circuit board CB1, the second cluster terminal BP2 may include a plurality of second terminals P2, D2 arranged adjacently on the second circuit board CB2, the third cluster terminal BP3 may include a plurality of third terminals P3, D3 arranged adjacently on the third circuit board CB3, the fourth cluster terminal BP4 may include a plurality of fourth terminals P4, D4 arranged adjacently on the fourth circuit board CB4, and the fifth cluster terminal BP5 may include a plurality of fifth terminals C2, P5, D5 arranged adjacently on the fifth circuit board CB5.

[0065] The data driver DD may include a plurality of driver circuits (DDC1, DDC2, DDC3, DDC4, DDC5; hereinafter, referred to as data driver circuits) arranged along a first direction DR1. For example, the data driver DD may include a first data driver circuit DDC1 mounted on a first circuit board CB1, a second data driver circuit DDC2 mounted on a second circuit board CB2, a third data driver circuit DDC3 mounted on a third circuit board CB3, a fourth data driver circuit DDC4 mounted on a fourth circuit board CB4, and a fifth data driver circuit DDC5 mounted on a fifth circuit board CB5.

[0066] Each of the data driving circuits DDC1-DDC5 can be electrically connected to the pads PD of the display panel 110 via each of the circuit boards CB1-CB5. For example, the first data driving circuit DDC1 may be electrically connected to the first pads C11, P11, and D11 of the display panel 110 via the first terminals C1, P1, and D1 of the first circuit board CB1, the second data driving circuit DDC2 may be electrically connected to the second pads P22 and D22 of the display panel 110 via the second terminals P2 and D2 of the second circuit board CB2, the third data driving circuit DDC3 may be electrically connected to the third pads P33 and D33 of the display panel 110 via the third terminals P3 and D3 of the third circuit board CB3, the fourth data driving circuit DDC4 may be electrically connected to the fourth pads P44 and D44 of the display panel 110 via the fourth terminals P4 and D4 of the fourth circuit board CB4, and the fifth data driving circuit DDC5 may be electrically connected to the fifth pads C22, P55, and D55 of the display panel 110 via the fifth terminals C2, P5, and D5 of the fifth circuit board CB5.

[0067] The plurality of data lines DL may be connected to the data driver DD. For example, the plurality of data lines DL may be divided and connected to a plurality of data driving circuits DDC1-DDC5. As a specific example, the plurality of data lines DL may include a plurality of first data lines connected to the first data driving circuit DDC1, a plurality of second data lines connected to the second data driving circuit DDC2, a plurality of third data lines connected to the third data driving circuit DDC3, a plurality of fourth data lines connected to the fourth data driving circuit DDC4, and a plurality of fifth data lines connected to the fifth data driving circuit DDC5.

[0068] The first terminals (C1, P1, D1; for example, the first cluster terminals BP1) may include a plurality of first control terminals C1, a plurality of first power supply terminals P1, and a plurality of first data terminals D1 arranged along a first direction DR1 on the first circuit board CB1. The first control terminal C1 may be connected to a timing control unit arranged on another circuit board (hereinafter, an external circuit board). The first power supply terminal P1 may be connected to a power supply unit arranged on the external circuit board. The first data terminal D1 may be connected to a first data driving circuit DDC1.

[0069] The second terminals (P2, D2; for example, the second cluster terminals BP2) may include a plurality of second power terminals P2 and a plurality of second data terminals D2 arranged along the first direction DR1 on the second circuit board CB2. The second power terminals P2 may be connected to a power supply disposed on an external circuit board. The second data terminals D2 may be connected to the second data driving circuit DDC2.

[0070] The third terminals (P3, D3; for example, the third cluster terminals BP3) may include a plurality of third power supply terminals P3 and a plurality of third data terminals D3 arranged along the first direction DR1 on the third circuit board CB3. The third power supply terminals P3 may be connected to a power supply disposed on an external circuit board. The third data terminals D3 may be connected to a third data driving circuit DDC3.

[0071] The fourth terminals (P4, D4; for example, the fourth cluster terminals BP4) may include a plurality of fourth power supply terminals P4 and a plurality of fourth data terminals D4 arranged along the first direction DR1 on the fourth circuit board CB4. The fourth power supply terminals P4 may be connected to a power supply disposed on an external circuit board. The fourth data terminals D4 may be connected to a fourth data driving circuit DDC4.

[0072] The fifth terminals (C2, P5, D5; for example, the fifth cluster terminal BP5) may include a plurality of second control terminals C2, a plurality of fifth power supply terminals P5, and a plurality of fifth data terminals D5 arranged along the first direction DR1 on the fifth circuit board CB5. The second control terminal C2 may be connected to a timing control unit arranged on the external circuit board. The fifth power supply terminal P5 may be connected to a power supply unit arranged on the external circuit board. The fifth data terminal D5 may be connected to a fifth data driving circuit DDC5.

[0073] The first terminals C1, P1, D1 of the first circuit board CB1, the second terminals P2, D2 of the second circuit board CB2, the third terminals P3, D3 of the third circuit board CB3, the fourth terminals P4, D4 of the fourth circuit board CB4, and the fifth terminals C2, P5, D5 of the fifth circuit board CB5 may be respectively connected to the first pads C11, P11, D11 of the first cluster pad PD1, the second pads P22, D22 of the second cluster pad PD2, the third pads P33, D33 of the third cluster pad PD3, the fourth pads P44, D44 of the fourth cluster pad PD4, and the fifth pads C22, P55, D55 of the fifth cluster pad PD5 of the display panel 110.

[0074] The first terminals C1, P1, D1 can be arranged to correspond to (or overlap with) the first pads C11, P11, D11, respectively, the second terminals P2, D2 can be arranged to correspond to (or overlap with) the second pads P22, D22, respectively, the third terminals P3, D3 can be arranged to correspond to (or overlap with) the third pads P33, D33, respectively, the fourth terminals P4, D4 can be arranged to correspond to (or overlap with) the fourth pads P44, D44, respectively, and the fifth terminals C2, P5, D5 can be arranged to correspond to (or overlap with) the fifth pads C22, P55, D55, respectively.

[0075] The first pads C11, P11, and D11 may include a plurality of first control pads C11, a plurality of first power pads P11, and a plurality of first data pads D11 arranged along a first direction DR1 on the pad area PA of the display panel 110. The first control pads C11 may be connected to the first control terminals C1. The first control pads C11 may be connected to the first gate driver GD1 and the second gate driver GD2. The first power pads P11 may be connected to the first power terminals P1. The first power pads P11 may be connected to the first gate driver GD1, the first light-emitting driver ED1, and the pixels PX. The first data pads D11 may be connected to the first data terminals D1. The first data pads D11 may be connected to the first data lines.

[0076] The second pads P22, D22 may include a plurality of second power supply pads P22 and a plurality of second data pads D22 arranged along the first direction DR1 on the pad area PA of the display panel 110. The second power supply pads P22 may be connected to the second power supply terminals P2, respectively. The second power supply pads P22 may be connected to the pixels PX. The second data pads D22 may be connected to the second data terminals D2, respectively. The second data pads D22 may be connected to the second data lines, respectively.

[0077] The third pads P33, D33 may include a plurality of third power supply pads P33 and a plurality of third data pads D33 arranged along the first direction DR1 on the pad area PA of the display panel 110. The third power supply pads P33 may be connected to the third power supply terminals P3, respectively. The third power supply pads P33 may be connected to the pixels PX, the third data pads D33 may be connected to the third data terminals D3, respectively. The third data pads D33 may be connected to the third data lines, respectively.

[0078] The fourth pads P44, D44 may include a plurality of fourth power supply pads P44 and a plurality of fourth data pads D44 arranged along the first direction DR1 on the pad region PA of the display panel 110. The fourth power supply pads P44 may be connected to the fourth power supply terminals P4, and the fourth power supply pads P44 may be connected to the pixels PX. The fourth data pads D44 may be connected to the fourth data terminals D4, and the fourth data pads D44 may be connected to the fourth data lines.

[0079] The fifth pads C22, P55, and D55 may include a plurality of second control pads C22, a plurality of fifth power pads P55, and a plurality of fifth data pads D55 arranged along the first direction DR1 on the pad area PA of the display panel 110. The second control pads C22 may be connected to the second control terminals C2, the fifth power pads P55 may be connected to the fifth power terminals P5, and the fifth power pads P55 may be connected to the pixels PX. The fifth data pads D55 may be connected to the fifth data terminals D5, and the fifth data pads D55 may be connected to the fifth data lines.

[0080] The above-mentioned first control pad C11 and first gate driver GD1 may be electrically connected to each other via a corresponding fanout line FL, and another first control pad C11 and first light-emitting driver ED1 may be electrically connected to each other via a corresponding fanout line FL.

[0081] The second control pad C22 and the second gate driver GD2 mentioned above may be electrically connected to each other via the corresponding fanout line FL, and another second control pad C22 and the second light-emitting driver ED2 may be electrically connected to each other via the corresponding fanout line FL.

[0082] The first to fifth data pads D11, D22, D33, D44, and D55 may be electrically connected to the first to fifth data lines through corresponding fan-out lines FL.

[0083] A gate timing control signal, a light-emitting timing control signal, a gate clock signal, and a light-emitting clock signal from the timing controller may be supplied to the first gate driver GD1 and the first light-emitting driver ED1 via the first control terminal C1 of the first circuit board CB1 and the first control pad C11 of the display panel 110. For example, the gate timing control signal and the gate clock signal may be supplied to the first gate driver GD1, and the light-emitting timing control signal and the light-emitting clock signal may be supplied to the first light-emitting driver ED1. A power signal from the power supply may be supplied to the first gate driver GD1, the first light-emitting driver ED1, and the pixel PX via the first power terminal P1 of the first circuit board CB1 and the first power pad P11 of the display panel 110. The power signal may include, for example, a driving voltage, a common voltage, a first initialization voltage, a second initialization voltage, and a bias voltage. A data signal from the first data driver circuit DDC1 may be supplied to the first data line via the first data terminal D1 of the first circuit board CB1 and the first data pad D11 of the display panel 110.

[0084] A power signal from the power supply unit can be supplied to the pixel PX via the second power terminal P2 of the second circuit board CB2 and the second power pad P22 of the display panel 110. A data signal from the second data driving circuit DDC2 can be supplied to the second data line via the second data terminal D2 of the second circuit board CB2 and the second data pad D22 of the display panel 110.

[0085] A power signal from the power supply unit may be supplied to the pixel PX via the third power terminal P3 of the third circuit board CB3 and the third power pad P33 of the display panel 110. A data signal from the third data driving circuit DDC3 may be supplied to the third data line via the third data terminal D3 of the third circuit board CB3 and the third data pad D33 of the display panel 110.

[0086] A power signal from the power supply unit may be supplied to the pixel PX via a fourth power terminal P4 of the fourth circuit board CB4 and a fourth power pad P44 of the display panel 110. A data signal from the fourth data driving circuit DDC4 may be supplied to the fourth data line via a fourth data terminal D4 of the fourth circuit board CB4 and a fourth data pad D44 of the display panel 110.

[0087] A gate timing control signal, a light-emitting timing control signal, a gate clock signal, and a light-emitting clock signal from the timing controller may be supplied to the second gate driver GD2 and the second light-emitting driver ED2 via the second control terminal C2 of the fifth circuit board CB5 and the second control pad C22 of the display panel 110. For example, the gate timing control signal and the gate clock signal may be supplied to the second gate driver GD2, and the light-emitting timing control signal and the light-emitting clock signal may be supplied to the second light-emitting driver ED2. A power signal from the power supply may be supplied to the second gate driver GD2, the second light-emitting driver ED2, and the pixel PX via the fifth power terminal P5 of the fifth circuit board CB5 and the fifth power pad P55 of the display panel 110. A data signal from the fifth data driver circuit DDC5 may be supplied to the fifth data line via the fifth data terminal D5 of the fifth circuit board CB5 and the fifth data pad D55 of the display panel 110.

[0088] At least one first alignment key AK1 may be arranged in the non-display area NDA. For example, the first alignment key AK1 may be arranged between adjacent circuit boards in the non-display area NDA. The first alignment key AK1 may be a mark for aligning the circuit boards. The first alignment key AK1 may be used to align the circuit boards. The first alignment key AK1 may also be used to check whether the circuit boards are accurately aligned with each other. The first alignment key AK1 may have, for example, a cross shape.

[0089] 4 is a circuit diagram for a pixel of a display device according to an embodiment, for example, the pixel PX of FIG.

[0090] As shown in FIG. 4, the pixel PX may be connected to a first gate line GWL, a second gate line GCL, a third gate line GIL, a fourth gate line EBL, an emission control line EML, a data line DL, a driving voltage line VDL, a common voltage line VSL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a bias voltage line VBL.

[0091] The pixel PX may include a pixel circuit PC and a light-emitting element LEL. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor Cst.

[0092] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 can control a source-drain current (hereinafter, referred to as a drive current) in response to a data voltage applied to the gate electrode. The drive current (e.g., Isd) flowing through the channel region of the first transistor T1 is proportional to the square of the difference between the voltage (Vsg) between the source electrode and gate electrode of the first transistor T1 and the threshold voltage (Vth) of the first transistor T1 (Isd=k×(Vsg-Vth)). 2 ) where k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vsg is the source-gate voltage of the first transistor T1, and Vth is the threshold voltage of the first transistor T1.

[0093] The light emitting element LEL receives the driving current Isd and emits light, and the amount of light emitted or the brightness of the light emitting element LEL may be proportional to the magnitude of the driving current Isd.

[0094] The light-emitting element LEL may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes. As another example, the light-emitting element LEL may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. As yet another example, the light-emitting element LEL may be a quantum dot light-emitting element including a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first and second electrodes. As yet another example, the light-emitting element LEL may be a micro light-emitting diode.

[0095] A first electrode of the light-emitting element LEL may be electrically connected to a fourth node N4. The first electrode of the light-emitting element LEL may be connected to the drain electrode of the sixth transistor T6 and the source electrode of the seventh transistor T7 via the fourth node N4. The first electrode of the light-emitting element LEL may be connected to a driving voltage line VDL. A second electrode of the light-emitting element LEL may receive a second driving voltage (VS; for example, a low-potential voltage) from a common voltage line VSL.

[0096] The second transistor T2 may be turned on by a first gate signal GW of the first gate line GWL to electrically connect the data line DL to a first node N1, which is a source electrode of the first transistor T1. The second transistor T2 may be turned on based on the first gate signal GW to supply a data voltage to the first node N1. The gate electrode of the second transistor T2 may be electrically connected to the first gate line GWL, the source electrode may be electrically connected to the data line DL, and the drain electrode may be electrically connected to the first node N1.

[0097] The third transistor T3 may be turned on by a second gate signal GC on the second gate line GCL to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the third node N3, which is the gate electrode of the first transistor T1. The third transistor T3 may be connected between the third node N3 and the second node N2. For example, the gate electrode of the third transistor T3 may be electrically connected to the second gate line GCL, the source electrode may be electrically connected to the third node N3, and the drain electrode may be electrically connected to the second node. The third transistor T3 may be turned on by a second gate signal on the second gate line GCL to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the third node N3, which is the gate electrode of the first transistor T1. The third transistor T3 may be a double-gate transistor having two gate electrodes (e.g., a gate electrode and an opposing gate electrode). The gate electrode and the opposing gate electrode may be arranged to face each other on different layers.

[0098] The fourth transistor T4 may be turned on by a third gate signal GI on the third gate line GIL to electrically connect the third node N3, which is the gate electrode of the first transistor T1, to the first initialization voltage line VIL1. The fourth transistor T4 may be connected in series between the third node N3 and the first initialization voltage line VIL1. For example, the gate electrode of the fourth transistor T4 may be electrically connected to the third gate line GIL, the source electrode may be electrically connected to the third node N3, and the drain electrode may be electrically connected to the first initialization voltage line VIL1. The fourth transistor T4 may be a double-gate transistor. The first initialization voltage line VIL1 may transmit the first initialization voltage VI1.

[0099] The fifth transistor T5 may be turned on by an emission control signal EM of the emission control line EML to electrically connect the driving voltage line VDL to a first node N1, which is the source electrode of the first transistor T1. The fifth transistor T5 may have a gate electrode electrically connected to the emission control line EML, a source electrode electrically connected to the driving voltage line VDL, and a drain electrode electrically connected to the first node N1.

[0100] The sixth transistor T6 is turned on by an emission control signal EM of the emission control line EML to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the fourth node N4, which is the first electrode of the light emitting element LEL. The sixth transistor T6 has a gate electrode electrically connected to the emission control line EML, a source electrode electrically connected to the second node N2, and a drain electrode electrically connected to the fourth node N4.

[0101] When the fifth transistor T5, the first transistor T1 and the sixth transistor T6 are all turned on, a driving current can be supplied to the light emitting element LEL.

[0102] The seventh transistor T7 may be turned on by a fourth gate signal EB of the fourth gate line EBL to electrically connect a fourth node N4, which is a first electrode of the light-emitting element LEL, to a second initialization voltage line VIL2. The seventh transistor T7 may be turned on based on the fourth gate signal EB to discharge the first electrode of the light-emitting element LEL to a second initialization voltage VI2. The gate electrode of the seventh transistor T7 may be electrically connected to the fourth gate line EBL, the source electrode may be electrically connected to the fourth node N4, and the drain electrode may be electrically connected to the second initialization voltage line VIL2. The second initialization voltage line VIL2 may transmit the second initialization voltage VI2.

[0103] The eighth transistor T8 may be turned on by a fourth gate signal EB of the fourth gate line EBL to electrically connect the bias voltage line VBL to a first node N1, which is the source electrode of the first transistor T1. The eighth transistor T8 may be turned on based on the fourth gate signal EB to supply a bias voltage VB to the first node N1. The eighth transistor T8 may improve hysteresis of the first transistor T1 by supplying the bias voltage VB to the source electrode of the first transistor T1. The gate electrode of the eighth transistor T8 may be electrically connected to the fourth gate line EBL, the source electrode may be electrically connected to the bias voltage line VBL, and the drain electrode may be electrically connected to the first node N1.

[0104] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may each include a silicon-based active layer. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may each be a p-type transistor including an active layer made of low-temperature polycrystalline silicon (LTPS). An active layer made of low-temperature polycrystalline silicon has high electron mobility and excellent turn-on characteristics. Therefore, by including transistors with excellent turn-on characteristics, the display device 100 can stably and efficiently drive the plurality of pixels PX. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may each output a current flowing into their source electrode to their drain electrode based on a gate low voltage applied to their gate electrode.

[0105] The third transistor T3 and the fourth transistor T4 may be n-type transistors including an oxide-based active layer. The transistor including the oxide-based active layer may have a coplanar structure with a gate electrode disposed thereon. The transistor including the oxide-based active layer may output a current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0106] The capacitor Cst may be electrically connected between a third node N3, which is the gate electrode of the first transistor T1, and the driving voltage line VDL. For example, a first electrode of the capacitor Cst is electrically connected to the third node N3, and a second electrode of the capacitor Cst is electrically connected to the driving voltage line VDL, thereby maintaining a potential difference between the driving voltage line VDL and the gate electrode of the first transistor T1.

[0107] FIG. 5 is a cross-sectional view showing a display device according to an embodiment.

[0108] 5, the display device 100 may include a substrate SUB, a barrier layer BR, a buffer layer BF, a thin film transistor layer TFTL, a light-emitting element layer EMTL, and an encapsulation layer ENC. The barrier layer BR, the thin film transistor layer TFTL, the light-emitting element layer EMTL, and the encapsulation layer ENC may be sequentially disposed on the substrate SUB along a third direction DR3.

[0109] The substrate SUB can be a rigid substrate or a flexible substrate that allows bending, folding, rolling, etc. The substrate SUB is made of an insulating material such as glass, quartz, or polymer resin. Examples of polymer materials include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terepthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. Alternatively, the substrate SUB may include a metallic material.

[0110] 5, a barrier layer BR may be disposed on the substrate SUB. The barrier layer BR may be disposed on the entire surface of the substrate SUB. The barrier layer BR may be a film for protecting the transistors T1-T8 of the thin film transistor layer TFTL and the light-emitting layer EL of the light-emitting element layer EMTL from moisture that may penetrate through the substrate SUB, which is susceptible to moisture permeation.

[0111] The barrier layer BR is made of a plurality of inorganic layers stacked alternately. For example, the barrier layer BR may be formed of a multilayer structure (e.g., a first barrier layer BR1 and a second barrier layer BR2) in which one or more inorganic layers selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are stacked alternately.

[0112] A first pattern layer may be disposed on the barrier layer BR. For example, a light-shielding layer BML may be disposed on the barrier layer BR. The light-shielding layer BML may be disposed on the barrier layer BR so as to cover an overlapping region (e.g., a first channel region CH1) where the first gate electrode GE1 and the first active layer ACT1 overlap in the third direction DR3, that is, so as to overlap the overlapping region in the third direction DR3. For example, the light-shielding layer BML may be disposed on the barrier layer BR so as to overlap the channel region CH1 of the first transistor T1, which is a drive transistor.

[0113] The light-shielding layer BML is made of a metal material such as chromium (Cr) or molybdenum (Mo), or black ink or black dye. When the light-shielding layer BML is made of a metal material, the light-shielding layer BML can be supplied with a positive power source. This prevents the light-shielding layer BML from being electrically floating, and allows the electrical characteristics of a transistor (e.g., the first transistor T1) on the light-shielding layer BML to be stabilized.

[0114] A buffer layer BF may be disposed on the light-shielding layer BML. The buffer layer BF may be disposed on the entire surface of the substrate SUB including the barrier layer BR. The buffer layer BF may be a film for protecting the transistors T1-T8 of the thin film transistor layer TFTL and the light-emitting layer EL of the light-emitting element layer EMTL from moisture that may penetrate through the substrate SUB, which is susceptible to moisture permeation.

[0115] The buffer layer BF may be formed of a multi-layer structure (e.g., a first buffer layer BF1 and a second buffer layer BF2) in which one or more inorganic layers selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

[0116] A second pattern layer may be disposed on the buffer layer BF. For example, a first active layer ACT1 may be disposed on the barrier layer BR. The first active layer ACT1 may include a first channel region CH1 of the first transistor T1, a second electrode E12 of the first transistor T1, a first electrode E61 of the sixth transistor T6, a second electrode E62 of the sixth transistor T6, and a sixth channel region CH6 of the sixth transistor T6.

[0117] The first active layer ACT1 may be an active layer made of low temperature polycrystalline silicon (LTPS).

[0118] A first gate insulating layer GTI1 may be disposed on the second pattern layer. For example, the first gate insulating layer GTI1 may be disposed on the first active layer ACT1. In this case, the first gate insulating layer GTI1 may be disposed over the entire surface of the substrate SUB including the first active layer ACT1.

[0119] The first gate insulating layer GTI1 may include at least one of tetraethoxysilane (tetraethylorthosilicate, TEOS), silicon nitride (SiNx), and silicon oxide (SiO2). For example, the first gate insulating layer GTI1 may have a double-layer structure in which a silicon nitride layer having a thickness of 40 nm and a tetraethoxysilane layer having a thickness of 80 nm are stacked in order.

[0120] A third pattern layer may be disposed on the first gate insulating layer GTI1. For example, the second gate electrode GE2, the first gate electrode GE1, the eighth gate electrode GE8, the emission control line EML, the fifth gate electrode GE5, and the sixth gate electrode GE6 may be disposed on the first gate insulating layer GTI1.

[0121] 5 shows an example in which the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML are arranged on the first gate insulating layer GTI1. The first gate electrode GE1 can be arranged on the first gate insulating layer GTI1 so as to overlap with the first channel region CH1 of the first active layer ACT1. The sixth gate electrode GE6 of the emission control line EML can be arranged on the first gate insulating layer GTI1 so as to overlap with the sixth channel region CH6 of the first active layer ACT1.

[0122] The third pattern layer includes at least one of molybdenum (Mo), copper (Cu), aluminum, and titanium (Ti) and is formed as a single layer or multiple layers. For example, the first gate electrode GE1 includes a triple layer including a titanium layer, an aluminum layer, and a titanium layer sequentially disposed on the first gate insulating layer GTI1 along the third direction DR3.

[0123] A second gate insulating layer GTI2 may be disposed on the third pattern layer. For example, the second gate insulating layer GTI2 may be disposed on the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML. The second gate insulating layer GTI2 may be disposed over the entire surface of the substrate SUB, including the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML.

[0124] The second gate insulating layer GTI2 may include the same material and structure as the first gate insulating layer GTI1 described above.

[0125] A fourth pattern layer may be disposed on the second gate insulating layer GTI2. For example, a fourth opposing gate electrode GEb4, a third opposing gate electrode GEb3, and a capacitor electrode CPE may be disposed on the second gate insulating layer GTI2. FIG. 5 shows an example in which the capacitor electrode CPE and the third opposing gate electrode GEb3 are disposed on the second gate insulating layer GTI2. The capacitor electrode CPE may be disposed on the second gate insulating layer GTI2 so as to overlap with the first gate electrode GE1. A capacitor Cst may be formed between the capacitor electrode CPE and the first gate electrode GE1.

[0126] The fourth pattern layer can have the same material or structure as the third pattern layer described above.

[0127] A first interlayer insulating layer ITL1 may be disposed on the fourth pattern layer. For example, the first interlayer insulating layer ITL1 may be disposed on the capacitor electrode CPE and the third opposing gate electrode GEb3. In this case, the first interlayer insulating layer ITL1 may be disposed over the entire surface of the substrate SUB including the capacitor electrode CPE and the third opposing gate electrode GEb3.

[0128] The first interlayer insulating layer ITL1 may include an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Note that the first interlayer insulating layer ITL1 may include a plurality of inorganic films.

[0129] A fifth pattern layer may be disposed on the first interlayer insulating layer ITL1. For example, a second active layer ACT2 may be disposed on the first interlayer insulating layer ITL1. The second active layer ACT2 may be disposed on the first interlayer insulating layer ITL1 to overlap with the third opposing gate electrode GEb3. The second active layer ACT2 may include a first electrode E31 of the third transistor T3, a second electrode E32 of the third transistor T3, and a third channel region CH3 of the third transistor T3. The third channel region CH3 of the second active layer ACT2 may overlap with the third opposing gate electrode GEb3.

[0130] The second active layer ACT2 may be an oxide-based active layer, for example, an oxide semiconductor including indium-gallium-zinc-oxide (IGZO) or indium-gallium-zinc-tin-oxide (IGZTO).

[0131] A third gate insulating layer GTI3 may be disposed on the fifth pattern layer. For example, the third gate insulating layer GTI3 may be disposed on the second active layer ACT2. The third gate insulating layer GTI3 may be disposed over the entire surface of the substrate SUB including the second active layer ACT2.

[0132] The third gate insulating layer GTI3 may have the same material and structure as the first gate insulating layer GTI1 described above.

[0133] A sixth pattern layer may be disposed on the third gate insulating layer GTI3. For example, a fourth gate electrode GE4 and a third gate electrode GE3 may be disposed on the third gate insulating layer GTI3.

[0134] 5 shows an example in which the third gate electrode GE3 is arranged on the third gate insulating layer GTI3. The third gate electrode GE3 can be arranged to overlap with the third channel region CH3 of the second active layer ACT2.

[0135] The sixth pattern layer may have the same material or structure as the third pattern layer described above.

[0136] A second interlayer insulating layer ITL2 may be disposed on the sixth pattern layer. For example, the second interlayer insulating layer ITL2 may be disposed on the third gate electrode GE3. The second interlayer insulating layer ITL2 may be disposed over the entire surface of the substrate SUB including the third gate electrode GE3.

[0137] The second interlayer insulating layer ITL2 may have the same material and structure as the first interlayer insulating layer ITL1 described above.

[0138] A seventh pattern layer may be disposed on the second interlayer insulating layer ITL2. For example, the first initialization voltage line VIL1, the third gate line GIL, the data connecting electrode DCE, the first gate line GWL, the second gate line GCL, the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, the capacitor connecting electrode CCE, the lower pixel connecting electrode PCEa, the fourth gate line EBL, and the second initialization voltage line VIL2 may be disposed on the second interlayer insulating layer ITL2.

[0139] 5 illustrates an example in which the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, and the lower pixel connecting electrode PCEa are disposed on the second interlayer insulating layer ITL2. The lower pixel connecting electrode PCEa may be connected to the second electrode E62 of the sixth transistor T6 via a first contact hole CT1 that penetrates the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the second gate insulating layer GTI2, and the first gate insulating layer GTI1. The active connecting electrode ACE may be connected to the second electrode E12 of the first transistor T1 and the first electrode E61 of the sixth transistor T6 via a second contact hole CT2 that penetrates the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the second gate insulating layer GTI2, and the first gate insulating layer GTI1. The active connecting electrode ACE may be connected to the second electrode E32 of the third transistor T3 through a fifth contact hole CT5 that penetrates the second interlayer insulating layer ITL2 and the third gate insulating layer GTI3. The gate connecting electrode GCE may be connected to the first gate electrode GE1 through a third contact hole CT3 that penetrates the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the hole 40 of the capacitor electrode CPE, and the second gate insulating layer GTI2. The gate connecting electrode GCE may be connected to the first electrode E31 of the third transistor T3 through a fourth contact hole CT4 that penetrates the second interlayer insulating layer ITL2 and the third gate insulating layer GTI3.

[0140] The seventh pattern layer may have the same material or structure as the third pattern layer described above.

[0141] A first planarization layer VA1 may be disposed on the seventh pattern layer. For example, the first planarization layer VA1 may be disposed on the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, and the lower pixel connecting electrode PCEa. The first planarization layer VA1 may be disposed over the entire surface of the substrate SUB, including the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, and the lower pixel connecting electrode PCEa.

[0142] The first planarization layer VA1 may include an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0143] An eighth pattern layer may be disposed on the first planarization layer VA1. For example, the first data line DL1, the driving voltage line VDL, and the upper pixel connecting electrode PCEb may be disposed on the first planarization layer VA1. FIG. 5 shows an example in which the driving voltage line VDL and the upper pixel connecting electrode PCEb are disposed on the first planarization layer VA1.

[0144] The upper pixel connecting electrode PCEb may be connected to the lower pixel connecting electrode PCEa through a sixth contact hole CT6 penetrating the first planarization layer VA1.

[0145] The eighth pattern layer may have the same material or structure as the third pattern layer described above.

[0146] A second planarization layer VA2 may be disposed on the eighth pattern layer. For example, the second planarization layer VA2 may be disposed on the driving voltage line VDL and the upper pixel connecting electrode PCEb. The second planarization layer VA2 may be disposed over the entire surface of the substrate SUB, including the driving voltage line VDL and the upper pixel connecting electrode PCEb.

[0147] The second planarization layer VA2 may have the same material and structure as the first planarization layer VA1 described above.

[0148] A ninth pattern layer may be disposed on the second planarization layer VA2. For example, a light emitting element layer EMTL including the ninth pattern layer may be disposed on the second planarization layer VA2. For example, a pixel electrode PE may be disposed as the ninth pattern layer on the second planarization layer VA2. The pixel electrode PE may be connected to the upper pixel connecting electrode PCEb through a seventh contact hole CT7 penetrating the second planarization layer VA2.

[0149] The light emitting element layer EMTL may further include a light emitting element LEL and a bank (or pixel defining layer) in addition to the ninth pattern layer.

[0150] The light-emitting element LEL may include a pixel electrode PE, an emitting layer EL, and a common electrode CM. The emitting area EA refers to the area where the pixel electrode PE, the emitting layer EL, and the common electrode CM are sequentially stacked, and where holes from the pixel electrode PE and electrons from the common electrode CM are combined in the emitting layer to emit light. In this case, the pixel electrode PE may be the anode electrode of the light-emitting element LEL, and the common electrode CM may be the cathode electrode of the light-emitting element LEL.

[0151] In a top emission structure that emits light from the light-emitting layer EL toward the common electrode CM, the pixel electrode PE can be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or to increase reflectivity, it can be formed of a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), APC alloy, or a laminated structure of APC alloy and ITO (ITO / APC / ITO). APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0152] The bank PDL may serve to define the light-emitting area EA of the pixel PX. To this end, the bank PDL may be disposed on the second planarization layer VA2 to expose a portion of the pixel electrode PE. The bank PDL may cover the edge of the pixel electrode PE. The bank PDL may also be disposed in a seventh contact hole CT7 penetrating the second planarization layer VA2. This allows the seventh contact hole CT7 penetrating the second planarization layer VA2 to be filled with the bank PDL. The bank PDL may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0153] A spacer SPC may be disposed on the bank PDL. The spacer SPC can serve to support a mask during the process of manufacturing the light-emitting layer EL. The spacer SPC may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0154] An emitting layer EL may be formed on the pixel electrode PE. The emitting layer EL may include an organic material and emit a predetermined color. For example, the emitting layer EL may include a hole transporting layer, an organic material layer, and an electron transporting layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits a predetermined light, and may be formed using a phosphorescent material or a fluorescent material.

[0155] The light-emitting element LEL is provided for each pixel PX. For example, the first pixel may include a first light-emitting element, the second pixel may include a second light-emitting element, and the third pixel may include a third light-emitting element. The first light-emitting element, the second light-emitting element, and the third light-emitting element may provide light of different colors. For example, the first light-emitting element may emit light of a first color, the second light-emitting element may emit light of a second color, and the third light-emitting element may emit light of a third color.

[0156] For example, the light-emitting layer of the first light-emitting element emitting light of the first color may be a phosphorescent material including a host material including CBP (carbazole biphenyl) or mCP (1,3-bis(carbazol-9-yl)) and a dopant including at least one selected from PIQIr(acac) (bis(1-phenylisoquinoline)acetylacetonate iridium), PQIr(acac) (bis(1-phenylquinoline)acetylacetonate iridium), PQIr (tris(1-phenylquinoline)iridium), and PtOEP (octaethylporphyrin platinum). Alternatively, the light-emitting layer of the first light-emitting element emitting light of the first color may be a fluorescent material including, but not limited to, PBD:Eu(DBM)3(Phen) or Perylene.

[0157] The light-emitting layer of the second light-emitting element emitting light of the second color may be a phosphorescent material containing a host material including CBP or mCP and a dopant material including Ir(ppy)3 (fac tris(2-phenylpyridine)iridium), or may be a fluorescent material containing Alq3 (tris(8-hydroxyquinolino)aluminum), but is not limited thereto.

[0158] The light-emitting layer of the third light-emitting element emitting light of a third color may be a phosphorescent material including a host material including CBP or mCP and a dopant material including (4,6-F2ppy)2Irpic or L2BD111, but is not limited thereto.

[0159] A common electrode CM may be disposed on each light-emitting layer (e.g., EL). The common electrode CM may be disposed so as to cover each light-emitting layer EL. The common electrode CM may be a common layer disposed in common to each pixel PX. A capping layer may also be formed on the common electrode CM.

[0160] In the top emission structure, the common electrode CM can be made of a transparent conductive material (TCO) such as ITO or IZO, which transmits light, or a semi-transmissive metallic material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).When the common electrode CM is made of a semi-transmissive metallic material, the light output efficiency increases due to the microcavities.

[0161] The encapsulation layer ENC may be disposed on the light-emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic film TFE1, TFE3 to prevent oxygen or moisture from penetrating into the light-emitting element layer EMTL. The encapsulation layer ENC may also include at least one organic film TFE2 to protect the light-emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0162] The first sealing inorganic film TFE1 may be disposed on the common electrode CM, the sealing organic film TFE2 may be disposed on the first sealing inorganic film TFE1, and the second sealing inorganic film TFE3 may be disposed on the sealing organic film TFE2. The first sealing inorganic film TFE1 and the second sealing inorganic film TFE3 may be formed of a multi-layer structure in which one or more inorganic films selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked. The sealing organic film TFE2 may be an organic film such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0163] 6 is a plan view showing a non-display area of ​​a display device according to an embodiment, illustrating a portion between a pad area PA where the first and second cluster pads PD1 and PD2 are arranged and a display area DA in FIG.

[0164] Referring to FIG. 6, a first power supply line VDD1, a second power supply line VDD2, a common line VSS, a data routing line DRL, and first and second cluster pads PD1 and PD2 may be arranged in the non-display area NDA.

[0165] The first power supply wiring VDD1 may transmit a driving voltage applied from the circuit board ("200" in FIG. 1) via the second power supply wiring VDD2. The driving voltage of the first power supply wiring VDD1 may be transmitted to a driving voltage line ("VDL" in FIG. 4) in the display area DA. The first power supply wiring VDD1 may extend in a first direction DR1 below the display area DA in a plan view, as shown in FIG. 6.

[0166] The second power supply wiring VDD2 may be arranged between the pad area PA and the first power supply wiring VDD1. The second power supply wiring VDD2 may extend in the second direction DR2 to connect the pad area PA and the first power supply wiring VDD1. A plurality of second power supply wirings VDD2 may be provided. For example, the second power supply wirings VDD2 may be arranged on both sides of the first cluster pad PD1, but are not limited to this. The second power supply wiring VDD2 may transmit a driving voltage applied from the circuit board ("200" in FIG. 1) to the first power supply wiring VDD1.

[0167] The common wiring VSS may be disposed between the pad area PA and the first power wiring VDD1. The common wiring VSS may extend in the second direction DR2 to connect the pad area PA and the display area DA. A plurality of common wirings VSS may be provided. In the example of FIG. 6, for example, two common wirings VSS are disposed on each side of the first cluster pad PD1, but this is not limiting. For example, the two common wirings VSS may be disposed adjacent to each other with the second power wiring VDD2 sandwiched therebetween. The common wiring VSS may transmit a low potential voltage applied from the circuit board to the common voltage line ("VSL" in FIG. 4) of the display area DA.

[0168] The data routing wiring DRL may extend from the display area DA to the pad area PA. The data routing wiring DRL may be connected to the data lines (“DL” in FIG. 4) of the display area DA and extend to the pad area PA. The data routing wiring DRL may transmit data voltages applied from the circuit board (“200” in FIG. 1) to the data lines (“DL” in FIG. 4) of the display area DA.

[0169] 7 is an enlarged plan view of region A in FIG. 6. FIG. 8 is a plan view schematically showing a first routing wiring. FIG. 9 is a plan view schematically showing a second routing wiring. FIG. 10 is a cross-sectional view taken along line Q1-Q1' in FIG. 7. FIG. 11 is an enlarged plan view of region B in FIG. 7. FIG. 12 is a cross-sectional view taken along lines Q2-Q2', Q3-Q3', and Q4-Q4' in FIG. 7.

[0170] FIG. 6 shows the data routing wiring DRL and the first power supply wiring VDD1 in the non-display area NDA.

[0171] 7 to 12 in conjunction with FIG. 6, the data routing line DRL may include a first routing line DRL1 and a second routing line DRL2. Each of the routing lines DRL1 and DRL2 may be connected to a data line ("DL" in FIG. 4) of a corresponding pixel PX to supply a data signal.

[0172] The first routing wires DRL1 may extend from the display area DA and be connected to the first cluster pads PD1. The first routing wires DRL1 may receive data signals from the first circuit board ("CB1" in FIG. 2) via the first cluster pads PD1.

[0173] The second routing wires DRL2 may extend from the display area DA and be connected to the second cluster pads PD2. The second routing wires DRL2 may receive data signals from a second circuit board (CB2 in FIG. 2) via the second cluster pads PD2.

[0174] In one embodiment, the first routing line DRL1 and the second routing line DRL2 have the same width. For example, the width W1 of the first routing line DRL1 and the width W2 of the second routing line DRL2 may be the same. If the width W1 of the first routing line DRL1 and the width W2 of the second routing line DRL2 are the same, the wiring resistances of the first routing line DRL1 and the second routing line DRL2 may be the same, thereby preventing a difference in data signals.

[0175] The first routing wire DRL1 and the second routing wire DRL2 have the same length. For example, the length of the first routing wire DRL1 and the length of the second routing wire DRL2 may be the same. Here, the length refers to the length extending from the boundary between the display area DA and the non-display area NDA to the pad area PA. If the lengths of the first routing wire DRL1 and the second routing wire DRL2 are the same, the wiring resistances of the first routing wire DRL1 and the second routing wire DRL2 can be made the same, thereby preventing differences in data signals.

[0176] According to an embodiment, in order to make the wiring resistances of the first routing wire DRL1 and the second routing wire DRL2 equal, the first routing wire DRL1 and the second routing wire DRL2 may have different shapes. As such shapes, for example, the first routing wire DRL1 and the second routing wire DRL2 may be formed in a detour shape.

[0177] Referring to FIG. 8, the first routing line DRL1 may include a first front portion STP1, a first middle portion MTP1, a first rear portion FTP1, a first connection portion DAP1, and a first extension portion EAP1.

[0178] The first front portion STP1 may be a portion extending from the display area DA to the non-display area NDA. The first front portion STP1 may extend in a second direction DR2 (for example, the second direction DR2 may be the direction from the display area DA toward the pad area PA, or may be the direction perpendicular to the first direction DR1 in which the display area DA and the pad area PA extend along each other). The first front portion STP1 may be arranged in a non-overlapping state (non-overlapping state) with the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view.

[0179] The first connecting portion DAP1 may be a portion bent and extending from the first front portion STP1. The first connecting portion DAP1 may extend in a fourth direction DR4 (e.g., a direction forming an acute angle with the first direction DR1). For example, the fourth direction DR4 intersects with the first direction DR1 at an acute angle on one side and at an obtuse angle on the other side within an angle range of approximately 180° based on the first direction DR1. The sum of the acute angle and the obtuse angle is approximately 180°. Furthermore, the sum of a first acute angle formed by the fourth direction DR4 with respect to the first direction DR1 and a second acute angle formed by the fourth direction DR4 with respect to the second direction DR2 is approximately 90°. For example, the first angle may be smaller than the second angle. For example, the first connecting portion DAP1 may be bent and extend from the first front portion STP1 in the fourth direction DR4. The first coupling portion DAP1 may extend in a direction toward the adjacent second routing wiring DRL2. In other words, the first coupling portion DAP1 may extend toward the second cluster pad PD2 adjacent to the first cluster pad PD1. In particular, in the examples of FIGS. 7 and 8, the first coupling portion DAP1 extends long and bent at a gentle slope from the first pre-stage portion STP1 toward the second cluster pad PD2. Furthermore, at least a portion of the first coupling portion DAP1 may be arranged to overlap the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view. In FIG. 7, most of the first coupling portion DAP1 is arranged to overlap the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view.

[0180] The first middle portion MTP1 may be a portion that is bent and extends from the first connecting portion DAP1. The first middle portion MTP1 may extend in the second direction DR2 (e.g., a direction perpendicular to the first direction DR1). For example, the first middle portion MTP1 may be bent and extend from the first connecting portion DAP1 in the second direction DR2. The first middle portion MTP1 may be disposed in a non-overlapping state (non-overlapping state) with the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view.

[0181] The first extension portion EAP1 may be a portion that is bent and extends from the first middle stage portion MTP1. The first extension portion EAP1 may extend in a fifth direction DR5 (e.g., a direction that forms an obtuse angle with the second direction DR2). For example, the fifth direction DR5 intersects with the second direction DR2 at an obtuse angle on one side and at an acute angle on the other side within an angle range of approximately 180° based on the second direction DR2. The sum of the obtuse angle and the acute angle is approximately 180°. Furthermore, the sum of a third acute angle that the fifth direction DR5 forms with the second direction DR2 and a fourth acute angle that the fifth direction DR5 forms with the first direction DR1 is approximately 90°. For example, the third angle may be larger than the fourth angle. For example, the first extension portion EAP1 may be bent and extend from the first middle stage portion MTP1 in a direction toward the adjacent first circuit board CB1. In other words, the first connecting portion DAP1 may extend from the first front portion STP1 toward the second cluster pad PD2, while the first extension portion EAP1 may extend from the first middle portion MTP1 toward the first cluster pad PD1, which is the side opposite to the first connecting portion DAP1. In particular, in the examples of Figures 7 and 8, the first extension portion EAP1 extends long and bent at a gentle slope from the first middle portion MTP1 toward the first cluster pad PD1. The first extension portion EAP1 may be disposed in a non-overlapping state with the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view.

[0182] The first rear portion FTP1 may be a portion that is bent and extends from the first extension portion EAP1. The first rear portion FTP1 may extend in the second direction DR2 (e.g., a direction perpendicular to the first direction DR1). For example, the first rear portion FTP1 may be bent and extend in the perpendicular direction from the first extension portion EAP1.

[0183] The first routing line DRL1 may include four bending portions SCP1, MCP1, ECP1, and FCP1. For example, the first routing line DRL1 may include a first front bending portion SCP1, a first middle bending portion MCP1, a first extended bending portion ECP1, and a first rear bending portion FCP1.

[0184] The first pre-stage bending portion SCP1 may be disposed between the first pre-stage portion STP1 and the first connecting portion DAP1. The first pre-stage bending portion SCP1 may be disposed in a non-overlapping state with the first power supply wiring VDD1 in the thickness direction in plan view.

[0185] The first middle bending portion MCP1 may be disposed between the first connecting portion DAP1 and the first middle portion MTP1. The first middle bending portion MCP1 may be disposed in a non-overlapping state (non-overlapping state) with the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view. The first power supply wiring VDD1 may be disposed between the first front bending portion SCP1 and the first middle bending portion MCP1 in a plan view.

[0186] The first extension bending portion ECP1 may be disposed between the first middle portion MTP1 and the first extension portion EAP1. The first extension bending portion ECP1 may be disposed farther away from the first power supply line VDD1 than the first middle bending portion MCP1.

[0187] The first subsequent bending portion FCP1 may be disposed between the first extension portion EAP1 and the first subsequent portion FTP1. The first subsequent bending portion FCP1 may be disposed adjacent to the pad area PA. For example, the first subsequent bending portion FCP1 may be disposed farther away from the first power supply line VDD1 than the first extension bending portion ECP1.

[0188] 8, the first routing wire DRL1 has a detour shape toward the adjacent second cluster pad PD2 rather than directly toward the first cluster pad PD1. When the first routing wire DRL1 has a detour shape like this, the lengths of the adjacent first routing wire DRL1 and second routing wire DRL2 can be compensated for and made equal. That is, the first routing wire DRL1 can be formed so that the lengths of the first routing wire DRL1 and the second routing wire DRL2 are approximately equal. Therefore, the wiring resistances between the routing wires DRL1 and DRL2 can be made equal, thereby preventing RC delay.

[0189] Referring to FIG. 9, the second routing line DRL2 may include a second front portion STP2, a second middle portion MTP2, a second rear portion FTP2, a second connecting portion DAP2, and a second extending portion EAP2.

[0190] The second front-end portion STP2 may be a portion extending from the display area DA to the non-display area NDA. The second front-end portion STP2 may extend in the second direction DR2 (e.g., a direction perpendicular to the first direction DR1). The second front-end portion STP2 may be arranged in a non-overlapping state (non-overlapping state) with the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view.

[0191] The second connecting portion DAP2 may be a portion that is bent and extends from the second front portion STP2. The second connecting portion DAP2 may extend in the fourth direction DR4 (e.g., a direction that forms an acute angle with the first direction DR1). For example, the second connecting portion DAP2 may be bent and extend from the second front portion STP2 in the fourth direction DR4. The second connecting portion DAP2 may extend in a direction toward the adjacent second cluster pad PD2. In particular, in the examples of FIGS. 7 and 9, the second connecting portion DAP2 is bent at a gentle slope from the second front portion STP2 toward the second cluster pad PD2 and extends long. At least a portion of the second connecting portion DAP2 may be arranged to overlap the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view. In FIG. 8, a majority of the second connecting portion DAP2 is arranged to overlap the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view. It is preferable that the size (area) of the overlapping region between the first coupling part DAP1 and the first power supply wiring VDD1 is approximately the same as the size (area) of the overlapping region between the second coupling part DAP2 and the first power supply wiring VDD1.

[0192] The second middle portion MTP2 may be a portion that is bent and extends from the second connecting portion DAP2. The second middle portion MTP2 may extend in the second direction DR2 (e.g., a direction perpendicular to the first direction DR1). For example, the second middle portion MTP2 may be bent and extend from the second connecting portion DAP2 in the second direction DR2. The second middle portion MTP2 may be disposed in a non-overlapping state with the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view.

[0193] The second extension portion EAP2 may be a portion that is bent and extends from the second middle portion MTP2. The second extension portion EAP2 may extend in the fourth direction DR4. For example, the second extension portion EAP2 may be bent and extend from the second middle portion MTP2 toward the adjacent second cluster pad PD2. The second extension portion EAP2 may be arranged in a non-overlapping state (non-overlapping state) with the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view.

[0194] The second rear portion FTP2 may be a portion that is bent and extends from the second extension portion EAP2. The second rear portion FTP2 may extend in the second direction DR2 (e.g., a direction perpendicular to the first direction DR1). For example, the second rear portion FTP2 may be bent and extend in the perpendicular direction from the second extension portion EAP2.

[0195] The second routing wire DRL2 may include four bending portions SCP2, MCP2, ECP2, and FCP2. For example, the second routing wire DRL2 may include a second front bending portion SCP2, a second middle bending portion MCP2, a second extension bending portion ECP2, and a second rear bending portion FCP2.

[0196] The second front-stage bending portion SCP2 may be disposed between the second front-stage portion STP2 and the second connecting portion DAP2. The second front-stage bending portion SCP2 may be disposed in a non-overlapping state (non-overlapping state) with the first power supply wiring VDD1 in the thickness direction in plan view.

[0197] The second middle bending portion MCP2 may be disposed between the second connecting portion DAP2 and the second middle portion MTP2. The second middle bending portion MCP2 may be disposed in a non-overlapping state (non-overlapping state) with the first power supply wiring VDD1 in the thickness direction (third direction DR3) in a plan view. The first power supply wiring VDD1 may be disposed between the second front bending portion SCP2 and the second middle bending portion MCP2 in a plan view.

[0198] The second extension bending portion ECP2 may be disposed between the second middle portion MTP2 and the second extension portion EAP2. The second extension bending portion ECP2 may be disposed farther away from the first power supply line VDD1 than the second middle bending portion MCP2.

[0199] The second rear bending portion FCP2 may be disposed between the second extension portion EAP2 and the second rear portion FTP2. The second rear bending portion FCP2 may be disposed adjacent to the pad area PA. For example, the second rear bending portion FCP2 may be disposed farther away from the first power supply wiring VDD1 than the second extension bending portion ECP2.

[0200] The second routing wire DRL2 has a detour shape including a bent portion rather than extending directly to the second cluster pad PD2. When the second routing wire DRL2 has a detour shape, the lengths of the adjacent first routing wire DRL1 and second routing wire DRL2 can be compensated for and made equal. That is, the second routing wire DRL2 can be formed so that the lengths of the first routing wire DRL1 and the second routing wire DRL2 are approximately equal. Therefore, the wiring resistances between the routing wires DRL1 and DRL2 can be made equal, thereby preventing RC delay.

[0201] 6 to 9, the first front stage portion STP1 of the first routing wiring DRL1 may be arranged side by side (so as to be substantially parallel) with the second front stage portion STP2 of the second routing wiring DRL2. The first connecting portion DAP1 of the first routing wiring DRL1 may be arranged side by side (so as to be substantially parallel) with the second connecting portion DAP2 of the second routing wiring DRL2. The first middle stage portion MTP1 of the first routing wiring DRL1 may be arranged side by side (so as to be substantially parallel) with the second middle stage portion MTP2 of the second routing wiring DRL2. The first rear stage portion FTP1 of the first routing wiring DRL1 may be arranged side by side (so as to be substantially parallel) with the second rear stage portion FTP2 of the second routing wiring DRL2.

[0202] The first extension portion EAP1 of the first routing wire DRL1 may extend in a different direction from the second extension portion EAP2 of the second routing wire DRL2. For example, the first extension portion EAP1 of the first routing wire DRL1 may extend in a fifth direction DR5. That is, the first extension portion EAP1 extends in the fifth direction DR5 toward the first cluster pad PD1. Meanwhile, the second extension portion EAP2 of the second routing wire DRL2 may extend in a fourth direction DR4. That is, the second extension portion EAP2 extends in the fourth direction DR4 toward the second cluster pad PD2.

[0203] 7, the first middle portion MTP1 of the first routing wire DRL1 and the second middle portion MTP2 of the second routing wire DRL2, which are adjacent to each other among the first routing wire DRL1 and the second routing wire DRL2, may be disposed in a region (e.g., a region indicated as "MPA") between the first cluster pad PD1 and the second cluster pad PD2. Here, the region MPA between the first cluster pad PD1 and the second cluster pad PD2 may be between the pads disposed on the first cluster pad PD1 that are adjacent to the second cluster pad PD2 and the pads disposed on the second cluster pad PD2 that are adjacent to the first cluster pad PD1. For example, the first middle portion MTP1 of the first routing wire DRL1 and the second middle portion MTP2 of the second routing wire DRL2 may be disposed in the region MPA between the first cluster pad PD1 and the second cluster pad PD2. For example, the first middle portion MTP1 of the first routing line DRL1 and the second middle portion MTP2 of the second routing line DRL2 can overlap the area MPA between the first cluster pad PD1 and the second cluster pad PD2 in a plan view when viewed in the second direction DR2.

[0204] Furthermore, the first middle bend portion MCP1 of the first routing wire DRL1 and the second middle bend portion MCP2 of the second routing wire DRL2 may be disposed in the region MPA between the first cluster pad PD1 and the second cluster pad PD2. For example, the first middle bend portion MCP1 of the first routing wire DRL1 and the second middle bend portion MCP2 of the second routing wire DRL2 may overlap in the second direction DR2 with the region MPA between the first cluster pad PD1 and the second cluster pad PD2 in a plan view. Furthermore, the first extended bend portion ECP1 of the first routing wire DRL1 and the second extended bend portion ECP2 of the second routing wire DRL2 may be disposed in the region MPA between the first cluster pad PD1 and the second cluster pad PD2. For example, the first extended bent portion ECP1 of the first routing wire DRL1 and the second extended bent portion ECP2 of the second routing wire DRL2 can overlap in the second direction DR2 with the region MPA between the first cluster pad PD1 and the second cluster pad PD2 in a plan view.

[0205] In the first routing wire DRL1 and the second routing wire DRL2 that are adjacent to each other, the first pre-stage bending portion SCP1 and the first post-stage bending portion FCP1 of the first routing wire DRL1 may be arranged to overlap the first cluster pad PD1 in the second direction DR2 in plan view. Also, the second pre-stage bending portion SCP2 of the second routing wire DRL2 may be arranged to overlap the first cluster pad PD1 in the second direction DR2 in plan view.

[0206] Referring to FIG. 10, the first routing wires DRL1 and the second routing wires DRL2 may be alternately arranged on different layers.

[0207] The first routing wiring DRL1 may include a first-first routing wiring DRL1-1 and a first-second routing wiring DRL1-2, and the second routing wiring DRL2 may include a second-first routing wiring DRL2-1 and a second-second routing wiring DRL2-2.

[0208] Specifically, a barrier layer BR, a buffer layer BF, and a thin film transistor layer TFTL may be sequentially disposed on a substrate SUB in the third direction DR3. For example, a first barrier layer BR1, a second barrier layer BR2, a first buffer layer BF1, a second buffer layer BF2, and a first gate insulating layer GTI1 may be disposed on the substrate SUB.

[0209] A first-1 routing line DRL1-1 and a second-1 routing line DRL2-1 may be disposed on the first gate insulating layer GTI1. A second gate insulating layer GTI2 may be disposed on the first-1 routing line DRL1-1 and the second-1 routing line DRL2-1. A first-2 routing line DRL1-2 and a second-2 routing line DRL2-2 may be disposed on the second gate insulating layer GTI2.

[0210] A first interlayer insulating layer ITL1, a third gate insulating layer GTI3, and a second interlayer insulating layer ITL2 may be disposed on the first-2 routing wiring DRL1-2 and the second-2 routing wiring DRL2-2. A first power supply wiring VDD1 may be disposed on the second interlayer insulating layer ITL2. A first planarization layer VA1 and a second planarization layer VA2 may be sequentially disposed on the first power supply wiring VDD1.

[0211] The 1-1 routing wiring DRL1-1 and the 1-2 routing wiring DRL1 of the first routing wiring DRL1 may be arranged on different layers. The 1-1 routing wiring DRL1-1 may be arranged on the first gate insulating layer GTI1 and sandwiched between the first gate insulating layer GTI1 and the second gate insulating layer GTI2. The 1-2 routing wiring DRL1-2 may be arranged on the second gate insulating layer GTI2 and sandwiched between the second gate insulating layer GTI2 and the first interlayer insulating layer ITL1. The 1-1 routing wiring DRL1-1 and the 1-2 routing wiring DRL1-2 may be arranged alternately and repeatedly with the second gate insulating layer GTI2 interposed therebetween.

[0212] The 2-1 routing wiring DRL2-1 and the 2-2 routing wiring DRL2 of the second routing wiring DRL2 may be arranged on different layers. The 2-1 routing wiring DRL2-1 may be arranged on the first gate insulating layer GTI1 and sandwiched between the first gate insulating layer GTI1 and the second gate insulating layer GTI2. The 2-2 routing wiring DRL2-2 may be arranged on the second gate insulating layer GTI2 and sandwiched between the second gate insulating layer GTI2 and the first interlayer insulating layer ITL1. The 2-1 routing wiring DRL2-1 and the 2-2 routing wiring DRL2-2 may be arranged alternately and repeatedly with the second gate insulating layer GTI2 interposed therebetween.

[0213] The first routing wiring DRL1 and the second routing wiring DRL2 may be arranged alternately in different layers. For example, in a plan view, the first direction DR1 may be arranged alternately in the following order: a 1-1 routing wiring DRL1-1 arranged on the first gate insulating layer GTI1, a 1-2 routing wiring DRL1-2 arranged on the second gate insulating layer GTI2, a 2-1 routing wiring DRL2-1 arranged on the first gate insulating layer GTI1, and a 2-2 routing wiring DRL2-2 arranged on the second gate insulating layer GTI2.

[0214] 10 and 11, the first routing wire DRL1 and the second routing wire DRL2 may be arranged to overlap the first power supply wire VDD1 in the third direction DR3 (e.g., the thickness direction). As described above, the first routing wire DRL1 and the second routing wire DRL2 may have the same width and length. The overlapping area between the first routing wire DRL1 and the first power supply wire VDD1 and the overlapping area between the second routing wire DRL2 and the first power supply wire VDD1 may be the same. If the overlapping areas between the first and second routing wires DRL1 and DRL2 and the first power supply wire VDD1 are different from each other, a difference in capacitance values ​​generated therebetween may occur, which may induce an RC delay.

[0215] In this embodiment, by forming the first routing wire DRL1 and the second routing wire DRL2 to have the same width and length, the capacitance values ​​formed between the first and second routing wires DRL1 and DRL2 and the first power supply wire VDD1 (or other wires) can be made the same, thereby improving the RC delay. Furthermore, by forming the first and second routing wires DRL1 and DRL2 to have the same length and width, it is possible to suppress differences in RC delay due to differences in length and differences in RC delay due to differences in width.

[0216] At least in a region where the first routing wire DRL1 and the second routing wire DRL2 overlap with the first power supply wire VDD1, the spacing (or pitch) between the routing wires DRL1 and DRL2 may be the same. For example, the spacing PH1 between the 1-1 routing wire DRL1-1 and the 1-2 routing wire DRL1-2, the spacing PH2 between the 1-2 routing wire DRL1-2 and the 2-1 routing wire DRL2-1, and the spacing PH3 between the 2-1 routing wire DRL2-1 and the 2-2 routing wire DRL2-2 may be the same.

[0217] The intervals between the plurality of first routing wires DRL1, the intervals between the first routing wires DRL1 and the second routing wires DRL2, and the intervals between the plurality of second routing wires DRL2 may be different from one another in each region.

[0218] 7, 8, and 12, the spacing between the first routing wire DRL1, for example, the 1-1 routing wire DRL1-1 and the 1-2 routing wire DRL1-2, may vary depending on the region. A spacing PH1 between the first front stage STP1 of the 1-1 routing wire DRL1-1 and the first front stage STP1 of the 1-2 routing wire DRL1-2, a spacing PH2 between the first middle stage MTP1 of the 1-1 routing wire DRL1-1 and the first middle stage MTP1 of the 1-2 routing wire DRL1-2, and a spacing PH3 between the first rear stage FTP1 of the 1-1 routing wire DRL1-1 and the first rear stage FTP1 of the 1-2 routing wire DRL1-2 may vary.

[0219] In one embodiment, a distance PH1 between the first front stage portion STP1 of the 1-1 routing wiring DRL1-1 and the first front stage portion STP1 of the 1-2 routing wiring DRL1-2 may be larger than a distance PH2 between the first middle stage portion MTP1 of the 1-1 routing wiring DRL1-1 and the first middle stage portion MTP1 of the 1-2 routing wiring DRL1-2 and a distance PH3 between the first rear stage portion FTP1 of the 1-1 routing wiring DRL1-1 and the first rear stage portion FTP1 of the 1-2 routing wiring DRL1-2. The distance PH2 between the first middle stage portion MTP1 of the 1-1 routing wiring DRL1-1 and the first middle stage portion MTP1 of the 1-2 routing wiring DRL1-2 may be larger than a distance PH3 between the first rear stage portion FTP1 of the 1-1 routing wiring DRL1-1 and the first rear stage portion FTP1 of the 1-2 routing wiring DRL1-2. That is, the distance PH1 between the first front stage STP1 of the 1-1 routing wiring DRL1-1 and the first front stage STP1 of the 1-2 routing wiring DRL1-2 may be the largest, and the distance PH3 between the first back stage FTP1 of the 1-1 routing wiring DRL1-1 and the first back stage FTP1 of the 1-2 routing wiring DRL1-2 may be the smallest.

[0220] However, without being limited to this, the distance PH1 between the first front stage STP1 of the 1-1 routing wiring DRL1-1 and the first front stage STP1 of the 1-2 routing wiring DRL1-2, the distance PH2 between the first middle stage MTP1 of the 1-1 routing wiring DRL1-1 and the first middle stage MTP1 of the 1-2 routing wiring DRL1-2, and the distance PH3 between the first back stage FTP1 of the 1-1 routing wiring DRL1-1 and the first back stage FTP1 of the 1-2 routing wiring DRL1-2 may be the same as each other. Furthermore, without being limited thereto, the distance PH1 between the first front stage portion STP1 of the 1-1 routing wiring DRL1-1 and the first front stage portion STP1 of the 1-2 routing wiring DRL1-2 may be larger than the distance PH2 between the first middle stage portion MTP1 of the 1-1 routing wiring DRL1-1 and the first middle stage portion MTP1 of the 1-2 routing wiring DRL1-2 and the distance PH3 between the first back stage portion FTP1 of the 1-1 routing wiring DRL1-1 and the first back stage portion FTP1 of the 1-2 routing wiring DRL1-2, and the distance PH2 between the first middle stage portion MTP1 of the 1-1 routing wiring DRL1-1 and the first middle stage portion MTP1 of the 1-2 routing wiring DRL1-2 and the distance PH3 between the first back stage portion FTP1 of the 1-1 routing wiring DRL1-1 and the first back stage portion FTP1 of the 1-2 routing wiring DRL1-2 may be the same as each other.

[0221] Furthermore, the intervals between the adjacent first routing wiring DRL1 and second routing wiring DRL2 may also be different from each other. Specifically, the 1-2 routing wiring DRL1-2 of the first routing wiring DRL1 and the 2-1 routing wiring DRL2-1 of the second routing wiring DRL2 may be disposed adjacent to each other. A interval PH4 between the first front stage portion STP1 of the 1-2 routing wiring DRL1-2 and the second front stage portion STP2 of the 2-1 routing wiring DRL2-1, a interval PH5 between the first middle stage portion MTP1 of the 1-2 routing wiring DRL1-2 and the second middle stage portion MTP2 of the 2-1 routing wiring DRL2-1, and a interval PH6 between the first rear stage portion FTP1 of the 1-2 routing wiring DRL1-2 and the second rear stage portion FTP2 of the 2-1 routing wiring DRL2-1 may be different from each other.

[0222] In one embodiment, a distance PH4 between the first front stage portion STP1 of the 1-2 routing wiring DRL1-2 and the second front stage portion STP2 of the 2-1 routing wiring DRL2-1 may be larger than a distance PH5 between the first middle stage portion MTP1 of the 1-2 routing wiring DRL1-2 and the second middle stage portion MTP2 of the 2-1 routing wiring DRL2-1 and may be smaller than a distance PH6 between the first rear stage portion FTP1 of the 1-2 routing wiring DRL1-2 and the second rear stage portion FTP2 of the 2-1 routing wiring DRL2-1. The distance PH5 between the first middle stage portion MTP1 of the 1-2 routing wiring DRL1-2 and the second middle stage portion MTP2 of the 2-1 routing wiring DRL2-1 may be smaller than the distance PH6 between the first rear stage portion FTP1 of the 1-2 routing wiring DRL1-2 and the second rear stage portion FTP2 of the 2-1 routing wiring DRL2-1. That is, the spacing PH6 between the first rear stage portion FTP1 of the 1-2 routing wiring DRL1-2 and the second rear stage portion FTP2 of the 2-1 routing wiring DRL2-1 may be the largest, and the spacing PH5 between the first middle stage portion MTP1 of the 1-2 routing wiring DRL1-2 and the second middle stage portion MTP2 of the 2-1 routing wiring DRL2-1 may be the smallest.

[0223] However, without being limited to this, the distance PH4 between the first front stage STP1 of the 1-2 routing wiring DRL1-2 and the second front stage STP2 of the 2-1 routing wiring DRL2-1 may be the same as the distance PH5 between the first middle stage MTP1 of the 1-2 routing wiring DRL1-2 and the second middle stage MTP2 of the 2-1 routing wiring DRL2-1.

[0224] Furthermore, the spacing of the second routing wiring DRL2, for example, between the 2-1 routing wiring DRL2-1 and the 2-2 routing wiring DRL2-2, may vary depending on the region. A spacing PH7 between the second front stage portion STP2 of the 2-1 routing wiring DRL2-1 and the second front stage portion STP2 of the 2-2 routing wiring DRL2-2, a spacing PH8 between the second middle stage portion MTP2 of the 2-1 routing wiring DRL2-1 and the second middle stage portion MTP2 of the 2-2 routing wiring DRL2-2, and a spacing PH9 between the second rear stage portion FTP2 of the 2-1 routing wiring DRL2-1 and the second rear stage portion FTP2 of the 2-2 routing wiring DRL2-2 may vary from region to region.

[0225] In one embodiment, a distance PH7 between the second front stage portion STP2 of the 2-1 routing wiring DRL2-1 and the second front stage portion STP2 of the 2-2 routing wiring DRL2-2 may be larger than a distance PH8 between the second middle stage portion MTP2 of the 2-1 routing wiring DRL2-1 and the second middle stage portion MTP2 of the 2-2 routing wiring DRL2-2 and a distance PH9 between the second rear stage portion FTP2 of the 2-1 routing wiring DRL2-1 and the second rear stage portion FTP2 of the 2-2 routing wiring DRL2-2. The distance PH8 between the second middle stage portion MTP2 of the 2-1 routing wiring DRL2-1 and the second middle stage portion MTP2 of the 2-2 routing wiring DRL2-2 may be larger than a distance PH9 between the second rear stage portion FTP2 of the 2-1 routing wiring DRL2-1 and the second rear stage portion FTP2 of the 2-2 routing wiring DRL2-2. That is, the distance PH7 between the second front stage STP2 of the 2-1 routing wiring DRL2-1 and the second front stage STP2 of the 2-2 routing wiring DRL2-2 may be the largest, and the distance PH9 between the second back stage FTP2 of the 2-1 routing wiring DRL2-1 and the second back stage FTP2 of the 2-2 routing wiring DRL2-2 may be the smallest.

[0226] However, without being limited to this, the distance PH7 between the second front stage portion STP2 of the 2-1 routing wiring DRL2-1 and the second front stage portion STP2 of the 2-2 routing wiring DRL2-2, the distance PH8 between the second middle stage portion MTP2 of the 2-1 routing wiring DRL2-1 and the second middle stage portion MTP2 of the 2-2 routing wiring DRL2-2, and the distance PH9 between the second back stage portion FTP2 of the 2-1 routing wiring DRL2-1 and the second back stage portion FTP2 of the 2-2 routing wiring DRL2-2 may be the same as each other. Furthermore, without being limited thereto, the distance PH7 between the second front stage portion STP2 of the 2-1 routing wiring DRL2-1 and the second front stage portion STP2 of the 2-2 routing wiring DRL2-2 may be larger than the distance PH8 between the second middle stage portion MTP2 of the 2-1 routing wiring DRL2-1 and the second middle stage portion MTP2 of the 2-2 routing wiring DRL2-2 and the distance PH9 between the second back stage portion FTP2 of the 2-1 routing wiring DRL2-1 and the second back stage portion FTP2 of the 2-2 routing wiring DRL2-2, and the distance PH8 between the second middle stage portion MTP2 of the 2-1 routing wiring DRL2-1 and the second middle stage portion MTP2 of the 2-2 routing wiring DRL2-2 and the distance PH9 between the second back stage portion FTP2 of the 2-1 routing wiring DRL2-1 and the second back stage portion FTP2 of the 2-2 routing wiring DRL2-2 may be the same as each other.

[0227] As long as the wiring resistance between the routing wires can be made uniform, various intervals can be set for the first routing wire DRL1 and the second routing wire DRL2 as described above.

[0228] As described above, in a display device according to an embodiment, the wiring resistance between the routing lines can be made uniform by adjusting the extension shape of the routing lines to make the width and length of the routing lines uniform, thereby preventing (or suppressing) RC delay, i.e., preventing (or suppressing) RC delay differences, thereby improving the brightness difference of the display device and improving display quality.

[0229] In this embodiment, particularly in a specific region where multiple routing wirings DRL gather between adjacent cluster pads (a region indicated as "MPA" in the example of FIG. 7, for example, a region corresponding to the region between the cluster pads), the lengths and widths of the multiple routing wirings DRL arranged to the left of the specific region in the first direction DR1 are made approximately the same as the lengths and widths of the multiple routing wirings DRL arranged to the right of the specific region. In this embodiment, the lengths of the multiple routing wirings DRL are made approximately the same by adjusting the length of each routing wiring DRL by making each routing wiring DRL meander. This makes the wiring resistances of the routing wirings DRL adjacent to the left and right and arranged including the specific region between adjacent cluster pads approximately the same. Therefore, degradation of display quality can be suppressed. Here, as in this embodiment, data signals from the left and right routing wirings DRL arranged including the specific region between adjacent cluster pads are transmitted to adjacent data wirings in the display area DA. By making the wiring resistances of the adjacent routing wirings DRL approximately the same as in this embodiment, data signals having approximately the same wiring delay, etc. can be transmitted to adjacent data wirings in the display area DA via the routing wiring DRL. Therefore, differences in display quality between adjacent pixels can be suppressed.

[0230] Furthermore, as described above, the first alignment keys AK1 are arranged between adjacent circuit boards CB. The area where the first alignment keys AK1 are arranged corresponds to the specific area between the cluster pads described above, and the above configuration makes it possible to effectively utilize such specific area between the circuit boards when adjusting the length of the routing wiring DRL. Furthermore, by forming the routing wiring DRL with the adjusted length, it is possible to suppress the difference in resistance between the left and right routing wiring DRL arranged including the specific area.

[0231] In this embodiment, the routing wiring DRL includes five parts, namely, a front part STP, a middle part MTP, a rear part FTP, a connecting part DAP, and an extension part EAP, and four bending parts SCP, MCP, ECP, and FCP. However, as long as the lengths and widths of the plurality of routing wirings DRL, particularly the adjacent plurality of routing wirings DRL, can be formed to be approximately the same, the number of parts and the number of bending parts included in the routing wiring DRL are not limited.

[0232] In the above, the configuration of this embodiment for suppressing resistance differences is applied to multiple routing wirings DRL arranged including a specific region between adjacent cluster pads, but the configuration of this embodiment can also be applied to routing wirings DRL adjacent to each other outside the specific region.

[0233] In the above-described embodiment, each of the first routing wire DRL1 and the second routing wire DRL2 includes a plurality of routing wires. However, as long as the difference in resistance between the routing wires on the left and right sides of the specific region can be suppressed as described above, each of the first routing wire DRL1 and the second routing wire DRL2 may include only one routing wire or may include three or more routing wires.

[0234] The display device according to the embodiment may be applied to various electronic devices. The electronic device according to the embodiment may include the display device described above, and may further include a module or device having additional functions other than the display device.

[0235] FIG. 13 is a block diagram of an electronic device according to one embodiment.

[0236] Referring to FIG. 13, an electronic device 1 according to one embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0237] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0238] The memory 15 stores data information necessary for the operation of the processor 12 and the display module 11. When the processor 12 executes an application stored in the memory 15, video data signals and / or input control signals are transmitted to the display module 11, and the display module 11 processes the provided signals and can output video information via a display screen.

[0239] The power supply module 14 may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for operation of the electronic device 1.

[0240] At least one of the components of the electronic device 1 described above may be included in the display device according to the above-described embodiment. Furthermore, some of the individual modules functionally included in one module may be included in the display device, while other modules may be provided separately from the display device. For example, the display device may include the display module 11, and the processor 12, memory 13, and power supply module 14 may be provided as other devices within the electronic device 1 rather than as part of the display device.

[0241] FIG. 14 is a schematic diagram of an electronic device according to various embodiments.

[0242] Referring to FIG. 14, various electronic devices to which the display device according to the embodiment is applied include not only electronic devices for displaying images such as a smartphone 10_1a, a tablet PC 10_1b, a laptop 10_1c, a TV 10_1d, and a desk monitor 10_1e, but also wearable electronic devices including a display module such as smart glasses 10_2a, a head-mounted display 10_2b, and a smart watch 10_2c, and vehicular electronic devices 10_3 including a display module such as a CID (Center Information Display) arranged on the dashboard, center fascia, or dashboard of a car, and a room mirror display.

[0243] Although the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above-described embodiment is illustrative in all respects and is not limiting. [Explanation of symbols]

[0244] 10 Display device DA display area NDA Hidden Area SUB board PA Pad Area PD1,2 1st and 2nd cluster pads DRL1,2 First and second data routing lines DRL1-1,1-2 1-1 and 1-2 routing wiring DRL2-1,2-2 2-1 and 2-2 routing wiring STP1,2 1st and 2nd front stages MTP1,2 1st and 2nd middle stages FTP1,2 1st and 2nd post-stages DAP1,2 First and second connection parts EAP1,2 First and second extensions SCP1,2 First and second pre-bending sections MCP1,2 1st and 2nd middle folding sections ECP1,2 First and second extension bends FCP1,2 First and second post-folding sections

Claims

1. a substrate including a display area and a non-display area; a pad area disposed in a non-display area of ​​the substrate; a first cluster pad and a second cluster pad disposed in the pad region; and a routing wiring disposed on the substrate and electrically connected from the display area to the first cluster pads and the second cluster pads; the routing wiring includes a first routing wiring extending to the first cluster pad and a second routing wiring extending to the second cluster pad; the first routing wiring and the second routing wiring are disposed adjacent to each other; the first routing wiring includes a first middle stage portion extending in a second direction intersecting a first direction that is a horizontal direction, and the second routing wiring includes a second middle stage portion adjacent to and aligned with the first middle stage portion; The display device, wherein the first middle section and the second middle section are disposed between the first cluster pad and the second cluster pad.

2. the first routing wiring includes a first front portion extending from the display area, a first connecting portion bent and extending from the first front portion, a first extending portion bent and extending from the first middle portion, and a first rear portion bent from the first extending portion and extending to the first cluster pad; The display device according to claim 1 , wherein the first middle section is bent and extends from the first connecting section.

3. The display device according to claim 2 , wherein the first front section, the first middle section, and the first rear section extend in a second direction and are aligned with one another.

4. The display device according to claim 2 , further comprising: a power supply wiring disposed on the non-display area, extending in the first direction, and overlapping with the routing wiring.

5. The display device according to claim 4 , wherein the first front portion and the first middle portion do not overlap with the power supply wiring, and the first extension portion overlaps with the power supply wiring.

6. the second routing wiring includes a second front portion extending from the display area, a second connecting portion bent and extending from the second front portion, a second extending portion bent and extending from the second middle portion, and a second rear portion bent from the second extending portion and extending to the second cluster pad; The display device according to claim 2 , wherein the second middle section is bent and extends from the second connecting section.

7. the second front section, the second middle section, and the second rear section extend in a second direction and are aligned with one another, The display device according to claim 6 , wherein the first front section and the second front section, the first middle section and the second middle section, and the first rear section and the second rear section are aligned with each other.

8. a power supply wiring disposed on the non-display area, extending in the first direction, and overlapping with the routing wiring; The display device according to claim 6 , wherein the second front portion and the second middle portion do not overlap with the power supply wiring, and the second extension portion overlaps with the power supply wiring.

9. 7. The display device of claim 6, wherein the first routing wiring includes a first front bend disposed between the first front portion and the first connecting portion, a first middle bend disposed between the first connecting portion and the first middle portion, a first extended bend disposed between the first middle portion and the first extended portion, and a first rear bend disposed between the first extended portion and the first rear portion.

10. 7. The display device of claim 6, wherein the second routing wiring includes a second front bend disposed between the second front portion and the second connecting portion, a second middle bend disposed between the second connecting portion and the second middle portion, a second extended bend disposed between the second middle portion and the second extended portion, and a second rear bend disposed between the second extended portion and the second rear portion.

11. 7. The display device of claim 6, wherein the distance between the first front section and the second front section is greater than the distance between the first middle section and the second middle section, and the distance between the first rear section and the second rear section is greater than the distance between the first front section and the second front section.

12. 3. The display device of claim 2, wherein the first routing wiring includes other adjacent first routing wiring, and the spacing between the first front stages of the adjacent first routing wiring is greater than the spacing between the first middle stages, and the spacing between the first middle stages is greater than the spacing between the first rear stages.

13. 7. The display device of claim 6, wherein the second routing wiring includes other adjacent second routing wiring, and the spacing between the second front stages of the adjacent second routing wiring is greater than the spacing between the second middle stages, and the spacing between the second middle stages is greater than the spacing between the second rear stages.

14. The display device according to claim 1 , wherein the width and length of the routing wires are the same.

15. Display panel; a plurality of pixels arranged in a display area of ​​the display panel; a pad area disposed in a non-display area of ​​the display panel, the pad area including first cluster pads and second cluster pads; data routing wiring extending from the display area to the pad area; and power supply wiring disposed in the non-display area and intersecting the data routing wiring; the data routing wiring includes a first data routing wiring extending to the first cluster pad and a second data routing wiring extending to the second cluster pad; The display device, wherein the first data routing wiring and the second data routing wiring each include a plurality of bent portions in a plan view.

16. the first data routing wiring includes a first front section extending from the display area, a first connecting section bent and extending from the first front section, a first middle section bent and extending from the first connecting section, a first extending section bent and extending from the first middle section, and a first rear section bent and extending from the first extending section to the first cluster pad; 16. The display device of claim 15, wherein the second data routing wiring includes a second front section extending from the display area, a second connecting section bent and extending from the second front section, a second middle section bent and extending from the second connecting section, a second extension section bent and extending from the second middle section, and a second rear section bent from the second extension section to extend to the second cluster pad.

17. the first data routing wiring includes a first front bent portion disposed between the first front portion and the first connecting portion, a first middle bent portion disposed between the first connecting portion and the first middle portion, a first extended bent portion disposed between the first middle portion and the first extended portion, and a first rear bent portion disposed between the first extended portion and the first rear portion; 17. The display device of claim 16, wherein the second data routing wiring includes a second front bend disposed between the second front portion and the second connecting portion, a second middle bend disposed between the second connecting portion and the second middle portion, a second extended bend disposed between the second middle portion and the second extended portion, and a second rear bend disposed between the second extended portion and the second rear portion.

18. In the first data routing wiring and the second data routing wiring that are arranged adjacent to each other, 18. The display device of claim 17, wherein the first front bend and the first rear bend of the first data routing wiring overlap with the first cluster pad in a second direction intersecting a first direction that is a horizontal direction in a plan view.

19. 19. The display device of claim 18, wherein the first middle bend and the first extended bend of the first data routing wiring and the second middle bend and the second extended bend of the second data routing wiring overlap between the first cluster pad and the second cluster pad in the second direction in a planar view.

20. The display device of claim 15 , wherein the first data routing wiring and the second data routing wiring have the same width and length.

21. a substrate including a non-display area including a pad area, and a display area; a first cluster pad and a second cluster pad disposed on the pad region of the substrate; a first data routing trace disposed on a non-display area of ​​the substrate and extending from the display area to the first cluster pad; a second data routing trace disposed on a non-display area of ​​the substrate and extending from the display area to the second cluster pad; a first insulating layer disposed on a non-display area of ​​the substrate; the first data routing wiring includes a first-1 routing wiring disposed under the first insulating layer and a first-2 routing wiring disposed over the first insulating layer; the second data routing wiring includes a second-first routing wiring disposed under the first insulating layer and a second-second routing wiring disposed over the first insulating layer; The display device, wherein the first-second routing wiring and the second-first routing wiring are adjacent to each other and each include a plurality of bent portions in a plan view.

22. The display device of claim 21, wherein the first-1 routing wiring and the first-2 routing wiring are arranged alternately and repeatedly with the first insulating layer therebetween, and the second-1 routing wiring and the second-2 routing wiring are arranged alternately and repeatedly with the first insulating layer therebetween.

23. further including a voltage wiring disposed on the first-second routing wiring and the second-first routing wiring; 22. The display device of claim 21, wherein the first data routing wiring and the second data routing wiring overlap the voltage wiring.

24. 22. The display device of claim 21, wherein the first data routing line and the second data routing line have the same width and length.

25. a display device that provides the image; a processor for providing a video data signal to said display device; a memory for storing data information for driving; and a power supply module for generating power; The display device includes: a substrate including a display area and a non-display area; a pad area disposed in a non-display area of ​​the substrate; a first cluster pad and a second cluster pad disposed in the pad region; and a routing wiring disposed on the substrate and electrically connected from the display area to the first cluster pads and the second cluster pads; the routing wiring includes a first routing wiring extending to the first cluster pad and a second routing wiring extending to the second cluster pad; the first routing wiring and the second routing wiring are disposed adjacent to each other; the first routing wiring includes a first middle stage portion extending in a second direction intersecting a first direction that is a horizontal direction, and the second routing wiring includes a second middle stage portion adjacent to and aligned with the first middle stage portion; the first middle portion and the second middle portion are disposed between the first cluster pad and the second cluster pad.

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