Manufacturing method of semiconductor device

Abstract

To provide a highly reliable thin-film transistor with stable electric characteristics in a thin-film transistor using an oxide semiconductor film.SOLUTION: Within a range of channel length of a thin-film transistor using an oxide semiconductor film of 1.5 μm or more to 100 μm or less, preferably, 3 μm or more to 10 μm or less, and within an operating temperature range of room temperature or more to 180°C or less or an operating temperature range of -25°C or more to 150°C or less, by setting variation width of threshold voltage to 3 V or less, preferably, to 1.5 V or less, a semiconductor device with stable electrical characteristics can be manufactured. Especially in a display device which is one embodiment of the semiconductor device, display unevenness caused by variation in the threshold voltage can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology of constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as C and electro-optical devices, especially in switching of image display devices. There are a wide variety of metal oxides, and they are used for a variety of purposes. Indium oxide is a well-known material that is needed in LCD displays and other applications. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include: For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using metal oxides with excellent semiconductor properties as the channel formation region are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] In an active matrix display device, the electrical properties of the thin film transistors that make up the circuit The electrical characteristics are important, and these characteristics determine the performance of the display device. Among the electrical characteristics of a semiconductor, the threshold voltage (hereinafter referred to as threshold or Vth) is important. Even if the field effect mobility is high, the threshold voltage is high or the threshold voltage is negative. If the threshold voltage is too low, it is difficult to control a circuit including the thin film transistor. In the case of thin film transistors with high threshold voltages and large absolute values, the driving voltage is low. In this state, the TFT cannot perform its switching function and may become a load. Also, if the threshold voltage is negative, the source electrode and drain electrode will not be connected even if the gate voltage is 0V. In this case, a current flows between the on-electrodes, which is called a normally-on state.

[0007] In the case of an n-channel thin film transistor, the channel is first generated when a positive voltage is applied to the gate. A thin film transistor is desirable in which a channel is formed and a drain current flows out. Thin film transistors in which a channel does not form unless a low voltage is applied, and thin film transistors in which a channel forms even under negative voltage conditions Thin film transistors that are formed by thin film transistors and through which drain current flows are used as thin film transistors in circuits. It is not suitable for this purpose.

[0008] For example, when the range of fluctuation in the characteristics of thin film transistors that constitute a circuit in a semiconductor device is large Therefore, there is a risk that malfunctions may occur due to the fluctuation of the threshold voltage. One aspect is a thin film transistor that operates stably over a wide temperature range and a semiconductor device using the same. The purpose is to provide a place [Means for solving the problem]

[0009] One embodiment of the present invention disclosed in this specification is a method for forming a gate electrode layer over a substrate having an insulating surface. a gate insulating layer formed over the gate electrode layer; and an oxide semiconductor layer formed over the gate insulating layer. A source electrode layer and a drain electrode layer are formed on the oxide semiconductor layer, and a gate insulating layer and an oxide semiconductor layer are formed on the oxide semiconductor layer. an insulating layer in contact with a part of the oxide semiconductor layer on the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; The semiconductor device is characterized by forming the above.

[0010] Furthermore, one embodiment of the present invention disclosed in this specification is a method for forming a gate electrode layer over a substrate having an insulating surface. a gate insulating layer over the gate electrode layer; and an oxide semiconductor layer over the gate insulating layer. After the oxide semiconductor layer is formed, a first heat treatment is performed to form a soak layer on the oxide semiconductor layer. a gate insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer; An insulating layer was formed on the drain electrode layer so as to be in contact with a part of the oxide semiconductor layer. Then, a second heat treatment is performed.

[0011] Note that the first heat treatment is preferably performed in a nitrogen atmosphere or a rare gas atmosphere. The first heat treatment is preferably carried out at a temperature of 350°C or higher and 750°C or lower.

[0012] The second heat treatment is carried out in an air atmosphere, an oxygen atmosphere, a nitrogen atmosphere, or a rare gas atmosphere. The second heat treatment is preferably carried out at a temperature of 100° C. or higher and the temperature of the first heat treatment or lower. Desirable.

[0013] The above configuration solves at least one of the above problems.

[0014] The oxide semiconductor used in this specification is InMO3(ZnO). m Thin (m>0) A thin film is formed, and a thin film transistor is fabricated using the thin film as an oxide semiconductor layer. However, m is not necessarily an integer. M can be selected from Ga, Fe, Ni, Mn, and Co. It denotes a selected metallic element or elements. For example, M can be Ga. In addition, there are cases where the above metal elements other than Ga are included, such as Ga and Ni or Ga and Fe. In addition to the metal element contained as M in the oxide semiconductor, impurity elements When Fe, Ni or other transition metal elements or oxides of said transition metals are contained as In this specification, InMO3(ZnO) m Acids with structures represented by (m>0) Among the oxide semiconductor layers, oxide semiconductors with a structure containing Ga as M are called In-Ga-Zn-O systems. This is called an oxide semiconductor, and the thin film is also called an In-Ga-Zn-O based non-single crystal film.

[0015] In addition to the above, oxide semiconductors that can be used for the oxide semiconductor layer include In-Sn-Zn- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In In addition, the above oxide semiconductors can be used. The oxide semiconductor layer may contain silicon oxide. SiO X (X>0)) during the manufacturing process. When a heat treatment is subsequently performed, crystallization can be suppressed. The conductor layer is preferably in an amorphous state, and may be partially crystallized.

[0016] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), dehydration is performed. It is effective to subject the product to a hydrogenation or dehydrogenation process.

[0017] In addition, depending on the conditions of the heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may become amorphous. In some cases, the film may turn from a pure state to a microcrystalline or polycrystalline film. Even in this case, the switching characteristics of the TFT can be obtained. [Effects of the Invention]

[0018] To manufacture and provide thin-film transistors with small threshold fluctuation range and stable electrical characteristics. Therefore, a semiconductor device having a thin film transistor with good electrical characteristics and high reliability can be obtained. A conductor device can be provided. [Brief explanation of the drawings]

[0019] [Figure 1] 2A to 2C illustrate a manufacturing process of a semiconductor device. [Figure 2] 1A to 1C illustrate a semiconductor device. [Figure 3] 10A and 10B show analysis results of hydrogen concentration in an oxide semiconductor layer and a schematic cross-sectional structure of a sample used in the analysis. [Figure 4] 3 is a graph showing current-voltage characteristics of the thin film transistor of Example 1. [Figure 5] 3 is a table and a graph showing the relationship between the operating temperature and the threshold value of the thin film transistor of Example 1. [Figure 6]FIG. 2 is a diagram illustrating the definition of a threshold value in this specification. [Figure 7] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 8] 1A and 1B are a diagram illustrating a circuit configuration of a signal line driver circuit and a timing chart illustrating the operation thereof; [Figure 9] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 10] 1A and 1B are a diagram illustrating a circuit configuration of a shift register and a timing chart illustrating the operation of the shift register; [Figure 11] 1A to 1C illustrate a semiconductor device. [Figure 12] 1A to 1C illustrate a semiconductor device. [Figure 13] 1A to 1C illustrate a semiconductor device. [Figure 14] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 15] 1A to 1C illustrate a semiconductor device. [Figure 16] 1A to 1C illustrate a semiconductor device. [Figure 17] 1A to 1C illustrate a semiconductor device. [Figure 18] 1A to 1C illustrate a semiconductor device. [Figure 19] 1A to 1C illustrate a semiconductor device. [Figure 20] FIG. 1 is a circuit diagram showing a configuration of a semiconductor device. [Figure 21] 1A to 1C illustrate a semiconductor device. [Figure 22] 1A to 1C illustrate a semiconductor device. [Figure 23] 1A to 1C illustrate a semiconductor device. [Figure 24] FIG. 1 is a circuit diagram showing a configuration of a semiconductor device. [Figure 25] FIG. 1 is a diagram showing an example of an electronic book. [Figure 26] FIG. 1 shows an example of a television device and a digital photo frame. [Figure 27] FIG. 1 is a diagram showing an example of a gaming machine. [Figure 28] 1A and 1B are diagrams showing examples of a portable computer and a mobile phone. [Figure 29]10A to 10C are diagrams illustrating calculation results of a semiconductor device and a cross-sectional structure of a semiconductor device used in the calculation. [Figure 30] 1 is a graph showing current-voltage characteristics of a thin film transistor. [Figure 31] 10 is a table and graph showing the relationship between the operating temperature and threshold voltage of a thin-film transistor. [Figure 32] 10A and 10B are diagrams showing cross-sectional structures used in calculations of semiconductor devices. [Figure 33] 10A to 10C are diagrams illustrating calculation results of a semiconductor device. [Figure 34] 10 is a graph showing current-voltage characteristics of the thin film transistor of Example 2. [Figure 35] 10 is a table and a graph showing the relationship between the operating temperature and the threshold value of the thin film transistor of Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0021] Voltage is the potential difference between two points, and potential is the difference in an electrostatic field at a point. The electrostatic energy (electrical potential energy) of a unit charge is Generally, the potential difference between the potential at a certain point and a reference potential (for example, ground potential) is It is often simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, the term "potential" may be read as "voltage" or "voltage." It may also be read as potential.

[0022] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. The gate is a semiconductor element in which a channel region is formed in the region overlapping the gate. By controlling the gate potential, the drain and source are connected via the channel region. The source and drain are thin film transistors. Which is the source or drain depends on the transistor structure and operating conditions. Therefore, it is difficult to define the regions that function as the source and drain. In some cases, they are not called sources or drains. In such cases, for example, they are called first It may be written as terminal or second terminal.

[0023] (Embodiment 1) In this embodiment, one mode of a manufacturing method of the thin film transistor 150 shown in FIG. The process for manufacturing a thin film transistor will be described with reference to cross-sectional views of FIGS. 1A to 1D. FIG. 1E is a top view of the thin film transistor 150 shown in FIG. The film transistor 150 is a type of bottom gate structure called a channel etch type. It is also a type of inverted staggered transistor.

[0024] First, a photolithography process is performed on a substrate 100 having an insulating surface using a photomask. The gate electrode layer 101 is formed by a lithography process. If the resist mask is formed by the ink-jet method, a photomask can be used. Since no external wiring is used, manufacturing costs can be reduced.

[0025] It is preferable to use a glass substrate as the substrate 100. If the temperature of the subsequent heat treatment is high, a substrate with a distortion point of 730°C or higher should be used. The substrate 100 may be made of, for example, aluminosilicate glass, aluminoborosilicate Glass materials such as glass and barium borosilicate glass are used. By containing more barium oxide (BaO) than conventional glass, a more practical heat-resistant glass can be obtained. For this reason, it is preferable to use a glass substrate that contains more BaO than B2O3.

[0026] The substrate 100 may be a ceramic substrate, a quartz substrate, a sapphire substrate, or the like instead of the glass substrate. A substrate made of an insulating material such as a substrate may be used. Alternatively, crystallized glass may be used. can.

[0027] In addition, an insulating film serving as a base film may be provided between the substrate 100 and the gate electrode layer 101. The film has a function of preventing the diffusion of impurity elements from the substrate 100, and is a silicon nitride film, a silicon oxide film, a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide nitride film, and a silicon oxynitride film; It can be formed by the structure.

[0028] By including halogen elements such as chlorine and fluorine in the underlayer, impurities from the substrate 100 can be removed. The function of preventing the diffusion of elements can be further enhanced. The element concentration is measured by the concentration peak obtained by analysis using SIMS (secondary ion mass spectrometry). 1×10 15 atoms / cm 3 More than 1×10 20 atoms / cm 3 If we do the following, stomach.

[0029] The gate electrode layer 101 can be formed using a metal conductive film. The elements are selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the elements mentioned above. It is preferable to use an alloy containing the above elements or an alloy combining the above elements. A three-layer stack consisting of an aluminum layer on a titanium layer and a titanium layer on the aluminum layer. Layer structure, or an aluminum layer on a molybdenum layer and a molybdenum layer on the aluminum layer Of course, it is also possible to use a single layer as the metal conductive film, or It may have a two-layer structure or a laminated structure of four or more layers.

[0030] Next, the gate insulating layer 102 is formed on the gate electrode layer 101 .

[0031] The gate insulating layer 102 is formed by depositing silicon oxide by plasma CVD, sputtering, or the like. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer is formed as a single layer or a stacked layer. For example, plasma CV can be performed using SiH4, oxygen, and nitrogen as the deposition gas. The silicon oxynitride layer may be formed by the method D. The thickness of the gate insulating layer 102 is 100 nm. In the case of a laminate, for example, the first layer has a thickness of 50 nm to 200 nm. a first gate insulating layer and a second gate insulating layer having a thickness of 5 nm to 300 nm on the first gate insulating layer; The laminate is made of insulating layers.

[0032] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, Heat treatment (400°C or higher but below the distortion point of the substrate) is performed under an atmosphere of argon, etc., to remove the The gate insulating layer 102 may be formed by removing impurities such as hydrogen and water.

[0033] Next, a film having a thickness of 5 nm to 200 nm, preferably 10 nm, is formed on the gate insulating layer 102. An oxide semiconductor film having a thickness of 50 nm or less is formed. After the oxide semiconductor film is formed, dehydration or Since the oxide semiconductor film is kept amorphous even after heat treatment for dehydrogenation, the thickness It is preferable to make the oxide semiconductor film thin, ie, 50 nm or less. When a heat treatment is performed after the semiconductor film is formed, crystallization can be suppressed.

[0034] Before the oxide semiconductor film was formed by a sputtering method, argon gas was introduced. Plasma is generated to perform reverse sputtering, and dust adhering to the surface of the gate insulating layer 102 is removed. It is preferable to remove the target. In a nitrogen atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. It is also possible to use nitrogen or helium instead of argon atmosphere. good.

[0035] The oxide semiconductor film is an In-Ga-Zn-O based non-single crystal film, an In-Sn-Zn-O based film, an In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Ga-O system In this embodiment, an oxide semiconductor film based on a Zn-based oxide, an In—O based oxide, an Sn—O based oxide, or a Zn—O based oxide is used. For example, it is formed by sputtering using an In-Ga-Zn-O based oxide semiconductor target. In addition, the film is formed under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) atmosphere. Typically, an oxide semiconductor film is formed by sputtering under an atmosphere of argon and oxygen. In addition, when the sputtering method is used, SiO2 is preferably contained in an amount of 2% by weight or more and 10% by weight or more. The oxide semiconductor film is deposited using a target containing SiOx(X >0), which crystallizes during the heat treatment for dehydration or dehydrogenation in the subsequent process. It is preferable to suppress this. This is preferable because it reduces dust and makes the film thickness distribution uniform.

[0036] The relative density of the oxide semiconductor in the oxide semiconductor target is preferably 99% or more. This makes it possible to reduce the impurity concentration in the formed oxide semiconductor film, In this embodiment, a thin film transistor having high electrical characteristics and high reliability can be obtained. An oxide semiconductor target with a relative density of 97% is used.

[0037] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply for the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used for.

[0038] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0039] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0040] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0041] In addition, the gate insulating layer 102 and the oxide semiconductor film can be formed in succession without being exposed to the air. By forming the film without exposing it to the atmosphere, it is possible to avoid the presence of water, hydrocarbons, etc. The interfaces of the layers can be formed without being contaminated by atmospheric components or impurity elements floating in the air. This makes it possible to reduce variations in the characteristics of thin film transistors.

[0042] Next, the oxide semiconductor film is formed into island-shaped oxide semiconductor layers 103 by a photolithography process. In addition, a laser for forming the island-shaped oxide semiconductor layer 103 is formed. The resist mask may be formed by an inkjet method. When the film is formed by the method described above, no photomask is used, and therefore the manufacturing cost can be reduced.

[0043] Next, first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer 103. The temperature of the first heat treatment for dehydration or dehydrogenation is preferably 350°C or higher and lower than 750°C. The temperature is usually 425°C or higher. If the temperature is 425°C or higher, the heat treatment time may be 1 hour or less. If the temperature is lower than 425°C, the heat treatment time is longer than 1 hour. For example, The substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated under a nitrogen atmosphere. After the heat treatment, the oxide semiconductor layer was prevented from being mixed with water or hydrogen without being exposed to the air. In this embodiment, the oxide semiconductor layer 103 can be obtained by preventing the intrusion of the oxide semiconductor. The temperature T is set to a temperature sufficient to prevent water from entering the layer 103. The same furnace was used until the temperature dropped by 100°C or more below the heating temperature T under a nitrogen atmosphere. The atmosphere is not limited to nitrogen, and degassing can be performed under helium, neon, argon, etc. Hydration or dehydrogenation is carried out.

[0044] The first heat treatment causes rearrangement at the atomic level of the oxide semiconductor constituting the oxide semiconductor layer 103. The first heat treatment is performed to prevent carrier movement in the oxide semiconductor layer 103. This is important because it can release the strain that occurs.

[0045] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. Alternatively, the nitrogen or The purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., 1 ppm or less, preferably It is preferable to keep the concentration below 0.1 ppm.

[0046] The heat treatment device for the first heat treatment is not limited to an electric furnace, and may be a heat treatment device using a heat source such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by thermal conduction or thermal radiation. RTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lam) p Rapid Thermal Anneal (RTA) equipment The LRTA device uses a halogen lamp. , metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium The light (electromagnetic waves) emitted from lamps such as mercury lamps and high-pressure mercury lamps can cause damage to the material being treated. The GRTA device is a device that uses high-temperature gas to perform heat treatment. The gases include rare gases such as argon, or nitrogen, which are easily absorbed by the material to be treated by the heat treatment. A non-reactive inert gas is used.

[0047] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may The oxide semiconductor layer may be crystallized to become a microcrystalline film or a polycrystalline film. The oxide semiconductor layer may be a microcrystalline film with a conversion rate of 80% or more or 90% or more. Depending on the material, the oxide semiconductor layer may not have crystals.

[0048] The first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into the island-shaped oxide semiconductor layer 103. In this case, after the first heat treatment, the substrate is removed from the heating device. The wafer is then taken out and subjected to a photolithography process.

[0049] Here, the results of hydrogen concentration analysis depending on whether or not dehydrogenation has occurred in the oxide semiconductor layer will be described. FIG. 3(A) is a schematic cross-sectional view of the sample used in this analysis. The oxynitride insulating layer 401 is formed by plasma CVD, and In-G is deposited on the oxynitride insulating layer 401. The a-Zn—O-based oxide semiconductor layer 402 was formed to a thickness of about 40 nm. The material was divided into two parts, one of which was not dehydrogenated, and the other was heated at 650 The dehydrogenation was carried out at 50° C. for 6 minutes. The effect of dehydrogenation by heat treatment was investigated by measuring the degree of dehydrogenation.

[0050] The hydrogen concentration in the oxide semiconductor layer was measured using secondary ion mass spectrometry (SIMS). Figure 3(B) shows the oxide The SIMS analysis results show the hydrogen concentration distribution in the thickness direction of the semiconductor layer. The depth of 0 nm at the left end is the top surface of the sample (the top surface of the oxide semiconductor layer). ) The analysis direction 403 shown in FIG. 3(A) indicates the analysis direction of the SIMS analysis. The analysis was carried out in the direction from the outermost surface of the oxide semiconductor layer toward the glass substrate 400. , the horizontal axis of FIG. 3(B) was moved from the left end to the right end. shows the hydrogen concentration and oxygen ion intensity in the sample at a specific depth on a logarithmic axis.

[0051] In FIG. 3(B), the hydrogen concentration profile 412 is the same as that of the oxide semiconductor that has not been dehydrogenated. The hydrogen concentration profile 413 in the conductor layer is shown. 1 shows a hydrogen concentration profile in an oxide semiconductor layer after dehydrogenation using an acid. The elementary ion intensity profile 411 was acquired simultaneously with the measurement of the hydrogen concentration profile 412. The oxygen ion intensity profile 411 shows no extreme fluctuations. Since a nearly constant ion intensity was obtained, it was confirmed that the SIMS analysis was performed accurately. Although not shown, the oxygen concentration profile 413 was also measured. The ionic strength was measured, and a nearly constant ionic strength was obtained. The hydrogen concentration profile 412 and the hydrogen concentration profile 413 are the same as the sample. The quantification was carried out using a standard sample made of a Zn-based oxide semiconductor layer.

[0052] In principle, SIMS analysis can only measure data near the sample surface or near the interface of laminated films made of different materials. It is known that it is difficult to obtain accurate data. It is thought that accurate data is not available from the depth of about 15 nm. The profiles from m onwards were evaluated.

[0053] From the hydrogen concentration profile 412, it can be seen that hydrogen is present in the oxide semiconductor layer that has not been dehydrogenated. Approximately 3×10 20 atoms / cm 3 That's about 5 x 10 20 atoms / cm 3 below, average Hydrogen concentration is about 4 x 10 20 atoms / cm 3 It can be seen that hydrogen is contained. From the concentration profile 413, it can be seen that the average hydrogen concentration in the oxide semiconductor layer is reduced by about 2× due to dehydrogenation. 10 19 atoms / cm 3 It can be seen that the noise level has been reduced to .

[0054] This analysis revealed that the hydrogen concentration in the oxide semiconductor layer was reduced by dehydrogenation through heat treatment. It was also confirmed that dehydration by the GRTA method in a nitrogen atmosphere at 650°C for 6 minutes was possible. It was confirmed that the hydrogen concentration in the oxide semiconductor layer can be reduced to 1 / 10 or less by oxidation. .

[0055] Next, a source electrode layer and a drain electrode layer are formed on the gate insulating layer 102 and the oxide semiconductor layer 103. A conductive film for forming an electrode layer is deposited.

[0056] As a conductive film for forming the source electrode layer and the drain electrode layer, the gate electrode layer 101 As in the above, a metal conductive film can be used. Materials for the metal conductive film include Al, Cr, An element selected from Cu, Ta, Ti, Mo, and W, or an alloy containing the above elements It is preferable to use an alloy or the like that combines the above elements. For example, A three-layer laminate structure in which a titanium layer is laminated on an aluminum layer, or a molybdenum layer A three-layer structure consisting of an aluminum layer on a molybdenum layer and an aluminum layer on top of the molybdenum layer. Of course, the metal conductive film may have a single layer, a two-layer structure, or a four-layer structure. A laminated structure of more than one layer may also be used.

[0057] A source electrode layer and a drain electrode layer are formed by a photolithography process using a photomask. The source electrode layer 105a or the drain electrode layer 105b is formed from a conductive film for forming the conductive layer. At this time, the oxide semiconductor layer 103 is also partly etched (see FIG. 1B). As a result, the oxide semiconductor layer 103 has a groove (depression).

[0058] Note that a resist mask for forming the source electrode layer 105a or the drain electrode layer 105b is used. The resist mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0059] In addition, the oxide semiconductor layer 103 and the source electrode layer 105a and / or the drain electrode layer 10 An oxide conductive layer having a lower resistance than the oxide semiconductor layer 103 may be formed between the oxide semiconductor layer 103 and the oxide semiconductor layer 103. By using such a laminated structure, the breakdown voltage of the thin film transistor can be improved. Specifically, the carrier concentration of the oxide conductive layer with low resistance is, for example, 1×10 20 / cm 3 End 1×10 21 / cm 3 It is preferable that the content is within the following range.

[0060] Next, the gate insulating layer 102, the oxide semiconductor layer 103, the source electrode layer 105a and the drain electrode layer 105b are A protective insulating layer 107 is formed to cover the electrode layer 105b and to be in contact with a part of the oxide semiconductor layer 103. (See FIG. 1(C)). The protective insulating layer 107 has a thickness of at least 1 nm or more. D method, sputtering method, etc., which do not mix impurities such as water and hydrogen into the protective insulating layer 107 Here, the protective insulating layer 107 is formed by a sputtering method. The protective insulating layer 107 formed in contact with part of the oxide semiconductor layer 103 is formed by a method. does not contain impurities such as moisture, hydrogen ions, or OH-, and these cannot penetrate from the outside. An inorganic insulating film that blocks the above-mentioned materials is used, typically a silicon oxide film, a silicon nitride oxide film, or a silicon nitride film. film, aluminum oxide film, aluminum oxynitride film, or aluminum nitride film. This can be done.

[0061] The protective insulating layer 107 is formed of a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an oxide A structure in which a silicon nitride film or an aluminum nitride film is laminated on an aluminum nitride film may also be used. In particular, silicon nitride film does not contain impurities such as moisture, hydrogen ions, or OH-, and these are This is preferable because it is easy to block intrusion from the inside.

[0062] The substrate temperature during the formation of the protective insulating layer 107 may be set to a temperature higher than or equal to room temperature and lower than or equal to 300° C. The film is formed by sputtering in a rare gas (typically argon) atmosphere or in an oxygen atmosphere. The reaction can be carried out under an atmosphere of air or a rare gas (typically argon) and oxygen. In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target is used and sputtered under an oxygen and nitrogen atmosphere. Silicon oxide can be formed.

[0063] Next, a second heat treatment is performed at a temperature of 100° C. or higher and equal to or lower than the temperature of the first heat treatment. For example, the substrate is placed in an electric furnace, which is a type of heat treatment device, and heated in a nitrogen atmosphere. The second heat treatment can be performed at any time after the formation of the protective insulating layer 107. That's fine.

[0064] Through the above steps, a gate electrode layer 101 is provided on a substrate 100 having an insulating surface. A gate insulating layer 102 is provided on the gate electrode layer 101, and the gate insulating layer 102 An oxide semiconductor layer 103 is provided on the surface of the semiconductor layer 102, and a source electrode layer 105 is provided on the oxide semiconductor layer 103. a or drain electrode layer 105b, a gate insulating layer 102, an oxide semiconductor layer 10 3. A layer covering the source electrode layer 105a and the drain electrode layer 105b and the oxide semiconductor layer 103 A channel-etched thin-film transistor having a protective insulating layer 107 in contact with a part of the transistor. 150 can be formed (see FIG. 1(D)).

[0065] FIG. 1(E) is a top view of the thin film transistor 150 described in this embodiment. ) shows the cross-sectional structure of the X1-X2 region in FIG. 1(E). In FIG. 1(E), L is W indicates the channel length, and A indicates the channel width. In the horizontal direction, the oxide semiconductor layer 103 is in contact with the source electrode layer 105a and the drain electrode layer 105b. Ls indicates the length of the region that does not overlap with the source electrode layer 105a and the gate electrode layer 105b. Ld indicates the overlap length of the drain electrode layer 105b and the gate electrode layer 101. 1 indicates the overlap length.

[0066] In this embodiment, the thin film transistor 150 is a thin film transistor having a single gate structure. However, if necessary, a thin film of a multi-gate structure having a plurality of channel forming regions may be used. a thin film transistor having a structure in which a second gate electrode layer is formed on the protective insulating layer 107; It can also be called a gista.

[0067] In this embodiment, a method for manufacturing the channel-etched thin film transistor 150 will be described. However, the configuration of this embodiment is not limited to this. A bottom-contact type (also called an inverted coplanar type) thin-film transistor with a bottom-gate structure is 2B, a channel protection type having a channel protection layer 110. The thin film transistor 170 (also called a channel stop type) is also made of the same material and by the same method. FIG. 2(C) shows another example of a channel-etched thin film transistor. In the thin film transistor 180 shown in FIG. 2C, the gate electrode layer 101 is made of an oxide. The structure extends outward beyond the end of the semiconductor layer 103 .

[0068] The channel length L (L in FIG. 1E) of the thin film transistor 150 is The distance between the drain electrode layer 105a and the drain electrode layer 105b is defined as the distance between the drain electrode layer 105a and the drain electrode layer 105b. The channel length of the transistor 170 is the width of the channel protection layer in the direction parallel to the carrier flow direction. is defined as:

[0069] According to this embodiment, the gate voltage of a thin film transistor including an oxide semiconductor layer can be set to 0 V. It is possible to fabricate thin-film transistors in which the channel is formed at a threshold voltage as close as possible. Cut.

[0070] In addition, the channel length of the thin film transistor is in the range of 3 μm to 10 μm, or 1. In the range of 5 μm to 100 μm, the operating temperature range is from room temperature to 180°C. The fluctuation range of the threshold voltage can be reduced to 3V or less, and further to 1.5V or less.

[0071] In addition, the threshold voltage fluctuation range is set to 3V or less in the operating temperature range of -25°C to 150°C. It can be set to below 1.5V or even below 1.5V.

[0072] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0073] Here, a thin film transistor having a stacked structure shown in FIG. 29(A) is used. The evaluation results of thin film transistor characteristics under the following conditions and 2D device simulation FIG. 29(A) shows a cross-sectional structure of a thin film transistor 850. This shows the structure.

[0074] First, a tungsten layer having a thickness of 100 nm is formed on a glass substrate 801 as a gate electrode layer 802. A gate insulating layer 803 is formed on the gate electrode layer 802 to a thickness of 1000 nm. 800 nm thick, and an In-Ga-Zn-O oxide semiconductor is formed on the gate insulating layer 803. A semiconductor layer 804 is formed to a thickness of 50 nm, and a source electrode layer 805 is formed on the oxide semiconductor layer 804. A titanium layer was formed as a drain electrode layer 806, and a thin film transistor 850 was fabricated. The channel length L of the thin film transistor 850 is 10 μm, and the channel width W is 100 μm. It was decided.

[0075] Next, the substrate temperature during measurement for the thin film transistor 850 was set to room temperature (25°C), 40°C , 60℃, 85℃, 100℃, 120℃, 140℃, 160℃, 180℃, and The current-voltage characteristics were measured at each substrate temperature (operating temperature). The voltage between the source and drain (hereinafter referred to as drain voltage or Vd) is set to 10 V. The voltage between the source and gate (hereinafter referred to as gate voltage or Vg) is set from -10V to 1 The drain current of the thin film transistor is measured by changing the gate voltage to 0V. The Vg-Id curve showing the change in

[0076] Figure 29(B) shows the Vg-Id curve obtained in this measurement. 811 shows the Vg-Id curve when the substrate temperature during measurement was room temperature (25°C). As the substrate temperature rises, the Vg-Id curve moves leftward in Figure 29(B), i.e., That is, Vg is shifted in the negative direction. All Vg-Id curves are given signs. The curve 818 located at the far left is the Vg-Id curve when the substrate temperature is 180°C. From Figure 29(B), it can be seen that the threshold It can be seen that the value has shifted by more than 5V.

[0077] Next, the threshold shift seen in Figure 29(B) is thought to be caused by electron excitation due to temperature. Reproduction verification was carried out using two-dimensional device simulation. The device simulator ATLAS manufactured by Co., Ltd. was used. g) to 3.05 eV, and electron mobility (μn) to 15 cm 2 / Vs, thin film transistor The current-voltage characteristics were calculated assuming a bottom-gate TFT with the same structure as TFT 850.

[0078] FIG. 29(C) is a Vg-Id curve reproduced by simulation. Curve 821 is the Vg-Id curve assumed at room temperature (25°C), and curve 828 is the Vg-Id curve assumed at 180°C. The calculated Vg-Id curve is in good agreement with the actual measured values ​​in Figure 29(B). Results are being obtained.

[0079] FIG. 29D shows the density of states in the oxide semiconductor layer obtained from the simulation results. The horizontal axis represents the band gap of the oxide semiconductor, and the vertical axis represents the density of states. In FIG. 29(D), curves 831 and 832 represent the donor in the band gap. The curve 833 shows the distribution of the acceptor level density in the band gap. The distribution of the level density is shown.

[0080] Curve 831 is distributed widely from the conduction band to the deep band gap, while curve 832 is , which is distributed in a very narrow range near the conduction band and has a very sharp peak. It is thought that the curve 831 is due to oxygen vacancies, and the curve 832 is due to hydrogen.

[0081] Next, a sample different from the sample for which the results shown in Figure 29(B) were obtained was prepared, and the obtained Based on the experimental results of thin film transistor characteristics under an environment of 50°C or less, the temperature of the threshold voltage The degree dependence will be discussed below.

[0082] The sample is a 300 nm silicon oxide film obtained by sputtering, stacked as shown in FIG. After forming the thin film transistor with the same structure, the current-voltage characteristics were measured. The channel length L of the transistor was set to 3 μm, and the channel width W was set to 50 μm.

[0083] For thin film transistors, the substrate temperature during measurement was set to 0°C, room temperature (25°C), 50°C, 10 The temperature was changed to 0°C, 150°C, and the current-voltage characteristics were measured at each substrate temperature (operating temperature). The current-voltage characteristics were measured with the drain voltage Vd set to 10 V and the gate voltage Vg set to -2 The gate voltage Vg of the thin film transistor was changed from 0V to 20V. The Vg-Id curve showing the change in drain current Id was obtained.

[0084] FIG. 30 shows the Vg-Id curve obtained in this measurement. In FIG. 30, curve 911 indicates the measured The Vg-Id curve is shown when the substrate temperature is 0°C at the time of measurement. Accordingly, the Vg-Id curve shifts to the left in Figure 30, that is, in the negative direction of Vg. The curve 918 located slightly to the left is the Vg-Id curve at a substrate temperature of 150°C. .

[0085] FIG. 31(A) is a table summarizing Vth (threshold voltage) obtained from the Vg-Id curve. In FIG. 31(A), the Vth fluctuation range represents the amount of Vth fluctuation between 0°C and 150°C. is doing.

[0086] FIG. 31(B) is a graph showing FIG. 31(A). The horizontal axis represents the measured temperature. , the substrate temperature (operating temperature) when measuring the current-voltage characteristics of the thin-film transistor, and Vth is the threshold voltage at each substrate temperature.

[0087] From Figure 31(A), when comparing when the substrate temperature is 0°C and when it is 150°C, the fluctuation of the threshold voltage It can be seen that the voltage is kept at about 1.5V.

[0088] Here, the temperature dependency of the threshold voltage (Vth) will be considered below.

[0089] The higher the temperature, the closer the Fermi level becomes to the intrinsic Fermi level. As shown in equation (1), The inversion threshold voltage is shown as a function of the Fermi potential. is defined as the difference between the intrinsic Fermi level and the Fermi level (Equation 2). When a p-type biased semiconductor is used for the channel, the threshold voltage shows temperature dependence. This becomes the case.

[0090]

number

[0091]

number

[0092] For example, in an n-type Si transistor that uses a p-type channel, as the temperature rises As φF approaches zero, the threshold voltage shifts in the negative direction. If it is i-type (intrinsic), no threshold voltage shift occurs.

[0093] On the other hand, in the thin film transistor having the measurement results shown in FIG. 30, when the substrate temperature rises, The threshold voltage is shifted in the negative direction. Generally, oxide semiconductors are difficult to make p-type. It is said that the oxide semiconductor in which the channel is formed is easily made n-type. When the threshold voltage is increased, the Fermi level changes in the opposite direction (in the case of an n-type channel, the threshold voltage is increased). Therefore, the threshold voltage of the oxide semiconductor It is necessary to consider a mechanism other than the Fermi level mentioned above as its origin.

[0094] Furthermore, the above discussion is an approximate solution assumed for an ideal single-crystal semiconductor, and there are no crystal defects or The temperature dependence of the species level must be considered separately. Looking at the Id curve, the current increase in the threshold region is significant, and the current in that region is supported. Generally, defects are assumed to be the mechanism by which the In the case of oxide semiconductors with a defect state, the defect level can be expressed as a function with a distribution. This is the general rule.

[0095] Reproducing the temperature dependence of Vth of thin-film transistors with oxide semiconductor channels through calculations The structure assumed in the calculation is shown in Figure 32(A) and Figure 32(B). On the silicon oxide nitride film 701, a gate insulating layer 702 having a thickness of 100 nm and a silicon oxide nitride film having a thickness of 3 Assume an inverted staggered thin film transistor having a 0 nm oxide semiconductor channel 703. The channel length L and channel width W of the thin film transistor were set to L / W=3 / 20 μm. 32(A) in which not only the channel 703 but the entire oxide semiconductor is made into an i-layer, and The source electrode layer 704b or the drain electrode layer 704a has a channel 703. Two types of TFTs with the structure shown in FIG. 32(B) assuming an N+ region 705a and an N+ region 705b below The N+ region 705a and the N+ region 705b in the structure of FIG. 19 / cm 3The donor (Nd) is assumed. The band gap of the oxide semiconductor is Eg = 3.15 eV The electron affinity χ was assumed to be 4.3 eV and the dielectric constant was assumed to be 15. The work function of the metal used for the drain electrode layer 704a is the same as the electron affinity of the oxide semiconductor. 4.3 eV was assumed.

[0096] In addition, it is considered that the defect level in amorphous semiconductors has a strong influence on the temperature characteristics, and the calculations are based on the The acceptor level density in the band gap, which is the curve 833 shown in 29(D), The calculation results are shown in Figure 33. Figure 33 shows the structure shown in Figure 32(A), the structure shown in Figure 32(B), For each of the structures, the distribution of acceptor level density is assumed and not assumed. In addition, Figure 33 shows the calculation results for Vg when the temperature is increased from 0°C to 150°C. The -Id curve and the Vth change (ΔVth) at that time are shown in Fig. 33(A). A) This is the calculation result when the distribution of acceptor level density is not assumed for the structure. , FIG. 33(B) does not assume the distribution of acceptor level density for the structure of FIG. 32(B). Figure 33(C) shows the calculation results for the acceptor level density for the structure shown in Figure 32(A). Figure 33(D) shows the calculation results assuming a distribution of the degree of This is the calculation result assuming a distribution of acceptor level density.

[0097] If we do not assume the distribution of acceptor level density in the band gap, i.e., Looking at the results of Fig. 32(A) and 33(B), it is clear that the Vth of both the Fig. 32(A) structure and the Fig. 32(B) structure is The temperature change was about 0.1V. According to Fermi-Dirac statistics, the temperature change from 0°C to 150°C When the temperature is increased to 200°C, the intrinsic carrier concentration increases by approximately 11 orders of magnitude. As the temperature (ni) increases, the number of carriers (electrons) increases according to the following equation (3).

[0098]

number

[0099] As a result, a smaller gate voltage is required to open the channel, and Vth is The difference is equivalent to 0.1V.

[0100] When assuming the distribution of acceptor level density in the band gap, i.e., Figure 33(C 32(A) and 33(D), ΔVth is The calculated value was close to the actual measurement result. If there is a distribution of acceptor level density within the band gap, temperature dependence will appear. was confirmed.

[0101] By assuming the distribution of acceptor level density in the band gap, the carrier (electric However, by increasing the temperature, the trapped carriers are released and the charge It is thought that the carrier concentration in the oxide semiconductor increased, causing a negative shift in Vth. is almost intrinsic, but the distribution of acceptor level density appears in the temperature dependence of Vth. It is thought that...

[0102] When comparing the structure in Figure 32(A) with the structure in Figure 32(B), no difference was observed between the two. The assumed TFT channel length L is 3 μm, so it is less affected by the N+ region. It is thought that...

[0103] (Embodiment 2) In this embodiment, at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0104] The thin film transistors arranged in the pixel portion are formed according to the first embodiment. The thin film transistor shown in the embodiment 1 is an n-channel TFT, so the n-channel A part of the driving circuit that can be configured with panel-type TFTs is the same as the thin film transistor of the pixel part. It is formed on a substrate.

[0105] An example of a block diagram of an active matrix display device is shown in FIG. On the plate 5300, a pixel portion 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, a The pixel portion 5301 has a plurality of signal lines. A plurality of scanning lines are arranged extending from the signal line driving circuit 5304, and the first scanning line driving circuit 5 302 and a scanning line driver circuit 5303. In the intersection area of ​​the lines 1 and 2, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is an FPC (Flexible Printed Circuit) t) and other connections to a timing control circuit 5305 (also called a controller or control IC). It is connected to the

[0106] In FIG. 7A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. The number of externally provided components such as drive circuits is reduced, which contributes to cost reduction. When a driving circuit is provided outside the substrate 5300, it becomes necessary to extend the wiring, and the connection between the wiring becomes difficult. If a driver circuit is mounted on the same board 5300, the number of connections between the wiring will be reduced. This can improve reliability or yield.

[0107] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1) (start pulse), the scanning line driving The timing control circuit 5305 supplies a clock signal (GCK1) for the first For the second scanning line driver circuit 5303, as an example, a start signal for the second scanning line driver circuit (GSP2) (also called start pulse), clock signal for scanning line driver circuit (GCK2) For example, a start signal for the signal line driver circuit is supplied to the signal line driver circuit 5304. signal (SSP), clock signal for signal line driver circuit (SCK), data for video signal (DAT A) (also called simply video signal), latch signal (LAT) are supplied. The clock signal may be a plurality of clock signals with different periods, or may be an inverted clock signal. The first scanning line driving circuit may be supplied together with the signal (CKB). It is possible to omit either the second scanning line driver circuit 5302 or the second scanning line driver circuit 5303.

[0108] In FIG. 7B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the second scanning line driving circuit 5303, The scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver This shows a structure in which the circuit 5304 is formed on a substrate different from that of the pixel portion 5301. The thin film transistor has a lower field-effect mobility than a transistor using a single-crystal semiconductor due to its structure. A driver circuit formed on the substrate 5300 can be configured using transistors. Therefore, it is possible to increase the size of the display device, reduce the number of processes, reduce costs, or improve yields. It is possible.

[0109] The thin film transistor described in Embodiment 1 is an n-channel TFT. FIG. 8B shows the configuration and operation of a signal line driver circuit configured with n-channel TFTs. An example will be given to explain.

[0110] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a plurality of circuits. , a plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) The thin film transistors 5603_1 to 5603_k are n-channel TFTs. An example will be explained.

[0111] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the first terminals of the thin film transistors 5603_1 to 5603_k. are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5604_1.

[0112] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in order.

[0113] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_N are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k. The thin film transistor 56 has a function of supplying the potential of the signal lines S1 to Sk. Each of 03_1 to 5603_N has a function as a switch.

[0114] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0115] Next, the operation of the signal line driver circuit of FIG. 8(A) will be explained with reference to the timing chart of FIG. 8(B). 8B, the signals Sout_1 to Sout_N and the signal Vda ta_1 to Vdata_k. 5601, and signals Vdata_1 to Vdata_k are , are examples of signals input to the wirings 5604_1 to 5604_k. One operation period of the drive circuit corresponds to one gate selection period in the display device. For example, the period is divided into periods T1 to TN. This is a period for writing video signal data (DATA) to pixels belonging to the selected row.

[0116] In the drawings of the present embodiment, the signal waveforms of the components are rounded for clarity. Therefore, the scale may not necessarily be limited to that shown. It should be noted that

[0117] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 5603_1 to 5603_k are turned on, so the wiring 5604_1 to 5604_k and the signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to the selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, the pixels in the first to k-th columns are written. Then, the video signal data (DATA) is sent to the pixels belonging to the selected row in order of k columns. It will be written.

[0118] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0119] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. In this case, a circuit configured with a thin film transistor shown in FIG. The polarity of all the transistors in the transistor 5601 is set to n-channel or p-channel. It can be configured with only one polarity.

[0120] Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register. In some cases, a level shifter or a buffer may be included. In the operation circuit, a clock signal (CK) and a start pulse signal (SP) are input to the shift register. ) is input, the selection signal is generated. The generated selection signal is The signal is buffered and amplified in the scanning line and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. Since they must all be turned on at the same time, the buffer must be able to pass a large current. It is used.

[0121] Regarding one form of a shift register used in a part of a scanning line driver circuit and / or a signal line driver circuit, This will be explained with reference to FIGS. 9 and 10.

[0122] The shift registers of the scanning line driver circuit and the signal line driver circuit will be described with reference to FIGS. 9 and 10. The shift register includes the first pulse output circuit 10_1 to the Nth pulse output circuit 10_2. 10_N (N is a natural number equal to or greater than 3) (see FIG. 9(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the soft register are A first clock signal CK1 is transmitted from the first wiring 11, and a second clock signal CK2 is transmitted from the second wiring 12. CK2, the third wiring 13 transmits the third clock signal CK3, and the fourth wiring 14 transmits the fourth clock signal CK4. In the first pulse output circuit 10_1, a clock signal CK4 is supplied to the fifth wiring 15. A start pulse SP1 (first start pulse) is input from the second stage onwards. In the n-th pulse output circuit 10_n (n is a natural number of 2 or more and N or less), the pulse The signal from the output circuit (called the previous signal OUT(n-1)) (n is a natural number greater than or equal to 2) is input. In addition, in the first pulse output circuit 10_1, the third pulse output circuit 10_2, which is two stages later, Similarly, in the n-th pulse output circuit 10_n in the second stage or later, , the signal from the (n+2)th pulse output circuit 10_n+2, which is two stages later (later stage signal OUT( Therefore, the pulse output circuit of each stage outputs the pulse to the next stage and / or The first output signal (OUT(1)(SR)~) is input to the pulse output circuit of the previous stage. OUT(N)(SR)), and the second output signal (OUT(1)~OUT(N)) on another wiring, etc. As shown in FIG. 9(A), the last two stages of the shift register are Since the subsequent signal OUT(n+2) is not input, for example, a second start signal is separately input. The first start pulse SP2 and the second start pulse SP3 may be input.

[0123] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The fourth clock signal (CK4) is delayed by 1 / 4 cycle in order. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is controlled by the GCK It is sometimes called SCK, but here we will explain it as CK.

[0124] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 9B, the input terminal 25, the first output terminal 26, and the second output terminal 27. The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 1. It is electrically connected to any one of the first to fourth wirings 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10_2 has The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the wiring 13, and the third input terminal 24 is electrically connected to the fourth wiring 14. are.

[0125] In the first pulse output circuit 10_1, a first clock signal CK is input to a first input terminal 21. 1 is input to the second input terminal 22, the second clock signal CK2 is input to the third input terminal 30, A third clock signal CK3 is input to a terminal 23, and a start pulse SP1 is input to the fifth input terminal 25, the subsequent signal OUT(3)(SR) is input to the fifth input terminal 26, The first output signal OUT(1)(SR) is output from the output terminal 26 of the first 27 outputs the second output signal OUT(1).

[0126] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are three-terminal thin film transistors. In addition to the transistor, a four-terminal thin film transistor can be used. The symbol for the thin film transistor 28 is shown below and will be used in the drawings etc. The thin-film transistor 28 receives a first control signal G1 input to a first gate electrode and a second control signal G2 input to a second gate electrode. The second control signal G2 input to the port electrode controls the electrical connection between the In terminal and the Out terminal. It is an element that can be controlled.

[0127] The threshold voltage of the thin film transistor 28 shown in FIG. 9C is Gate electrodes are provided above and below the panel formation region via gate insulating films, and By controlling the potential of the gate electrode, it can be controlled to a desired value.

[0128] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0129] The first pulse output circuit 10_1 includes a first transistor 31 to a thirteenth transistor 43. (See FIG. 9(D)). In addition, the first input terminal 21 to the fifth input terminal 25, a first output terminal 26, a second output terminal 27, and a first high power supply potential VDD a power supply line 51 to which a second high power supply potential VCC is supplied, a power supply line 52 to which a low power supply potential V The first transistor 31 to the thirteenth transistor 43 are connected to the power supply line 53 through which the SS is supplied. A signal or a power supply potential is supplied to each power supply line. The relationship is that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential V CC is set to a potential higher than the third power supply potential VSS. The fourth clock signal (CK4) is a signal that alternates between high and low levels at regular intervals. When it is at H level, it is VDD, and when it is at L level, it is VSS. By making the potential VDD higher than the potential VCC of the power supply line 52, the operation is not affected. The potential applied to the gate electrode of the transistor can be kept low without This reduces the shift in the threshold voltage of the transistor, thereby suppressing degradation. In this way, among the first transistor 31 to the thirteenth transistor 43, the first transistor The sixth transistor 31 and the sixth to ninth transistors 36 to 39 are connected to the same transistors as shown in FIG. It is preferable to use a four-terminal thin film transistor 28. The sixth to ninth transistors 36 to 39 operate in a manner similar to that of the source or drain. The potential of the node to which one of the electrodes is connected is switched by the control signal of the gate electrode. The transistor is required to respond to a control signal input to the gate electrode. Fast (steep rise of on-current) reduces malfunction of pulse output circuits Therefore, the four-terminal thin film transistor shown in Figure 9(C) By using 28, the threshold voltage can be controlled, and malfunctions can be further reduced. In FIG. 9(D), the first control signal G1 and the second control signal G2 are Although the control signal G2 is the same control signal, a different control signal may be input.

[0130] In FIG. 9D, the first terminal of the first transistor 31 is electrically connected to the power supply line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode ( The first gate electrode and the second gate electrode are electrically connected to a fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal a gate electrode electrically connected to the first terminal of the ninth transistor 39; The third transistor 33 has a first terminal electrically connected to the gate electrode of the third transistor 34. The first terminal is electrically connected to the input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the power supply line 53. The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 One terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate voltage of the second transistor 32. and the gate electrode of the fourth transistor 34, the gate electrode of which is electrically connected to the fourth input The sixth transistor 36 has a first terminal electrically connected to the power supply line 5. 2, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the fourth transistor The gate electrode (first gate electrode and second gate electrode) is electrically connected to the gate electrode of the transistor 34. The gate electrode of the seventh transistor 3 is electrically connected to the fifth input terminal 25. The first terminal of the transistor 7 is electrically connected to the power supply line 52, and the second terminal of the transistor 38 is electrically connected to the power supply line 52. The gate electrodes (first gate electrode and second gate electrode) are electrically connected to the second terminal. The eighth transistor 38 is electrically connected to the third input terminal 23. The gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. and the gate electrodes (first gate electrode and second gate electrode) are connected to the second input terminal 2 The ninth transistor 39 has a first terminal electrically connected to the first transistor 2. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are supplied with a voltage. The gate electrodes (first gate electrode and second gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 21. , the second terminal is electrically connected to the second output terminal 27, and the gate electrode is The second terminal of the ninth transistor 39 is electrically connected to the second terminal of the eleventh transistor 4 1 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. and the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the second output terminal 27, The gate electrode of the seventh transistor 37 (the first gate electrode and the second gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 53. , the second terminal is electrically connected to the first output terminal 26, and the gate electrode is The gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37 are electrically connected. are actively connected.

[0131] In FIG. 9D, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40 The connection point of the gate electrode of the ninth transistor 39 and the second terminal of the ninth transistor 39 is referred to as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the gate electrode of the fifth transistor 35, the second terminal of the sixth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point between the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is referred to as node B. Let's say.

[0132] FIG. 10A shows the pulse output circuit described in FIG. 9D as a first pulse output circuit 10_1. When applied to the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26, 2 and the signals input to or output from the second output terminal 27.

[0133] Specifically, a first clock signal CK1 is input to the first input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a second input terminal CK3 is input. The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0134] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. The gate is a semiconductor element in which a channel region is formed in the region overlapping the gate. By controlling the gate potential, the drain and source are connected via the channel region. The source and drain are thin film transistors. Which is the source or drain depends on the transistor structure and operating conditions. Therefore, it is difficult to define the regions that function as the source and drain. In some cases, they are not called sources or drains. In such cases, for example, they are called first It may be written as terminal or second terminal.

[0135] In FIG. 9(D) and FIG. 10(A), the node A is set to the floating state, and the bootstrap A capacitor may be provided separately to perform the trapping operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0136] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. The shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 10(B) corresponds to the vertical blanking period, and the period 62 corresponds to the gate selection period. do.

[0137] As shown in FIG. 10A, the ninth transistor, whose gate is supplied with the second power supply potential VCC, By providing the transistor 39, the following occurs before and after the bootstrap operation: There are advantages like this.

[0138] If the ninth transistor 39 having the second potential VCC applied to its gate electrode is not present, the boot When the potential at node A rises due to the strapping operation, the second terminal of the first transistor 31 The potential of the source, which is the first power supply potential VDD, rises and becomes higher than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. In the first transistor 31, the gate and source are electrically connected to each other, and the gate and drain are electrically connected to each other. In addition, a large bias voltage is applied, which causes a large stress and leads to transistor deterioration. Therefore, the ninth transistor, to whose gate electrode the second power supply potential VCC is applied, By providing transistor 39, the potential of node A is However, the potential of the second terminal of the first transistor 31 does not increase. That is, by providing the ninth transistor 39, the first transistor The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the gate of the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the first-order This can suppress the deterioration of the transistor 31.

[0139] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0140] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and It is possible to increase the field effect mobility and reduce the degree of degradation, so it is possible to In addition, a transistor using an oxide semiconductor can be Compared to transistors using silicon, a high potential is applied to the gate electrode. The degree of deterioration of the transistor is small. Therefore, the power supply line that supplies the second power supply potential VCC The same operation can be obtained by supplying the first power supply potential VDD to the Since the number of lines can be reduced, the circuit can be made smaller.

[0141] The gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37 the clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38 The voltage supplied to the gate electrodes (first gate electrode and second gate electrode) by the second input terminal 22 is The clock signal is applied to the gate electrode of the seventh transistor 37 (the gate electrode of the first and second transistors). a clock signal provided by the second input terminal 22 to the gate electrode of the eighth transistor; The third input terminal 23 is connected to the gate electrodes (first gate electrode and second gate electrode) of the gate electrode 38. The same effect can be achieved by switching the wiring so that the clock signal is supplied by In the shift register shown in FIG. 10A, the seventh transistor 37 and The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. The transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor By turning off the input terminal 38, the second input terminal 22 and the third input terminal 23 The potential at node B decreases as a result of the potential at node B decreasing. due to a drop in the potential of the gate electrode of the eighth transistor 38 and a drop in the potential of the gate electrode of the eighth transistor 39. On the other hand, in the shift register shown in FIG. 10(A), the seventh The seventh transistor 37 and the eighth transistor 38 are both in an on state. 7 is on, the eighth transistor 38 is off, then the seventh transistor 37 is on. By turning off the eighth transistor 38, the second input terminal 22 and The potential drop at the node B caused by the potential drop at the third input terminal 23 is suppressed by the eighth transistor. The potential drop of the gate electrode of the transistor 38 can be reduced to one time. The gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37 are connected to the third A clock signal CK3 is supplied from the input terminal 23, and the gate voltage of the eighth transistor 38 is A clock signal C is input from the second input terminal 22 to the electrodes (first gate electrode and second gate electrode). It is preferable to have a wiring relationship in which K2 is supplied because the voltage of node B fluctuates. This is because the number of signals is reduced, which reduces noise.

[0142] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, the pulse output This can suppress malfunction of the power circuit.

[0143] The thin film transistor of the driver circuit can be manufactured by the manufacturing method of the thin film transistor described in Embodiment 1. By fabricating a thin film transistor, high-speed operation of the driving circuit section can be achieved, resulting in power saving. This can be achieved.

[0144] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0145] (Embodiment 3) In this embodiment mode, a thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a In the case of manufacturing a semiconductor device (also called a display device) having a display function by using it in a driver circuit, In addition, a part or the whole of a driver circuit is formed by using a thin film transistor. and a system-on-panel can be formed by integrally forming the display and the display on the same substrate.

[0146] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) Also, electronic inks and other electronic devices are also included. A display medium whose contrast changes due to mechanical action can also be applied.

[0147] The display device also includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process of manufacturing the display element, the element substrate corresponds to one form before the display element is completed, The element substrate includes means for supplying a current to each of the plurality of pixels. Specifically, only the pixel electrodes of the display element may be formed, or the pixel electrodes and After forming a conductive film, the state before etching to form a pixel electrode is shown. is fine, and all forms apply.

[0148] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0149] In this embodiment, a liquid crystal display device will be described as an example of a semiconductor device which is one embodiment of the present invention. First, the appearance and cross section of a liquid crystal display panel, which corresponds to one form of a semiconductor device, will be shown in FIG. 11(A1) and 11(A2) show the In-G film formed on the first substrate 4001. Highly reliable thin film transistors containing a-Zn-O based non-single crystal film as a semiconductor layer 4010 4011 and a liquid crystal element 4013 are disposed between a second substrate 4006 and a sealant 4005. 11(A1) and 11(A2). Equivalent to the cross-sectional view at -N.

[0150] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0151] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 11(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0152] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 11B, the thin film transistor included in the pixel portion 4002 is a thin film transistor 4010 and a thin film transistor 401 included in a scanning line driver circuit 4004 The insulating layers 4020 and 4011 are formed on the thin film transistors 4010 and 4011. 21 is provided.

[0153] The thin film transistors 4010 and 4011 are the signal transistors including the oxide semiconductor layer described in Embodiment 1. In this embodiment, a thin film transistor having high reliability can be applied. The transistors 4010 and 4011 are n-channel thin film transistors.

[0154] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is formed on the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the layer at a position overlapping the channel forming region of the nitride semiconductor layer, In this case, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0155] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0156] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Aluminum foil can also be used with PVF film or polyester film. A sheet sandwiched between films can also be used.

[0157] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031, A spherical spacer may be used. The counter electrode layer 4031 is , which is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the counter electrode layer 403 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 400 to the common potential line. Include in 5.

[0158] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec or less. It is short and optically isotropic, so alignment treatment is not required, and viewing angle dependency is small.

[0159] The liquid crystal display device shown in this embodiment is an example of a transmission type liquid crystal display device. The device can be applied to both reflective and semi-transmissive liquid crystal display devices.

[0160] In addition, in the liquid crystal display device described in this embodiment mode, a polarizing plate is provided on the outer side (viewing side) of the substrate, and In this example, a colored layer and an electrode layer for a display element are provided on the side of the substrate in this order. The laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and the polarizing plate may be provided on the The thickness may be appropriately set depending on the material of the colored layer and the manufacturing process conditions. A light-shielding film that functions as a block matrix may be provided.

[0161] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, To improve the reliability of thin film transistors, the film functions as a protective film and a planarizing insulating film. The insulating layer 4020 and the insulating layer 4021 are used to cover the insulating layer 4020 and the insulating layer 4021. is intended to prevent the intrusion of polluting impurities such as organic matter, metals, and water vapor floating in the air. The protective film is preferably a silicon oxide film, a silicon nitride film, or the like, which is formed by sputtering. Silicon film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, aluminum nitride Aluminum nitride film, aluminum oxide nitride film, or aluminum nitride oxide film, or a single layer or laminated layer. In this embodiment, an example in which the protective film is formed by sputtering is shown, but the method is not particularly limited. The insulating film may be formed by various methods.

[0162] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. When a silicon film is used, the aluminum film used as the source electrode layer and the drain electrode layer can be It is effective in preventing locking.

[0163] In addition, an insulating layer is formed as the second layer of the protective film. A silicon nitride film is formed by sputtering. When this happens, ions such as sodium penetrate into the semiconductor region and change the electrical properties of the TFT. This can be suppressed.

[0164] After forming the protective film, the semiconductor layer may be annealed (at 300°C to 400°C). stomach.

[0165] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0166] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0167] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, The semiconductor layer may be annealed (at 300°C to 400°C) at the same time as the step of annealing. By combining the firing process of the edge layer 4021 with the annealing of the semiconductor layer, semiconductor devices can be efficiently manufactured. It becomes possible to do this.

[0168] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0169] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (also known as a conductive polymer). The conductive composition may be used to form the conductive layer. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 7.0 at a wavelength of 550 nm. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0% or more. It is preferable that the resistivity is 0.1 Ω·cm or less.

[0170] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0171] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0172] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive film as the thin film transistors 4010 and 40 The source electrode layer and the drain electrode layer 11 are formed of the same conductive film.

[0173] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0174] In FIG. 11, a signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0175] FIG. 12 shows a liquid crystal display module, which corresponds to one form of semiconductor device, using a TFT substrate 2600. An example of the configuration is shown below.

[0176] FIG. 12 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0177] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0178] Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device. .

[0179] A thin film transistor in a pixel portion of a liquid crystal display device using the thin film transistor described in Embodiment 1 By fabricating a thin film transistor, the threshold voltage of each pixel is reduced. Display unevenness can be suppressed.

[0180] In addition, a driver circuit of a liquid crystal display device can be manufactured by using the manufacturing method of a thin film transistor described in Embodiment 1. By fabricating thin film transistors of This can be achieved, thereby saving power.

[0181] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0182] (Fourth embodiment) An example of electronic paper will be shown as one mode of the semiconductor device.

[0183] The thin film transistor of the first embodiment uses an element electrically connected to the switching element. The present invention may be applied to electronic paper that drives electronic ink by electrophoretic display. Also known as electrophoretic displays, they are as easy to read as paper and are comparable to other display devices. It has the advantage of being able to consume less power and be made thinner and lighter than conventional LCDs.

[0184] Electrophoretic displays can be of various forms, but the first particle has a positive charge. A microcapsule containing a negatively charged particle and a second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0185] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0186] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0187] Furthermore, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cell, display can be performed. For example, in the thin film transistor of the first embodiment, An active matrix substrate obtained by a photodiode may be used.

[0188] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0189] Figure 13 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the same as the thin film transistor shown in Embodiment 1. The thin film transistor includes an oxide semiconductor layer and is highly reliable.

[0190] The electronic paper in Figure 13 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by generating a magnetic field and controlling the orientation of spherical particles.

[0191] The thin film transistor 581 formed on the substrate 580 is a thin film transistor of a bottom gate structure. The thin film transistor 581 is covered with an insulating film 583 that is in contact with the semiconductor layer. The source or drain electrode layer is formed on the first electrode layer 587 and the insulating layers 583 and 585. The first electrode layer 587 and the substrate 596 are in contact with each other through an opening formed therebetween and are electrically connected. The second electrode layer 588 has black areas 590a and white areas 590b between it and the first electrode layer 588. a spherical particle 589 having a liquid-filled cavity 594 therearound; The spherical particles 589 are filled with a filler 595 such as a resin (see FIG. 13). The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. The common connection portion is connected to the second through conductive particles disposed between the pair of substrates. The electrode layer 588 can be electrically connected to a common potential line.

[0192] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, the image that has been displayed can be retained. Therefore, the semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0193] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0194] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0195] (Embodiment 5) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that utilizes electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0196] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0197] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0198] FIG. 14 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0199] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The figure shows an n-channel transistor using an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0200] The pixel 6400 includes a switching transistor 6401 and a light-emitting element driving transistor 6402. 402, a light emitting element 6404 and a capacitor element 6403. The gate of the gate electrode 6401 is connected to the scanning line 6406, and the first electrode (the source electrode and the drain electrode) The second electrode (one of the source and drain electrodes) is connected to a signal line 6405, and the second electrode (the other of the source and drain electrodes) is connected to a signal line 6405. The other end is connected to the gate of the light-emitting element driving transistor 6402. The transistor 6402 has a gate connected to a power supply line 6407 through a capacitor element 6403. The first electrode is connected to a power supply line 6407, and the second electrode is connected to a first electrode (pixel The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0201] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0202] The capacitor element 6403 is substituted for the gate capacitance of the light-emitting element driving transistor 6402. It is possible to omit it. Regarding the gate capacitance of the light-emitting element driving transistor 6402 Alternatively, a capacitance may be formed between the channel region and the gate electrode.

[0203] In the case of a voltage input voltage driving method, the gate of the light emitting element driving transistor 6402 The light emitting element driving transistor 6402 is either fully turned on or off. In other words, the light emitting element driving transistor 6402 The light emitting element driving transistor 6402 is operated in the linear region. Therefore, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the light emitting element driving transistor 6402. The signal line 6405 is connected to the power supply line voltage + transistor for driving the light emitting element. Apply a voltage higher than the Vth of 6402.

[0204] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By using the same pixel configuration as in FIG. 14, it is possible to use the same pixel configuration as in FIG.

[0205] When analog gradation driving is performed, a light emitting element is connected to the gate of the light emitting element driving transistor 6402. Apply a voltage equal to or greater than the forward voltage of 6404 and the Vth of the light-emitting element driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage required to achieve a desired luminance. At least the forward threshold voltage is included. By inputting a video signal that operates in the region, a current is passed through the light emitting element 6404. In order to operate the light emitting element driving transistor 6402 in the saturation region, The potential of the transistor 407 is set higher than the gate potential of the light emitting element driving transistor 6402. By converting the video signal into an analog signal, a current corresponding to the video signal flows to the light emitting element 6404, Analog gray scale driving is possible.

[0206] Note that the pixel configuration shown in Fig. 14 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0207] Next, the configuration of the light emitting element will be described with reference to FIG. 15. Here, the driving TFT is The cross-sectional structure of a pixel will be explained using the example of the type shown in Figures 15(A), (B), and (C). TFT7001 and TFT7011 are TFTs for driving light emitting elements used in semiconductor devices. The TFT 7021 can be manufactured in the same manner as the thin film transistor shown in Embodiment 1, and The thin film transistor is highly reliable and includes a dielectric layer.

[0208] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure that emits light from the side, and the pixel configuration is It can also be applied to optical elements.

[0209] A light emitting element with a bottom emission structure will be described with reference to FIG.

[0210] The TFT 7011 is n-type, and light emitted from the light-emitting element 7012 is emitted to the cathode 7013 side. 15A shows a cross-sectional view of a pixel when the TFT 7011 is electrically connected to the pixel. A cathode 7013 of the light-emitting element 7012 is formed over the light-transmitting conductive film 7017. An EL layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. The conductive film 7017 having the insulating property includes the oxide insulating layer 7031, the overcoat layer 7034, and The drain potential of the TFT 7011 is connected to the protective insulating layer 7035 through a contact hole formed in the protective insulating layer 7035. It is electrically connected to the electrode layer.

[0211] The light-transmitting conductive film 7017 may be formed of indium oxide containing tungsten oxide, oxide Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Conductive materials with transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A membrane can be used.

[0212] The cathode 7013 can be made of various materials, but a material with a small work function, for example Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr In addition to metals and alloys containing them (Mg:Ag, Al:Li, etc.), Yb, Er, etc. Rare earth metals are preferred. In FIG. 15(A), the thickness of the cathode 7013 is set to a level that allows light to pass through. (Preferably, about 5 nm to 30 nm) For example, an aluminum film having a thickness of 20 nm is A ZnO film is used as the cathode 7013 .

[0213] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The conductive film 7017 and the cathode 7013 may be formed by the same mask. It is possible to etch it using a etchant, which is preferable.

[0214] The periphery of the cathode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide, aluminum, and the like. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes The partition wall 7019 is formed by using a photosensitive resin material, and has an opening on the cathode 7013. The side wall of the opening is shaped to be an inclined surface formed with a continuous curvature. When a photosensitive resin material is used for the partition wall 7019, a resist mask is preferably used. The step of forming a mask can be omitted.

[0215] The EL layer 7014 formed on the cathode 7013 and the partition wall 7019 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7013 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, the hole transport layer, and the hole injection layer are laminated in this order. stomach.

[0216] The stacking order is not limited to the above, and a hole injection layer, a hole transport layer, and a light emitting layer may be stacked on the cathode 7013. However, when comparing power consumption, the cathode layer may be stacked in this order. An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the electrode 7013 in this order. Layering is preferable because it consumes less power.

[0217] In addition, various materials can be used for the anode 7015 formed on the EL layer 7014. However, materials with large work functions, such as titanium nitride, ZrN, Ti, W, Ni, Pt, Cr, etc., and transparent conductive materials such as ITO, IZO (indium zinc oxide), and ZnO. It is also preferable to provide a shielding film 7016 on the anode 7015, such as a metal that blocks light or a light that reflects light. In this embodiment, an ITO film is used as the anode 7015, and a shielding film A Ti film is used as 7016.

[0218] The region where the EL layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light emitting element 7012. In the case of the element structure shown in FIG. 15A, the light emitted from the light emitting element 7012 is emitted toward the cathode 7013 as indicated by the arrow.

[0219] Note that FIG. 15A shows an example in which a light-transmitting conductive film is used as a gate electrode layer. The light emitted from the light emitting element 7012 passes through the color filter layer 7033 and is reflected by the TFT The light is emitted through the gate electrode layer and source electrode layer of the TFT7011. A light-transmitting conductive film is used as the electrode layer or the source electrode layer, and the aperture ratio can be improved. do.

[0220] The color filter layer 7033 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0221] The color filter layer 7033 is covered with an overcoat layer 7034, which is further provided with a protective insulating layer. 15A, the overcoat layer 7034 is thin. As shown in the figure, the overcoat layer 7034 has irregularities caused by the color filter layer 7033. It has the function of flattening the surface.

[0222] In addition, the oxide insulating layer 7031, the overcoat layer 7034, and the protective insulating layer 7035 are formed. The contact hole that reaches the drain electrode layer is formed at a position where it overlaps with the partition wall 7019. In FIG. 15(A), a contact hole reaching the drain electrode layer and a partition wall 70 By overlapping the layout of 19 and , the aperture ratio can be improved.

[0223] Next, a light emitting element with a dual emission structure will be described with reference to FIG.

[0224] In FIG. 15B, a light-transmitting conductive film 7027 electrically connected to the TFT 7021 A cathode 7023 of the light-emitting element 7022 is formed on the cathode 7023. An EL layer 70 24 and an anode 7025 are laminated in this order. The conductive layer 7041, the overcoat layer 7044, and the protective insulating layer 7045 are formed on the conductive layer 7041, the overcoat layer 7044, and the protective insulating layer 7045. It is electrically connected to the drain electrode layer of the TFT 7021 via a contact hole.

[0225] The light-transmitting conductive film 7027 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Conductive materials with transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A membrane can be used.

[0226] The cathode 7023 can be made of various materials, but a material with a small work function, for example Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr In addition to metals and alloys containing them (Mg:Ag, Al:Li, etc.), Yb, Er, etc. Rare earth metals are preferred. In this embodiment, the cathode 7023 has a thickness large enough to transmit light. (Preferably, about 5 nm to 30 nm) For example, an aluminum film having a thickness of 20 nm is A ZnO film is used as the cathode 7023 .

[0227] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The conductive film 7027 and the cathode 7023 may be formed by the same mask. It is possible to etch it using a etchant, which is preferable.

[0228] The periphery of the cathode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimide, aluminum, and the like. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes The partition wall 7029 is formed by using a photosensitive resin material, and has an opening on the cathode 7023. The side wall of the opening is shaped to be an inclined surface formed with a continuous curvature. When a photosensitive resin material is used for the partition wall 7029, a resist mask is preferably used. The step of forming a mask can be omitted.

[0229] The EL layer 7024 formed on the cathode 7023 and the partition wall 7029 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7023 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, the hole transport layer, and the hole injection layer are laminated in this order. stomach.

[0230] The stacking order is not limited to the above, and a hole injection layer, a hole transport layer, and a light emitting layer may be stacked on the cathode 7023. However, when comparing power consumption, the cathode layer may be stacked in this order. An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the electrode 7023 in this order. Layering is preferable because it consumes less power.

[0231] In addition, various materials can be used for the anode 7025 formed on the EL layer 7024. However, materials with a large work function, such as transparent conductive materials such as ITO, IZO, and ZnO, In this embodiment, an ITO film containing silicon oxide is used as the anode 7025.

[0232] The region where the EL layer 7024 is sandwiched between the cathode 7023 and the anode 7025 is the light emitting element 7022 In the case of the element structure shown in FIG. 15B, the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0233] Note that FIG. 15B shows an example in which a light-transmitting conductive film is used as a gate electrode layer. The light emitted from the light emitting element 7022 to the cathode 7023 side is reflected by the color filter layer 7043. The light passes through the gate electrode layer and source electrode layer of the TFT7021 and is emitted. By using a light-transmitting conductive film as the gate electrode layer and the source electrode layer of 7021, The aperture ratio on the electrode 7025 side and the aperture ratio on the cathode 7023 side can be made almost the same.

[0234] The color filter layer 7043 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0235] The color filter layer 7043 is covered with an overcoat layer 7044, which is further provided with a protective insulating layer. Covered by layer 7045.

[0236] In addition, the oxide insulating layer 7041, the overcoat layer 7044, and the protective insulating layer 7045 are formed. The contact hole that reaches the drain electrode layer is formed at a position where it overlaps with the partition wall 7029. The contact hole reaching the drain electrode layer and the partition wall 7029 are overlapped. By doing so, the aperture ratio on the anode 7025 side and the aperture ratio on the cathode 7023 side are made almost the same. It is possible.

[0237] However, if a light-emitting element with a dual-side emission structure is used and both display surfaces are full color, Since light from the anode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable to provide a sealing substrate with a filter layer above the anode 7025.

[0238] Next, a light emitting element with a top emission structure will be described with reference to FIG.

[0239] In FIG. 15(C), a TFT 7001 which is a driving TFT is an n-type, and a light emitting element 7002 emits light. FIG. 15(C) shows a cross-sectional view of a pixel when incident light exits the anode 7005 side. A cathode 7003 of a light emitting element 7002 electrically connected to a TFT 7001 is formed. An EL layer 7004 and an anode 7005 are laminated in this order on the cathode 7003 .

[0240] The cathode 7003 can be made of various materials, but a material with a small work function, for example Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr In addition to metals and alloys containing them (Mg:Ag, Al:Li, etc.), Yb, Er, etc. Rare earth metals are preferred.

[0241] The periphery of the cathode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimide, aluminum, and the like. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes The partition wall 7009 is formed by using a photosensitive resin material, and has an opening on the cathode 7003. The side wall of the opening is shaped to be an inclined surface formed with a continuous curvature. When a photosensitive resin material is used for the partition wall 7009, a resist mask is preferably used. The step of forming a mask can be omitted.

[0242] The EL layer 7004 formed on the cathode 7003 and the partition wall 7009 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7003 is composed of multiple layers, an electron injection layer, an electron transport layer, and a light emitting layer are disposed on the cathode 7003. The layer, the hole transport layer, and the hole injection layer are laminated in this order. stomach.

[0243] The stacking order is not limited to the above, and a hole injection layer, a hole transport layer, and a light emitting layer may be stacked on the cathode 7003. The cathode 700 may be laminated in this order, i.e., the electron transport layer and the electron injection layer. 3 will function as the anode.

[0244] In Figure 15(C), hole injection is performed on a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order. The electron injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked in this order, and Mg:A A laminate of a g-alloy thin film and ITO is formed.

[0245] However, when comparing power consumption, the cathode 7003 is covered with an electron injection layer, an electron transport layer, a light emitting layer, It is preferable to stack the hole transport layer and the hole injection layer in this order, as this reduces power consumption.

[0246] The anode 7005 is formed using a conductive material that transmits light, such as titanium oxide. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, oxide Indium oxide containing titanium, indium tin oxide containing titanium oxide, indium stannate Indium tin oxide with added silicon dioxide, indium zinc oxide, A conductive film having such a structure may be used.

[0247] The region where the EL layer 7004 is sandwiched between the cathode 7003 and the anode 7005 forms the light emitting element 7002. In the case of the pixel shown in FIG. 15(C), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0248] In addition, in FIG. 15(C), a TFT 7001 is an example in which a thin film transistor 150 is used. However, there is no particular limitation, and thin film transistors 160, 170, and 180 may be used. can.

[0249] 15(C), the cathode 7003 is formed by an oxide insulating layer 7051 and a planarizing insulating layer 7052. 7053 and the insulating layer 7055 through contact holes formed in the TFT 7001. The planarization insulating layer 7053 is electrically connected to the rain electrode layer. Resin materials such as polyethylene terephthalate, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above resin materials, low-k materials, siloxane resins, PSG ( Phosphorus glass, BPSG (borophosphorus glass), etc. can be used. The planarization insulating layer 7053 may be formed by stacking a plurality of insulating films formed from a material. The method for forming the planarization insulating layer 7053 is not particularly limited, and may be a sputtering method depending on the material. , SOG method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater A coater, knife coater, etc. can be used.

[0250] In addition, a partition wall 7009 is provided to insulate the cathode 7003 from the cathode of an adjacent pixel. The partition wall 7009 is made of organic resin film such as polyimide, acrylic, polyamide, epoxy, etc., or inorganic insulating film. The partition wall 7009 is formed by using an insulating film or organic polysiloxane. An opening is formed on the cathode 7003 using a material, and the sidewall of the opening has a continuous curvature. It is preferable to form the inclined surface.

[0251] In the structure of FIG. 15C, when full color display is performed, for example, the light emitting element 70 02 is a green light emitting element, one of the adjacent light emitting elements is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is also included, making a total of four A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0252] In the structure of FIG. 15(C), all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By combining a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0253] Of course, a single-color display may be performed. For example, a lighting device may be formed using white light. Alternatively, a monochromatic light emitting device may be used to form an area color type light emitting device.

[0254] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0255] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0256] The thin film transistor (driving TFT) that controls the driving of the light emitting element and the light emitting element are electrically However, the current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the power supply is connected to the power supply.

[0257] Next, the appearance and structure of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of a semiconductor device, will be described. The cross section will be explained with reference to FIG. 16. FIG. 16(A) shows a thin film formed on a first substrate. A panel in which a film transistor and a light-emitting element are sealed between a second substrate and the panel by a sealant. 16(B) is a plan view of the device, and FIG. 16(B) corresponds to a cross-sectional view taken along line HI in FIG. 16(A).

[0258] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0259] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 16B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0260] The thin film transistors 4509 and 4510 are the signal transistors including the oxide semiconductor layer described in Embodiment 1. In this embodiment, a thin film transistor having high reliability can be applied. Transistors 4509 and 4510 are n-channel thin film transistors.

[0261] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping the channel forming region. By placing the gate electrode at a position overlapping the channel formation region of the semiconductor layer, the The amount of change in the threshold voltage of the thin film transistor 4509 can be reduced. The potential of the gate electrode layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or may be different. The conductive layer 4 may be formed of a metal or a silicon dioxide film, and may function as a second gate electrode layer. The potential of 540 may be GND, 0V, or may be in a floating state.

[0262] The thin film transistor 4509 has a protective insulating film connected to a semiconductor layer including a channel formation region. The insulating layer 4541 is formed as the protective insulating layer described in Embodiment 1. The layer 107 may be formed using the same material and method as the layer 107. In order to reduce the noise, the insulating layer 4544 is covered with the insulating layer 4544, which functions as a planarization insulating film. In this example, the insulating layer 4541 is formed by sputtering in the same manner as the protective insulating layer 107 described in Embodiment 1. A silicon oxide film is formed by a method.

[0263] An insulating layer 4544 is formed as a planarization insulating film. The insulating layer 4021 may be formed using the same material and method as the insulating layer 4021 described in Embodiment 2. Acrylic is used as layer 4544.

[0264] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0265] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0266] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0267] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0268] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a and FPC 4518b. Powered by 518b.

[0269] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source of the thin film transistors 4509 and 4510. The source electrode layer and the drain electrode layer are formed from the same conductive film.

[0270] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0271] The substrate located in the direction of light extraction from the light emitting element 4511 must be transparent. In this case, a glass plate, a plastic plate, a polyester film or an acrylic film A light-transmitting material such as aluminum is used.

[0272] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's fine.

[0273] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0274] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0275] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0276] A thin film transistor in a pixel portion of a light-emitting display device can be manufactured by the manufacturing method of the thin film transistor described in Embodiment 1. By fabricating a transistor, the variation in the threshold voltage of the thin film transistor of each pixel can be reduced. Therefore, it is possible to suppress display unevenness caused by the above.

[0277] In addition, a driver circuit of a light-emitting display device can be manufactured by using the manufacturing method of a thin film transistor described in Embodiment 1. By fabricating thin film transistors of This can be achieved, thereby saving power.

[0278] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0279] (Embodiment 6) In this embodiment mode, the thin film transistor described in Embodiment 1 is used as one mode of a semiconductor device. An example of a liquid crystal display device using a liquid crystal element having the above structure will be described with reference to FIGS. 17 to 20. The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. The thin film transistor shown in FIG. 1 can be applied to the present invention and can be manufactured in the same manner as in Embodiment 1. The TFT628 and TFT629 are thin film transistors with excellent electrical characteristics and high reliability. 17 to 20 are thin film transistors in which an oxide semiconductor layer is used as a channel formation region. In the case where the thin film transistor shown in FIG. 2C is used as an example of the thin film transistor, However, the present invention is not limited to this.

[0280] A VA (Vertical Alignment) type liquid crystal display device will be described below. A VA type liquid crystal display device is a type of method that controls the alignment of liquid crystal molecules in a liquid crystal display panel. In a VA type liquid crystal display device, when no voltage is applied, the liquid crystal molecules are aligned with the panel surface. In this embodiment, pixels are divided into several areas. The molecules are tilted in different directions in each sub-pixel. This is called multi-domain or multi-domain design. In the following explanation, multi-domain A liquid crystal display device with carefully considered design will be described.

[0281] 18 and 19 show the pixel electrode and the counter electrode, respectively. 1 is a plan view of a substrate on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. 17. Also, FIG. 19 is a plan view of the substrate side on which the counter electrode is formed. The following description will be given with reference to these figures.

[0282] FIG. 17 shows a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode layer 640 and the like are formed is superimposed on the counter substrate 601. The figure shows the state in which the liquid crystal is injected.

[0283] Although not shown, a protrusion 644 is formed between the substrate 600 and the opposing substrate 601. By forming the highest columnar spacer, the distance between the pixel electrode layer 624 and the counter electrode layer 640 (cell The gap is set constant. An alignment film 648 is formed on the pixel electrode layer 624. An alignment film 646 is also formed on the counter electrode layer 640. A liquid crystal layer 650 is formed between them. It is being done.

[0284] Although the spacers described here are columnar spacers, bead spacers may also be dispersed. Furthermore, the spacers may be formed on the pixel electrode layer 624 formed on the substrate 600 .

[0285] On the substrate 600, a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 6 The pixel electrode layer 624 includes a TFT 628, a wiring 616, and a storage capacitor 6 The insulating film 620 covering the insulating film 620 and the insulating film 622 covering the insulating film 620 are formed by contacts. The TFT 628 is connected to the wiring 618 through a hole 623. The storage capacitor 630 is connected to the gate of the TFT 628. The first capacitance wiring 604 formed at the same time as the wiring 602 and the gate insulating film 60 6, and a capacitance wiring 617 which is a second capacitance wiring formed at the same time as the wirings 616 and 618. will be done.

[0286] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been completed.

[0287] 18 shows a planar structure on a substrate 600. The pixel electrode layer 624 contains tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as I TO), indium zinc oxide, indium tin oxide with silicon oxide added, etc. A light-transmitting conductive material such as the above can be used.

[0288] The pixel electrode layer 624 is made of a conductive material containing a conductive polymer. The pixel electrode formed using the conductive composition can be formed by the sheet. Resistance is 10,000Ω / □ or less, and light transmittance at a wavelength of 550nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that:

[0289] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0290] The pixel electrode layer 624 is provided with a slit 625. The slit 625 controls the alignment of the liquid crystal. This is for the purpose.

[0291] The TFT 629 shown in FIG. 18 and the pixel electrode layer 626 and storage capacitor 631 connected thereto are The TFT 628, the pixel electrode layer 624, and the storage capacitor 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. The pixel of the panel is composed of pixel electrode layer 624 and pixel electrode layer 626. The pixel electrode layer 624 and the pixel electrode layer 626 constitute a sub-pixel.

[0292] 19 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is the same as the pixel electrode layer 624. On the counter electrode layer 640, a protrusion for controlling the alignment of the liquid crystal is formed. The beginning 644 is formed.

[0293] The equivalent circuit of this pixel structure is shown in Figure 20. Both TFT628 and TFT629 have gate electrodes. The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the liquid crystal elements 651 and 652 can be made to operate differently. That is, by individually controlling the potentials of the capacitance wiring 604 and the capacitance wiring 605, the liquid crystal The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0294] When a voltage is applied to the pixel electrode layer 624 in which the slit 625 is provided, a The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (oblique electric field). By arranging the 644 in an alternating interdigitated manner, a diagonal electric field is effectively generated, By controlling the orientation, the direction in which the liquid crystal is oriented varies depending on the location. The multi-domain technology widens the viewing angle of the LCD panel.

[0295] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 21 to 24. do.

[0296] 21 and 22 show the pixel structure of a VA type liquid crystal display panel. FIG. 21 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The following description will refer to both figures.

[0297] This pixel structure has multiple pixel electrodes in one pixel, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. In other words, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independently The system has a configuration for controlling the temperature.

[0298] The pixel electrode layer 624 is connected to the TFT 628 through the contact hole 623 by the wiring 618. The pixel electrode layer 626 is connected to the wiring 619 through the contact hole 627. The gate wiring 602 of the TFT 628 and the gate of the TFT 629 are connected. The wiring 603 is separated so that different gate signals can be applied. The wiring 616 functioning as a data line is used in common by the TFT 628 and the TFT 629. The thin film transistors shown in Embodiment Mode 1 are used as the TFTs 628 and 629. In addition, a capacitance wiring 690 is provided.

[0299] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes, and the pixel electrode layer 624 and the pixel electrode layer 626 are V-shaped. A pixel electrode layer 626 is formed so as to surround the outside of the pixel electrode layer 624. By applying different voltages to the electrode layer 626 to the TFTs 628 and 629, The equivalent circuit of this pixel structure is shown in Figure 24. The TFT 629 is connected to the gate wiring 602, and the TFT 629 is connected to the gate wiring 603. The TFT 628 and the TFT 629 are both connected to the wiring 616. By individually controlling the signals applied to the output wiring 603, the liquid crystal element 651 and the liquid crystal element The voltages applied to TFT 628 and TFT 652 can be different. By individually controlling the operation of 29, different liquid crystals are formed in the liquid crystal element 651 and the liquid crystal element 652. This allows for a wider viewing angle.

[0300] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 23 shows the structure of the opposing substrate side. The opposing electrode layer 640 is shared between different pixels. The electrode has a slit 641 formed therein. The polar layer 624 and the slits 625 on the pixel electrode layer 626 side are arranged so as to interdigitate with each other. This effectively generates an oblique electric field and controls the alignment of the liquid crystal. This allows the liquid crystal to be oriented in different directions depending on the location, thereby widening the viewing angle. In FIG. 23, pixel electrode layers 624 and 626 formed on the substrate 600 are indicated by dashed lines. The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged to overlap each other. This shows how it is being used.

[0301] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626. An alignment film 646 is also formed on the layer 640. The liquid crystal layer 640 is disposed between the substrate 600 and the counter substrate 601. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are formed. The pixel electrode layer 626 and the liquid crystal layer 627 are overlapped with each other to form a first liquid crystal element. The layer 650 and the counter electrode layer 640 overlap each other to form a second liquid crystal element. The pixel structure of the display panel described in FIGS. 21 to 24 has a first liquid crystal element and a second liquid crystal element in one pixel. It has a multi-domain structure with crystal elements.

[0302] In this embodiment, a liquid crystal display device having the thin film transistor described in Embodiment 1 is We have explained about A-type liquid crystal display devices, but we have also discussed IPS-type liquid crystal display devices and TN-type liquid crystal display devices. The present invention can also be applied to devices and the like.

[0303] The thin film transistor of the pixel portion of the liquid crystal display device is manufactured by the manufacturing method of the thin film transistor described in Embodiment 1. By fabricating thin film transistors, the variation in threshold voltage of the thin film transistors of each pixel can be reduced. It is possible to suppress display unevenness caused by the adhesion.

[0304] (Embodiment 7) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, trains, etc. It can be used for in-car advertising, displaying on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 25.

[0305] 25 shows an example of an electronic book. For example, an electronic book 2700 includes a housing 2701 and a The housing 2701 and the housing 2703 are The shaft 2711 serves as an axis for opening and closing. This configuration allows the device to operate like a paper book.

[0306] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 25) and An image can be displayed on the display unit 2707 in FIG.

[0307] 25 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a board, a pointing device, etc. Also, the back and sides of the housing may be On the front, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable). The configuration includes a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. Good too.

[0308] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0309] (Embodiment 8) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also known as mobile phones or mobile phone devices), (c), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples include:

[0310] FIG. 26(A) shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. The figure shows the configuration.

[0311] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0312] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0313] FIG. 26(B) shows an example of a digital photo frame. The frame 9700 has a display unit 9703 built into a housing 9701. 3 is capable of displaying various images, for example, images taken with a digital camera. By displaying data, it can function like a regular photo frame.

[0314] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0315] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0316] FIG. 27(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 27(A) also includes a speaker unit 9884, a recording medium insertion unit 988, 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the semiconductor device disclosed in the above is included, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. 27(A) can be The function of reading out programs or data and displaying them on the display, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 27(A) has the function of sharing information by performing the above. The functions are not limited to these, and various functions can be provided.

[0317] FIG. 27(B) shows an example of a slot machine, which is a large gaming machine. 900 has a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to the above, and any other configuration may be used as long as it includes at least the semiconductor device disclosed in this specification. The configuration may be such that ancillary equipment is provided as appropriate.

[0318] FIG. 28A is a perspective view showing an example of a portable computer.

[0319] The portable computer of FIG. 28(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display portion 9303 and a keyboard. The lower housing 9302 having the card 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to input data on the keyboard, the hinge unit can be opened. The user can perform input operations by looking at the display portion 9303.

[0320] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the lower housing 9302. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted. There are.

[0321] The upper housing 9301 further includes a display unit 93 that can be slid into the upper housing 9301 and stored therein. 07, which allows for a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display section.

[0322] The display portion 9303 or the storable display portion 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses a light-emitting display panel made of inorganic light-emitting elements.

[0323] The portable computer shown in FIG. 28(A) is configured with a receiver and the like, and is also used for television broadcasting. It is possible to receive broadcasts and display images on the display portion 9303 or the display portion 9307. In addition, the hinge unit connecting the upper housing 9301 and the lower housing 9302 is kept closed. Also, the display part 9307 can be slid to expose the entire screen, and the user can adjust the screen angle. You can also watch TV broadcasts. In this case, the hinge unit is opened and the display unit 9 303 is not displayed, and only the circuit that displays the TV broadcast is started. Portable computers with limited power consumption and limited battery capacity It is useful in

[0324] FIG. 28(B) shows a portable telephone that can be worn on the user's arm like a wristwatch. FIG. 10 is a perspective view showing an example of a story.

[0325] This mobile phone includes a main body having at least a communication device with a telephone function and a battery, A band for attaching the body to the arm, and an adjustment unit 92 for adjusting the fastening state of the band to the arm 05, it is composed of a display unit 9201, a speaker 9207, and a microphone 9208.

[0326] The main body also has an operation switch 9203, which is used for power input and display switching. In addition to the switch and the switch to start shooting, for example, when you press a button, a program for the Internet It will be launched.

[0327] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the display portion 9201. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 28(B) shows a display button 9202 displayed on a display unit 9201, and Input can be made by touching the screen.

[0328] The main body also contains an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. It has a camera unit 9206 with a step. Note that it is not necessary to provide a camera unit.

[0329] The mobile phone shown in FIG. 28(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in a memory or the like. The system is configured with a storage device and the like, so that television broadcasts can be recorded in the memory. The mobile phone shown in FIG. 1 may have a function for collecting location information such as GPS.

[0330] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in Figure 28(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force-actuable panel.

[0331] Although FIG. 28(B) illustrates an electronic device that is worn on the arm, it is not limited to this. It is sufficient that the device has a portable shape. [Example]

[0332] In this example, a thin film transistor is manufactured by the manufacturing method shown in Embodiment Mode 1. The results of evaluating the thin film transistor characteristics in environments ranging from 25° C. to 180° C. are shown.

[0333] In this example, thin films with channel lengths L of 3 μm, 5 μm, and 10 μm are formed on the same substrate. Several transistors were fabricated and the thin-film transistor characteristics were tested in an environment between room temperature and 180°C. The channel width W was set to 20 μm for all thin film transistors. The manufacturing method will be described.

[0334] First, a silicon oxynitride film with a thickness of 100 nm was formed on a glass substrate as an underlayer by the CVD method. A 150 nm thick tantalum film was formed on the silicon oxynitride film as a gate electrode layer by sputtering. The tungsten film was then selectively etched to form a gate electrode layer. was formed.

[0335] Next, a 100 nm thick silicon oxynitride film was formed on the gate electrode layer by CVD as a gate insulating layer. A bare film was formed.

[0336] Next, an In-Ga-Zn-O oxide semiconductor target (In2O3 :Ga2O3:ZnO=1:1:1) and the distance between the substrate and the target was set to 60 m. m, pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, argon and oxygen (argon: oxygen The film was formed at room temperature (25°C) under a SiO2 atmosphere (30sccm:15sccm) to a thickness of 50nm. Here, the oxide semiconductor layer was selectively etched to form island-shaped An oxide semiconductor layer was formed.

[0337] Next, the oxide semiconductor layer was subjected to first heat treatment at 450° C. for 1 hour in a nitrogen atmosphere.

[0338] Next, a titanium film (thickness: 50 nm), an aluminum film (thickness 100 nm), and a titanium film (thickness 50 nm) were laminated. The conductive film was formed at room temperature (25°C) by sputtering. The source electrode layer and the drain electrode layer are formed by etching, and the channel length L of the thin film transistor is The lengths of the channels are 3 μm, 5 μm, and 10 μm, and the channel width W is 20 μm. Ta.

[0339] Next, a protective insulating layer with a thickness of 300 nm was formed by sputtering so as to contact the oxide semiconductor layer. The silicon oxide film was formed at 100° C. Here, the silicon oxide film, which is a protective layer, was selectively etched. Then, openings were formed over the gate electrode layer, the source electrode layer, and the drain electrode layer.

[0340] Next, a titanium film (50 nm thick) and an aluminum film (100 nm thick) were used as the measurement electrode layer. ), and a titanium film (thickness 5 nm) were laminated by sputtering at room temperature (25°C). Here, the measurement electrode layer is selectively etched, and the gate electrode is exposed through the opening. a measurement electrode layer electrically connected to the source electrode layer; a measurement electrode layer electrically connected to the drain electrode layer; A measurement electrode layer was formed to be electrically connected to the rain electrode layer. A second heat treatment was performed at 0° C. for 1 hour.

[0341] Through the above steps, the channel width W is set to 20 μm, and the channel length L is set to 3 μm and 5 μm. Thin film transistors with thicknesses of 10 μm and 10 μm were fabricated on the same substrate.

[0342] Next, the current-voltage characteristics of each thin-film transistor were measured. The solution to the change in the voltage between the source and gate (hereinafter referred to as the gate voltage or Vg) The change in the current flowing between the source and drain (hereafter referred to as drain current or Id) Figure 4(A) shows the Vg-Id curves of a thin-film transistor with a channel length L of 3 μm. Figure 4(B) shows the Vg-Id curves of a thin film transistor with a channel length L of 5 μm. The Vg-Id curves of the thin-film transistor are shown in Figure 4(C), where the channel length L is 10 μm. 4(A) to 4(C) are the Vg-Id curves of the thin film transistor. The voltage is shown on a linear scale, and the vertical axis shows the drain current on a logarithmic scale.

[0343] The current-voltage characteristics were measured with a voltage between the source and drain of 10 V and a gate voltage of -20 The voltage was changed from 0V to 20V. The substrate temperature during the measurement was set at room temperature (25°C), 40°C, , 75℃, 100℃, 125℃, 150℃, 180℃, and each substrate temperature ( The current-voltage characteristics were measured at various temperatures (operating temperature). To make it easier to understand the relationship between the substrate temperature and the Vg-Id curve, the gate voltage is set to -10V to 1 Only the range where the voltage is 0V is shown.

[0344] Curves 201, 211, and 221 shown in FIGS. 4A to 4C are the substrates at the time of measurement. This shows the Vg-Id curve at room temperature (25°C). The substrate temperature rises during measurement. Therefore, the Vg-Id curve moves leftward in Figure 4, i.e., in the negative direction of Vg. The transistor is normally on. Although the Vg-Id curves are not marked, the curves 207 and 217 located at the leftmost Curve 227 is the Vg-Id curve when the substrate temperature during measurement is 180°C.

[0345] The threshold voltages were calculated from the Vg-Id curves obtained. Although not detailed, under all the measurement conditions mentioned above, the relative dielectric constant of the gate insulating layer was set to 4.1 The maximum value of the field-effect mobility calculated as 2 / Vs or higher has been achieved.

[0346] Here, the definition of Vth in this specification will be explained. The horizontal axis of FIG. 6 is the gate voltage is shown on a linear scale, and the vertical axis is the square root of the drain current (hereinafter referred to as √Id) The curve 501 shows the drain current versus the gate voltage. The square root of Id is the Id of the Vg-Id curve measured with Vd at 10 V. This is a curve expressed by the root (hereinafter also referred to as the √Id curve).

[0347] First, calculate the √Id curve (curve 501) from the Vg-Id curve measured with Vd set to 10 V. Next, a line passing through point 502 where Vg is 5 V on the √Id curve and point 503 where Vg is 20 V is drawn. Next, extend the line 504 and calculate Vg when Id becomes 0 A on the line 504. That is, the value of the intercept 505 between the line 504 and the gate voltage axis is defined as Vth.

[0348] FIG. 5A shows Vth calculated from the Vg-Id curves shown in FIGS. 4A to 4C. In FIG. 5(A), the TFT303 column shows a thin film transistor with a channel length L of 3 μm. The Vth of the thin film transistor with a channel length L of 5 μm is shown in the TFT305 column. The TFT310 column shows the Vth of a thin film transistor with a channel length L of 10 μm. The Vth fluctuation range is the maximum Vth value within the measurement temperature range of each thin-film transistor. The difference in minimum values ​​is shown.

[0349] FIG. 5(B) is a graph showing FIG. 5(A). The horizontal axis indicates the measured temperature. The vertical axis indicates the substrate temperature (operating temperature) when measuring the current-voltage characteristics of the transistor. The threshold voltage at the temperature is shown in FIG. This is the threshold value of a thin film transistor with a length L of 3 μm, and is indicated by a square in the figure. The threshold value 315 is the threshold value of a thin film transistor with a channel length L of 5 μm. The threshold value 320 indicated by "x" in the figure is the thickness of the thin film with the channel length L set to 10 μm. This is the threshold voltage of the film transistor.

[0350] The thin film transistor fabricated in this example exhibits a threshold voltage in an environment between room temperature and 180°C. It was confirmed that the fluctuation range of the voltage was 3V or less. [Example]

[0351] In this example, a thin film transistor is manufactured by the manufacturing method shown in Embodiment Mode 1. The results of evaluating the thin film transistor characteristics in an environment of 5°C to 150°C are shown.

[0352] In this example, a thin film having a channel length L of 3 μm and a channel width W of 50 μm is formed on the same substrate. A thin film transistor with a channel length L of 20 μm and a channel width W of 20 μm. The thin-film transistor characteristics were measured in an environment between -25°C and 150°C. First, a method for manufacturing a thin film transistor will be described.

[0353] First, a silicon oxynitride film with a thickness of 100 nm was formed on a glass substrate as an underlayer by the CVD method. A 150 nm thick tantalum film was formed on the silicon oxynitride film as a gate electrode layer by sputtering. The tungsten film was then selectively etched to form a gate electrode layer. was formed.

[0354] Next, a 100 nm thick silicon oxynitride film was formed on the gate electrode layer by CVD as a gate insulating layer. A bare film was formed.

[0355] Next, an In-Ga-Zn-O oxide semiconductor target (In2O3 :Ga2O3:ZnO=1:1:1) and the distance between the substrate and the target was set to 60 m. m, pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, argon and oxygen (argon: oxygen =30sccm:15sccm) atmosphere at room temperature (25℃), and a film with a thickness of 50nm was formed. Here, the oxide semiconductor layer was selectively etched to form island-shaped oxide A compound semiconductor layer was formed.

[0356] Next, the oxide semiconductor layer was subjected to first heat treatment at 450° C. for 1 hour in a nitrogen atmosphere.

[0357] Next, a titanium film (thickness 10 0 nm), an aluminum film (200 nm thick), and a titanium film (50 nm thick) were stacked. The conductive film was formed at room temperature (25°C) by sputtering. The source electrode layer and the drain electrode layer are formed by etching, and the channel length of the thin film transistor is The lengths L were set to 3 μm and 20 μm, and the channel widths W were set to 50 μm and 20 μm.

[0358] Next, a protective insulating layer with a thickness of 300 nm was formed by sputtering so as to contact the oxide semiconductor layer. The silicon oxide film was formed at 100° C. Here, the silicon oxide film, which is a protective layer, was selectively etched. Then, openings were formed over the gate electrode layer, the source electrode layer, and the drain electrode layer.

[0359] Next, an ITO film (thickness 110 nm) was formed as a measurement electrode layer by sputtering at room temperature (25 The measurement electrode layer was selectively etched to expose the electrode through the opening. The measurement electrode layer is electrically connected to the gate electrode layer, and the measurement electrode layer is electrically connected to the source electrode layer. A measurement electrode layer was formed to be electrically connected to the measurement electrode layer and the drain electrode layer. A second heat treatment was carried out at 250° C. for 1 hour in an atmosphere.

[0360] Through the above steps, a thin film transistor with a channel length L of 3 μm and a channel width W of 50 μm was fabricated. and a thin-film transistor with a channel length L of 20 μm and a channel width W of 20 μm. were fabricated on the same substrate.

[0361] Next, the current-voltage characteristics of each thin film transistor were measured. of the change in the voltage between the source and gate (hereinafter referred to as gate voltage or Vg) The change in the current flowing between the source and drain (hereafter referred to as drain current or Id) FIG. 34(A) shows the Vg-Id curves when the channel length L is 3 μm and the channel width W is 50 μm. 34(B) shows the Vg-Id curves of a thin film transistor with a channel length L of 2 μm. 3 shows the Vg-Id curves of a thin-film transistor with a gate voltage of 0 μm and a channel width W of 20 μm. In both Fig. 4(A) and Fig. 34(B), the horizontal axis represents the gate voltage on a linear scale, and the vertical axis shows the drain current in logarithmic scale.

[0362] The current-voltage characteristics were measured with a voltage between the source and drain of 10 V and a gate voltage of -20 The voltage was changed from -25°C to 20V. The substrate temperature during the measurement was set to -25°C, 0°C, room temperature ( 25℃), 40℃, 85℃, 100℃, 125℃, and 150℃, and each substrate The current-voltage characteristics were measured at various temperatures (operating temperatures). ) is set to the gate voltage to make it easier to understand the relationship between the substrate temperature and the Vg-Id curve during measurement. Only the range from -10 to 10V is shown.

[0363] The curves 251 and 261 shown in FIGS. 34(A) and 34(B) are the substrate temperatures at the time of measurement. The Vg-Id curves at -25°C are shown. As the substrate temperature increases during measurement, The Vg-Id curve shifts leftward in Figure 34, i.e., in the negative Vg direction. In particular, in FIG. 34(A), as the substrate temperature during measurement increases, the transistor Normally off (when Vg is 0V, Id hardly flows) to normally on To make the figure easier to read, all Vg-Id curves are labeled. The curves 258 and 268 located at the far left are not included in the graph, but the curves 258 and 268 are the curves at which the substrate temperature at the time of measurement is 1 This is the Vg-Id curve at 50°C.

[0364] In the negative Vg region of Figures 34(A) and 34(B), Id is 1×10 12 A The following values ​​were detected, but this is known to be noise mixed in during measurement. It should be noted that this noise does not affect the calculation of Vth.

[0365] From the obtained Vg-Id curves, the respective Vths were calculated in the same manner as in Example 1. .

[0366] FIG. 35(A) shows the Vt calculated from the Vg-Id curves shown in FIGS. 34(A) and 34(B). In FIG. 35(A), the TFT331 column shows that the channel length L is 3 μm, The Vth of a thin film transistor with a channel width W of 50 μm is The figure shows the Vth of a thin film transistor with a channel width W of 20 μm. The Vth fluctuation range is the maximum and minimum Vth values ​​within the measurement temperature range of each thin-film transistor. This shows the difference between

[0367] FIG. 35(B) is a graph showing FIG. 35(A). The horizontal axis indicates the measured temperature. The vertical axis indicates the substrate temperature (operating temperature) when measuring the current-voltage characteristics of the transistor. The threshold voltage at the substrate temperature is shown in the figure. The threshold voltage of a thin-film transistor with a channel length L of 3 μm and a channel width W of 50 μm is shown in Fig. The threshold value 342 indicated by the triangle in the middle is the threshold value when the channel length L is 20 μm and the channel width W is 2 This is the threshold value of a 0 μm thin-film transistor.

[0368] The thin film transistor fabricated in this example exhibits the following characteristics in an environment of -25°C or higher and 150°C or lower: It was confirmed that the fluctuation range of the threshold voltage was 2V or less. [Explanation of symbols]

[0369] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 input terminals 25 Input terminals 26 Output terminal 27 Output terminal 28 Thin-film transistor 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 36 transistors 37 Transistor 38 transistors 39 Transistor 40 transistors 41 Transistor 42 transistors 43 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 100 boards 101 gate electrode layer 102 Gate insulating layer 103 Oxide semiconductor layer 107 Protective insulation layer 110 Channel protection layer 150 Thin-Film Transistor 160 Thin-Film Transistor 170 Thin-Film Transistor 180 Thin-Film Transistor 201 Curve 207 Curve 211 Curve 217 Curve 221 Curve 227 Curve 251 Curve 258 curve 261 Curve 268 curve 303 TFT 305 TFT 310 TFT 313 Value 315 Value 320 Value 331 TFT 332 TFT 341 Value 342 Value 400 glass substrate 401 Oxidized nitride insulating layer 402 In-Ga-Zn-O oxide semiconductor layer 403 Analysis direction 411Oxygen ion intensity profile 412 Hydrogen concentration profile 413 Hydrogen concentration profile 501 curve 502 points 503 points 504 straight line 505 Intercept 580 board 581 Thin-film transistor 583 Insulating Film 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material 596 PCB 600 boards 601 Opposing substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate insulating film 616 Wiring 617 Capacitance wiring 618 Wiring 619 Wiring 620 insulating film 622 insulating film 623 Contact Hole 624 Pixel electrode layer 625 Slit 626 Pixel electrode layer 627 Contact Hole 628 TFT 629 TFT 630 Holding capacity section 631 Holding capacity section 636 Colored film 637 Planarization film 640 Counter electrode layer 641 Slit 644 Protrusion 646 Alignment Film 648 Alignment Film 650 LCD layer 651 Liquid crystal element 652 Liquid crystal element 690 Capacitance wiring 701 Gate electrode layer 702 Gate insulating layer 703 Channel 801 Glass substrate 802 gate electrode layer 803 Gate insulating layer 804 Oxide semiconductor layer 805 Source electrode layer 806 Drain electrode layer 811 Curve 818 curve 821 Curve 828 curve 831 curve 832 curve 833 curve 850 Thin Film Transistor 911 curve 918 curve 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 Thin Film Transistor 4011 Thin-film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4040 Conductive layer 4501 Circuit Board 4502 Pixel section 4505 Sealing material 4506 board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4541 Insulation layer 4544 Insulation layer 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin-film transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Light-emitting element driving transistor 6403 Capacitor element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7001 TFT 7002 Light-emitting element 7003 Cathode 7004 EL layer 7005 Anode 7009 Bulkhead 7011 TFT 7012 Light-emitting element 7013 Cathode 7014 EL layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7019 Bulkhead 7021 TFT 7022 Light-emitting element 7023 Cathode 7024 EL layer 7025 Anode 7026 Anode 7027 Conductive film 7029 Bulkhead 7031 Oxide insulating layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7041 Oxide insulating layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7051 Oxide insulating layer 7053 Planarization insulating layer 7055 Insulation layer 9201 Display section 9202 Display button 9203 Operation switch 9205 Adjustment part 9206 Camera Department 9207 Speaker 9208 Microphone 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Controlled Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section 105a Source electrode layer 105b drain electrode layer 4503a Signal line driver circuit 4504a Scanning line driver circuit 4518a FPC 4518b FPC 590a black area 590b White area 704a Drain electrode layer 704b Source electrode layer 705a N+ area 705b N+ region

Claims

[Claim 1] forming a gate electrode layer over a substrate having an insulating surface; forming a gate insulating layer on the gate electrode layer; forming an oxide semiconductor layer on the gate insulating layer; After the oxide semiconductor layer is formed, a first heat treatment is performed; forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer; forming a protective insulating layer on the gate insulating layer, the oxide semiconductor layer, the source electrode layer, and the drain electrode layer so as to be in contact with a part of the oxide semiconductor layer; After forming the protective insulating layer, a second heat treatment is performed; The second heat treatment is performed at a temperature lower than that of the first heat treatment; The first heat treatment is performed at a temperature of 350° C. or higher and 750° C. or lower, the first heat treatment is performed in a nitrogen atmosphere or a rare gas atmosphere; The second heat treatment is performed at a temperature of 100° C. or higher and the first heat treatment temperature or lower, a second heat treatment being performed in an air atmosphere, an oxygen atmosphere, a nitrogen atmosphere, or a rare gas atmosphere;

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