Semiconductor device

Abstract

To provide an SiC semiconductor device in which detection accuracy of a main current value by a current-sensing unit can be improved as a result of suppressing an escape of heat from the current-sensing unit to a wiring member bonded to a sensing-side surface electrode.SOLUTION: Provided is a semiconductor device 1 including: an SiC semiconductor substrate; a source unit 27 that includes a main current-side unit cell 34; a current-sensing unit 26 that includes a sensing-side unit cell 40; a source-side surface electrode 5 that is positioned above the source unit 27; and a sensing-side surface electrode 6 that is positioned above the current-sensing unit 26 and has a sensing-side pad 15 to which a sensing-side wire is bonded. The sensing-side unit cell 40 is positioned so as to avoid being located directly below the sensing-side pad 15.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a SiC semiconductor device having a current sensing unit. [Background technology]

[0002] BACKGROUND ART Conventionally, semiconductor devices that include a current sensing unit for detecting the current value of the main current of the device have been known, and for example, semiconductor devices disclosed in Patent Documents 1 and 2 have been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-46193 [Patent Document 2] Japanese Patent Application Publication No. 11-74370 Summary of the Invention [Problem to be solved by the invention]

[0004] The current sense section is generally formed with a smaller area than the source section through which the main current flows. The area ratio between the current sense section and the source section defines the sense ratio when detecting the main current. The current value of the main current is calculated by multiplying the current value actually flowing through the current sense section by the sense ratio.

[0005] If all conditions except for the area were the same, it might be possible to accurately detect the main current value simply by considering the sense ratio. However, in reality, there are differences in the conditions under which the current sense section and source section are placed, and these differences affect the detection accuracy.

[0006] For example, the source pad is relatively large, and the bonding wire occupies a small area relative to the pad, while the current sense pad is relatively small, and the bonding wire occupies a large area relative to the pad. This results in a difference in the amount of heat dissipated through the bonding wire, which can increase the error in the on-resistance between the source and current sense sections. This error in on-resistance affects the accuracy of detecting the main current value.

[0007] The object of the present invention is to provide a SiC semiconductor device that can improve the detection accuracy of the current value of the main current by the current sense section by suppressing heat loss from the current sense section to the wiring material joined to the sense-side surface electrode. [Means for solving the problem]

[0008] A semiconductor device according to one embodiment of the present invention includes a semiconductor layer made of SiC, a source section formed in the semiconductor layer and including a first unit cell on the main current side, a current sense section formed in the semiconductor layer and including a second unit cell on the current detection side, a source-side surface electrode arranged above the source section, and a sense-side surface electrode arranged so as to include at least a portion above the current sense section, and the second unit cell is arranged below the sense-side surface electrode and in a position that avoids an area directly below a joint portion of a wiring material.

[0009] According to this configuration, the second unit cell on the current detection side is positioned away from the area directly below the wiring connection. This allows a certain distance to be maintained between the second unit cell and the wiring, preventing heat generated in the second unit cell from being preferentially transferred to the wiring and dissipating. This reduces the error in on-resistance between the first unit cell in the source section and the second unit cell in the current sense section. Furthermore, because the second unit cell is not positioned directly below the wiring connection, the impact generated when joining the wiring to the sense-side surface electrode is prevented from being directly transmitted to the second unit cell, thereby preventing damage to the second unit cell. As a result, the current sense section can detect the main current with improved accuracy.

[0010] The use of a semiconductor layer made of SiC makes it possible to position the second unit cell in a position that avoids the area directly below the bonding portion of the wiring material. In other words, since a Si semiconductor device can only handle a small amount of current per unit area, a sense unit with a relatively large cell area is required to achieve an appropriate sense ratio (approximately 1000 to 2000) with high detection accuracy for a source unit with a large area through which a large current flows, making it difficult to form the second unit cell in a position that avoids the area directly below the source unit. In contrast, a SiC semiconductor device can handle a large amount of current per unit area, so an appropriate sense ratio can be achieved even with a sense unit with a small cell area relative to the source unit, making it possible to form the second unit cell in a position that avoids the area directly below the source unit.

[0011] The semiconductor device may include an interlayer insulating film arranged between the current sensing portion and the sense-side surface electrode, and a gate insulating film formed below the interlayer insulating film, and the interlayer insulating film may be formed thicker than the gate insulating film.

[0012] This configuration reduces the impact on the second unit cell when joining the wiring material to the sense-side surface electrode, thereby ensuring reliable detection accuracy of the main current value.

[0013] In the semiconductor device, the current sensing portion may be formed in a region surrounded by the source portion.

[0014] According to this configuration, the heat generation amount of the current sensing section can be brought closer to the source section, so that the error in the on-resistance caused by the difference in the heat generation amount can be reduced.

[0015] The semiconductor device may include a passivation film that selectively covers a portion of the sense-side surface electrode directly above the second unit cell and has an opening that exposes a portion of the sense-side surface electrode as a sense-side pad.

[0016] With this configuration, the area directly above the second unit cell and the sense-side pad are clearly distinguished from each other when viewed from the outside of the semiconductor device, which prevents the wiring from being mistakenly joined directly above the second unit cell, thereby ensuring a constant distance between the second unit cell and the wiring.

[0017] In the semiconductor device, the first unit cell and the second unit cell may have the same cell structure.

[0018] According to this configuration, the sense ratio for calculating the current value of the main current can be estimated from the cell ratio between the first unit cell and the second unit cell, making it easy to detect the current.

[0019] In the semiconductor device, the current sensing portion may be formed at only one location in an in-plane direction of the semiconductor layer.

[0020] This configuration makes it possible to reduce the space required for the surface portion of the semiconductor layer.

[0021] In the semiconductor device, the interlayer insulating film may have a thickness of 1 μm or more.

[0022] This configuration can provide the interlayer insulating film with sufficient impact resistance (for example, wire bonding resistance).

[0023] The semiconductor device may include a gate-side surface electrode disposed on the semiconductor layer and having a gate-side junction region to which a wiring material is bonded, and the interlayer insulating film may also be disposed directly below the gate-side junction region.

[0024] According to this configuration, the interlayer insulating film covering the source section and the gate section can be formed in the same process, thereby shortening the manufacturing process.

[0025] In the semiconductor device, the interlayer insulating film may include an SiO2 film, and the SiO2 film may contain P (phosphorus) or B (boron).

[0026] SiO2 films are easy to fabricate, and if the SiO2 film contains P (phosphorus) or B (boron), it can be reflowed after deposition. Reflowing makes it easy to flatten the interlayer insulating film (SiO2 film), making it easier to bond wiring materials, which can affect the heat dissipation of the current sensing section, as designed.

[0027] In the semiconductor device, the sense-side surface electrode may include an electrode having a laminated structure in which Ti, TiN, and AlCu are laminated in this order from the bottom.

[0028] According to this configuration, by forming the outermost surface of the sense-side surface electrode from AlCu, the electrode can be given sufficient impact resistance (for example, wire bonding resistance).

[0029] The semiconductor device may include a gate-side surface electrode arranged on the semiconductor layer, and a passivation film having an opening that exposes a portion of the sense-side surface electrode as a sense-side pad and an opening that exposes a portion of the gate-side surface electrode as a gate-side pad, and the sense-side pad and the gate-side pad may be formed in elongated shapes extending in the same direction.

[0030] According to this configuration, the wiring material can be extended and joined to the sense-side pad and the gate-side pad in the same direction, which makes it easy to wire when assembling the package. [Brief explanation of the drawings]

[0031] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged view of the area surrounded by the dashed line II in FIG. [Figure 3] FIG. 3 is an enlarged view of the area surrounded by the dashed line III in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. [Figure 5] FIG. 5 is an enlarged view of the periphery of the gate-side pad in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along the line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along the line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along the line VIII-VIII in FIG. [Figure 9] FIG. 9 is a circuit diagram for explaining current detection in the semiconductor device. [Figure 10] FIG. 10 is a flow chart showing the manufacturing process of the semiconductor device. [Figure 11] FIG. 11 is a diagram showing a modified example of the gate structure of the semiconductor device. [Figure 12] FIG. 12 is a diagram showing a modified example of the sense-side pad of the semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0033] FIG. 1 is a schematic plan view of a semiconductor device 1 according to one embodiment of the present invention.

[0034] The semiconductor device 1 includes a semiconductor substrate 2 that is an example of a semiconductor layer of the present invention and has a quadrangular shape in plan view. The semiconductor substrate 2 has four sides 3A, 3B, 3C, and 3D in plan view.

[0035] A plurality of surface electrode films 4 are formed on the semiconductor substrate 2, separated from one another. The plurality of surface electrode films 4 include a source-side surface electrode 5, a sense-side surface electrode 6, and a gate-side surface electrode 7. The source-side surface electrode 5 is formed in most of the area on the semiconductor substrate 2 (the hatched area in FIG. 1 and the area of ​​source-side pads 14A, 14B, 14B described later), and areas 8 and 9 where part of the source-side surface electrode 5 is removed are the areas where the sense-side surface electrode 6 and the gate-side surface electrode 7 are formed. Both of the removed areas 8 and 9 are formed and surrounded by the source-side surface electrode 5.

[0036] A passivation film 10 is formed on the semiconductor substrate 2, collectively covering the plurality of surface electrode films 4. The passivation film 10 has a plurality of pad openings 11, 12, and 13. The source-side surface electrode 5, the sense-side surface electrode 6, and the gate-side surface electrode 7 are exposed from the pad openings 11, 12, and 13 as source-side pads 14A and 14B, a sense-side pad 15, and a gate-side pad 16, respectively.

[0037] The source-side pads 14A, 14B are arranged in a plurality of locations, separated from one another. In FIG. 1, three source-side pads 14A, 14B, 14B are provided on the semiconductor substrate 2. One source-side pad 14A is arranged near one side 3A of the semiconductor substrate 2 in the center along the side 3A, and the remaining source-side pads 14B, 14B are arranged on both sides of the source-side pad 14A, one on each side. The source-side pads 14B on both sides have extensions 17, 17 that extend toward the opposite side 3C of the side 3A relative to the central source-side pad 14A. The extensions 17 face each other with a gap between them, and define a region 18 in which a gate-side pad 16 is arranged adjacent to the central source-side pad 14A. Although the multiple source-side pads 14A, 14B appear to be separated from one another, they are connected to one another as an integrated source-side surface electrode 5 below the passivation film 10 via the hatched region in FIG.

[0038] The sense-side pad 15 is disposed at only one corner of the rectangular semiconductor substrate 2. This allows space to be saved on the semiconductor substrate 2. The sense-side pad 15 is formed in an elongated shape along the sides 3B and 3D of the semiconductor substrate 2, and is surrounded by one of the source-side pads 14B on both sides. As shown in FIG. 1, the sense-side pad 15 may be surrounded partly by the source-side pad 14B, or the entire periphery thereof may be surrounded by the source-side pad 14B (not shown).

[0039] The gate-side pad 16 is disposed in a region 18 between the source-side pads 14B, 14B facing each other. Similar to the sense-side pad 15, the gate-side pad 16 is formed in an elongated shape along the sides 3B, 3D of the semiconductor substrate 2.

[0040] The gate-side surface electrode 7 further includes a gate finger 19 extending from the gate-side pad 16. The gate finger 19 is covered with a passivation film 10. The gate finger 19 includes a central portion 20 extending from one side 3C of the semiconductor substrate 2 toward the opposite side 3A so as to penetrate through the center of the source-side surface electrode 5, and a peripheral portion 21 extending along the periphery of the semiconductor substrate 2 (sides 3B, 3C, and 3D in FIG. 1 ) and surrounding the source-side surface electrode 5.

[0041] A source-side wire 22, a sense-side wire 23, and a gate-side wire 24 are connected to the source-side pads 14A and 14B, the sense-side pad 15, and the gate-side pad 16, respectively. For example, aluminum wires are used as the wires 22 to 24. Aluminum wires are typically bonded using elongated wedge bonding rather than ball bonding. Therefore, as shown in FIG. 1, if the sense-side pad 15 and the gate-side pad 16 are shaped to be elongated in the same direction, the wires 23 and 24 can be extended and bonded to the sense-side pad 15 and the gate-side pad 16 in the same direction. This facilitates wiring during package assembly.

[0042] Furthermore, the diameters of the wires 22 to 24 may be, for example, 300 μm to 500 μm for the source side wire 22, and 100 μm to 200 μm for the sense side wire 23 and the gate side wire 24.

[0043] The wiring material connecting the source side pads 14A, 14B, the sense side pad 15, and the gate side pad 16 to the outside does not have to be a bonding wire, but may be other wiring material such as a bonding plate or a bonding ribbon.

[0044] FIG. 2 is an enlarged view of the area surrounded by the dashed line II in FIG.

[0045] As shown in Fig. 2, the sense-side surface electrode 6 is formed in a rectangular shape in a plan view, but in appearance, a part (one corner in Fig. 2) is covered with a passivation film 10 and is exposed as a sense-side pad 15 having a substantially rectangular shape in a plan view. The length L1 of the long side and the length L2 of the short side of the sense-side pad 15 are preferably 1.2 mm or less and 0.6 mm or less, respectively. This allows the size of the sense-side pad 15 to be reduced to 0.72 mm. 2 or less, it is possible to suppress an increase in the on-resistance of the sense side unit cell 40 (described later). Also, by making the length L1 of the long side about twice the length L2 of the short side to form an elongated sense side pad 15, it is possible to easily join a bonding wire (sense side wire 23) by wedge bonding.

[0046] The region 25 covered with the passivation film 10 is formed in a rectangular shape in a plan view, with one short side and one long side constituting extensions of the short side and long side of the sense-side pad 15, respectively. Note that the covered region 25 does not need to be rectangular in a plan view, and may have other shapes (for example, a square, a circle, a triangle, etc.). Of course, its position does not need to be at a corner of the sense-side surface electrode 6, and may be, for example, halfway along a side of the sense-side surface electrode 6.

[0047] A current sense section 26 as an assembly of a large number of sense-side unit cells 40 (described later) is formed directly below the covering region 25. On the other hand, the current sense section 26 is not formed directly below the sense-side pad 15. In other words, in this embodiment, the entire current sense section 26 is formed at a position that avoids the area directly below the sense-side pad 15.

[0048] Meanwhile, a source section 27 is formed as an assembly of a large number of main current side unit cells 34 (described later) around the sense side surface electrode 6. The source section 27 is formed directly below the source side surface electrode 5 so as to surround the sense side surface electrode 6 in plan view. Although not shown, the source section 27 may be formed directly below the entire source side surface electrode 5 shown in FIG. 1.

[0049] FIG. 3 is an enlarged view of the area surrounded by dashed line III in FIG. 2. FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. 3. FIG. 5 is an enlarged view of the periphery of the gate-side pad 16 in FIG. 1. FIG. 6 is a cross-sectional view taken along the line VI-VI in FIG. 5. FIG. 7 is a cross-sectional view taken along the line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view taken along the line VIII-VIII in FIG. 5. Note that FIG. 4 omits some of the horizontally repeated portions of FIG. 3.

[0050] 4 and 6 to 8, the semiconductor substrate 2 may be a SiC epitaxial substrate including a base substrate 28 and an epitaxial layer 29 on the base substrate 28. In this embodiment, the semiconductor substrate 2 is an n + A base substrate 28 made of type SiC (for example, with a concentration of 1×10 17 cm -3 ~1×10 19 cm -3 ) and n - An epitaxial layer 29 made of type SiC (for example, with a concentration of 1×10 14 cm -3 ~1×10 17 cm -3 ) and

[0051] n - The surface of the epitaxial layer 29 is - Mold well 30 (for example, concentration 1 x 10 14 cm -3 ~1×10 19 cm -3 ) is formed. - The well 30 is a main current side p - Type body well 31, sense side p - Type body well 32 and gate side p - The main current side p - Type body well 31 and sense side p - The mold body wells 32 are formed separately from each other as shown in FIG. - As shown in FIG. 6, the type well 33 is- The mold body well 31 is connected to the mold body well 31.

[0052] Main current side p - The mold body well 31 includes a cell forming portion 35 that constitutes a main current side unit cell 34, which is an example of a first unit cell of the present invention, and a relatively wide field forming portion 36. In other words, each cell forming portion 35 defines a main current side unit cell 34, which is the smallest unit through which a main current flows.

[0053] As shown in FIGS. 3 and 5, a large number of cell formation portions 35 are arranged in a matrix, thereby forming the source portion 27.

[0054] The field forming portion 36 is formed so as to surround a large number of the cell forming portions 35, and connects the adjacent cell forming portions 35 across the outer periphery of the source portion 27.

[0055] Main current side p - The mold body well 31 further includes a connection portion 37 formed at the intersection of a lattice region defined by the matrix of cell forming portions 35. The connection portion 37 connects adjacent cell forming portions 35 inside the source portion 27.

[0056] In this way, the cell forming portions 35 are electrically connected to each other on the outer periphery and inside of the source portion 27 by the field forming portions 36 and the connecting portions 37. This allows the many cell forming portions 35 to be held at the same potential.

[0057] In the inner region of the cell forming portion 35, + The n-type source region 38 is formed. + type source region 38 (e.g., concentration 1×10 17 cm -3 ~1×10 21 cm -3 ) in the inner region of p + The body contact region 39 (for example, the concentration is 1×10 17 cm -3 ~1×10 21 cm -3) is formed.

[0058] Sense side p - The mold body well 32 includes a cell formation portion 41 that constitutes a sense side unit cell 40 as an example of the second unit cell of the present invention, and a relatively wide field formation portion 42. In other words, each cell formation portion 41 defines a sense side unit cell 40, which is the smallest unit through which a main current flows.

[0059] 3, a large number of cell formation portions 41 are arranged in a matrix at positions avoiding the area directly below the sense-side pad 15, thereby forming the current sense portion 26. The cell formation portions 41 have the same cell structure (size and pitch) as the cell formation portion 35 on the main current side.

[0060] The field forming portion 42 is formed so as to surround a large number of cell forming portions 41, and connects adjacent cell forming portions 41 across the outer periphery of the current sensing portion 26.

[0061] Sense side p - The mold body well 32 further includes a connection portion 43 formed at the intersection of a lattice region defined by the matrix of cell forming portions 41. The connection portion 43 connects adjacent cell forming portions 41 inside the current sensing unit 26.

[0062] In this way, the cell formation portions 41 are electrically connected to each other on the outer periphery and inside of the current sense portion 26 by the field formation portions 42 and the connection portions 43. This allows the large number of cell formation portions 41 to be held at the same potential.

[0063] In the inner region of the cell forming portion 41, + source region 44 (e.g., concentration 1×10 17 cm -3 ~1×10 21 cm -3 ) is formed, and this n + The inner region of the source region 44 is p + The body contact region 45 (for example, the concentration is 1×10 17cm -3 ~1×10 21 cm -3 ) is formed.

[0064] The field formation portion 42 is formed to extend from the outer periphery of the cell formation portion 41 to the area directly below the sense-side pad 15. In this embodiment, the field formation portion 42 extends over the entire area directly below the sense-side pad 15. That is, in FIG. 2 , the field formation portion 42 is formed over the entire area directly below the sense-side surface electrode 6, which has a generally rectangular shape in plan view, excluding the covering region 25.

[0065] Also, the surface of the field forming portion 42 directly below the sense side pad 15 is + Mold region 46 (for example, concentration is 1 × 10 17 cm -3 ~1×10 21 cm -3 ) is formed. + The p-type region 46 is directly connected to the sense-side surface electrode 6. + By forming the mold region 46, the potential directly below the sense-side pad 15 can be stably maintained at the same potential.

[0066] As shown in Figure 6, the gate side p - The mold well 33 is formed directly below the gate-side pad 16. - The surface of the mold well 33 is + Mold region 47 (for example, concentration is 1 × 10 17 cm -3 ~1×10 21 cm -3 ) is formed.

[0067] A gate insulating film 48 is formed on the semiconductor substrate 2, and a gate electrode 49 is formed on this gate insulating film 48. The gate insulating film 48 is made of, for example, silicon oxide (SiO2), and the gate electrode 49 is made of, for example, polysilicon.

[0068] The gate electrode 49 is formed along a lattice region defined by the matrix of unit cells 34, 40 in the current sense section 26 and the source section 27, and includes a functional section 52 that spans adjacent unit cells 34, 40. As a result, the gate electrode 49 faces the channel regions 50, 51 of each unit cell 34, 40 via the gate insulating film 48. The channel regions 50, 51 are p - In the cell forming portions 35, 41 of the mold body wells 31, 32, n + The outer regions of the source regions 38 and 44.

[0069] 4, the gate electrode 49 includes a functional portion 52 facing the channel regions 50, 51 of each unit cell 34, 40, as well as a connecting portion 53. The connecting portion 53 traverses the removed region 8 between the source-side surface electrode 5 and the sense-side surface electrode 6 below the surface electrode film 4, and extends across the current sense portion 26 and the source portion 27. The connecting portion 53 ensures electrical connection between the functional portions 52 of the current sense portion 26 and the source portion 27. In other words, the gate electrode 49 serves as a common electrode between the current sense portion 26 and the source portion 27.

[0070] 7 and 8, the gate electrode 49 is connected to the gate-side surface electrode 7 at the gate finger 19 of the semiconductor device 1. That is, the gate electrode 49 is formed to extend from the source portion 27 downwardly of the gate finger 19, and has a contact portion 62 directly below the gate finger 19. As a result, the gate voltage applied to the gate-side pad 16 is also applied to the gate electrode 49 of the current sense portion 26 via the contact portion 62 (FIG. 7) and the connection portion 53 (FIG. 4).

[0071] The gate insulating film 48 is disposed below the gate electrode 49 to ensure insulation between the gate electrode 49 and the semiconductor substrate 2, and in this embodiment, is also formed directly below the sense-side pad 15 and the gate-side pad 16. This gate insulating film 48 is configured with an extension portion continuing to the gate insulating film 48 directly below the functional portion 52 of the gate electrode 49, as shown in FIGS.

[0072] An interlayer insulating film 54 is formed on the semiconductor substrate 2 to cover the gate electrode 49. The interlayer insulating film 54 is made of, for example, silicon oxide (SiO2), and preferably contains P (phosphorus) or B (boron). That is, the interlayer insulating film 54 may be BPSG (boron phosphorus silicon glass) or PSG (phosphorus silicon glass). An SiO2 film is easy to fabricate, and if the SiO2 film contains P (phosphorus) or B (boron), it can be reflowed after deposition. Because the interlayer insulating film 54 (SiO2 film) can be easily planarized by reflow, it becomes easier to bond the sense side wire 23, which can affect the heat dissipation performance of the current sense unit 26, as designed.

[0073] The interlayer insulating film 54 integrally includes a first portion 55 that covers the gate electrode 49 in the current sense section 26 and the source section 27, a second portion 56 that is disposed directly below the sense-side pad 15, and a third portion 57 that is disposed directly below the gate-side pad 16. By thickening the interlayer insulating film 54 directly below the sense-side pad 15 and the gate-side pad 16, it is possible to provide the interlayer insulating film 54 with sufficient impact resistance (for example, wire bonding resistance).

[0074] The surface electrode film 4 (the source-side surface electrode 5, the sense-side surface electrode 6, and the gate-side surface electrode 7) is formed on the interlayer insulating film 54. The source-side surface electrode 5 penetrates the interlayer insulating film 54 and the gate insulating film 48. + type source region 38 and p + The sense-side surface electrode 6 is connected to the n-type body contact region 39. The n-type body contact region 39 is connected to the n-type body contact region 39. The sense-side surface electrode 6 penetrates the interlayer insulating film 54 and the gate insulating film 48. + type source region 44 and p + The gate electrode 49 is connected to the body contact region 45. The gate-side surface electrode 7 (gate finger 19) penetrates the interlayer insulating film 54 and is connected to the gate electrode 49.

[0075] The surface electrode film 4 may also be an electrode film having a laminated structure in which Ti, TiN, and AlCu are laminated in this order from the bottom (semiconductor substrate 2 side). By making the top surface of the surface electrode film 4 AlCu, the electrode film 4 can be endowed with sufficient impact resistance (for example, wire bonding resistance) compared to when Al is used.

[0076] A passivation film 10 is formed on the front electrode film 4. The passivation film 10 may be made of, for example, silicon nitride (SiN). As described above, the pad openings 11 to 13 are formed in the passivation film 10.

[0077] A drain electrode 58 is formed on the back surface of the semiconductor substrate 2. The drain electrode 58 may be an electrode film having a laminated structure in which Ti, Ni, Au, and Ag are laminated in this order from the semiconductor substrate 2 side. The drain electrode 58 is also a common electrode between the current sensing unit 26 and the source unit 27.

[0078] Next, a method of detecting a current in the semiconductor device 1 will be described as an example with reference to Fig. 9. Fig. 9 is a circuit diagram for explaining current detection in the semiconductor device 1.

[0079] 9, the semiconductor device 1 includes a source section 27 on the main current side and a current sense section 26 on the current detection side within a single chip. A detection resistor 59 is connected to the source S of the current sense section 26. The detection resistor 59 may be incorporated into a module when the semiconductor device 1 is incorporated into the module, or may be incorporated inside the semiconductor device 1. As described above, the gate G and drain D are common to the current sense section 26 and the source section 27.

[0080] When a voltage equal to or greater than the threshold is applied to the gate G while a voltage is applied between each source S and drain D, a current flows between the source S and drain D, and the semiconductor device 1 is turned on. As a result, a detection current I SENSEflows through the source 27, while the main current I MAIN is playing.

[0081] Main current I MAIN Whether or not a short circuit current is detected is determined by the voltage V across the detection resistor 59. SENSE The resistance R of the detection resistor 59 is monitored to determine whether it exceeds a certain threshold. SENSE Since is constant, the voltage V SENSE is the detected current I SENSE Therefore, the voltage V SENSE exceeds the threshold, it means that the detection current I SENSE This means that the main current I is flowing, and the main current value I is calculated based on the sense ratio between the current sense unit 26 and the source unit 27. MAIN This also indicates that it is excessive.

[0082] In the above detection method, the actual main current I MAIN and the detected current I SENSE The main current I is calculated by multiplying the sense ratio by MAIN If these conditions match, the short circuit detection can be performed with high accuracy, and the gate voltage can be cut off at an appropriate timing.

[0083] 1, the source-side pads 14A and 14B are relatively large, and the area occupied by the source-side wire 22 relative to the pads 14A and 14B is small, while the sense-type pad 15 is relatively small, and therefore the area occupied by the sense-side wire 23 relative to the pad 15 is large. This causes a difference in the amount of heat escape via the wires 22 and 23, which may increase the error in the on-resistance between the source section 27 and the current sense section 26. As a result, in reality, the main current I MAIN Although there is no short circuit current, an excessive detection current I SENSE In this case, short circuit detection is based solely on the voltage V of the detection resistor 59 on the current detection side. SENSE Therefore, there is a risk that a short circuit will be detected even when it is not necessary, and the gate voltage will be cut off.

[0084] Therefore, according to the semiconductor device 1, as shown in FIG. 2, the current sense unit 26 is positioned away from the area directly below the sense-side pad 15. This allows a certain distance to be maintained between the current sense unit 26 and the sense-side wire 23 when the sense-side wire 23 (FIG. 1) is connected to the sense-side pad 15, thereby preventing heat generated in the current sense unit 26 from being preferentially transferred to the sense-side wire 23 and dissipating. This reduces the error in the on-resistance between the main-current-side unit cell 34 of the source unit 27 and the sense-side unit cell 40 of the current sense unit 26. Furthermore, because the current sense unit 26 is not positioned directly below the sense-side pad 15, the impact of connecting the sense-side wire 23 to the sense-side pad 15 is prevented from being directly transmitted to the current sense unit 26, thereby preventing damage to the current sense unit 26. As a result, the accuracy of detecting the current value of the main current by the current sense unit 26 can be improved.

[0085] The use of a semiconductor substrate 2 made of SiC makes it possible to position the current sense unit 26 in a position that avoids the area directly below the sense-side pad 15. In other words, in a Si semiconductor device, the amount of current that can flow per unit area is small, and therefore a sense unit with a fairly large cell area is required to achieve an appropriate sense ratio (approximately 1000 to 2000) with high detection accuracy for a source unit with a large area through which a large current flows, making it difficult to form the current sense unit in a position that avoids the area. In contrast, in a SiC semiconductor device, the amount of current that can flow per unit area is large, and therefore an appropriate sense ratio can be ensured even with a sense unit with a small cell area relative to the source unit, making it possible to form the current sense unit in a position that avoids the area.

[0086] 3, in this embodiment, the current sense unit 26 is surrounded by the source unit 27, so the amount of heat generated by the current sense unit 26 can be brought closer to that of the source unit 27. This makes it possible to reduce errors in on-resistance that occur due to differences in the amount of heat generated.

[0087] 2, in this embodiment, the entire current sense section 26 is covered with the covering region 25 of the passivation film 10, and the area directly above the current sense section 26 and the sense-side pad 15 are clearly distinguished when viewed from the outside of the semiconductor device 1. This prevents the sense-side wire 23 from being erroneously joined directly above the current sense section 26. A constant distance can be reliably maintained between the current sense section 26 and the sense-side wire 23.

[0088] 4 and 5, in this embodiment, the interlayer insulating film 54 has a relatively thick (for example, 1 μm or more) second portion 56 directly below the sense-side pad 15. This can reduce the impact transmitted to the current sensing unit 26 when the sense-side wire 23 is joined to the sense-side pad 15. As a result, it is possible to ensure the reliability of the detection accuracy of the current value of the main current.

[0089] Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIG.

[0090] For example, first, by epitaxial growth, n + On the base substrate 28 - A type epitaxial layer 29 is formed to form a semiconductor substrate 2 (step S1).

[0091] Next, p-type impurity ions are selectively implanted into the surface of the semiconductor substrate 2, thereby forming p - A mold well 30 is formed (step S2).

[0092] Next, n-type impurity ions are selectively implanted into each of the cell formation portions 35 and 41, thereby forming n + The source regions 38 and 44 are formed (step S3).

[0093] Next, p - p-type impurity ions are selectively implanted into the p-type well 30, + The body contact regions 39, 45 and p +Mold regions 46 and 47 are formed (step S4).

[0094] Next, the gate insulating film 48 is formed on the surface of the semiconductor substrate 2 by, for example, thermal oxidation (step S5).

[0095] Next, polysilicon is deposited on the semiconductor substrate 2 by, for example, CVD, and is patterned to form the gate electrode 49 (step S6).

[0096] Next, an interlayer insulating film 54 is formed on the semiconductor substrate 2 by, for example, CVD (step S7).

[0097] Next, after contact holes are formed through the interlayer insulating film 54 and the gate insulating film 48, the surface electrode film 4 is formed by, for example, sputtering (steps S8 and S9).

[0098] Next, a passivation film 10 is formed to cover the surface electrode film 4, and then pad openings 11, 12, and 13 are formed by patterning (steps S10 and S11).

[0099] In this way, the above-described semiconductor device 1 is obtained.

[0100] Although the embodiment of the present invention has been described above, the present invention can be embodied in other forms.

[0101] For example, the gate structure of the semiconductor device 1 is not limited to the planar gate structure shown in Fig. 4, but may also be a trench gate structure as shown in Fig. 11. In the trench gate structure, a gate trench 60 is formed in the semiconductor substrate 2, and a gate electrode 49 is embedded therein. In this case, since the gate electrode 49 does not protrude above the semiconductor substrate 2, the first portion 55 and the second portion 56 of the interlayer insulating film 54 may have the same thickness.

[0102] 2 in which the current sense unit 26 is entirely covered with the passivation film 10, but may be only partially covered with the passivation film 10 as shown in Fig. 12. In this case, the current sense unit 26 partially overlaps directly below the sense-side pad 15, but the bonding region 61 of the sense-side wire 23 in the sense-side pad 15 may be virtually set at a position that avoids the current sense unit 26. In other words, the sense-side bonding region of the present invention does not necessarily have to coincide with the sense-side pad 15.

[0103] In addition, various design modifications can be made within the scope of the claims.

[0104] This application corresponds to Patent Application No. 2015-247727 filed with the Japan Patent Office on December 18, 2015, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0105] 1. Semiconductor device 2. Semiconductor substrate 4 Surface electrode film 5. Source side surface electrode 6 Sense side surface electrode 7 Gate side surface electrode 10 Passivation film 12 Pad opening 15 Sense side pad 23 Sense side wire 26 Current sense section 27 Source Section 34 Main current side unit cell 40 Sense side unit cell 54 Interlayer insulating film 55 Part 1 56 Part 2 57 Part 3 61 Joint area

Claims

1. a semiconductor chip having a first surface and a second surface; a first element portion formed on the first surface side of the semiconductor chip and including a first unit cell on a main current side; a current sensing section formed on the first surface side of the semiconductor chip and including a second unit cell on a current detection side; a first element side surface electrode disposed above the first element portion; a sense-side surface electrode having a generally rectangular shape in a plan view, the surface electrode being disposed so as to include at least a portion above the current sense unit; a first element side wiring member joined to the first element side surface electrode; a sense-side wiring member that is disposed at a position avoiding an area above the current sense unit, that is joined to the sense-side surface electrode, and that is thinner than the first element-side wiring member; a passivation film selectively covering a portion of the sense-side surface electrode directly above the second unit cell and having a first opening that exposes a portion of the sense-side surface electrode as a sense-side pad, the second unit cell is disposed below the sense-side surface electrode and at a position that avoids a position directly below a joint portion of the sense-side wiring material, The semiconductor device, wherein the sense-side pads are arranged along a first periphery of the semiconductor chip.

2. 2. The semiconductor device according to claim 1, wherein said current sensing portion is smaller than said sense-side pad.

3. 3. The semiconductor device according to claim 1, wherein the sense-side wiring member is shorter than the first element-side wiring member.

4. 4. The semiconductor device according to claim 1, wherein the sense-side wiring material and the first element-side wiring material extend in different directions from the semiconductor chip.

5. an interlayer insulating film disposed between the current sensing section and the sense-side surface electrode; a surface insulating film formed below the interlayer insulating film, 5. The semiconductor device according to claim 1, wherein said interlayer insulating film is formed to be thicker than said surface insulating film.

6. 6. The semiconductor device according to claim 1, wherein the current sensing portion is formed in a region surrounded by the first element portion.

7. 7. The semiconductor device according to claim 1, wherein the first unit cell and the second unit cell have the same cell structure.

8. 8. The semiconductor device according to claim 1, wherein the current sensing section is formed at only one location in an in-plane direction of the semiconductor chip.

9. 6. The semiconductor device according to claim 5, wherein said interlayer insulating film has a thickness of 1 [mu]m or more.

10. the first element unit and the current sense unit are switching elements having control terminals, the semiconductor device includes a control terminal-side surface electrode disposed on the semiconductor chip and having a control terminal-side bonding region to which a wiring material is bonded; 10. The semiconductor device according to claim 5, wherein the interlayer insulating film is also disposed directly below the control terminal side junction region.

11. The interlayer insulating film is made of SiO ２ 11. The semiconductor device of claim 5, 9 or 10, comprising a film.

12. The SiO ２ 12. The semiconductor device according to claim 11, wherein the film contains P (phosphorus).

13. The SiO ２ 12. The semiconductor device according to claim 11, wherein the film contains B (boron).

14. 14. The semiconductor device according to claim 1, wherein the sense-side surface electrode includes an electrode having a laminated structure in which Ti, TiN, and AlCu are laminated in this order from the bottom.

15. the first element unit and the current sense unit are switching elements having control terminals, at least one of the first element unit and the current sense unit includes a control terminal side surface electrode disposed on the semiconductor chip; the passivation film has a second opening that exposes a part of the control terminal side surface electrode as a control terminal side pad; 10. The semiconductor device according to claim 1, wherein the sense-side pad and the control-terminal-side pad are formed in a shape elongated in the same direction.

16. 16. The semiconductor device according to claim 1, wherein the sense-side pad is formed in a rectangular shape in plan view, with long sides of 1.2 mm or less and short sides of 0.6 mm or less.

17. the sense-side surface electrode is a covered region, a part of which is covered with the passivation film, the covering region is formed in an inner region of the sense-side surface electrode so as to have short sides and long sides that form part of short sides and long sides of the sense-side surface electrode in a plan view, 4. The semiconductor device according to claim 1, wherein the current sensing section is formed directly below the covering region.

18. 18. The semiconductor device according to claim 1, wherein the sense-side wiring material has a diameter of 100 μm to 200 μm.

19. the first element side wiring member is made of a first wire, 19. The semiconductor device according to claim 1, wherein the sense side wiring material is a second wire.

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