Semiconductor device

Abstract

To provide a semiconductor device in which the reliability of a gate insulating layer is improved.SOLUTION: A semiconductor device in an embodiment includes a first electrode, a second electrode, and a semiconductor layer having a first surface and a second surface and existing between the first electrode and the second electrode. The semiconductor layer includes a plurality of first trenches and a second trench that is adjacent to the first trench existing at the outermost end part. The semiconductor device includes a first gate electrode having a first length in the first trench, a second gate electrode, in the second trench, having a second length on the first trench side that is larger than a third length on the opposite side of the first trench, a first gate insulating layer with a first thickness between the first gate electrode and the semiconductor layer, a second gate insulating layer with a second thickness between the second gate electrode and the semiconductor layer on the first trench side, and a third gate insulating layer with a third thickness larger than the second thickness between the second gate electrode and the semiconductor layer on the opposite side of the first trench.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] One example of a power semiconductor device is a vertical trench-gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in which a source electrode and a drain electrode are provided above and below a semiconductor layer, and a gate electrode is provided in a trench. In a vertical trench-gate MOSFET, electric field concentration occurs in the outermost trenches of multiple trenches arranged parallel to each other. This electric field concentration poses a problem for the reliability of the gate insulating layer provided in the outermost trenches. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 1,121,7689 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device in which the reliability of the gate insulating layer is improved. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes a semiconductor layer having a first electrode, a second electrode, a first surface provided between the first electrode and the second electrode and facing the first electrode, and a second surface provided between the first electrode and the second electrode, the semiconductor layer including a plurality of first trenches provided on the side of the first surface, extending in a first direction parallel to the first surface, and repeatedly arranged in a second direction parallel to the first surface and perpendicular to the first direction; and a first trench provided on the side of the first surface, extending in the first direction, and a first trench located at an end of the plurality of first trenches in the second direction. a semiconductor layer including: second trenches adjacent to each other in a second direction; a first semiconductor region of a first conductivity type electrically connected to the second electrode; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface and between the two first trenches; and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface and between the two first trenches and electrically connected to the first electrode; and a semiconductor layer including: a first semiconductor region of a first conductivity type provided in the first trench and extending along a first length in a third direction perpendicular to the first direction and the second direction; a first gate electrode having a length in the third direction of a portion on the side of the first trench that is greater than a third length in the third direction of a portion on the opposite ... a first gate insulating layer having a first thickness, a first field plate insulating layer provided between the first field plate electrode and the semiconductor layer, a first inter-electrode insulating layer provided between the first gate electrode and the first field plate electrode, a second gate insulating layer having a second thickness provided between the second gate electrode and the semiconductor layer on the side of the first trench, and a third gate insulating layer having a third thickness that is thicker than the second thickness and provided between the second gate electrode and the semiconductor layer on the side opposite to the first trench;a second field plate insulating layer provided between the second field plate electrode and the semiconductor layer, and a second inter-electrode insulating layer provided between the second gate electrode and the second field plate electrode. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic diagram of a semiconductor device according to an embodiment; [Figure 2] FIG. 2 is a schematic cross-sectional view of a part of the semiconductor device according to the embodiment. [Figure 3] FIG. 2 is a schematic top view of a part of the semiconductor device according to the embodiment. [Figure 4] FIG. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the embodiment. [Figure 5] FIG. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the embodiment. [Figure 6] 3A to 3C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 3A to 3C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 3A to 3C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 3A to 3C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 3A to 3C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] 3A to 3C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 3A to 3C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] FIG. 10 is a schematic cross-sectional view of a portion of a semiconductor device according to a first comparative embodiment. [Figure 14] FIG. 10 is a schematic cross-sectional view of a portion of a semiconductor device according to a second comparative embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0008] In this specification, n + shape, n shape, n - When there is a notation with form, n + shape, n shape, n - This means that the n-type impurity concentration decreases in the order of the p + shape, p shape, p - If there is a form notation, p + shape, p shape, p - This means that the p-type impurity concentration decreases in the order of the type.

[0009] The impurity concentration of a semiconductor device can be measured by, for example, secondary ion mass spectrometry (SIMS). The relative level of the impurity concentration of a semiconductor device can also be determined from the level of the carrier concentration determined by, for example, scanning capacitance microscopy (SCM). Distances such as the width and depth of an impurity region of a semiconductor device can be determined by, for example, SIMS. Distances such as the width and depth of an impurity region of a semiconductor device can also be determined from, for example, an SCM image.

[0010] Qualitative and quantitative analysis of the chemical composition of the components constituting the semiconductor device herein can be performed by, for example, SIMS, energy dispersive X-ray spectroscopy (EDX), or Rutherford backscattering spectroscopy (RBS). Furthermore, for example, a scanning electron microscope (SEM) or a transmission electron microscope (TEM) can be used to measure the thickness of the components constituting the semiconductor device, the distance between the components, and the like.

[0011] The semiconductor device of the embodiment includes a first electrode, a second electrode, and a semiconductor layer provided between the first electrode and the second electrode, the semiconductor layer having a first surface facing the first electrode and a second surface facing the second electrode. The semiconductor layer includes: a plurality of first trenches provided on the first surface side, extending in a first direction parallel to the first surface, and repeatedly arranged in a second direction parallel to the first surface and perpendicular to the first direction; a second trench provided on the first surface side, extending in the first direction, and adjacent in the second direction to a first trench located at an endmost position in the second direction among the plurality of first trenches; a first semiconductor region of a first conductivity type electrically connected to a second electrode; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface and between the two first trenches; and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface, between the two first trenches, and electrically connected to the first electrode. The semiconductor device includes a first gate electrode provided in a first trench and having a first length in a third direction perpendicular to the first direction and the second direction; a first field plate electrode provided in the first trench and between the first gate electrode and a second surface; a second gate electrode provided in a second trench, the second length in the third direction of a portion on the first trench side being greater than the third length in the third direction of a portion on an opposite side to the first trench; a second field plate electrode provided in the second trench and between the second gate electrode and the second surface; a first gate insulating layer provided between the first gate electrode and a semiconductor layer and having a first thickness; The semiconductor device comprises: a first field plate insulating layer provided between the first field plate electrode and the semiconductor layer; a first inter-electrode insulating layer provided between the first gate electrode and the first field plate electrode; a second gate insulating layer having a second thickness provided between the second gate electrode and the semiconductor layer on the side of the first trench; a third gate insulating layer having a third thickness that is thicker than the second thickness provided between the second gate electrode and the semiconductor layer on the opposite side of the first trench; a second field plate insulating layer provided between the second field plate electrode and the semiconductor layer; and a second inter-electrode insulating layer provided between the second gate electrode and the second field plate electrode.

[0012] The following description will be given taking as an example a case where the first conductivity type is n-type and the second conductivity type is p-type, that is, an n-channel MOSFET in which electrons are carriers.

[0013] The semiconductor device of the embodiment is a MOSFET 100. The MOSFET 100 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0014] In this specification, a trench is a groove-shaped or recessed structure that the semiconductor layer itself has, and a structure other than the semiconductor layer can be provided inside the trench. The trench is a part of the semiconductor layer.

[0015] 1(a) and 1(b) are schematic diagrams of a semiconductor device according to an embodiment of the present invention, in which Fig. 1(a) is a top view of a MOSFET 100, and Fig. 1(b) is a bottom view of the MOSFET 100.

[0016] 1(a), a source electrode 10, a gate electrode pad 12, and a gate electrode wiring 12x are provided on the surface side of the MOSFET 100. The gate electrode wiring 12x is connected to the gate electrode pad 12.

[0017] As shown in FIG. 1(b), a drain electrode 20 is provided on the back surface side of the MOSFET 100.

[0018] A plurality of transistors are provided below the source electrode 10. The gate electrode pad 12 and the gate electrode wiring 12x are electrically connected to the gate electrodes of the transistors. A gate voltage is applied to the gate electrode pad 12 to control the switching operation of the transistors.

[0019] 2 is a schematic cross-sectional view of a part of the semiconductor device according to the embodiment, taken along the line AA' in FIG.

[0020] Fig. 3 is a schematic top view of a portion of the semiconductor device of the embodiment. Fig. 3 is a top view of a portion corresponding to Fig. 2. Fig. 3 is a view of a position corresponding to the first face F1 of the semiconductor layer 30. Fig. 3 is a view excluding components above the first face F1.

[0021] The MOSFET 100 includes a source electrode 10 (first electrode), a drain electrode 20 (second electrode), a semiconductor layer 30, a first gate electrode 41, a second gate electrode 42, a first gate insulating layer 46, a second gate insulating layer 47, a third gate insulating layer 48, a first field plate electrode 51, a second field plate electrode 52, a first field plate insulating layer 56, a second field plate insulating layer 57, a first inter-electrode insulating layer 61, a second inter-electrode insulating layer 62, and an interlayer insulating layer 65.

[0022] The semiconductor layer 30 includes a cell trench 31 (first trench), a termination trench 32 (second trench), and + shaped drain region 33, n - a p-type drift region 34 (first semiconductor region), a p-type body region 35 (second semiconductor region), and an n-type + The source region 36 (third semiconductor region) is of a crystalline form.

[0023] The semiconductor layer 30 is provided between the source electrode 10 and the drain electrode 20. The semiconductor layer 30 has a first surface ("F1" in FIG. 2) and a second surface ("F2" in FIG. 2). The second surface F2 faces the first surface F1.

[0024] The first face F1 faces the source electrode 10. The second face F2 faces the drain electrode 20.

[0025] The first direction and the second direction are parallel to the first face F1. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first face F1. The third direction is perpendicular to the first direction and the second direction.

[0026] Hereinafter, the term "depth" refers to the depth based on the first plane F1, that is, the distance in the third direction based on the first plane F1.

[0027] The semiconductor layer 30 is, for example, single-crystal silicon (Si). When the semiconductor layer 30 is single-crystal silicon, the surface of the semiconductor layer 30 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (100) plane.

[0028] n + A drain region 33 having a shape is provided in the semiconductor layer 30. The drain region 33 is in contact with the second face F2. The drain region 33 is in contact with the drain electrode 20. The drain region 33 is electrically connected to the drain electrode 20.

[0029] The drain region 33 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0030] n - A drift region 34 having a shape similar to that of the first face F1 is provided in the semiconductor layer 30. The drift region 34 is provided between the drain region 33 and the first face F1. The drift region 34 is provided on the drain region 33. The drift region 34 functions as a current path when the MOSFET 100 is in an on-state.

[0031] The drift region 34 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration is, for example, 1×10 15 cm -3 More than 1×10 18 cm -3 The following is the result.

[0032] The thickness of the drift region 34 in the third direction is, for example, not less than 5 μm and not more than 15 μm.

[0033] A p-type body region 35 is provided in the semiconductor layer 30. The body region 35 is provided between the drift region 34 and the first face F1.

[0034] The body region 35 is provided between two adjacent cell trenches 31. The body region 35 is provided between the cell trench 31 and the termination trench 32.

[0035] The body region 35 is in contact with, for example, the source electrode 10. The body region 35 is electrically connected to, for example, the source electrode 10.

[0036] When the MOSFET 100 is in an on-state, an inversion layer channel is formed in the body region 35 facing the first gate electrode 41 .

[0037] The body region 35 contains p-type impurities. The p-type impurities are, for example, boron (B). The p-type impurity concentration is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0038] n + A source region 36 having a shape similar to that of the body region 35 is provided in the semiconductor layer 30. The source region 36 is provided between the body region 35 and the first face F1.

[0039] The source region 36 is in contact with the first face F1. The source region 36 is in contact with the source electrode 10. The source region 36 is electrically connected to the source electrode 10.

[0040] The source region 36 is provided between two adjacent cell trenches 31.

[0041] 2, the source region 36 is not provided between the cell trench 31 and the termination trench 32. Also, the source region 36 is not provided between the final cell trench 31 and the adjacent cell trench 31, as shown in FIG. 2, for example. By not providing the source region 36 at the end, for example, the discharge of holes to the source electrode 10 during the off operation of the MOSFET 100 is promoted. Therefore, destruction of the MOSFET 100 due to avalanche breakdown is suppressed.

[0042] The source region 36 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0043] The cell trench 31 exists in the semiconductor layer 30. The cell trench 31 is located on the first face F1 side of the semiconductor layer 30. The cell trench 31 is a groove formed in the semiconductor layer 30.

[0044] The cell trench 31 extends in a first direction. The plurality of cell trenches 31 are repeatedly arranged in a second direction. For example, the plurality of cell trenches 31 are repeatedly arranged at a constant pitch in the second direction.

[0045] The cell trench 31 penetrates the body region 35 and reaches the drift region 34. The depth of the cell trench 31 is, for example, not less than 1 μm and not more than 5 μm. The width of the cell trench 31 in the second direction is, for example, not less than 0.3 μm and not more than 1 μm.

[0046] The termination trench 32 exists in the semiconductor layer 30. The termination trench 32 is located on the first face F1 side of the semiconductor layer 30. The termination trench 32 is a groove formed in the semiconductor layer 30.

[0047] The termination trench 32 extends in the first direction. The termination trench 32 is adjacent in the second direction to the cell trench 31 that is located at the endmost end in the second direction among the multiple cell trenches 31. The termination trench 32 is provided outside the multiple cell trenches 31. For example, no trench is provided on the side of the termination trench 32 opposite the multiple cell trenches 31.

[0048] The termination trench 32 is deeper than the body region 35 and reaches the drift region 34. For example, the body region 35 is not provided outside the termination trench 32. For example, the entire outer side surface of the termination trench 32 contacts the drift region 34.

[0049] The depth of the termination trench 32 is, for example, not less than 1 μm and not more than 5 μm, and the width of the termination trench 32 in the second direction is, for example, not less than 0.3 μm and not more than 1 μm.

[0050] The width in the second direction of termination trench 32 is, for example, substantially equal to the width in the second direction of cell trench 31. The width in the second direction of termination trench 32 is, for example, 0.9 to 1.1 times the width in the second direction of cell trench 31.

[0051] The first gate electrode 41 is provided in the cell trench 31. The first gate electrode 41 is electrically connected to the gate electrode wiring 12x and the gate electrode pad 12 by using, for example, a contact structure (not shown).

[0052] The first gate electrode 41 is a conductor and is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0053] The second gate electrode 42 is provided in the termination trench 32. The second gate electrode 42 is electrically connected to the gate electrode wiring 12x and the gate electrode pad 12 using, for example, a contact structure (not shown).

[0054] The second gate electrode 42 is a conductor and is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0055] The first gate insulating layer 46 is provided between the first gate electrode 41 and the semiconductor layer 30. The first gate insulating layer 46 is provided between the first gate electrode 41 and the body region 35. The first gate insulating layer 46 is provided between the first gate electrode 41 and the drift region 34. The first gate insulating layer 46 is provided between the first gate electrode 41 and the source region 36. The first gate insulating layer 46 is, for example, silicon oxide.

[0056] The second gate insulating layer 47 is provided between the second gate electrode 42 and the semiconductor layer 30 on the cell trench 31 side of the second gate electrode 42. The second gate insulating layer 47 is provided between the second gate electrode 42 and the body region 35. The second gate insulating layer 47 is provided between the second gate electrode 42 and the drift region 34. The second gate insulating layer 47 is, for example, silicon oxide.

[0057] The third gate insulating layer 48 is provided between the second gate electrode 42 and the semiconductor layer 30 on the opposite side of the cell trench 31 from the second gate electrode 42. The third gate insulating layer 48 is provided between the second gate electrode 42 and the drift region 34. The second gate electrode 42 is provided between the second gate insulating layer 47 and the third gate insulating layer 48 in the second direction. The third gate insulating layer 48 is, for example, silicon oxide.

[0058] The thickness of the third gate insulating layer 48 in the second direction is greater than the thickness of the second gate insulating layer 47 in the second direction.

[0059] The first field plate electrode 51 is provided in the cell trench 31. The first field plate electrode 51 is provided between the first gate electrode 41 and the second face F2 in the third direction. The first field plate electrode 51 extends in the first direction.

[0060] The first field plate electrode 51 has the function of changing the electric field distribution in the drift region 34 when the MOSFET 100 is in an off state, thereby improving the breakdown voltage of the MOSFET 100.

[0061] The first field plate electrode 51 is electrically connected to the source electrode 10 using, for example, a contact structure (not shown).

[0062] The first field plate electrode 51 is a conductor and is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0063] The second field plate electrode 52 is provided in the termination trench 32. The second field plate electrode 52 is provided in the third direction between the second gate electrode 42 and the second face F2. The second field plate electrode 52 extends in the first direction.

[0064] The second field plate electrode 52 has the function of changing the electric field distribution in the drift region 34 when the MOSFET 100 is in an off state, thereby improving the breakdown voltage of the MOSFET 100.

[0065] The second field plate electrode 52 is electrically connected to the source electrode 10 using, for example, a contact structure (not shown).

[0066] The second field plate electrode 52 is a conductor and is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0067] The first field plate insulating layer 56 is provided between the first field plate electrode 51 and the semiconductor layer 30. The first field plate insulating layer 56 is provided between the first field plate electrode 51 and the drift region 34. The first field plate insulating layer 56 is made of, for example, silicon oxide.

[0068] The thickness of the first field plate insulating layer 56 is, for example, thicker than the thickness of the first gate insulating layer 46. The thickness of the first field plate insulating layer 56 is, for example, not less than 3 times and not more than 30 times the thickness of the first gate insulating layer 46.

[0069] The second field plate insulating layer 57 is provided between the second field plate electrode 52 and the semiconductor layer 30. The second field plate insulating layer 57 is provided between the second field plate electrode 52 and the drift region 34. The second field plate insulating layer 57 is made of, for example, silicon oxide.

[0070] The thickness of the second field plate insulating layer 57 is, for example, thicker than the thickness of the second gate insulating layer 47. The thickness of the second field plate insulating layer 57 is, for example, not less than 3 times and not more than 30 times the thickness of the second gate insulating layer 47.

[0071] The first interelectrode insulating layer 61 is provided between the first gate electrode 41 and the first field plate electrode 51. The first interelectrode insulating layer 61 is made of, for example, silicon oxide.

[0072] The thickness of the first inter-electrode insulating layer 61 is greater than the thickness of the first gate insulating layer 46 and the thickness of the first field plate insulating layer 56, for example.

[0073] The second inter-electrode insulating layer 62 is provided between the second gate electrode 42 and the second field plate electrode 52. The second inter-electrode insulating layer 62 is, for example, silicon oxide.

[0074] The second inter-electrode insulating layer 62 may be continuous with, for example, the third gate insulating layer 48. The second inter-electrode insulating layer 62 is made of, for example, the same material as the third gate insulating layer 48.

[0075] The thickness of the second inter-electrode insulating layer 62 is greater than the thickness of the second gate insulating layer 47 and the thickness of the second field plate insulating layer 57, for example.

[0076] The interlayer insulating layer 65 is provided between the first gate electrode 41 and the source electrode 10. The interlayer insulating layer 65 is provided between the second gate electrode 42 and the source electrode 10. The interlayer insulating layer 65 has a function of electrically isolating the first gate electrode 41 and the second gate electrode 42 from the source electrode 10.

[0077] The interlayer insulating layer 65 is, for example, silicon oxide.

[0078] The source electrode 10 is provided on the first face F1 side of the semiconductor layer 30. The source electrode 10 is provided on the first face F1 of the semiconductor layer 30.

[0079] The source electrode 10 is electrically connected to the source region 36 and the body region 35. The source electrode 10 contacts the source region 36 and the body region 35, for example.

[0080] The source electrode 10 is a region to which, for example, a bonding wire is connected when the MOSFET 100 is mounted.

[0081] The source electrode 10 is made of metal and has, for example, a laminated structure of titanium (Ti) and aluminum (Al).

[0082] The drain electrode 20 is provided on the second face F2 side of the semiconductor layer 30. The drain electrode 20 is provided on the second face F2 of the semiconductor layer 30. The drain electrode 20 is electrically connected to the drain region 33. The drain electrode 20 contacts the drain region 33.

[0083] The drain electrode 20 is made of metal and has a laminated structure of a material selected from, for example, titanium (Ti), aluminum (Al), nickel (Ni), copper (Cu), silver (Ag), and gold (Au).

[0084] The gate electrode pad 12 is provided on the first face F1 side of the semiconductor layer 30. The gate electrode pad 12 is provided on the first face F1 of the semiconductor layer 30. The gate electrode pad 12 and the gate electrode wiring 12x surround, for example, the source electrode 10, as shown in FIG. 1(a).

[0085] The gate electrode pad 12 is electrically connected to the first gate electrode 41 and the second gate electrode 42. When the MOSFET 100 is mounted, the gate electrode pad 12 is a region to which, for example, a bonding wire is connected.

[0086] The gate electrode pad 12 is made of metal. The gate electrode pad 12 has a laminated structure of, for example, titanium (Ti) and aluminum (Al). The material of the gate electrode pad 12 is the same as the material of the source electrode 10, for example.

[0087] The gate electrode wiring 12x is electrically connected to the first gate electrode 41 and the second gate electrode 42. The gate electrode pad 12 is electrically connected to the first gate electrode 41 and the second gate electrode 42 using the gate electrode wiring 12x.

[0088] The gate electrode wiring 12x is made of a metal. The gate electrode wiring 12x has, for example, a laminated structure of titanium (Ti) and aluminum (Al). The material of the gate electrode wiring 12x is, for example, the same as the material of the source electrode 10 and the material of the gate electrode pad 12.

[0089] Fig. 4 is an enlarged schematic cross-sectional view of a portion of the semiconductor device of the embodiment. Fig. 4 is an enlarged view of the portion surrounded by the dotted line in Fig. 2. Fig. 4 omits the source electrode 10 and the interlayer insulating layer 65.

[0090] The first gate electrode 41 has a first length in the third direction (L1 in FIG. 4). A second length in the third direction (L2 in FIG. 4) of a first portion of the second gate electrode 42 on the cell trench 31 side is greater than a third length in the third direction (L3 in FIG. 4) of a second portion of the second gate electrode 42 on the opposite side of the cell trench 31.

[0091] The second gate electrode 42 has a first portion on the cell trench 31 side and a second portion on the opposite side to the cell trench 31. A second length L2 of the first portion in the third direction is greater than a third length L3 of the second portion in the third direction.

[0092] The second length L2 is, for example, 1.2 times or more and 3 times or less the third length L3.

[0093] The second length L2 is, for example, substantially the same as the first length L1. The second length L2 is, for example, 0.9 to 1.1 times the first length L1.

[0094] The surface of the second gate electrode 42 on the second face F2 side has a step St (the region surrounded by the dotted line in FIG. 4). The lower surface of the second gate electrode 42 has a step St.

[0095] The first gate insulating layer 46 has a first thickness (t1 in FIG. 4) in the second direction. The second gate insulating layer 47 has a second thickness (t2 in FIG. 4) in the second direction. The third gate insulating layer 48 has a third thickness (t3 in FIG. 4) in the second direction.

[0096] The first thickness t1 of the first gate insulating layer 46 is, for example, the thickness of the thinnest portion of the first gate insulating layer 46. The second thickness t2 of the second gate insulating layer 47 is, for example, the thickness of the thinnest portion of the second gate insulating layer 47. The third thickness t3 of the third gate insulating layer 48 is, for example, the thickness of the thinnest portion of the third gate insulating layer 48.

[0097] The third thickness t3 is greater than the second thickness t2 and is, for example, 1.5 to 5 times the second thickness t2.

[0098] The second thickness t2 is, for example, substantially the same as the first thickness t1, and is, for example, 0.9 to 1.1 times the first thickness t1.

[0099] The first thickness t1 is, for example, 30 nm or more and 100 nm or less, the second thickness t2 is, for example, 30 nm or more and 100 nm or less, and the third thickness t3 is, for example, 45 nm or more and 500 nm or less.

[0100] At a first position (P1 in FIG. 4) in the second interelectrode insulating layer 62, the distance in the third direction between the second gate electrode 42 and the second field plate electrode 52 is a first distance (d1 in FIG. 4). At a second position (P2 in FIG. 4) in the second interelectrode insulating layer 62, the distance in the third direction between the second gate electrode 42 and the second field plate electrode 52 is a second distance (d2 in FIG. 4).

[0101] The first position P1 is closer to the cell trench 31 in the second direction than the second position P2. In other words, the second position P2 is farther from the cell trench 31 in the second direction than the first position P1.

[0102] The first distance d1 is smaller than the second distance d2. In other words, the second distance d2 is larger than the first distance d1. The second distance d2 is, for example, 1.2 times or more and 2 times or less the first distance d1.

[0103] Fig. 5 is an enlarged schematic cross-sectional view of a portion of the semiconductor device of the embodiment. Fig. 5 is an enlarged view of the portion surrounded by the dotted line in Fig. 2. Fig. 5 omits illustration of the source electrode 10 and the interlayer insulating layer 65. Fig. 5 shows the same portion as Fig. 4.

[0104] 5 is a cross section parallel to the second direction and the third direction. In the cross section parallel to the second direction and the third direction, when the second direction is defined as the left-right direction, the shape of the second gate electrode 42 is asymmetric.

[0105] In a cross section parallel to the second and third directions, a line segment drawn in the second direction through the second gate electrode 42 and passing through a position where the second gate electrode 42 has the maximum width in the second direction is defined as a first line segment (LS1 in FIG. 5). A second line segment (LS2 in FIG. 5) passing through the midpoint (M in FIG. 5) of the first line segment LS1 and extending in the third direction virtually divides the second gate electrode 42 into left and right halves. The second gate electrode 42 is divided by the second line segment LS2 into a first region 42a on the cell trench 31 side and a second region 42b on the opposite side of the cell trench 31. In this case, the first area (S1 in FIG. 5) of the first region 42a is larger than the second area (S2 in FIG. 5) of the second region 42b.

[0106] The first area S1 of the first region 42a is, for example, 1.2 times or more and 5 times or less the second area of ​​the second region 42b.

[0107] Next, an example of a method for manufacturing the semiconductor device according to the embodiment will be described.

[0108] 6, 7, 8, 9, 10, 11, and 12 are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment, and are cross-sectional views corresponding to FIG.

[0109] First, using known process techniques, - A cell trench 31 and a termination trench 32 are formed in a semiconductor layer 30 having a shape similar to that of a semiconductor substrate 10 (FIG. 6). The cell trench 31 and the termination trench 32 are formed simultaneously. A portion of the semiconductor layer 30 will eventually become a drift region 34.

[0110] Next, using a known process technique, a first field plate insulating layer 56 and a first field plate electrode 51 are formed in the cell trench 31. Also, using a known process technique, a second field plate insulating layer 57 and a second field plate electrode 52 are formed in the termination trench 32 (FIG. 7).

[0111] Next, a first silicon oxide film 70 is formed so as to fill a portion of the cell trench 31 and the termination trench 32. The first silicon oxide film 70 is formed by, for example, a chemical vapor deposition method (CVD method). Portions of the first silicon oxide film 70 will eventually become the first inter-electrode insulating layer 61, the second inter-electrode insulating layer 62, and the third gate insulating layer 48.

[0112] Next, a resist film 71 for patterning the first silicon oxide film 70 is formed on the first silicon oxide film 70 (FIG. 8). The resist film 71 covers a portion of the first silicon oxide film 70 that fills the termination trench 32, and exposes another portion. In other words, an end of the resist film 71 is provided in the termination trench 32.

[0113] Next, the resist film 71 is used as a mask to remove a portion of the first silicon oxide film 70 (FIG. 9). The portion of the first silicon oxide film 70 is removed by, for example, wet etching.

[0114] By removing a portion of the first silicon oxide film 70, the semiconductor layer 30 on both side surfaces of the upper part of the cell trench 31 is exposed. Also, the semiconductor layer 30 on the side surface of the upper part of the termination trench 32 on the cell trench 31 side is exposed. The side surface of the upper part of the termination trench 32 opposite the cell trench 31 remains covered with the first silicon oxide film 70. The first silicon oxide film 70 covering the side surface of the upper part of the termination trench 32 opposite the cell trench 31 will eventually become the third gate insulating layer 48.

[0115] Next, the resist film 71 is removed. Next, using a known process technology, the first gate electrode 41, the second gate electrode 42, the first gate insulating layer 46, and the second gate insulating layer 47 are formed (FIG. 10).

[0116] Next, using known process techniques, the p-type body region 35 and n + A source region 36 having a shape similar to that of the source region 36 is formed (FIG. 11).

[0117] Next, a second silicon oxide film 72 is formed on the semiconductor layer 30. The second silicon oxide film 72 is formed by, for example, a CVD method. A part of the second silicon oxide film 72 will eventually become the interlayer insulating layer 65.

[0118] Next, an opening 74 is formed in the second silicon oxide film 72, reaching the surface of the semiconductor layer 30 (FIG. 12). The opening 74 is formed by, for example, lithography and reactive ion etching (RIE). Note that, for example, the semiconductor layer 30 at the bottom of the opening 74 may also be etched, so that the opening 74 penetrates the source region 36.

[0119] Thereafter, the opening 74 is filled with a metal film using a known process technique to form the source electrode 10. Also, the drain region 33 and the drain electrode 20 are formed on the back surface side of the semiconductor layer 30 using a known process technique.

[0120] By the above-described method for manufacturing a semiconductor device, the MOSFET 100 of the embodiment shown in FIG. 2 is manufactured.

[0121] Next, the operation and effects of the semiconductor device of the embodiment will be described.

[0122] 13 is a schematic cross-sectional view of a part of a semiconductor device of a first comparative example, which corresponds to FIG.

[0123] The MOSFET 901 of the first comparative example differs from the MOSFET 100 of the embodiment in that the length of the second gate electrode 42 in the third direction is constant. The MOSFET 901 of the first comparative example also differs from the MOSFET 100 of the embodiment in that the thickness of the third gate insulating layer 48 is the same as the thickness of the second gate insulating layer 47.

[0124] In the MOSFET 901, when the MOSFET 901 is in an off state, electric field concentration occurs outside the termination trench 32. Specifically, the electric field strength applied to the third gate insulating layer 48 between the drift region 34 outside the termination trench 32 and the second gate electrode 42 increases. This makes the third gate insulating layer 48 more susceptible to dielectric breakdown, which may reduce the reliability of the gate insulating layer.

[0125] 14 is a schematic cross-sectional view of a portion of a semiconductor device of a second comparative embodiment, which corresponds to FIG.

[0126] The MOSFET 902 of the second comparative embodiment differs from the MOSFET 100 of the embodiment in that the length of the second gate electrode 42 in the third direction is constant. The MOSFET 902 of the second comparative embodiment also differs from the MOSFET 901 of the first comparative embodiment in that the thickness of the third gate insulating layer 48 is thicker than the thickness of the second gate insulating layer 47.

[0127] In the MOSFET 902, the third gate insulating layer 48 is thicker than the second gate insulating layer 47, which reduces the electric field strength applied to the third gate insulating layer 48 when the MOSFET 902 is in the off state. This improves the reliability of the gate insulating layer compared to the MOSFET 901 of the first comparative example.

[0128] 4, in the MOSFET 100 of the embodiment, the second length (L2 in FIG. 4) in the third direction of the first portion of the second gate electrode 42 on the cell trench 31 side is greater than the third length (L3 in FIG. 4) in the third direction of the second portion of the second gate electrode 42 on the opposite side to the cell trench 31. In other words, the third length L3 is smaller than the second length L2.

[0129] This reduces the area of ​​the second gate electrode 42 that faces the drift region 34 outside the termination trench 32 across the thin portion of the third gate insulating layer 48. This reduces the capacitance between the second gate electrode 42 of the MOSFET 100 and the drift region 34 outside the termination trench 32 compared to that of the MOSFET 902. This reduces the gate-drain capacitance of the MOSFET 100.

[0130] Furthermore, in MOSFET 100, the area of ​​second gate electrode 42 facing drift region 34 outside termination trench 32 across the thin portion of third gate insulating layer 48 is reduced, thereby improving the reliability of the gate insulating layer compared to MOSFET 902 of the first comparative example.

[0131] 4, in the MOSFET 100 of the embodiment, the second distance (d2 in FIG. 4) between the second gate electrode 42 and the second field plate electrode 52 at a second position (P2 in FIG. 4) far from the cell trench 31 is greater than the first distance (d1 in FIG. 4) between the second gate electrode 42 and the second field plate electrode 52 at a first position (P1 in FIG. 4) close to the cell trench 31. Therefore, the capacitance between the second gate electrode 42 and the second field plate electrode 52 of the MOSFET 100 is smaller than that of the MOSFET 902. The second field plate electrode 52 is electrically connected to the source electrode 10. Therefore, the gate-source capacitance of the MOSFET 100 is smaller.

[0132] The MOSFET 100 of the embodiment has a reduced gate capacitance compared to the MOSFET 902 of the second comparative example, which, for example, improves the operating speed of the MOSFET 100 and reduces power consumption.

[0133] From the viewpoint of improving the reliability of the gate insulating layer, the third thickness t3 of the third gate insulating layer 48 is preferably 1.5 times or more, more preferably 2 times or more, and even more preferably 3 times or more, the second thickness t2 of the second gate insulating layer 47.

[0134] From the viewpoint of reducing the gate capacitance and improving the reliability of the gate insulating layer, the second length L2 of the second gate electrode 42 is, for example, preferably 1.2 times or more, and more preferably 1.5 times or more, the third length L3 of the second gate electrode 42.

[0135] From the viewpoint of reducing the gate capacitance, the second distance d2 between the second gate electrode 42 and the second field plate electrode 52 is preferably 1.2 times or more, and more preferably 1.5 times or more, the first distance d1.

[0136] From the viewpoint of reducing the gate capacitance and improving the reliability of the gate insulating layer, the first area S1 of the first region 42a shown in FIG. 5 is preferably 1.2 times or more, and more preferably 1.5 times or more, the second area of ​​the second region 42b.

[0137] In the embodiment, the semiconductor layer is made of single crystal silicon, but the semiconductor layer is not limited to single crystal silicon. For example, the semiconductor layer may be made of other single crystal semiconductors such as single crystal silicon carbide.

[0138] In the embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but it is also possible to configure the first conductivity type as p-type and the second conductivity type as n-type.

[0139] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0140] 10 source electrode (first electrode) 20 Drain electrode (second electrode) 30 Semiconductor layer 31 Cell trench (first trench) 32 Termination trench (second trench) 34 drift region (first semiconductor region) 35 body region (second semiconductor region) 36 Source region (third semiconductor region) 41 first gate electrode 42 second gate electrode 42a First Region 42b Second Area 46 First gate insulating layer 47 Second gate insulating layer 48 Third gate insulating layer 51 First field plate electrode 52 Second field plate electrode 56 First field plate insulating layer 57 Second field plate insulating layer 61 First inter-electrode insulating layer 62 Second inter-electrode insulating layer 100 MOSFET (semiconductor device) F1 First Side F2 Second side L1 First length L2 Second length L3 Third length LS1 First line segment LS2 Second line segment M midpoint P1 First position P2 Second position S1 First area S2 Second area St Step d1 First distance d2 Second distance t1 First thickness t2 Second thickness t3 Third thickness

Claims

1. a first electrode; a second electrode; and a semiconductor layer provided between the first electrode and the second electrode, the semiconductor layer having a first surface facing the first electrode and a second surface facing the second electrode, a plurality of first trenches provided on the first surface side, extending in a first direction parallel to the first surface, and repeatedly arranged in a second direction parallel to the first surface and perpendicular to the first direction; a second trench provided on the first surface side, extending in the first direction, and adjacent in the second direction to a first trench located at an end of the plurality of first trenches in the second direction; a first semiconductor region of a first conductivity type electrically connected to the second electrode; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface and between two of the first trenches; a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface, between two of the first trenches, and electrically connected to the first electrode; a semiconductor layer comprising: a first gate electrode disposed in the first trench and having a first length in a third direction perpendicular to the first direction and the second direction; a first field plate electrode provided in the first trench and between the first gate electrode and the second surface; a second gate electrode provided in the second trench, the second length in the third direction of a portion on the first trench side being greater than the third length in the third direction of a portion on an opposite side to the first trench; a second field plate electrode provided in the second trench and between the second gate electrode and the second surface; a first gate insulating layer provided between the first gate electrode and the semiconductor layer and having a first thickness; a first field plate insulating layer provided between the first field plate electrode and the semiconductor layer; a first inter-electrode insulating layer provided between the first gate electrode and the first field plate electrode; a second gate insulating layer having a second thickness and disposed between the second gate electrode and the semiconductor layer on the side of the first trench; a third gate insulating layer provided between the second gate electrode and the semiconductor layer on the opposite side of the first trench, the third gate insulating layer having a third thickness greater than the second thickness; a second field plate insulating layer provided between the second field plate electrode and the semiconductor layer; a second inter-electrode insulating layer provided between the second gate electrode and the second field plate electrode; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein said second length is at least 1.2 times as long as said third length.

3. 2. The semiconductor device according to claim 1, wherein a surface of said second gate electrode on said second surface side has a step.

4. 2. The semiconductor device according to claim 1, wherein the second length is 0.9 to 1.1 times the first length.

5. 2. The semiconductor device according to claim 1, wherein said third thickness is at least 1.5 times as large as said second thickness.

6. 2. The semiconductor device according to claim 1, wherein said second thickness is not less than 0.9 times and not more than 1.1 times said first thickness.

7. a first distance in the third direction between the second gate electrode and the second field plate electrode at a first position; 2. The semiconductor device according to claim 1, wherein the distance between the second gate electrode and the second field plate electrode in the third direction is smaller than a second distance between the second gate electrode and the second field plate electrode at a second position farther from the first trench in the second direction than the first position.

8. 2. The semiconductor device according to claim 1, wherein the second distance is at least 1.2 times the first distance.

9. 2. The semiconductor device according to claim 1, wherein the width of said second trench in said second direction is 0.9 to 1.1 times the width of said first trench in said second direction.

10. 2. The semiconductor device according to claim 1, wherein, in a cross section parallel to said second direction and said third direction, when said second direction is defined as a left-right direction, a shape of said second gate electrode is asymmetrical.

11. 2. The semiconductor device according to claim 1, wherein, in a cross section parallel to the second direction and the third direction, when the second gate electrode is virtually divided into a first region on the side of the first trench and a second region on the opposite side of the first trench by a second line segment extending in the third direction, the second line segment passing through a position where the second gate electrode has a maximum width in the second direction and passing through a midpoint of a first line segment drawn in the second direction within the second gate electrode, the first area of ​​the first region is larger than a second area of ​​the second region.

12. 12. The semiconductor device according to claim 11, wherein said first area is 1.2 times or more as large as said second area.

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