Memory wordline isolation for improvement in reliability, availability, and scalability (RAS)

Abstract

To provide a memory device, a system and a method for simplifying an ECC overhead.SOLUTION: A memory device that performs internal ECC (error checking and correction) treats an N-bit channel as two N / 2-bit channels for application of ECC. The ECC for an N / 2-bit channel is simpler than the ECC for N bits, and thus, each N / 2-bit portion is separately correctable when treated as two N / 2-bit portions. The memory device includes additional hardware for application of the ECC to the channel as two sub-channels. For example, the memory device includes an additional subarray to store ECC bits for the internal ECC to enable the application of the ECC to two sub-channels of the N-bit channel and an additional driver to access the additional subarray when applied.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Priority This application is a non-provisional application and claims the benefit of priority to U.S. Provisional Application No. 62 / 927,116, filed October 28, 2019.

[0002] The description relates generally to memory devices, and more particularly, the description relates to an architecture for improving RAS (reliability, availability, and scalability) through error handling. [Background technology]

[0003] The overhead required to handle errors in memory channels continues to increase as narrower channels are used. Error handling overhead can be referred to as RAS (reliability, availability, serviceability) overhead, and refers to the fact that error handling is used to meet RAS expectations. RAS expectations often include expectations for maximum SDDC (single device data correction) capability, where errors due to maximum device failures can be corrected.

[0004] Legacy SDDC operation has 8 ECC (error checking and correcting, also often called error correction coding) bits per 64 data bits, a 12.5% ​​overhead. Newer memory systems with narrower channels still require 8 ECC bits for SDDC operation, but with a 32-bit channel, the overhead becomes 25%. [Brief explanation of the drawings]

[0005] The following description includes discussion of figures having illustrations given as examples of implementations. The figures should be understood as examples and not as limitations. As used herein, reference to one or more examples should be understood as describing particular features, structures, or characteristics included in at least one implementation of the invention. Phrases such as "in one example" or "in an alternative example" appearing herein provide examples of implementations of the invention and do not necessarily all refer to the same implementation. However, they are not necessarily mutually exclusive.

[0006] [Figure 1] FIG. 1 is a block diagram of an example memory architecture having additional drivers for isolating data relative to conventional architectures.

[0007] [Figure 2] FIG. 2 is a block diagram of an example data architecture for the memory architecture of FIG. 1.

[0008] [Figure 3] FIG. 10 is a flow diagram of an example process for applying ECC for a read command in a system with ECC sub-channel separation.

[0009] [Figure 4] FIG. 10 is a flow diagram of an example process for applying ECC for write commands in a system with ECC sub-channel separation.

[0010] [Figure 5] FIG. 1 is a block diagram of an example on-die error checking and correction (ECC) subsystem for implementing ECC sub-channel separation.

[0011] [Figure 6] FIG. 1 is a block diagram of an example memory subsystem in which ECC sub-channel separation can be implemented.

[0012] [Figure 7]FIG. 1 is a block diagram of an example computing system in which ECC subchannel separation can be implemented.

[0013] [Figure 8] 1 is a block diagram of an example mobile device in which ECC subchannel separation can be implemented.

[0014] A description of specific details and implementations follows, including a non-limiting description of figures that may show some or all examples, as well as other possible implementations. DETAILED DESCRIPTION OF THE INVENTION

[0015] As described herein, a memory device is divided into multiple separate portions for ECC (Error Checking and Correction) separation for internal or on-die ECC application. The different portions can still be treated as one segment for external or system-level ECC by a memory controller at the system level. Thus, the internal ECC can correct two sub-channels individually, while the system-level ECC will correct the entire channel. The internal ECC separation allows the memory device to use less overhead to provide the same level of ECC. The available additional ECC bits can be used as additional metadata.

[0016] A memory device that implements internal ECC can treat an N-bit channel as two N / 2-bit channels for applying the ECC. Splitting an N-bit channel can refer to treating the data bits for the N signal lines of the channel as two groups of N / 2 bits each or two portions of N / 2 signal lines. The memory device applies ECC to N bits of ECC data corresponding to the N signal lines of the channel. ECC for an N / 2-bit channel is simpler than ECC for N bits, and therefore each N / 2-bit portion may be individually correctable when treated as two N / 2-bit portions. The memory device may include additional hardware for applying ECC to the channel as two sub-channels. For example, the memory device may include an additional sub-array to store ECC bits for the internal ECC, enabling application of ECC to two sub-channels of the N-bit channel. The memory device may include an additional driver for accessing the additional sub-array, if applicable.

[0017] For example, a x4 memory device can be treated internally as two x2 devices. Correcting errors for x2 devices requires less RAS (reliability, availability, and serviceability) overhead than for x4 devices. RAS code can be targeted to determine common memory error types, such as a single bit, a single sub-wordline (SWL) driver, or one arm of an SWL driver. References to sub-wordlines can refer to an architecture that subdivides wordlines to reduce driver load, sometimes referred to as local wordlines (LWLs). Experiments have shown that device-wide (e.g., die-wide) failures are very rare for the failures described above. The provided architecture allows for low-cost correction of more common failures while still allowing for correction of device-wide failures.

[0018] Depending on the terminology used, the SWL or LWL can be considered part of a master word line (MWL) or a global word line (GWL). Generally, the MWL / GWL is divided into smaller chunks within a memory device until the driver can meet the latency requirements for the memory device. The division of the device can vary by memory type, memory manufacturer, or driver design.

[0019] RAS overhead relative to overall single-device data correction (SDDC) continues to increase as memory systems use narrower channel or chipkill solutions. RAS overhead can alternatively be referred to as ECC (error checking and correction) overhead. The term RAS overhead refers to the overall goal for error correction, while the term ECC overhead more specifically refers to the mechanism of correction to achieve the desired RAS goal.

[0020] The described ECC isolation can reduce ECC overhead by half relative to internal ECC and reduce DIMM (dual in-line memory module) power. Memory devices that implement ECC isolation can be described as having failure modes that are isolated to a limited number of I / O (input / output) pins. For example, a DRAM device in a x4 implementation can be limited to having failure modes that are isolated on two DQs instead of having failures across all four DQ signal lines. In one example, different implementations can have different isolation granularities per device. The isolation granularity can be defined by a standard.

[0021] The channel width for DDR5 is half that of DDR4 (e.g., 32 bits vs. 64 bits), allowing the memory core to maintain the same internal cycle time while transferring data externally at higher speeds. Changing the internal core cycle time is significantly more expensive than adjusting the I / O cycle time. DDR5 has a burst length of BL18, transmitting 64 bits per device in addition to ECC bits. The overall interface will be a 32-bit wide channel divided among four devices for a x8 implementation or eight devices for a x4 implementation.

[0022] Generally, to implement SDDC, a system requires a number of ECC bits equal to twice the device interface. Thus, a x4 implementation requires 8 ECC bits on the channel, and a x8 interface requires 16 ECC bits. SDDC can become impractical for x8, but is more manageable for x4 implementations. As channels move from 64b data + 8b ECC to 32b data + 8b ECC, additional ECC devices will be required to meet the same RAS performance as legacy systems.

[0023] 1 is a block diagram of an example memory architecture with additional drivers for isolating data relative to conventional architectures. Memory segment 102 represents a portion of a memory array for providing data to data channels to which memory devices are connected. A DDR5 (Double Data Rate Version 5) data channel has a 32b data bus width with 16b for ECC, which would result in a 25% RAS / ECC overhead. On the other hand, a DDR4 (Double Data Rate Version 4) data channel has a 64b data bus width with 8 bits for ECC, which would result in a 12.5% ​​overhead.

[0024] Segment 102 may include sub-wordline (SWL) drivers driving 8 bits of data on each side. As shown, the dashed box indicates 16 bits of data driven by a driver (DRVR) in the center of the bit. Bits to the left of the driver can be considered the left sub-array or left arm of the driver. Similarly, bits to the right of the driver can be considered the right sub-array or right arm of the driver. It will be understood that right and left are relative terms and refer only to the orientation of the diagram. In actual implementation, bits considered left or right may switch. Thus, the description of left and right arms refers only to the fact that a driver between a group of bits or memory cells or memory locations drives bits in either physical location on the driver circuit side, reducing the length of signal lines that need to be driven between the driver circuit and the memory cells or bit cells of the memory array. There are bits driven in each direction from the active components of the driver. As shown, it can be seen that a failure of one arm (SWL arm) results in an 8b failure because one arm failure makes one sub-array inaccessible, while a driver failure (SWL driver failure) results in a 16b failure because both arms become inaccessible.

[0025] Segment 104 represents a channel similar to the channel for segment 102, but with an additional driver and an additional sub-array. Segment 104 can be considered to be further divided or partitioned into sub-channel A and sub-channel B, with a separation between the sub-channels. Each driver in segment 104 includes at least a left sub-array or a right sub-array, with most drivers having both a left and a right sub-array. Drivers at the ends may have only one arm. The separation in the middle can be considered a logical separation and need not be a physical separation in hardware. Thus, for example, separation can refer to the fact that, for ECC purposes, one ECC circuit provides ECC for one sub-channel and a separate ECC circuit provides ECC for the other sub-channel. With the separation hardware, the memory can provide ECC protection for the entire channel as two separate sub-portions, simplifying ECC overhead.

[0026] Segment 104 provides separation of data fetched from the memory array. In one example, additional drivers allow a single channel to be treated as two separate portions. Adding a driver can allow access of data in two separate portions for ECC operations. The additional drivers allow the channel to be subdivided for the purpose of applying internal ECC to smaller portions of the data, thus confining errors to a sub-portion of the overall memory interface. Diagram 106 shows further details of a driver with a left arm on one side and a right arm on the other side. The right arm drives the right sub-array and the left arm drives the left sub-array.

[0027] In one example, memory segment 104 can be part of a memory device with a common die implementation. A common die implementation refers to a memory device designed to be configurable as either a x4 or x8 device. Such a device would have internal logic that routes bits to selected I / O pins. The internal logic can include control logic as well as hardware circuitry for routing bits to segments of memory. In a common die implementation, in one example, additional drivers are not needed if ECC isolation is not used, for example, in a x8 implementation of the device. The memory array can be designed to allow selective utilization of additional drivers for ECC isolation without significant waste of addressable memory space. Thus, additional subarrays can be used in other ways without the need to activate the drivers. Alternatively, selected drivers can be designed as dual drivers for different implementations, driving only one arm instead of two.

[0028] FIG. 2 is a block diagram of an example data architecture for the memory architecture of FIG. 1. Graphic 202 represents a core memory architecture, such as a DDR5 implementation. As shown, the memory core performs 128b internal prefetching and includes 8b ECC for internal ECC. It will be understood that an x8 implementation uses all 128 bits of data, while an x4 implementation prefetches 128 bits, with only 64 bits being used in any given memory access (e.g., read or write) operation. A x4 implementation refers to an implementation in which a memory device having an array of graphic 202 includes an interface to four data signal lines or four bits of a data bus, which may be referred to as an implementation in which M=4, where M represents the number of signal lines. A x8 implementation refers to an implementation in which a memory device having an array of graphic 202 includes an interface to eight data signal lines or eight bits of a data bus, which may be referred to as an implementation in which M=4.

[0029] In a x8 implementation, 128 bits can be exchanged with a host or associated memory controller for each memory access transaction based on eight signal lines having a burst length of 16 (BL16), since 8×16=128. Thus, as shown, both the upper half of the array and the lower half of the array each provide 64 bits of data. The upper half can be based on the architecture and addressing structure of the memory and is not specifically shown in diagram 202. While lightly shaded blocks in diagram 202 represent the upper half, unshaded blocks represent the lower half, and vice versa. Darkly shaded bits represent ECC bits. For a x4 implementation, 64 bits can be exchanged with a host or associated memory controller for each memory access transaction based on four signal lines (4×16=64) via BL16. As shown, the 64 bits of data can be fetched from the lower half or from the upper half, or can be split between the upper and lower halves. A multiple half split implies utilizing only 4 bits of each 8 bits from a sub-array. In such an implementation, ECC would not cover SWL driver or MWL failures.

[0030] Diagram 204 illustrates a similar architecture to diagram 202, but includes separation. Diagram 204 specifically illustrates the application of memory device 210 having I / O circuitry 250 for interfacing with four DQ (data) signal lines, DQ[3:0]. Memory device 210 includes memory array 220, shown in prefetch 230, which is separated into multiple different sub-arrays.

[0031] Diagram 204 may correspond to memory segment 104 of FIG. 1. As shown, diagram 204 includes a memory array that provides data for prefetching. The prefetch includes 128 bits of data, similar to diagram 202, and either 4 or 8 bits of ECC data per separate portion. As shown, 8 bits of ECC data are shown for each sub-portion or sub-array. In one example, only 4 bits of ECC are provided per sub-portion. In one example, the additional ECC bits can be used for other purposes, such as directory information, two-level memory (2LM) metadata, data integrity features, or some other purpose. In another example, the ECC bits can be used for on-die single-bit error correction and are not transferred to the host. In such an example, the data can be transferred to the host via BL16.

[0032] It will be understood that if not all of the prefetched data is used, all of the prefetched data is placed in the sense amplifiers and then only selected data is used for the memory access. Thus, prefetch 230 represents the data in the sense amplifiers and select 240 represents the data from the sense amplifiers that is sent to the I / O for a read operation.

[0033] For example, data is placed into sense amplifiers, and then addressing operates to select a particular portion of the data to be written for a write operation or read for a read operation. The addressing can select the data in any manner that makes sense for the architecture. In one example, the additional hardware (e.g., drivers and other logic) for isolation in each bank (e.g., edge sub-word line drivers) may add only approximately 1-2 percent die size.

[0034] In one example, a portion of the prefetched data is selected for an access operation. As shown, four of the eight bits are selected from each sub-array. The sub-array selection allows the internal ECC operation to correct errors that occur in the driver as well as the driver arm. A failure of the SWL arm or SWL driver will only affect two of the DQ bits (either the upper or lower two DQs). Such a failure does not result in a loss in bank resources for a x4 implementation.

[0035] For a write operation, the arrows in diagram 204 may be reversed, where selected data is received from I / O circuitry 250 and provided from the I / O circuitry to selected locations in the sense amplifier circuitry at 230. Instead of being prefetched to the sense amplifiers for a write operation, the sense amplifier array can be driven to a corresponding selected sub-array of memory array 220. As with a read operation, the addressing of the sense amplifier elements can determine what is written to the memory array.

[0036] In one example, the routing in the spine of memory device 210 for a dedicated x4 device is 72b versus 136b for a common x4 / x8 device, resulting in a die savings of 2-3%. The implementation of the dedicated portion can therefore offset the die area cost versus isolation.

[0037] As shown in diagram 204, selected data and ECC bits can be routed to I / O circuitry 250 of memory device 210. While the arrows point downward for the illustrated read, it will be understood that for a write, data results in selected bits being written to memory device 210 and back to memory array 220. In one example, 36 bits per separate plane are transferred via BL18 on two DQ signal lines. The illustration of BL18 is an example only. In another example, the system transfers bits via BL16. The total for the device is 72 bits over four DQ signal lines, which are treated internally as two x2 interfaces. Although not specifically shown, the I / O circuitry can include ECC circuitry, or the ECC circuitry can be located on the input / output path between the sense amplifiers and I / O circuitry 250. The result of the architecture of diagram 204 is 8b ECC for every 64b of data available on BL18, with a 12.5% ​​RAS overhead, similar to legacy systems.

[0038] It will be understood that specific examples include ECC bits for a specific number of data and a specific number of I / O signal lines. These specific examples are illustrative and not limiting. In general, an N-bit channel can be subdivided into different portions for internal ECC, such as two N / 2-bit sub-portions or sub-channels. N bits can be the total amount of data transferred over the burst length (e.g., 64 bits of pure data bits excluding ECC bits). The subdivision can alternatively be considered relative to the interface width (e.g., a x4 channel treated as two separate x2 sub-channels). Thus, an N-bit channel generally refers to N bits of data transmitted over multiple M signal lines over the burst length. In one example, a channel interface may alternatively refer to an M-bit interface where data bits are transmitted or received. Typically, ECC bits apply to the entire payload of data bits received over all signal lines for the burst length, and references to the application of ECC bits to a channel will generally be understood to refer to all bits covered by the ECC bits.

[0039] Subdivision can treat bits or interfaces to a data bus as being separated into different portions, which can refer to separation for purposes of performing ECC operations. A system-level ECC implemented by an associated memory controller or host can treat all bits or signal lines as a single channel, instead of treating the bits or signal lines as two separate, separated channels, as shown in diagram 204. Thus, for example, a memory device can process N bits as two portions of N / 2 bits with separate ECCs, while the host treats the N bits as N bits for system-level ECC purposes. Such an approach allows correction within the memory device of a portion of the channel, allowing data to be reconstructed with less ECC overhead. Separation allows the memory device, more specifically, to separate errors for purposes of ECC correction. As another example, a memory device can treat N signal lines of a data bus interface as two portions of N / 2 signal lines with separate ECCs, while the host treats the N signal lines of the data bus interface as an N-bit channel for system-level ECC purposes. Implementations may vary due to different interfaces and internal array sizes, but the result will be a reduction in ECC overhead at the system level while providing the ability to perform internal ECC at higher performance. System-level ECC refers to ECC provided by a host or associated memory controller, which provides ECC operations on data from multiple memory devices in parallel.

[0040] 3 is a flow diagram of an example process for applying ECC for a read command in a system with ECC sub-channel separation. Process 300 provides an example of performing a read operation in a memory device with ECC including sub-channel separation. Process 300 can be implemented, for example, by memory device 210 of diagram 204 of FIG. 2.

[0041] The memory device receives a read command from a host at block 302. In one example, the memory device prefetches data to serve the read in an amount of data equal to or greater than N bits at block 304. In one example, the memory device selects a portion of the prefetched data for the read operation at block 306, where the amount of selected data is N bits.

[0042] In one example, a memory device can be configured to either apply sub-channel separation for ECC or not apply sub-channel separation. The system can determine the configuration of the memory device at block 308. If sub-channel separation is not applied, then at block 310, NO branch, the memory device can perform ECC on the N bits as an N-bit channel at block 312.

[0043] If sub-channel separation is applied, then in the YES branch of block 310, the memory device can perform ECC on the N bits as two N / 2 bit channels in block 314. Similar to what was described above, the application of ECC on the N / 2 bits can be to the total bits themselves or to a portion of the bits of the data bus.

[0044] Once the ECC has been applied, either as one channel or two sub-channels, the memory device provides the data to the I / O circuitry for transmission to the host in block 316. In one example, the host applies system ECC to the N bits of data in block 318 as a single N-bit channel.

[0045] 4 is a flow diagram of an example process for applying ECC for a write command in a system with ECC sub-channel separation. Process 400 provides an example of performing a write operation in a memory device with ECC including sub-channel separation. Process 400 can be implemented, for example, by memory device 210 of diagram 204 of FIG. 2.

[0046] In one example, the host or associated memory controller applies ECC to N bits of data addressed to the memory device at block 402. The host sends a write command that is received by the memory device at block 404. Either along with the write command or some time delay after the command, the memory device receives the N bits of data from the host associated with the write command at block 406.

[0047] In one example, a memory device can be configured to either apply sub-channel separation for ECC or not apply sub-channel separation. The system can determine the configuration of the memory device at block 408. If sub-channel separation is not applied, then at block 410, NO branch, the memory device can calculate ECC for N bits of data as an N-bit channel at block 412.

[0048] If sub-channel separation is applied, then on the YES branch of block 410, the memory device may calculate the ECC for the N bits of data as two N / 2 bit channels at block 414. Similar to what is described above, the application of the ECC for the N / 2 bits can be to the total bits themselves or to a portion of the bits of the data bus. Once the ECC has been calculated, either as one channel or two sub-channels, the memory device stores the data and associated ECC bits in its memory array at block 418.

[0049] 5 is a block diagram of an example on-die error checking and correction (ECC) subsystem for implementing ECC sub-channel separation. System 500 provides an example of on-die ECC circuitry for a system according to a system compatible with diagram 202. Host 510 includes a memory controller or equivalent or alternative circuitry or component that manages access to memory 520. Host 510 performs external ECC on data read from memory 520. Memory 520 implements on-die ECC to check and correct data before sending it to host 510.

[0050] The system 500 shows a write path 532 in the memory 520, which represents the path of data written from the host 510 to the memory 520. The host 510 provides data 542 to the memory 520 for writing to the memory array. In one example, the memory 520 generates check bits 544 in a check bit generator 522 for storage with the data in the memory. The check bits 544, referred to as ECC bits, can enable the memory 520 to correct errors that may occur in writing to and reading from the memory array. The data 542 and check bits 544 can be included as a codeword input 546, which is written to the memory resource.

[0051] The read path 534 represents a path for data read from the memory 520 to the host 510. In one example, at least certain hardware components of the write path 532 and the read path 534 are the same hardware. In one example, the memory 520 fetches a codeword output 552 in response to a read command from the host 510. The codeword may include data 554 and check bits 556. The data 554 and check bits 556 may correspond to the data 542 and check bits 544, respectively, written to the write path 532. Thus, a read can access the data and ECC bits. It will be appreciated that error correction in the read path 534 may include application of an XOR (exclusive-OR) tree to a corresponding H matrix to detect and selectively correct errors (in the case of a single-bit error). As understood in the art, an H matrix refers to a Hamming code parity check matrix that indicates how linear combinations of digits in a codeword equal zero. Thus, the rows of the H matrix identify the coefficients of a parity check equation that must be satisfied for the components or digits that are part of the codeword. In one example, memory 520 includes syndrome decode 524, which enables the memory to apply check bits 556 to data 554 to detect errors in read data. Syndrome decode 524 can generate syndrome 558 for use in generating appropriate error information for the read data. Data 554 can also be forwarded to error correction 528 for correction of detected errors.

[0052] In one example, the syndrome decode 524 passes the syndrome 558 to the syndrome generator 526 to generate an error vector. In one example, the check bit generator 522 and the syndrome generator 526 are fully specified by the corresponding H matrix for the memory device. In one example, if there are no errors in the read data (e.g., zero syndrome 558), the syndrome generator 526 does not generate an error signal 562. In one example, if there are multiple errors in the read data (e.g., non-zero syndrome 558 that does not match any of the columns in the corresponding H matrix), the syndrome generator 526 generates a DUE (detected uncorrected error) signal 564, which indicates a detected uncorrected error. The DUE signal 564 can indicate a multi-bit error that the memory 520 was unable to correct using its internal ECC.

[0053] In one example, if there is a single-bit error (e.g., a non-zero syndrome 558 that matches one of the columns of the corresponding H matrix), the syndrome generator 526 can generate a CE (corrected error) signal at the error location 560, which is a corrected error indicator to the error correction logic 528. The error correction 528 can apply the corrected error to the identified location in the data 554 and generate corrected data 566 for output to the host 510. In one example, the error correction 528 also generates check bits 568, which include check bits for the read data.

[0054] The check bits 568 can be considered an error vector that indicates the state of errors in the read data sent to the host 510. It will be appreciated that the zero syndrome (no errors 562) condition and the corrected SBE resulting in the corrected data 566 will have the same check bits 568, indicating no errors to the host 510. Thus, the check bits 568 provide only multi-bit errors and not information about SBEs in the memory 520. In one example, the system 500 writes the corrected data back to the memory array.

[0055] In one example, system 500 includes an internal ECC write path 532 and an internal ECC read path 534 for each portion of the array. In accordance with a system compatible with diagram 202, memory device 520 may include one path for half of its I / O pins and a second path for the other half of its I / O pins. Thus, memory 520 can perform ECC isolation with hardware resources to isolate the application of ECC to individual subportions of the overall data provided by the memory device.

[0056] 6 is a block diagram of an example memory subsystem in which ECC sub-channel separation can be implemented. System 600 includes elements of a memory subsystem and a processor in a computing device. System 600 is an example of a system that can incorporate a system compatible with diagram 202.

[0057] In one example, memory device 640 includes ECC isolation 680 in memory array 660. ECC isolation 680 represents hardware and logic for implementing ECC isolation internal to the memory device within a channel subdivision according to any example herein. ECC isolation includes additional hardware resources to provide more driver circuitry for managing portions of the memory array as separate sub-channels for purposes of internal ECC operations. ECC isolation 680 can control the application of ECC by on-die ECC circuitry.

[0058] Processor 610 represents a processing unit of a computing platform that may execute an operating system (OS) and applications; processing units may collectively be referred to as hosts or users of memory. The OS and applications perform operations that result in memory accesses. Processor 610 may include one or more individual processors. Each individual processor may include a single processing unit, a multi-core processing unit, or a combination. A processing unit may be a primary processor, such as a central processing unit (CPU), a peripheral processor, such as a graphics processing unit (GPU), or a combination thereof. Memory accesses may also be initiated by devices such as a network controller or hard disk controller. Such devices may be integrated with the processor in some systems or may be connected to the processor via a bus (e.g., PCI Express), or a combination thereof. System 600 may be implemented as a system-on-chip (SOC) or as a standalone component.

[0059] References to memory devices can apply to different memory types. Memory devices often refer to volatile memory technology. Volatile memory is memory whose state (and therefore the data stored in it) is indeterminate if power to the device is removed. Non-volatile memory refers to memory whose state is determinate even when power to the device is removed. Dynamic volatile memory requires refreshing the data stored in the device to maintain its state. An example of dynamic volatile memory is DRAM (Dynamic Random Access Memory) or some variants such as Synchronous DRAM (SDRAM). The memory subsystem as described herein may be based on a variety of standards, including DDR4 (Double Data Rate (DDR) Version 4, JESD79-4, originally published by JEDEC in September 2012), LPDDR4 (Low Power DDR Version 4, JESD209-4, originally published by JEDEC in August 2014), WIO2 (Wide I / O2, JESD229-2, originally published by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235 A, originally published by JEDEC in November 2015), DDR5 (DDR version 5, currently being discussed by JEDEC), LPDDR5 (LPDDR version 5, JESD209-5, originally published by JEDEC in February 2019), HBM2 (HBM version 2, currently being discussed by JEDEC), or others, or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.

[0060] In one example, in addition to or alternatively to volatile memory, reference to a memory device can refer to a non-volatile memory device whose state is deterministic even when power to the device is interrupted. In one example, the non-volatile memory device is a block-addressable memory device, such as NAND or NOR technology. Accordingly, the memory device can also include future generations of non-volatile devices, such as three-dimensional cross-point memory devices and other byte-addressable non-volatile memory devices. The memory device can include a non-volatile byte-addressable medium that stores data based on the resistance state of a memory cell or the phase of a memory cell. In one example, the memory device can use a chalcogenide phase-change material (e.g., a chalcogenide glass). In one example, the memory device can be or include multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM) or switched phase change memory (PCMS), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory incorporating memristor technology, or spin transfer torque (STT)-MRAM, or any combination of the above, or other memory.

[0061] The memory controller 620 represents one or more memory controller circuits or devices for the system 600. The memory controller 620 represents control logic that generates memory access commands in response to the execution of operations by the processor 610. The memory controller 620 accesses one or more memory devices 640. The memory devices 640 can be DRAM devices according to any of the above references. In one example, the memory devices 640 are organized and managed as different channels, each channel coupled to buses and signal lines that couple multiple memory devices in parallel. Each channel is independently operable. Thus, each channel is independently accessed and controlled, and timing, data transfer, command and address exchange, and other operations are individual for each channel. Coupling can refer to electrical coupling, communicative coupling, physical coupling, or a combination thereof. Physical coupling can include direct contact. Electrical coupling includes interfaces or interconnections that allow electrical flow between components, signal transmission between components, or both. Communicative coupling includes connections, including wired or wireless, that allow components to exchange data.

[0062] In one example, the configuration of each channel is controlled by a separate mode register or other register setting. In one example, each memory controller 620 manages a separate memory channel, although system 600 can be configured to have multiple channels managed by a single controller or to have multiple controllers on a single channel. In one example, memory controller 620 is part of host processor 610, such as logic implemented on the same die or in the same package space as the processor.

[0063] The memory controller 620 includes I / O interface logic 622 for coupling to a memory bus, such as the memory channel mentioned above. The I / O interface logic 622 (as well as the I / O interface logic 642 of the memory device 640) may include pins, pads, connectors, signal lines, traces, or wires, or other hardware connecting devices, or a combination thereof. The I / O interface logic 622 may include a hardware interface. As shown, the I / O interface logic 622 includes at least drivers / transceivers for the signal lines. Typically, wires in an integrated circuit interface couple with pads, pins, or connectors to interface signal lines or traces or other wires between devices. The I / O interface logic 622 may include drivers, receivers, transceivers, or terminations, or other circuits or combinations of circuits, to exchange signals on the signal lines between devices. The exchange of signals includes at least one of sending or receiving. While shown coupling I / O 622 from memory controller 620 to I / O 642 of memory device 640, it will be understood that in implementations of system 600 where a group of memory devices 640 are accessed in parallel, multiple memory devices may include I / O interfaces to the same interface of memory controller 620. In implementations of system 600 that include one or more memory modules 670, I / O 642 may include interface hardware of the memory modules in addition to interface hardware on the memory devices themselves. Other memory controllers 620 include separate interfaces to other memory devices 640.

[0064] The bus between the memory controller 620 and the memory devices 640 can be implemented as multiple signal lines coupling the memory controller 620 to the memory devices 640. The bus typically includes at least a clock (CLK) 632, a command / address (CMD) 634, write data (DQ) and read data (DQ) 636, and zero or more other signal lines 638. In one example, the bus or connection between the memory controller 620 and the memory can be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The CMD signal line can be referred to as a "C / A bus" (or ADD / CMD bus, or some other name indicating the transfer of command (C or CMD) and address (A or ADD) information), and the write and read DQ signal lines can be referred to as a "data bus." In one example, independent channels have different clock signals, C / A bus, data bus, and other signal lines. Thus, system 600 can be considered to have multiple “buses,” in the sense that independent interface paths can be considered separate buses. It will be understood that, in addition to the lines explicitly shown, a bus can include at least one of a strobe signaling line, an alert line, an auxiliary line, or other signal lines, or a combination thereof. It will also be understood that serial bus technology can be used for the connection between memory controller 620 and memory devices 640. An example of a serial bus technology is 8B10B encoding and transmission of high-speed data with an embedded clock over a single differential pair of signals in each direction. In one example, CMD 634 represents a signal line shared with multiple memory devices in parallel. In one example, multiple memory devices share the encoding command signal line of CMD 634, each with an individual chip select (CS_n) signal line for selecting an individual memory device.

[0065] It will be appreciated that in the example system 600, the bus between the memory controller 620 and the memory devices 640 includes a subordinate command bus (CMD 634) and an auxiliary bus to carry write and read data, DQ 636. In one example, the data bus can include bidirectional lines for read data and write / command data. In another example, the auxiliary bus DQ 636 can include a unidirectional write signal line for writing and data from the host to the memory, and a unidirectional line for reading data from the memory to the host. Depending on the selected memory technology and system design, other signals 638 can be associated with the bus or sub-bus, such as a strobe line DQS. Based on the design or implementation of the system 600, the data bus can have more or less bandwidth per memory device 640 if the design supports multiple implementations. For example, the data bus can support memory devices with either a x4 interface, a x8 interface, a x16 interface, or other interfaces. In the convention "xW," W is an integer that refers to the interface size or width of the interface of the memory device 640, representing the number of signal lines for exchanging data with the memory controller 620. The interface size of a memory device is the controlling factor for how many memory devices can be used simultaneously per channel in the system 600 or coupled in parallel to the same signal lines. In one example, high-bandwidth memory devices, wide-interface devices, or stacked memory configurations, or a combination thereof, can enable a wider interface, such as a x128 interface, a x256 interface, a x512 interface, a x1024 interface, or other data bus interface width.

[0066] In one example, the memory device 640 and the memory controller 620 exchange data over the data bus in bursts, or a continuous series of data transfers. A burst corresponds to the number of transfer cycles related to the bus frequency. In one example, a transfer cycle can be a full clock cycle of transfers occurring on the same clock or strobe signal edge (e.g., rising edge). In one example, every clock cycle, which refers to a cycle of the system clock, is divided into multiple unit intervals (UIs), with each UI being a transfer cycle. For example, a double data rate transfer triggers on both edges (e.g., rising and falling) of the clock signal. A burst can last for a configured number of UIs, which can be a registered or triggered on the fly. For example, a series of eight consecutive transfer periods can be considered a burst length 8 (BL8), with each memory device 640 transferring data on each UI. Thus, a x8 memory device operating at BL8 can transfer 64 bits of data (8 data signal lines x 8 data bits transferred per line via the burst). It will be understood that this simple example is merely illustrative and not limiting.

[0067] The memory devices 640 represent memory resources for the system 600. In one example, each memory device 640 is an individual memory die. In one example, each memory device 640 can interface with multiple (e.g., two) channels per device or per die. Each memory device 640 includes I / O interface logic 642 with a bandwidth (e.g., x16, x8, or some other interface bandwidth) determined by the device implementation. The I / O interface logic 642 allows the memory device to interface with the memory controller 620. The I / O interface logic 642 can include a hardware interface and can follow the I / O 622 of the memory controller, but at the memory device end. In one example, multiple memory devices 640 are connected in parallel to the same command and data bus. In another example, multiple memory devices 640 are connected in parallel to the same command bus and to different data buses. For example, the system 600 can be configured with multiple memory devices 640 coupled in parallel, each responding to commands and accessing its own internal memory resources 660. For write operations, each memory device 640 can write a portion of an entire data word, and for read operations, each memory device 640 can fetch a portion of an entire data word, with the remaining bits of the word being provided or received in parallel by other memory devices.

[0068] In one example, memory device 640 is disposed directly on a motherboard of a computing device or host system platform (e.g., a PCB (printed circuit board) on which processor 610 is disposed). In one example, memory device 640 can be configured into memory module 670. In one example, memory module 670 represents a dual in-line memory module (DIMM). In one example, memory module 670 represents other organization of multiple memory devices that share at least a portion of access or control circuitry, which may be separate circuits, separate devices, or separate boards from the host system platform. Memory module 670 can include multiple memory devices 640, and memory modules can include support for multiple separate channels to the contained memory devices disposed therein. In other examples, memory device 640 can be integrated into the same package as memory controller 620 by techniques such as multi-chip module (MCM), package-on-package, through silicon via (TSV), or other techniques or combinations thereof. Similarly, in one example, multiple memory devices 640 can be integrated into memory module 670, which itself can be integrated into the same package as memory controller 620. It will be appreciated that in these and other implementations, memory controller 620 may be part of host processor 610.

[0069] The memory devices 640 each include one or more memory arrays 660. The memory arrays 660 represent addressable memory locations or storage locations for data. Typically, the memory arrays 660 are managed as rows of data and accessed via wordline (row) and bitline (individual bits within a row) control. The memory arrays 660 can be organized as separate channels, ranks, and banks of memory. A channel may refer to an independent control path to storage locations within the memory device 640. A rank may refer to a common location across multiple memory devices in parallel (e.g., the same row address in different devices). A bank may refer to a sub-array of memory locations within the memory device 640. In one example, a bank of memory is divided into sub-banks with at least some of the circuitry for the sub-banks (e.g., drivers, signal lines, control logic) shared to enable individual addressing and access. It will be understood that channels, ranks, banks, sub-banks, bank groups, or other configurations of memory locations, and combinations of these configurations, may overlap in application to physical resources. For example, the same physical memory location can belong to a rank and be accessed through a particular channel as a particular bank. Thus, the configuration of memory resources will be understood in an inclusive manner, rather than an exclusive manner.

[0070] In one example, memory device 640 includes one or more registers 644. Registers 644 represent one or more storage devices or storage locations that provide configuration or settings for operation of the memory device. In one example, registers 644 can provide storage locations in memory device 640 that store data for access by memory controller 620 as part of control or management operations. In one example, registers 644 include one or more mode registers. In one example, registers 644 include one or more general-purpose registers. Configuration of locations in registers 644 can configure memory device 640 to operate in different “modes,” and command information can trigger different operations in memory device 640 based on the mode. Additionally or alternatively, different modes can also trigger different operations from address information or other signal lines depending on the mode. Settings in registers 644 can indicate configuration of I / O settings (e.g., timing, termination or ODT (on-die termination) 646, driver configuration, or other I / O settings).

[0071] In one example, the memory device 640 may include an ODT 646 as part of the interface hardware associated with the I / O 642. The ODT 646 may be configured as described above to provide a setting for the impedance applied to the interface for specific signal lines. In one example, the ODT 646 is applied to the DQ signal lines. In one example, the ODT 646 is applied to the command signal lines. In one example, the ODT 646 is applied to the address signal lines. In one example, the ODT 646 may be applied to any combination of the above. The ODT setting may be changed based on whether the memory device is the selected target or non-target device of an access operation. The ODT 646 setting may affect the timing and reflection of signaling on the termination lines. Careful control of the ODT 646 may improve the matching of the applied impedance and load, enabling high-speed operation. The ODT 646 may be applied to specific signal lines of the I / O interface 642, 622 (e.g., ODT for the DQ lines or ODT for the CA lines), but not necessarily to all signal lines.

[0072] The memory device 640 includes a controller 650, which represents control logic within the memory device for controlling internal operations within the memory device. For example, the controller 650 decodes commands sent by the memory controller 620 and generates internal operations to execute or satisfy the commands. The controller 650 may be referred to as an internal controller and is separate from the host's memory controller 620. The controller 650 may determine which mode is selected based on the register 644 and configure internal execution for operations to access the memory resources 660 or other operations based on the selected mode. The controller 650 generates control signals that control the routing of bits within the memory device 640 to provide an appropriate interface for the selected mode and to send commands to the appropriate memory locations or addresses. The controller 650 includes command logic 652 that can decode command encodings received on the command and address signal lines. Thus, the command logic 652 may be or include a command decoder. Using the command logic 652, the memory device can identify commands and generate internal operations to execute the requested commands.

[0073] Referring again to memory controller 620, memory controller 620 includes command (CMD) logic 624, which represents logic or circuitry for generating commands to send to memory device 640. Generating a command refers to a command prior to scheduling or preparing a queued command ready for transmission. Typically, signaling in a memory subsystem includes address information within or accompanying a command to indicate or select one or more memory locations where the memory device should execute the command. In response to scheduling a transaction for memory device 640, memory controller 620 can issue a command via I / O 622 to cause memory device 640 to execute the command. In one example, controller 650 of memory device 640 receives and decodes command and address information received from memory controller 620 via I / O 642. Based on the received command and address information, controller 650 can control the timing of operation of logic and circuitry within memory device 640 to execute the command. Controller 650 is responsible for compliance with standards or specifications, such as timing and signaling requirements, within memory device 640. Memory controller 620 can implement compliance with standards or specifications by scheduling and controlling accesses.

[0074] The memory controller 620 includes a scheduler 630, which represents logic or circuitry for generating and sequencing transactions for transmission to the memory device 640. From one perspective, the primary function of the memory controller 620 is to schedule memory accesses and other transactions to the memory device 640. Such scheduling may include generating the transactions themselves, implementing requests for data by the processor 610, and maintaining data integrity (e.g., using refresh-related commands). A transaction may include one or more commands, resulting in the transfer of commands, data, or both over one or more timing cycles, such as a clock cycle or a unit interval. Transactions may be for accesses, such as reads or writes, or related commands, or combinations thereof, while other transactions may include memory management commands for configuration, settings, data integrity, or other commands, or combinations thereof.

[0075] The memory controller 620 typically includes logic, such as a scheduler 630, that enables the selection and ordering of transactions to improve performance of the system 600. Thus, the memory controller 620 can select which outstanding transactions should be sent to the memory devices 640 and in what order, which is typically achieved with logic much more complex than a simple first-in-first-out algorithm. The memory controller 620 manages the sending of transactions to the memory devices 640 and manages the timing associated with the transactions. In one example, the transactions are managed by the memory controller 620 and have deterministic timing that can be used in determining how to schedule the transactions using the scheduler 630.

[0076] In one example, the memory controller 620 includes refresh (REF) logic 626. The refresh logic 626 can be used for memory resources that are volatile and need to be refreshed to maintain a defined state. In one example, the refresh logic 626 indicates the location of the refresh and the type of refresh to perform. The refresh logic 626 can trigger a self-refresh in the memory device 640 or perform an external refresh (which can be referred to as an auto-refresh command) by sending a refresh command, or a combination thereof. In one example, the controller 650 in the memory device 640 includes refresh logic 654 to apply the refresh in the memory device 640. In one example, the refresh logic 654 can generate an internal operation to perform the refresh according to the external refresh received from the memory controller 620. The refresh logic 654 can determine that a refresh is targeted to the memory device 640 and which memory resource 660 to refresh in response to the command.

[0077] 7 is a block diagram of an example computing system in which ECC sub-channel separation can be implemented. System 700 represents a computing device according to any example herein and may be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, an embedded computing device, or other electronic device. System 700 provides an example of a system in which a system compatible with diagram 202 may be incorporated.

[0078] In one example, memory subsystem 720 includes ECC isolation 790 in memory 730. ECC isolation represents hardware and logic for implementing ECC isolation internal to a memory device within a channel subdivision according to any example herein. ECC isolation includes additional hardware resources to provide more driver circuitry for managing portions of the memory array as separate subchannels for purposes of internal ECC operations. ECC isolation 790 can control the application of ECC by on-die ECC circuitry.

[0079] System 700 has a processor 710, which may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or combination thereof, to provide processing or execution of instructions for system 700. Processor 710 controls the overall operation of system 700 and may be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., or a combination of such devices.

[0080] In one example, system 700 includes an interface 712 coupled to processor 710, which may represent a higher speed or higher throughput interface for system components requiring a higher bandwidth connection, such as memory subsystem 720 or graphics interface component 740. Interface 712 represents interface circuitry that may be a standalone component or integrated into the processor die. Interface 712 may be integrated into the processor die as a circuit or into a system-on-chip as a component. If included, graphics interface 740 interfaces to a graphics component to provide a visual display to a user of system 700. Graphics interface 740 may be a standalone component or integrated into the processor die or system-on-chip. In one example, graphics interface 740 can drive a high-definition (HD) display or an ultra-high-definition (UHD) display to provide output to the user. In one example, the display may include a touchscreen display. In one example, graphics interface 740 generates a display based on data stored in memory 730, or based on operations performed by processor 710, or both.

[0081] Memory subsystem 720 represents the main memory of system 700 and provides storage for code to be executed by processor 710 or data values ​​to be used in the execution of routines. Memory subsystem 720 can include one or more memory devices 730, such as read-only memory (ROM), flash memory, one or more variants of random access memory (RAM) such as DRAM, 3DXP (three-dimensional crosspoint), or other memory devices, or a combination of such devices. Memory 730 stores and hosts, among other things, an operating system (OS) 732, providing a software platform for the execution of instructions within system 700. Furthermore, applications 734 can execute on the software platform of OS 732 from memory 730. Applications 734 represent programs that have their own operational logic for performing the execution of one or more functions. Processes 736 represent agents or routines that provide auxiliary functionality to OS 732 or one or more applications 734, or a combination thereof. OS 732, applications 734, and processes 736 provide software logic that provides functionality for system 700. In one example, memory subsystem 720 includes memory controller 722, which is a memory controller that generates and issues commands to memory 730. It will be appreciated that memory controller 722 may be a physical part of processor 710 or a physical part of interface 712. For example, memory controller 722 may be an integrated memory controller and may be integrated into circuitry with processor 710, such as integrated into a processor die or system-on-chip.

[0082] Although not specifically shown, it will be understood that system 700 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, or an interface bus. A bus or other signal lines may communicatively or electrically couple components to each other, or may couple components both communicatively and electrically. A bus may include physical communication lines, point-to-point connections, circuits such as bridges, adapters, or controllers, or combinations thereof. A bus may include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or other bus, or combinations thereof.

[0083] In one example, system 700 includes interface 714, which may be coupled to interface 712. Interface 714 may be a lower speed interface than interface 712. In one example, interface 714 represents an interface circuit, which may include standalone components and integrated circuits. In one example, multiple user interface components or peripherals, or both, are coupled to interface 714. Network interface 750 provides system 700 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 750 may include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a Universal Serial Bus (USB), or other wired or wireless standard-based or proprietary interface. Network interface 750 may exchange data with remote devices, which may include sending data stored in memory or receiving data stored in memory.

[0084] In one example, system 700 includes one or more input / output (I / O) interfaces 760. I / O interface 760 can include one or more interface components through which a user interacts with system 700 (e.g., audio, alphanumeric, haptic / touch, or other interface methods). Peripheral interface 770 can include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that are dependently connected to system 700. A dependent connection is one in which system 700 provides a software or hardware platform, or both, on which operations execute and with which a user interacts.

[0085] In one example, system 700 includes a storage subsystem 780 for storing data in a nonvolatile manner. In one example, in a particular system implementation, at least certain components of storage 780 can overlap with components of memory subsystem 720. Storage subsystem 780 includes storage device 784, which can be or can include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid-state, 3DXP, or optical-based disks, or a combination thereof. Storage 784 holds code or instructions and data 786 in a persistent state (i.e., retains value even when power to system 700 is interrupted). While memory 730 is typically the executing or operating memory for providing instructions to processor 710, storage 784 can generally be considered to be “memory.” While storage 784 is nonvolatile, memory 730 can include volatile memory (i.e., the value or state of data is indeterminate when power to system 700 is interrupted). In one example, storage subsystem 780 includes a controller 782 that interfaces with storage 784. In one example, controller 782 may be a physical portion of interface 714 or processor 710, or may include circuitry or logic in both processor 710 and interface 714.

[0086] The power source 702 provides power to the components of the system 700. More specifically, the power source 702 typically interfaces to one or more power supplies 704 in the system 700 to provide power to the components of the system 700. In one example, the power supply 704 includes an AC-DC (alternating current to direct current) adapter that connects to a wall outlet. Such AC power can be a renewable energy (e.g., solar-powered) power source 702. In one example, the power source 702 includes a DC power source, such as an external AC-DC converter. In one example, the power source 702 or the power supply 704 includes wireless charging hardware for charging in proximity to a charging field. In one example, the power source 702 can include an internal battery or fuel cell power source.

[0087] 8 is a block diagram of an example of a mobile device in which ECC subchannel separation can be implemented. System 800 represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wearable computing device, or other mobile or embedded computing device. It will be understood that some of the components are shown generically, and not all components of such a device are shown in system 800. System 800 provides an example of a system in which a system compatible with diagram 202 can be incorporated.

[0088] In one example, memory subsystem 860 includes ECC isolation 890 in memory 862. ECC isolation represents hardware and logic for implementing ECC isolation internal to a memory device within a subdivision of a channel according to any example herein. ECC isolation includes additional hardware resources to provide more driver circuitry for managing portions of the memory array as separate subchannels for purposes of internal ECC operations. ECC isolation 890 can control the application of ECC by on-die ECC circuitry.

[0089] System 800 includes a processor 810 that performs the primary processing operations of system 800. Processor 810 may include one or more physical devices such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. The processing operations performed by processor 810 include running an operating platform or operating system on which applications and device functions run. The processing operations may include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting system 800 to other devices, or any combination thereof. The processing operations may also include operations related to audio I / O, display I / O, or other interfaces, or any combination thereof. Processor 810 may execute data stored in memory. Processor 810 may write or edit data stored in memory.

[0090] In one example, system 800 includes one or more sensors 812. Sensors 812 represent built-in sensors, interfaces to external sensors, or a combination thereof. Sensors 812 enable system 800 to monitor or detect one or more conditions of the environment or device in which system 800 is implemented. Sensors 812 may include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors for detecting physiological attributes, heart rate monitors, or other sensors), or other sensors, or combinations thereof. Sensors 812 may also include sensors for biometric systems, such as fingerprint recognition systems, face detection or recognition systems, or other systems that detect or recognize user features. Sensors 812 should be understood broadly and are not limiting of the many different types of sensors that may be implemented in system 800. In one example, the one or more sensors 812 couple to the processor 810 through front-end circuitry integrated into the processor 810. In one example, the one or more sensors 812 couple to the processor 810 through other components of the system 800.

[0091] In one example, system 800 includes an audio subsystem 820 that represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. Audio functionality may include speaker or headphone output, as well as a microphone input. Devices for such functionality may be integrated into or connected to system 800. In one example, a user interacts with system 800 by providing audio commands that are received and processed by processor 810.

[0092] Display subsystem 830 represents hardware components (e.g., display devices) and software components (e.g., drivers) that provide a visual display for presentation to a user. In one example, the display includes a tactile component or touchscreen element through which a user interacts with the computing device. Display subsystem 830 includes display interface 832, which includes a particular screen or hardware device used to provide a display to a user. According to one example, display interface 832 includes logic circuitry separate from processor 810 (e.g., a graphics processor) for performing at least some processing related to the display. In one example, display subsystem 830 includes a touchscreen device that provides both output and input to a user. In one example, display subsystem 830 includes a high-definition (HD) or ultra-high-definition (UHD) display that provides output to a user. In one example, display subsystem 830 includes or drives a touchscreen display. In one example, display subsystem 830 generates display information based on data stored in memory, based on operations performed by processor 810, or both.

[0093] I / O controller 840 represents hardware devices and software components related to user interaction. I / O controller 840 may operate to manage hardware that is part of audio subsystem 820 or display subsystem 830, or both. Additionally, I / O controller 840 represents connection points for additional devices that connect to system 800 through which a user can interact with the system. For example, devices that may be attached to system 800 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, buttons / switches, or other I / O devices for use with particular applications, such as a card reader or other device.

[0094] As described above, I / O controller 840 can interact with audio subsystem 820, display subsystem 830, or both. For example, input through a microphone or other audio device may provide input or commands for one or more applications or functions of system 800. Furthermore, audio output may be provided instead of, or in addition to, display output. In another example, if the display subsystem includes a touchscreen, the display device also operates as an input device that may be at least partially managed by I / O controller 840. Additional buttons or switches may also be present on system 800 to provide I / O functions managed by I / O controller 840.

[0095] In one example, I / O controller 840 manages devices or sensors 812, such as accelerometers, cameras, light or other environmental sensors, gyroscopes, global positioning systems (GPS), or other hardware that may be included in system 800. The inputs may be part of direct user interaction and may also provide environmental input to the system to affect its operation (such as filtering noise, adjusting a display for brightness detection, applying a flash for a camera, or other features).

[0096] In one example, system 800 includes power management 850, which manages battery power usage, battery charging, and functions related to power-saving operation. Power management 850 manages power from a power source 852 and provides power to components of system 800. In one example, power source 852 includes an AC-DC (alternating current to direct current) adapter that connects to a wall outlet. Such AC power can be renewable energy (e.g., solar power, motion-based power). In one example, power source 852 includes only DC power, which can be provided by a DC power source, such as an external AC-DC converter. In one example, power source 852 includes wireless charging hardware for charging in proximity to a charging field. In one example, power source 852 can include an internal battery or fuel cell power source.

[0097] Memory subsystem 860 includes memory device 862 for storing information within system 800. Memory subsystem 860 can include nonvolatile (state does not change when power to the memory device is removed) or volatile (state is indeterminate when power to the memory device is removed) memory devices, or a combination thereof. Memory 860 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of system 800. In one example, memory subsystem 860 includes memory controller 864 (which may also be considered part of the control of system 800 and potentially part of processor 810). Memory controller 864 includes a scheduler for generating and issuing commands that control access to memory device 862.

[0098] The connectivity functionality 870 includes hardware devices (e.g., wireless or wired connectors and communications hardware, or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) that enable the system 800 to communicate with external devices. The external devices can be other computing devices, discrete devices such as wireless access points or base stations, and peripherals such as headsets, printers, or other devices. According to one example, the system 800 exchanges data with the external devices for storage in memory or for display on a display device. The exchanged data can include data to be stored in memory or data already stored in memory for reading, writing, or editing data.

[0099] Connectivity functionality 870 can include multiple different types of connectivity functionality. Generalizing, system 800 is shown with cellular connectivity functionality 872 and wireless connectivity functionality 874. Cellular connectivity functionality 872 generally refers to cellular network connectivity provided by a wireless carrier, such as that provided via GSM (global system for mobile communications) or variants or derivatives, CDMA (code division multiple access) or variants or derivatives, TDM (time division multiplexing) or variants or derivatives, LTE (long term evolution—also referred to as “4G”), 5G, or other cellular service standards. Wireless connectivity functionality 874 refers to non-cellular wireless connectivity functionality and can include personal area networks (e.g., Bluetooth), local area networks (e.g., WiFi), wide area networks (e.g., WiMax), or other wireless communications, or combinations thereof. Wireless communications refers to the transfer of data through the use of modulated radio wave radiation over a non-solid medium. Wired communication occurs over a solid communication medium.

[0100] Peripheral connections 880 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for making peripheral connections. It will be understood that system 800 can be a peripheral device to other computing devices (“out” 882) or have peripheral devices connected to system 800 (“from” 884). System 800 typically has a “docking” connector for connecting to other computing devices for purposes such as managing (e.g., downloading, uploading, modifying, syncing) content on system 800. Additionally, the docking connector may allow system 800 to connect to certain peripherals that allow system 800 to control content output to, for example, audiovisual or other systems.

[0101] In addition to dedicated docking connectors or other dedicated connection hardware, system 800 can provide peripheral connectivity 880 via common or standards-based connectors. Common types can include Universal Serial Bus (USB) connectors (which can include any of several different hardware interfaces), DisplayPorts, including Mini DisplayPort (MDP), High-Definition Multimedia Interface (HDMI), or other types.

[0102] Generally, with respect to the description herein, in one example, a memory device includes an additional driver and an additional sub-array for each channel, and the channel is treated as two sub-channels with error checking and correction for each sub-portion internal to the memory device on the channel as a whole at the system level.

[0103] In one example, the additional sub-array stores additional ECC (Error Checking and Correction) data. In one example, the data bus is x4 or x8, and the additional sub-array and additional driver are for x4 implementations only. In one example, the channel is 64 bits across burst length. In one example, 128 bits are prefetched and only 64 bits are transferred to the I / O (Input / Output) circuitry. In one example, the memory device includes a dynamic random access memory (DRAM) device. In one example, the DRAM device includes a synchronous DRAM (SDRAM) device compatible with the double data rate (DDR) standard.

[0104] Generally, with respect to the description herein, in one example, a system has a controller and a memory device including an additional driver and an additional sub-array for each channel, and the channel is treated as two sub-channels with error checking and correction for each sub-portion internal to the memory device on the channel as a whole at the system level.

[0105] In one example, the additional sub-array stores additional ECC (Error Checking and Correction) data. In one example, the data bus is x4 or x8, and the additional sub-array and additional driver are for x4 implementation only. In one example, the channel is 64-bit across burst length. In one example, 128 bits are prefetched and only 64 bits are transferred to the I / O (Input / Output) circuitry. In one example, the memory device includes a dynamic random access memory (DRAM) device. In one example, the DRAM device includes a synchronous DRAM (SDRAM) device compatible with the double data rate (DDR) standard. In one example, the system further includes one or more of a host processor device coupled to the memory device, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery that provides power to the system.

[0106] Generally, with respect to the description herein, in one example, a memory device comprises a hardware interface that couples to data signal lines for exchanging data with a host, and error checking and correction (ECC) hardware within the memory device for applying ECC to N data bits in two groups of N / 2 bits.

[0107] In one example, N is equal to 64. In one example, the memory device includes hardware for prefetching 128 bits of data and transferring only 64 bits of data to I / O (input / output) circuitry of the hardware interface. In one example, the memory device further includes a memory array, the memory array including multiple sub-arrays for providing N data bits, the memory array including an additional sub-array beyond the N data bits for storing additional ECC data. In one example, the memory device includes drivers associated with the sub-arrays, the memory device including an additional driver for controlling access to the additional sub-array. In one example, the hardware interface is for coupling to a data bus that is x4 or x8, the additional sub-array and the additional driver only applying when the hardware interface couples to a x4 data bus. In one example, the N data bits include a channel, the ECC hardware treats the channel as two sub-channels each having N / 2 bits, and the host treats the channel as an N-bit channel for system-level ECC purposes. In one example, N data bits comprise a channel, and the ECC hardware treats the channel as two sub-channels, each having N / 2 bits, with each sub-channel being independently correctable. In one example, the memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard.

[0108] Generally, with respect to the description herein, in one example, a system includes a plurality of memory devices, the memory devices having hardware interfaces for coupling to data signal lines for exchanging data with a host and error checking and correction (ECC) hardware within the memory devices for applying ECC to N data bits in two groups of N / 2 bits, and a memory controller coupled to the memory devices, the memory controller providing system level ECC for data bits received from the memory devices.

[0109] In one example, N is equal to 64. In one example, the memory device includes hardware for prefetching 128 bits of data and transferring only 64 bits of data to I / O (input / output) circuitry of the hardware interface. In one example, the memory device includes a memory array, the memory array including multiple sub-arrays for providing N data bits, and the memory array including an additional sub-array beyond the N data bits for storing additional ECC data. In one example, the memory device includes drivers associated with the sub-arrays, and the memory device includes an additional driver for controlling access to the additional sub-array. In one example, the hardware interface is for coupling to a data bus that is x4 or x8, and the additional sub-array and additional driver apply only when the hardware interface couples to a x4 data bus. In one example, the N data bits include a channel, and the ECC hardware treats the channel as two sub-channels each having N / 2 bits, and the memory controller provides system-level ECC for the N data bits. In one example, the N data bits comprise a channel, and the ECC hardware treats the channel as two sub-channels, each having N / 2 bits, with each sub-channel being independently correctable. In one example, the memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard. In one example, the system further comprises one or more of a host processor device coupled to the memory controller, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery that provides power to the system.

[0110] Generally with respect to the description herein, in one example, a method includes receiving a data access command for accessing N data bits of a memory array of a memory device, and applying error checking and correction (ECC) to the N data bits in two groups of N / 2 bits within the memory device.

[0111] In one example, N is equal to 64. In one example, internally applying the ECC to the N data bits includes applying the ECC to N data bits transmitted in response to a read command, including performing error correction on each group of N / 2 bits. In one example, internally applying the ECC to the N data bits includes applying the ECC to N data bits received with a write command, including writing an error code for each group of N / 2 bits. In one example, prefetching 128 bits of data and transferring only 64 bits of data to an I / O (input / output) circuit of the memory device. In one example, the memory array includes multiple sub-arrays for providing the N bits, and the memory array includes additional sub-arrays beyond the N bits for storing additional ECC data. In one example, the memory device includes drivers associated with the sub-arrays, and the memory device includes an additional driver for controlling access to the additional sub-arrays. In one example, the memory device includes a hardware interface for coupling to a data bus that is x4 or x8, and the additional sub-arrays and additional drivers are applied only when the hardware interface couples to the x4 data bus. In one example, the N data bits comprise a channel, and applying the ECC comprises treating the channel as two sub-channels each having N / 2 bits, and a host coupled to the memory device treats the channel as an N-bit channel for system-level ECC purposes. In one example, the N data bits comprise a channel, and the ECC hardware treats the channel as two sub-channels each having N / 2 bits, and each sub-channel is independently correctable. In one example, the memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard.

[0112] The flow diagrams shown herein provide example sequences of various processing operations. The flow diagrams may depict operations to be performed by software or firmware routines as well as physical operations. The flow diagrams may depict example implementations of states of a finite state machine (FSM), which may be implemented in hardware and / or software. Although shown in a particular order or sequence, unless otherwise specified, the order of operations may be modified. Therefore, the illustrated diagrams should be understood as examples only, and processing may be performed in a different order, and some actions may be performed in parallel. Additionally, one or more operations may be omitted, and therefore not all implementations may perform all operations.

[0113] To the extent that various operations or functions are described herein, they may be described or defined as software code, instructions, configurations, and / or data. Content may be directly executable ("object" or "executable"), source code, or differential code ("delta" or "patch" code). The software content described herein may be provided via a product on which the content is stored or via a method of operating a communications interface to transmit data over the communications interface. A machine-readable storage medium may cause a machine to perform the described functions or operations and includes any mechanism for storing information in a form accessible by a machine (e.g., a computing device, an electronic system, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communications interface may include any mechanism, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc., that interfaces with a hardwired, wireless, optical, etc. medium to communicate with another device. The communications interface may be configured by providing a number of configuration parameters and / or sending signals to prepare the communications interface to provide data signals describing the software content. The communications interface may be accessed via one or more commands or signals sent to the communications interface.

[0114] Various components described herein may be means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. The components may be implemented as software modules, hardware modules, dedicated hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuitry, etc.

[0115] In addition to what is described herein, various modifications can be made to the disclosed subject matter and implementations of the invention without departing from their scope. Accordingly, the illustrations and examples herein should be construed in an illustrative sense, and not in a limiting sense. The scope of the invention should be determined solely by reference to the claims that follow. Other possible claims [Item 1] 1. A memory device comprising: a hardware interface coupled to the data signal lines for exchanging data with a host; and error checking and correction (ECC) hardware within the memory device that applies ECC to the N data bits in two groups of N / 2 bits. Memory device. [Item 2] N is equal to 64 Item 1. The memory device of item 1. [Item 3] The memory device includes hardware for prefetching 128 bits of data and transferring only 64 bits of the data to I / O (input / output) circuitry of the hardware interface. Item 2. The memory device of item 2. [Item 4] The memory device further includes a memory array, the memory array including a plurality of sub-arrays for providing the N data bits, the memory array including additional sub-arrays beyond the N data bits for storing additional ECC data. Item 1. The memory device of item 1. [Item 5] The memory device includes a driver associated with the sub-array, and the memory device includes an additional driver for controlling access to the additional sub-array. Item 4. The memory device of item 4. [Item 6] The hardware interface is for coupling to a data bus that is x4 or x8, and the additional sub-arrays and additional drivers only apply when the hardware interface couples to a x4 data bus. Item 5. The memory device of item 5. [Item 7] The N data bits comprise a channel, and the ECC hardware applies ECC to the channel in sub-channels of N / 2 data bits each, each sub-channel being independently correctable. Item 1. The memory device of item 1. [Item 8] The memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard. Item 1. The memory device of item 1. [Item 9] a plurality of memory devices, each of the memory devices having a hardware interface for coupling to a data signal line for exchanging data with a host; the plurality of memory devices having error checking and correction (ECC) hardware within the memory devices for applying ECC to N data bits in two groups of N / 2 bits; a memory controller coupled to the memory device, the memory controller providing system level ECC for data bits received from the memory device. system. [Item 10] N is equal to 64 Item 9. The system according to item 9. [Item 11] The memory device includes hardware for prefetching 128 bits of data and transferring only 64 bits of the data to I / O (input / output) circuitry of the hardware interface. Item 11. The system according to item 10. [Item 12] The memory device includes a memory array, the memory array including a plurality of sub-arrays for providing the N data bits, the memory array including additional sub-arrays beyond the N data bits for storing additional ECC data. Item 9. The system according to item 9. [Item 13] The memory device includes a driver associated with the sub-array, and the memory device includes an additional driver for controlling access to the additional sub-array. Item 13. The system according to item 12. [Item 14] The hardware interface is for coupling to a data bus that is x4 or x8, and the additional sub-arrays and additional drivers only apply when the hardware interface couples to a x4 data bus. Item 14. The system according to item 13. [Item 15] The N data bits comprise a channel, and the ECC hardware applies ECC to the channel in two sub-channels of N / 2 data bits each, each sub-channel being independently correctable. Item 9. The system according to item 9. [Item 16] The memory device includes a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard. Item 9. The system according to item 9. [Item 17] and further comprising one or more of a host processor device coupled to the memory controller, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery for powering the system. Item 9. The system according to item 9. [Item 18] receiving a data access command for accessing N data bits of a memory array of a memory device; applying error checking and correction (ECC) to the N data bits in two groups of N / 2 bits within the memory device. method. [Item 19] Internally applying an ECC to the N data bits includes applying an ECC to the N data bits for transmission in response to a read command, and includes performing error correction on individual groups of N / 2 bits. Item 19. The method according to item 18. [Item 20] The step of internally applying an ECC to the N data bits comprises applying an ECC to the N data bits received with a write command, and includes writing an error code for each group of N / 2 bits. Item 19. The method according to item 18.

Claims

1. 1. A dynamic random access memory (DRAM) device comprising: a memory array for storing data, wherein data bits and error checking and correction bits (ECC bits) are prefetched from the memory array for a memory access operation; ECC hardware within the DRAM device that applies ECC to a first group of early data bits checked by early ECC bits in parallel with applying ECC to a second group of later data bits checked by later ECC bits; The data of the first group and the second group are exchanged via data signal lines corresponding to the first group and the second group, respectively. Memory device.

2. the DRAM device includes hardware for prefetching 128 data bits and 8 data bits of ECC bits; The ECC hardware checks two groups of 64 data bits with two groups of 4 ECC bits. The memory device of claim 1 .

3. the DRAM device further comprises a hardware interface connected to a memory controller; The hardware interface exchanges only 64 of the 128 data bits with the memory controller for the memory access operation. The memory device of claim 2 .

4. The ECC hardware performs ECC on the prefetched data bits for a read operation and corrects errors in the data bits before sending them to a memory controller. The memory device of claim 1 .

5. The ECC hardware performs ECC on the write data bits for write operations and generates the ECC bits that are stored in the memory array. The memory device of claim 1 .

6. The DRAM device comprises a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard. The memory device of claim 1 .

7. The SDRAM device has a x4 data (DQ) interface that exchanges data over a burst length of 18 (BL18). The memory device of claim 6.

8. 1. A system comprising: a plurality of dynamic random access memory (DRAM) devices coupled in parallel, said DRAM devices comprising: a memory array for storing data, wherein data bits and error checking and correction bits (ECC bits) are prefetched from the memory array for a memory access operation; ECC hardware within the DRAM device that applies ECC to a first group of data bits that are checked by the first ECC bits in parallel with applying ECC to a second group of data bits that are checked by the second ECC bits; a memory controller coupled to the DRAM devices, the memory controller providing system level ECC for data bits received in parallel from the plurality of DRAM devices; The data of the first group and the second group are exchanged via data signal lines corresponding to the first group and the second group, respectively. system.

9. the DRAM device includes hardware for prefetching 128 data bits and 8 ECC bits; The ECC hardware checks two groups of 64 data bits with two groups of 4 ECC bits. The system of claim 8.

10. The memory controller exchanges only 64 of the 128 data bits with each DRAM device for memory access operations. The system of claim 9.

11. The ECC hardware performs ECC on the prefetched data bits for a read operation and corrects errors in the data bits before sending the data bits to the memory controller. The system of claim 8.

12. The ECC hardware performs ECC on the write data bits for write operations and generates the ECC bits that are stored in the memory array. The system of claim 8.

13. The DRAM device comprises a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard. The system of claim 8.

14. The SDRAM device has a x4 data (DQ) interface that exchanges data over a burst length of 18 (BL18). The system of claim 13.

15. and further comprising one or more of a host processor device coupled to the memory controller, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery for powering the system. The system of claim 8.

16. receiving a data access command for a memory access operation; prefetching data bits and error checking and correction bits (ECC bits) from a memory array in a memory device; applying ECC to a second group of later data bits checked by later ECC bits in parallel with applying ECC to a first group of earlier data bits checked by later ECC bits within the DRAM device; The data of the first group and the second group are exchanged via data signal lines corresponding to the first group and the second group, respectively. method.

17. The prefetching step includes prefetching 128 data bits and 8 ECC bits, The step of applying the ECC involves checking two groups of 64 data bits with two groups of 4 ECC bits.

17. The method of claim 16.

18. The step of applying the ECC includes performing ECC on the data bits prefetched for a read operation and correcting errors in the data bits before transmitting the data bits to a memory controller.

17. The method of claim 16.

19. The memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard.

17. The method of claim 16.

20. The SDRAM device has a x4 data (DQ) interface that exchanges data over a burst length of 18 (BL18).

20. The method of claim 19.

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