Semiconductor device

Abstract

To provide a semiconductor device in which switching breakdown is suppressed.SOLUTION: A semiconductor device includes a gate trench part 40 and a dummy trench part 30 adjacent to the gate trench part. The semiconductor device includes a drift region of a first conductivity type provided on a semiconductor substrate 10, a base region 14 of a second conductivity type provided over the drift region, an emitter region 12 of the first conductivity type provided over the base region and having higher doping concentration than the drift region, and a contact region 15 of the second conductivity type provided over the base region and having higher doping concentration than the base region. In a mesa part 71 between the gate trench part and the dummy trench part, the contact region is provided below a lower end of the emitter region on the dummy trench part side.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 states that "the characteristics such as saturation current of a semiconductor device are improved." [Prior art document] [Patent documents] [Patent Document 1] JP 2018-195798 A [Patent Document 2] International Publication No. 2018 / 052098 Pamphlet Summary of the Invention [Problem to be solved by the invention]

[0003] A semiconductor device that suppresses switching breakdown is provided. [Means for solving the problem]

[0004] A first aspect of the present invention provides a semiconductor device including a gate trench portion and a first trench portion adjacent to the gate trench portion. The semiconductor device may include a drift region of a first conductivity type provided in a semiconductor substrate, a base region of a second conductivity type provided above the drift region, an emitter region of the first conductivity type provided above the base region and having a doping concentration higher than that of the drift region, and a contact region of the second conductivity type provided above the base region and having a doping concentration higher than that of the base region. In a mesa portion between the gate trench portion and the first trench portion, the contact region may be provided below a lower end of the emitter region.

[0005] The contact region may contact the first trench portion.

[0006] In the mesa portion, the contact region may be spaced apart from the gate trench portion.

[0007] The contact region may be spaced apart from the gate trench portion by 0.6 μm or more in the trench arrangement direction.

[0008] The contact region may be provided on the front surface of the semiconductor substrate, on a sidewall of the first trench portion.

[0009] The semiconductor device may include an interlayer insulating film provided above the semiconductor substrate, and the emitter region may be electrically connected to the emitter electrode via a contact hole provided through the interlayer insulating film.

[0010] The emitter region may extend from the gate trench portion across the contact hole toward the first trench portion in the trench arrangement direction.

[0011] The semiconductor device may include an accumulation region of the first conductivity type between the drift region and the base region, the accumulation region having a doping concentration higher than that of the drift region.

[0012] The semiconductor device may include a plurality of gate trench portions and a plurality of first trench portions, and the ratio of the number of the plurality of gate trench portions to the number of the plurality of first trench portions may be 1:1.

[0013] The semiconductor device may include a plurality of gate trench portions and a plurality of first trench portions, and the ratio of the number of the plurality of gate trench portions to the number of the plurality of first trench portions may be 1:2.

[0014] The emitter region may extend from the gate trench portion to the dummy trench portion in the trench arrangement direction, and may terminate without reaching the first trench portion.

[0015] The emitter region may extend from the gate trench portion to the first trench portion in the trench arrangement direction.

[0016] On the front surface of the semiconductor device, contact regions and emitter regions may be provided alternately in contact with each other in the extension direction of the gate trench portion.

[0017] The first trench portion may be set to an emitter potential.

[0018] The first trench portion may be set to a gate potential.

[0019] The first trench portion may be a dummy trench. The emitter region may be in contact with the gate trench portion in the mesa portion and may be spaced apart from the first trench portion. The contact region may be provided in the mesa portion below a lower end of the emitter region on the first trench portion side.

[0020] The first trench portion may include a dummy gate trench portion that is set to a gate potential and does not contact the emitter region.

[0021] The first trench portion may include a dummy trench portion that is set to the emitter potential.

[0022] The emitter region may have a first emitter region in the mesa portion that is in contact with the gate trench portion and spaced apart from the first trench portion. The contact region may be provided in the mesa portion below the lower end of the first emitter region on the first trench portion side.

[0023] The emitter region may further include a second emitter region in the mesa portion that is in contact with the first trench portion and spaced apart from the gate trench portion. The contact region may also be provided below the lower end of the second emitter region on the gate trench portion side in the mesa portion.

[0024] The first emitter regions and the second emitter regions may be provided alternately in the trench extension direction of the gate trench portion.

[0025] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0026] [Figure 1A] A top view of a semiconductor device 100 is shown. [Figure 1B] 1B is an example of a cross-sectional view taken along line aa' in FIG. 1A. [Figure 1C] 1B is an example of a cross-sectional view taken along the line bb' in FIG. 1A. [Figure 2] 1 shows an example of an enlarged cross-sectional view of a mesa portion 71. [Figure 3] 1 shows an example of a top view of a semiconductor device 100 having an unopened contact hole 54. [Figure 4A] An example of the simulation results of the static characteristics of the semiconductor device 100 is shown. [Figure 4B] An example of the simulation results of the on-characteristics of the semiconductor device 100 is shown. [Figure 4C] An example of a simulation result of the off-characteristics of the semiconductor device 100 is shown. [Figure 5A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 5B] 5B is an example of a cross-sectional view taken along the line c-c' in FIG. [Figure 6A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 6B] FIG. 6B is an example of a cross-sectional view taken along line dd' in FIG. 6A. [Figure 7A] 1 shows an example of a top view of a semiconductor device 100 according to a modified example. [Figure 7B] 7B is an example of a cross-sectional view taken along the line ee' in FIG. 7A. [Figure 8A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 8B] FIG. 8B is an example of a cross-sectional view taken along line ff' in FIG. 8A. [Figure 9A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 9B] FIG. 9B is an example of a cross-sectional view taken along line gg' in FIG. 9A. [Figure 10A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 10B] FIG. 10B is an example of a cross-sectional view taken along line hh' in FIG. 10A. [Figure 10C] 10B is another example of the cross-sectional view taken along line hh' in FIG. 10A. [Figure 11A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 11B] FIG. 11B is an example of a cross-sectional view taken along line ii' in FIG. 11A. [Figure 12A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 12B] FIG. 12B is an example of a cross-sectional view taken along line jj' in FIG. 12A. [Figure 13A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 13B] FIG. 13B is an example of a cross-sectional view taken along the line k-k' in FIG. 13A. DETAILED DESCRIPTION OF THE INVENTION

[0027] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0028] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one side is referred to as the front side and the other side is referred to as the back side. The directions of "upper," "lower," "front," and "back" are not limited to the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.

[0029] In this specification, technical matters may be explained using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the front surface of the semiconductor substrate is defined as the XY plane, and a direction that forms a right-handed system with the X and Y axes and is parallel to the depth direction of the semiconductor substrate is defined as the Z axis.

[0030] In each embodiment, an example is shown in which the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will be opposite polarities.

[0031] In this specification, layers and regions marked with an N or P have majority carriers of electrons or holes, respectively, and the + and - symbols attached to N and P indicate higher and lower doping concentrations, respectively, than layers and regions without those symbols.

[0032] 1A shows an example of a top view of a semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a trench-gate RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) in which multiple trench sections are arranged. In this example, the multiple trench sections are arranged in the X-axis direction and extend in the Y-axis direction.

[0033] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10, as will be described later in FIG. 1B. The collector region 22 has a second conductivity type. In this example, the collector region 22 is, for example, a P+ type. The transistor section 70 includes a transistor such as an IGBT.

[0034] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10, as will be described later in FIG. 1B. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is an N+ type, for example. The diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0035] FIG. 1A shows the region around the chip edge, which is the edge side of semiconductor device 100, and omits other regions. For example, an edge termination structure is provided in the region on the negative side in the Y-axis direction of semiconductor device 100 in this example. The edge termination structure relieves electric field concentration on the upper surface side of semiconductor substrate 10. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, this example describes the edge on the negative side in the Y-axis direction, but the same applies to other edges of semiconductor device 100.

[0036] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0037] The semiconductor device 100 of this example includes, on the front surface of the semiconductor substrate 10, a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface of the semiconductor substrate 10.

[0038] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The gate metal layer 50 is provided above the gate trench portion 40 and the well region 17.

[0039] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. For example, at least a portion of the emitter electrode 52 is formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium, a titanium compound, or the like below the region formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0040] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in Fig. 1A. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0041] The contact hole 55 connects the gate metal layer 50 and the gate conductive portion in the gate trench portion 40 of the transistor section 70. Inside the contact hole 55, a plug made of tungsten or the like may be formed.

[0042] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug made of tungsten or the like may be formed.

[0043] The connection portion 25 electrically connects a front surface electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material, such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface of the semiconductor substrate 10 via an insulating film, such as an oxide film.

[0044] The gate trench portions 40 are arranged at predetermined intervals along a predetermined trench arrangement direction (the X-axis direction in this example). As an example, the gate trench portions 40 are arranged at trench intervals of 1.5 μm, but the trench interval is not limited to this interval. The gate trench portion 40 in this example may have two extension portions 41 extending along a trench extension direction (the Y-axis direction in this example) that is parallel to the front surface of the semiconductor substrate 10 and perpendicular to the trench arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0045] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 in the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0046] The dummy trenches 30 in this example are trenches electrically connected to the emitter electrode 52 and set to the emitter potential. Like the gate trenches 40, the dummy trenches 30 are arranged at predetermined intervals along a predetermined trench arrangement direction (the X-axis direction in this example). As an example, the dummy trenches 30 are arranged at intervals of 1.5 μm, but the interval is not limited to this. In particular, the intervals between the dummy trenches 30 may be different from the intervals between the gate trenches 40. Like the gate trenches 40, the dummy trenches 30 in this example have a U-shape on the front surface of the semiconductor substrate 10. That is, the dummy trenches 30 may have two extension portions 31 extending along the trench extension direction and a connection portion 33 connecting the two extension portions 31. The dummy trenches 30 may be at a floating potential. The dummy trench portion 30 is an example of a first trench portion adjacent to the gate trench portion 40.

[0047] The transistor section 70 of this example has a structure in which two gate trench sections 40 each having a connection portion 43 and two dummy trench sections 30 each having no connection portion are repeatedly arranged. That is, the arrangement ratio of the gate trench sections 40 to the dummy trench sections 30 may be set to a predetermined desired arrangement ratio. In the transistor section 70 of this example, the ratio of the number of gate trench sections 40 to the number of dummy trench sections 30 is 1:1. The transistor section 70 of this example has a dummy trench section 30 between two extension sections 41 connected by the connection portion 43. Note that the number of gate trench sections 40 may be the number of extension sections 41. The number of dummy trench sections 30 may be the number of extension sections 31.

[0048] However, the ratio of the gate trenches 40 to the dummy trenches 30 is not limited to this example. The ratio of the gate trenches 40 to the dummy trenches 30 may be 2:3 or 2:4. Increasing the number of dummy trenches 30 relative to the gate trenches 40 reduces electric field concentration in the mesa portion 71, thereby increasing the voltage and current tolerance of the semiconductor device 100. Adjusting the ratio of the gate trenches 40 to the dummy trenches 30 also adjusts the gate capacitance for driving the semiconductor device 100. Increasing the number of dummy trenches 30 relative to the gate trenches 40 increases the gate capacitance and reduces the saturation current. Alternatively, the transistor portion 70 may have no dummy trenches 30 and be entirely made up of gate trenches 40, resulting in a so-called full-gate structure. The ratio of the gate trenches 40 to the dummy trenches 30 disclosed in this specification may be interpreted as the ratio of the gate trenches 40 to the dummy trenches. The dummy trench includes a trench in which no channel is formed on the sidewall, such as the dummy trench portion 30 or a dummy gate trench portion 130 described later.

[0049] The well region 17 is a second conductivity type region provided closer to the front surface of the semiconductor substrate 10 than the drift region 18, which will be described later. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. The well region 17 is, for example, P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the trench extension direction may be covered by the well region 17.

[0050] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The emitter region 12 and the contact region 15 are exposed in the contact holes 54. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the trench extension direction.

[0051] The mesa portion 71 and the mesa portion 81 are mesa portions provided adjacent to the trench portion in a plane parallel to the front surface of the semiconductor substrate 10. A mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface of the semiconductor substrate 10 to the deepest bottom of each trench portion. An extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0052] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface of the semiconductor substrate 10.

[0053] On the other hand, the mesa portion 81 is provided adjacent to the dummy trench portion 30 in the diode portion 80. The trench portion in the mesa portion 81 may be electrically connected to the emitter electrode 52 through the contact hole 56 and set to the emitter potential. In other words, the trench portion provided in the diode portion 80 may be the dummy trench portion 30.

[0054] The mesa portion 81 has a well region 17 and a base region 14 on the front surface of the semiconductor substrate 10. An emitter electrode 52 is also disposed on the upper surface of the mesa portion 81. That is, the metal layer of the emitter electrode 52 may function as an anode electrode in the diode portion 80.

[0055] The base region 14 is a second conductivity type region provided on the front surface side of the semiconductor substrate 10 in the transistor portion 70. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 in the Y-axis direction. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

[0056] The emitter region 12 is a region of a first conductivity type having a doping concentration higher than that of the drift region 18 described later with reference to FIG. 1B. In this example, the emitter region 12 is, for example, an N+ type. For example, the dopant of the emitter region 12 is phosphorus (P) or arsenic (As). The emitter region 12 is provided on the front surface of the mesa portion 71 in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one to the other of the two trench portions sandwiching the mesa portion 71. The emitter region 12 is also provided below the contact hole 54.

[0057] The emitter region 12 may extend to the dummy trench portion 30 and be in contact with the dummy trench portion 30. However, the emitter region 12 may terminate without reaching the dummy trench portion 30 and not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is not in contact with the dummy trench portion 30.

[0058] The contact region 15 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the contact region 15 is of P+ type, for example. An example of a dopant for the contact region 15 is boron (B). In this example, the contact region 15 is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one to the other of the two trench portions sandwiching the mesa portion 71. However, the contact region 15 may be spaced apart from the gate trench portion 40 below the emitter region 12 in the portion where the emitter region 12 contacts the gate trench portion 40.

[0059] The contact region 15 may or may not be in contact with the gate trench portion 40. Furthermore, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54. The contact region 15 may also be provided in the mesa portion 81.

[0060] 1B is an example of an a-a' cross-sectional view in FIG. 1A. The a-a' cross-section is an XZ plane that extends from the transistor section 70 to the diode section 80 and passes through the emitter region 12 in the transistor section 70. In the a-a' cross-section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0061] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0062] The buffer region 20 is a region of a first conductivity type provided below the drift region 18. In this example, the buffer region 20 is, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0063] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal.

[0064] The base region 14 is a second conductivity type region provided above the drift region 18 in the mesa portion 71 and the mesa portion 81. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0065] The emitter region 12 is provided in the mesa portion 71 between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0066] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, and the contact region 15 is provided, each trench also penetrates these regions to reach the drift region 18. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed after the doped regions are formed. The trenches penetrating the doped regions also include trenches formed after the trenches are formed.

[0067] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38. The potential of the gate electrode of an IGBT or the like is applied to the gate conductive portion 44.

[0068] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0069] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38. The potential of the emitter electrode of an IGBT or the like is applied to the dummy conductive portion 34. The dummy conductive portion 34 may be at a floating potential.

[0070] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided so as to penetrate the interlayer insulating film 38.

[0071] The lower end 13 is the lower end of the emitter region 12 on the dummy trench portion 30 side of the mesa portion 71. When the emitter region 12 reaches the dummy trench portion 30, the lower end 13 contacts the dummy trench portion 30.

[0072] At least a portion of the contact region 15 is provided below the lower end 13 of the mesa portion 71. That is, the contact region 15 is provided deeper than the emitter region 12 and is provided so as to partially overlap the emitter region 12. In this example, the contact region 15 is provided extending from the dummy trench portion 30 to below the lower end 13 of the emitter region 12 in the trench arrangement direction. This makes it difficult for holes below the emitter region 12 to be directly extracted through the emitter region 12, and makes it easier for hole current to be extracted from the contact region 15. This makes it difficult for an NPNP-type parasitic thyristor from the emitter region 12 to the collector region 22 to be turned on, thereby suppressing latch-up of the semiconductor device 100.

[0073] In the cross section of this example, the contact region 15 is separated from the gate trench portion 40 in the mesa portion 71. This prevents the contact region 15 from interfering with the formation of an inversion layer on the side surface of the gate trench portion 40, allowing the semiconductor device 100 to operate stably.

[0074] The contact region 15 in this example is provided across both sides of the dummy trench portion 30 in the X-axis direction. In the manufacturing process for the contact region 15 in this example, a resist is provided on the semiconductor substrate 10, and the contact region 15 across the region where the trench portion is provided can be provided by ion implantation. The dummy trench portion 30 can be provided by etching the semiconductor substrate 10 after the contact region 15 is provided.

[0075] In recent years, efforts have been made to reduce the spacing between mesa portions 71, or to reduce the process pitch, in order to achieve miniaturization of semiconductor devices 100. For example, when a diffusion region is formed in a silicon semiconductor substrate 10 by ion implantation, the dopant tends to diffuse within a certain range. The structure of the contact region 15 in this example facilitates the fabrication of a contact region 15 that extends below the lower end 13 of the emitter region 12 and is separated from the gate trench portion 40, even when the process pitch is reduced. This allows for the provision of a semiconductor device 100 with high latch-up resistance without significantly affecting electrical characteristics. However, the latch-up suppression effect can be achieved as long as the contact region 15 is provided so as to be connected in the trench extension direction, and the contact region 15 is not limited to a configuration in which the contact region 15 contacts the dummy trench portion 30.

[0076] In the diode section 80, a buffer region 20 is stacked above a cathode region 82, and a drift region 18 is stacked above the buffer region 20. In the mesa section 81, a base region 14 is stacked above the drift region 18, and a PN junction is formed between the base region 14 and the drift region 18. The base region 14 is electrically connected to the emitter electrode 52 via a contact hole 54.

[0077] 1C is an example of a cross-sectional view taken along the line b-b' in FIG. 1A. The cross-section b-b' is an XZ plane that does not pass through the emitter region 12 in the transistor section 70. In this example, the mesa section 71 in the transistor section 70 has a base region 14 and a contact region 15 above the drift region 18. In the diode section 80, the mesa section 81 has a structure similar to that in the example in FIG. 1B.

[0078] The contact region 15 extends from the gate trench portion 40 to the dummy trench portion 30. A contact hole 54 is provided above the contact region 15. Holes are extracted from the contact region 15 through the contact hole 54.

[0079] When the contact region 15 provided below the emitter region 12 and the contact region 15 in the cross section of this example are provided by the same process, the contact regions 15 are provided to the same depth. In this case, the contact region 15 is deeper than the emitter region 12. However, the contact region 15 below the emitter region 12 may be provided at a different depth from that in other regions.

[0080] 2 shows an example of an enlarged cross-sectional view of the mesa portion 71. In this example, the XZ plane passing through the emitter region 12 in the transistor portion 70 is shown.

[0081] The emitter regions 12 extend from the gate trench portions 40, across the contact holes 54, to the dummy trench portions 30 in the trench arrangement direction. This facilitates current conduction from the emitter regions 12 through the contact holes 54, improving the electrical characteristics of the semiconductor device 100. In this example, the emitter regions 12 extend from the gate trench portions 40 to the dummy trench portions 30 in the trench arrangement direction, and terminate without reaching the dummy trench portions 30. However, the emitter regions 12 may also be provided extending from the gate trench portions 40 to the dummy trench portions 30 in the trench arrangement direction.

[0082] The contact region 15 is provided on the front surface 21 of the semiconductor substrate 10 on the sidewall of the dummy trench portion 30. The contact region 15 includes a surface region 92 and a lower region 94.

[0083] The surface region 92 is a region in the semiconductor substrate 10 that has the same depth as the emitter region 12. As an example, the depth of the surface region 92 is 0.5 μm. However, the depth of the surface region 92 may be different. When the emitter region 12 extends from the gate trench portion 40 to the dummy trench portion 30 and reaches the dummy trench portion 30, the surface region 92 is not provided in the cross section where the emitter region 12 is exposed on the front surface 21 of the semiconductor substrate 10. The impurity concentration of the surface region 92 may be in the range of 5E19 / cm3 or more and 2E20 / cm3 or less.

[0084] The lower region 94 is provided in a region of the semiconductor substrate 10 that is deeper than the emitter region 12. The lower region 94 extends toward the gate trench portion 40, beyond a lower end 13 on the gate trench portion 40 side of the emitter region 12 that extends from the gate trench portion 40 to the dummy trench portion 30. The impurity concentration of the lower region 94 may be in the range of 1E19 / cm3 or more and 1E20 / cm3 or less.

[0085] The width Wc is the width of the contact region 15 in the trench arrangement direction. The width Wc is the width measured from the center of the dummy trench portion 30 to the lower end of the emitter region 12 on the dummy trench portion 30 side. In other words, the width Wc corresponds to the maximum reach position of the lower region 94 on the gate trench portion 40 side, measured from the center of the dummy trench portion 30. The width Wc may be 1.2 μm or less, or 1.1 μm or less. Here, the width of the surface region 92 in the trench arrangement direction may be in the range of 15% to 40% of the distance between adjacent trenches. The width of the lower region 94 in the trench arrangement direction may be in the range of 30% to 70% of the distance between adjacent trenches. Furthermore, the width of the portion where the lower region 94 overlaps with the emitter region 12 in the trench arrangement direction may be in the range of 0% to 30% of the distance between adjacent trenches, and more preferably in the range of 10% to 20%.

[0086] The thickness Dc is the thickness of the contact region 15 in the depth direction of the semiconductor substrate 10. The thickness Dc is greater than the depth of the lower end 13 of the emitter region 12 and less than the depth of the base region 14. For example, the thickness Dc is 0.5 μm or more and 2.0 μm or less. The thickness of the surface region 92 may be in the range of 0.3 μm or more and 0.8 μm or less. The thickness of the lower region 94 may be in the range of 0.3 μm or more and 1.1 μm or less.

[0087] The width Ws is the distance between the contact region 15 and the gate trench portion 40 in the trench arrangement direction. The width Ws may be set so that a channel can be formed at the end of the gate trench portion 40. In other words, the width Ws corresponds to the separation distance between the contact region 15 and the gate trench portion 40. In one example, the width Ws is 0.6 μm or more. Furthermore, the width Ws in the trench arrangement direction may be in the range of 30% to 70% of the distance between adjacent trenches.

[0088] 3 shows an example of a top view of the semiconductor device 100 having the unopened contact hole 54. FIG. 3 is an example of an enlarged view of the top surface of the semiconductor device 100.

[0089] The non-connection region 59 is a region where the emitter electrode 52 is not electrically connected to the contact region 15 on the front surface 21. For example, the non-connection region 59 is an unopened region where the contact hole 54 is not formed in the interlayer insulating film 38 due to an oxide film etching defect caused by particles or foreign matter, etc. Alternatively, the non-connection region 59 may be a region where the contact region 15 on the front surface 21 is not formed due to a resist residue, etc.

[0090] In this example, the hole current that would have been extracted in the non-connection region 59 flows through the contact region 15 and is extracted via the contact hole 54 above another nearby contact region 15. That is, the hole current does not flow through the base region 14 below the emitter region 12, but flows through the contact region 15, which has lower resistance to holes than the base region 14, thereby suppressing latch-up. This suppresses switching breakdown caused by process defects. Therefore, a semiconductor device 100 is provided that has a redundant element structure that is resistant to process defects.

[0091] FIG. 4A shows an example of a simulation result of the static characteristics of the semiconductor device 100. This example shows the change in the static characteristics with respect to the width Wc of the contact region 15. This example shows an example in which the width of the mesa portion 71 between the dummy trench portion 30 and the gate trench portion 40 is 1.5 μm. Note that, in order to show the qualitative nature of the simulation results, the numerical values ​​on the vertical axis in this example are scaled to normalized values ​​with an initial value of 1, which corresponds to the width Wc of the contact region=0. The units of each normalized value may be appropriate units having dimensions according to the respective physical quantities.

[0092] The graph shows the relationship between the width Wc and the collector-emitter saturation voltage Vce when the semiconductor device 100 is operating, the relationship between the collector-emitter saturation current when the semiconductor device 100 is operating, and the relationship between the threshold voltage Vth of the semiconductor device 100. When the width Wc is 1.2 μm or less, the contact region 15 has little effect on the channel formation in the base region 14. Therefore, when the width Wc is in this range, the effect on all of these static characteristic values ​​can be kept small.

[0093] 4B shows an example of a simulation result of the on-characteristics of the semiconductor device 100. In this example, the change in the on-characteristics is shown relative to the width Wc of the contact region 15. Note that the numerical values ​​on the vertical axis in this example are scaled to normalized values.

[0094] The relationship between Wc and the maximum value dV / dt_max (Normalized) of the change in collector-emitter voltage Vce over time when the semiconductor device 100 is operating, the relationship between Wc and the maximum value di / dt_max (Normalized) of the change in collector-emitter current over time when the semiconductor device 100 is operating, and the on-loss Eon (Normalized) of the semiconductor device 100 are shown. When the width Wc is 1.2 μm or less, the contact region 15 has little effect on the channel formation in the base region 14. Therefore, when the width Wc is within this range, the effect on all of these on-characteristic values ​​can be kept small.

[0095] 4C shows an example of a simulation result of the off-characteristics of the semiconductor device 100. In this example, the change in the off-characteristics is shown relative to the width Wc of the contact region 15. Note that the numerical values ​​on the vertical axis in this example are scaled to normalized values.

[0096] The relationship between Wc and the maximum value dV / dt_max (Normalized) of the change in collector-emitter voltage Vce over time when the semiconductor device 100 is operating, the relationship between Wc and the maximum value di / dt_max (Normalized) of the change in collector-emitter current over time when the semiconductor device 100 is operating, and the off-state loss Eoff (Normalized) of the semiconductor device 100 are shown. When the width Wc is 1.2 μm or less, the contact region 15 has little effect on the channel formation in the base region 14. Therefore, when the width Wc is within this range, the effect on all of these off-state characteristic values ​​can be kept small.

[0097] As shown in the simulation results of Figures 4B and 4C, the semiconductor device 100 of this example does not affect the dynamic electrical characteristics due to the structure of the contact region 15. Therefore, as shown in the simulation results of Figures 4A to 4C, the semiconductor device 100 of this example does not significantly affect the electrical characteristics, both static and dynamic. The semiconductor device 100 of this example improves latch-up resistance without causing fluctuations in the electrical characteristics.

[0098] 5A shows an example of a top view of the semiconductor device 100. This example differs from FIG. 1A in that the emitter region 12 is provided in contact with the dummy trench portion 30. This example will be described in particular with respect to the differences from FIG. 1A.

[0099] In this example, the emitter regions 12 extend in the trench arrangement direction from the gate trench portions 40 to the dummy trench portions 30. The emitter regions 12 and the contact regions 15 are provided on the front surface 21 of the semiconductor substrate 10 so as to alternately contact the gate trench portions 40 and the dummy trench portions 30 in the trench extension direction.

[0100] 5B is an example of a c-c' cross section in FIG. 5A. The c-c' cross section is an XZ plane that extends from the transistor section 70 to the diode section 80 and passes through the emitter region 12 in the transistor section 70. Note that the XZ cross section that extends from the transistor section 70 to the diode section 80 and passes through the contact region 15 in the transistor section 70 is the same as FIG. 1C.

[0101] In this example, the surface region 92 of the contact region 15 is not provided in the c-c' cross section. The contact region 15 of this example has a structure in the lower region 94 similar to that of the example in FIG. 1B. That is, at least a portion of the contact region 15 is provided below the lower end 13 of the mesa portion 71. This makes it difficult for holes below the emitter region 12 to be directly extracted through the emitter region 12, and hole current can be extracted from the contact region 15 to suppress latch-up.

[0102] 6A shows an example of a top view of the semiconductor device 100. In this example, the ratio of the number of gate trench portions 40 to the number of dummy trench portions 30 is 1:2. In the semiconductor device 100 of this example, by increasing the ratio of the dummy trench portions 30, it is possible to improve the defect tolerance.

[0103] In this example, a U-shaped gate trench 40 and two I-shaped dummy trenches 30 are arranged in the transistor section 70 on the front surface of the semiconductor substrate 10. However, as long as the arrangement ratio of the gate trenches 40 and the dummy trenches 30 can be maintained at 1:2, the structures of the gate trenches 40 and the dummy trenches 30 are not limited to this. As an example, the dummy trench 30 may have a U-shaped structure, and the region inside the dummy trench may be a floating region.

[0104] Fig. 6B is an example of a dd' cross section in Fig. 6A. The dd' cross section is an XZ plane that extends from the transistor section 70 to the diode section 80 and passes through the emitter region 12 in the transistor section 70. In the dd' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38. The semiconductor device 100 of this example also has an accumulation region 16 between the drift region 18 and the base region 14.

[0105] The accumulation region 16 is a region of a first conductivity type provided between the base region 14 and the drift region 18. In this example, the accumulation region 16 is, for example, an N+ type. The accumulation region 16 is provided in the transistor section 70 and the diode section 80. This allows the semiconductor device 100 to avoid mask misalignment of the accumulation region 16.

[0106] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose of ion implantation into the accumulation region 16 is 1E12 cm -2 Above, 1E13cm -2 The ion implantation dose of the accumulation region 16 may be 3E12 cm -2 Above, 6E12cm -2 By providing the accumulation region 16, the carrier injection enhancement effect can be increased, and the on-voltage of the transistor section 70 can be reduced. Note that E represents a power of 10, and for example, 1E12 cm -2 is 1 x 10 12 cm -2 means.

[0107] In this example, the contact regions 15 also electrically connect adjacent contact regions 15 below the emitter regions 12. The semiconductor device 100 can suppress latch-up by the structure of the contact regions 15, regardless of the presence or absence of the accumulation region 16 and the arrangement ratio of the gate trench portions 40 and the dummy trench portions 30.

[0108] 7A shows an example of a top view of a semiconductor device 100 according to a modified example. In this example, differences from FIG. 1A will be particularly described. The semiconductor device 100 of this example includes a dummy gate trench 130 that does not contact the emitter region 12, instead of the dummy trench 30. The dummy gate trench 130 is an example of a first trench adjacent to the gate trench 40.

[0109] The dummy gate trench portion 130 is a trench portion that is set to the gate potential and does not contact the emitter region 12. In other words, the dummy gate trench portion 130 is a trench portion that is set to the gate potential but does not drive a transistor in the adjacent mesa portion 71, and is an example of a dummy trench portion different from the dummy trench portion 30. In order to set the dummy gate trench portion 130 to the gate potential, the dummy gate trench portion 130 extends in the Y-axis direction to the region where the gate metal layer 50 is provided. The dummy gate trench portion 130 is connected to the gate metal layer 50 via a contact hole 58 and is set to the gate potential.

[0110] Although the dummy gate trench 130 is set to the gate potential, it is not in contact with the emitter region 12, and therefore a channel due to an inversion layer of the first conductivity type is not formed on the sidewall of the dummy gate trench 130. The dummy gate trench 130 facilitates the attraction of carriers to the mesa portion 71, and therefore has different properties, such as gate capacitance, from the dummy gate trench 130. Therefore, by using the dummy gate trench 130 and the dummy trench 30 in combination, it is possible to adjust the threshold voltage, saturation current, electric field concentration, gate capacitance, and other properties of the semiconductor device 100.

[0111] On the front surface of the semiconductor substrate 10, the gate trench portion 40 in this example has a U-shaped structure, and the dummy gate trench portion 130 has an I-shaped structure. However, the structures of the gate trench portion 40 and the dummy gate trench portion 130 are not limited to these structures as long as the desired arrangement ratio can be achieved.

[0112] In this example, the dummy gate trench portion 130 in the diode portion 80 has the same structure as that shown in Fig. 1A. That is, the dummy gate trench portion 130 is connected to the emitter electrode 52 via the contact hole 56 and is set to the emitter potential.

[0113] 7B is an example of the e-e' cross section in FIG. 7A. The e-e' cross section is an XZ plane that extends from the transistor section 70 to the diode section 80 and passes through the emitter region 12 in the transistor section 70. The dummy gate trench section 130 has a second gate insulating film 132 and a second gate conductive section 134.

[0114] 1B, except that the dummy gate trench portion 130 of the semiconductor device 100 has an emitter potential. That is, in this example, the contact regions 15 also electrically connect adjacent contact regions 15 below the emitter region 12. Therefore, the semiconductor device 100 can suppress latch-up due to the structure of the contact regions 15, regardless of the potential of the dummy gate trench portion.

[0115] 8A shows an example of a top view of the semiconductor device 100. The semiconductor device 100 of this example includes a contact trench portion 60.

[0116] The contact trench portion 60 is provided extending from the front surface 21 in the depth direction of the semiconductor substrate 10. The contact trench portion 60 electrically connects the emitter electrode 52 and the semiconductor substrate 10. The contact trench portion 60 is provided extending in the trench extension direction. In this example, the contact trench portion 60 is arranged in a stripe pattern along the gate trench portion 40 and the dummy trench portion 30.

[0117] The contact trench portion 60 is formed above the emitter region 12 and the contact region 15 in the transistor portion 70. The contact trench portion 60 is formed above the base region 14 in the diode portion 80. The contact trench portion 60 is not provided above the well regions 17 provided at both ends in the Y-axis direction. One or more contact trench portions 60 may be provided extending in the trench extension direction.

[0118] In the mesa portion 71 between the gate trench portion 40 and the contact trench portion 60, the emitter regions 12 and the contact regions 15 may be alternately arranged in the trench extension direction. The width of the emitter regions 12 in the trench extension direction may be larger than the width of the contact regions 15. The width of the emitter regions 12 in the trench extension direction may be 0.6 μm or more and 1.6 μm or less. By appropriately controlling the ratio of the emitter regions 12 to the contact regions 15, latch-up can be easily suppressed.

[0119] 8B is an example of a cross-sectional view taken along line ff' in FIG. 8A. The contact trench portion 60 of this example is formed shallower than the emitter region 12.

[0120] The contact trench portion 60 extends toward the back surface 23 of the semiconductor substrate 10 beyond the front surface 21. In this example, the lower end of the contact trench portion 60 is shallower than the lower end of the emitter region 12. The emitter region 12 is provided on both ends of the contact trench portion 60 in the trench arrangement direction. The contact trench portion 60 has a plug 62 and a barrier metal layer 64.

[0121] The plug 62 is a conductive material provided inside the contact trench portion 60. The plug 62 may be made of the same material as the emitter electrode 52 or a different material. The plug 62 may include a material such as tungsten.

[0122] A barrier metal layer 64 is provided below the plug 62. In this example, the barrier metal layer 64 is provided between the plug 62 and the emitter region 12. The barrier metal layer 64 may include a material such as titanium nitride.

[0123] The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is provided extending closer to the dummy trench portion 30 than the contact trench portion 60 in the trench arrangement direction. In other words, the lower end 13 is provided between the dummy trench portion 30 and the contact trench portion 60 in the trench arrangement direction.

[0124] At least a portion of the contact region 15 is provided below the lower end 13 of the mesa portion 71. The contact region 15 of this example is provided extending from the dummy trench portion 30 to below the lower end 13 of the emitter region 12 in the trench arrangement direction. The contact region 15 may or may not extend beyond the contact trench portion 60 in the trench arrangement direction from the dummy trench portion 30. The contact region 15 of this example is provided between the dummy trench portion 30 and the contact trench portion 60 in the trench arrangement direction.

[0125] The trench bottom region 19 is a second conductivity type region provided below the dummy trench portion 30 and the gate trench portion 40. In this example, the trench bottom region 19 covers the lower ends of the dummy trench portion 30 and the gate trench portion 40. The doping concentration of the trench bottom region 19 may be lower than that of the base region 14. The trench bottom region 19 is provided between the drift region 18a and the drift region 18b. The provision of the trench bottom region 19 improves the avalanche resistance. Note that although an embodiment in which the semiconductor device 100 includes the trench bottom region 19 will be described, the trench bottom region 19 may be omitted.

[0126] Drift region 18a is provided between base region 14 and trench bottom region 19 in mesa portion 71 and mesa portion 81. Drift region 18b is provided below trench bottom region 19. The doping concentrations of drift region 18a and drift region 18b may be the same.

[0127] 9A shows an example of a top view of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 8A in the arrangement of the emitter region 12 and the contact region 15 on the front surface 21. In this example, differences from the embodiment of FIG. 8A will be particularly described. This example differs from the embodiment of FIG. 8A in that the emitter region 12 is provided on one side of the contact trench portion 60.

[0128] The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 is provided extending from the gate trench portion 40 to the sidewall of the contact trench portion 60 in the trench arrangement direction. The emitter region 12 does not have to be provided between the dummy trench portion 30 and the contact trench portion 60.

[0129] Fig. 9B is an example of a cross-sectional view taken along line g-g' in Fig. 9A. The contact trench portion 60 of this example is formed deeper than the embodiment of Fig. 8B.

[0130] The contact trench portion 60 is provided so as to extend closer to the back surface 23 of the semiconductor substrate 10 than the emitter region 12. That is, the lower end of the contact trench portion 60 in this example is deeper than the lower end of the emitter region 12. The lower end of the contact trench portion 60 in this example is shallower than the lower end of the contact region 15.

[0131] The emitter region 12 is provided to extend in the trench arrangement direction from the gate trench portion 40 to the sidewall of the contact trench portion 60. Therefore, the lower end 13 is located on the sidewall of the contact trench portion 60 between the gate trench portion 40 and the contact trench portion 60 in the trench arrangement direction.

[0132] Fig. 10A shows an example of a top view of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of Fig. 8A in that it does not include the diode section 80.

[0133] Fig. 10B is an example of a cross-sectional view taken along the line hh' in Fig. 10A. The contact trench portion 60 of this example is formed deeper than the embodiment of Fig. 8B.

[0134] The contact trench portion 60 is provided so as to extend closer to the back surface 23 of the semiconductor substrate 10 than the emitter region 12. In this example, the lower end of the contact trench portion 60 is deeper than the lower end of the emitter region 12 and shallower than the lower end of the contact region 15. The emitter region 12 is provided on both ends of the contact trench portion 60 in the trench arrangement direction.

[0135] The emitter region 12 is provided to extend toward the dummy trench portion 30 side in the trench arrangement direction relative to the contact trench portion 60. That is, the lower end 13 is provided between the dummy trench portion 30 and the contact trench portion 60 in the trench arrangement direction.

[0136] 10C is another example of the cross-sectional view taken along line h-h' in FIG. 10A. In this example, the depth of the contact trench portion 60 differs from that of the embodiment in FIG. 10B. The contact trench portion 60 in this example is formed shallower than the emitter region 12. That is, the lower end of the contact trench portion 60 in this example is shallower than the lower end of the emitter region 12.

[0137] As described above, the depth of the contact trench portion 60 is not limited to the embodiments and may be changed as appropriate. Furthermore, the emitter region 12 may be provided on both ends of the contact trench portion 60 in the trench arrangement direction, or on one side. Furthermore, in each embodiment, the semiconductor device 100 may or may not include a trench bottom region 19.

[0138] 11A shows an example of a top view of the semiconductor device 100. The semiconductor device 100 of this example includes a dummy trench 30 provided adjacent to the gate trench 40, and a dummy gate trench 130 provided adjacent to the gate trench 40.

[0139] The dummy gate trench portion 130 is set to the gate potential and is a trench portion that is not in contact with the emitter region 12. In this example, the dummy gate trench portion 130 is connected to the extension portion 41 by a connection portion 43.

[0140] The emitter region 12 is provided in the mesa portion 71 between the gate trench portion 40 and the dummy gate trench portion 130 so as to be in contact with the gate trench portion 40 and spaced apart from the dummy gate trench portion 130 .

[0141] The emitter region 12 is provided in a mesa portion 71 between the gate trench portion 40 and the dummy trench portion 30 so as to be in contact with the gate trench portion 40 and spaced apart from the dummy trench portion 30 .

[0142] FIG. 11B is an example of a cross-sectional view taken along line i-i' in FIG. 11A. The semiconductor device 100 of this example includes contact trench portions 60 that are shallower than the emitter regions 12, and emitter regions 12 provided at both ends of the contact trench portions 60 in the trench arrangement direction, but is not limited to this. The dummy gate trench portions 130 are dummy trenches, just like the dummy trench portions 30. Therefore, a portion of the dummy gate trench portions 130 may be replaced with dummy trench portions 30 at the emitter potential. This allows the gate capacitance to be adjusted, thereby achieving optimal switching speed.

[0143] The contact region 15 is provided in the mesa portion 71 between the gate trench portion 40 and the dummy gate trench portion 130, below the lower end 13 of the emitter region 12 on the dummy gate trench portion 130 side. The contact region 15 is also provided in the mesa portion 71 between the gate trench portion 40 and the dummy trench portion 30, below the lower end 13 of the emitter region 12 on the dummy trench portion 30 side.

[0144] 12A shows an example of a top view of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 11A in that the first trench portion adjacent to the gate trench portion 40 is the gate trench portion 40 and has a staggered structure. The semiconductor device 100 has a plurality of adjacent gate trench portions 40. The adjacent gate trench portions 40 may be connected to each other by a connection portion 43.

[0145] Adjacent gate trenches 40 are in contact with the emitter regions 12 at different positions in the trench extension direction. That is, the semiconductor device 100 has a staggered structure with the emitter regions 12 arranged alternately. In this case, each of adjacent gate trenches 40 has both a portion that will become a gate trench and a portion that will become a first trench. That is, the mesa portion between adjacent gate trenches 40 has an emitter region 12 (first emitter region) that is in contact with one gate trench 40 and spaced apart from the other gate trench 40, and an emitter region 12 (second emitter region) that is spaced apart from one gate trench 40 and in contact with the other gate trench 40. The contact region 15 is provided in a region including below the lower end 13 of the first emitter region on the other side of the gate trench portion 40 and below the lower end 13 of the second emitter region on one side of the gate trench portion 40. In the trench extension direction of the gate trench portion 40, the first emitter regions and the second emitter regions are provided alternately with the contact region 15 sandwiched therebetween.

[0146] 12B is an example of a cross-sectional view taken along the line j-j' in FIG. 12A. The semiconductor device 100 of this example includes a contact trench portion 60 shallower than the emitter region 12 and emitter regions 12 provided on both ends of the contact trench portion 60 in the trench arrangement direction, but is not limited to this. That is, the semiconductor device 100 may include a contact trench portion 60 deeper than the emitter region 12, or may include an emitter region 12 provided on one side of the contact trench portion 60. The semiconductor device 100 may or may not include a trench bottom region 19.

[0147] FIG. 13A shows an example of a top view of a semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 12A in that it does not include a dummy trench portion 30 and only includes a gate trench portion 40. Similar to the embodiment of FIG. 12A, the semiconductor device 100 of this example has a staggered structure in which the emitter regions 12 are arranged in a staggered pattern. The semiconductor device 100 of this example has a larger proportion of the emitter regions 12 on the front surface 21 than the embodiment of FIG. 12A. Even when the proportion of the emitter regions 12 on the front surface 21 is increased, the semiconductor device 100 of this example can suppress latch-up because a portion of the emitter regions 12 is separated from the gate trench portion 40.

[0148] 13B is an example of a k-k' cross-sectional view in FIG. 13A. The semiconductor device 100 of this example includes contact trench portions 60 shallower than the emitter regions 12, and emitter regions 12 provided at both ends of the contact trench portions 60 in the trench arrangement direction, but is not limited to this. The emitter regions 12 of this example are provided at both ends of the gate trench portion 40 in the trench arrangement direction. In this case, by collectively patterning the emitter regions 12 adjacent to each other across the gate trench portion 40, process reliability can be maintained even when the mesa width is reduced.

[0149] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. For example, although the present invention has been described using an RC-IGBT as an example, it is also applicable to IGBTs and MOSFETs.

[0150] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0151] 10 semiconductor substrate, 12 emitter region, 13 bottom end, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 19 trench bottom region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 25 connection portion, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 33 connection portion, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 41 extension portion, 42 gate insulating film, 43 connection portion, 44 gate conductive portion, 50 gate metal layer, 52 emitter electrode, 54 contact hole, 55 contact hole, 56 contact hole, 58 contact hole, 59 non-connection region, 60 contact trench portion, 62 plug, 64 barrier metal layer, 70 transistor portion, 71 mesa portion, 80 diode portion, 81 mesa portion, 82 cathode region, 92 surface region, 94 lower region, 100 semiconductor device, 130 dummy gate trench portion, 132 second gate insulating film, 134 second gate conductive portion

Claims

[Claim 1] A semiconductor device including a first trench portion and a second trench portion, a first conductivity type drift region provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a front surface electrode provided on a front surface side of the semiconductor substrate and made of a conductive material or a metal material; a first high concentration region of a first conductivity type that is in contact with the front surface side electrode and the second trench portion and has a doping concentration higher than that of the drift region; a second high concentration region of a second conductivity type that is in contact with the front surface side electrode and the first trench portion and has a doping concentration higher than that of the base region; a mesa portion provided between the first trench portion and the second trench portion; Equipped with the second high concentration region has an extension portion that extends from below a lower end of the first high concentration region on the first trench portion side toward the second trench portion side in a cross section parallel to a trench arrangement direction, the first trench portion includes any one of a dummy trench portion, a dummy gate trench portion, and a gate trench portion, and the second trench portion is a gate trench portion; the second high concentration region is exposed on the front surface of the semiconductor substrate between the first high concentration region and the first trench portion in a cross section that passes through the first high concentration region and is parallel to the trench arrangement direction; the second high concentration region includes a surface region having the same depth as the first high concentration region and a lower region deeper than the first high concentration region; the lower region has the extension portion, The lower region extends from the first trench portion in the trench arrangement direction and terminates just below a contact hole provided above the front surface of the semiconductor substrate. Semiconductor device.

Images