Semiconductor device

Abstract

To provide a semiconductor device in which the separation of a protection film with respect to a re-wire can be suppressed.SOLUTION: A semiconductor device A10 includes a main body 11 including a semiconductor layer 112, an electrode 12 existing on one side of the main body 11 in a thickness direction z of the main body 11 and electrically connected to the semiconductor layer 112, a re-wire 20 existing on the opposite side of the main body 11 based on the electrode 12 in the thickness direction z and electrically connected to the electrode 12, a first protection film 3 existing on the same side as the re-wire 20 based on the electrode 12 in the thickness direction z and overlapping the re-wire 20 when viewed in the thickness direction z, and a second protection film 4 existing between the main body 11 and the first protection film 3 in the thickness direction z. The re-wire 20 includes an opposite surface 201 facing the first protection film 3 in the thickness direction z. The opposite surface 201 includes at least one depressed part 203 that is recessed in the thickness direction z. The first protection film 3 enters at least one depressed part 203.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses an example of a WL-CSP (wafer-level chip-size package) type semiconductor device. The semiconductor device described in Patent Document 1 includes a semiconductor chip, a passivation film (surface protection film) covering the surface of the semiconductor chip (the surface on which functional elements are formed), a stress relaxation layer laminated on the passivation film, rewiring formed on the stress relaxation layer, an encapsulating resin layer laminated on the rewiring, and metal balls arranged on the encapsulating resin layer. The encapsulating resin layer is a protective film that covers the rewiring and is located on the surface of the semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-91453

[0004] [overview] In conventional semiconductor devices, moisture (humidity) in the air can penetrate the surface protective film and oxidize the rewiring. This oxidation of the rewiring can form an oxide film on the surface of the rewiring, which can reduce the adhesion between the rewiring and the protective film. This can result in peeling of the protective film from the rewiring.

[0005] The present disclosure has been made in view of the above circumstances, and has an object to provide a semiconductor device capable of suppressing peeling of a protective film due to rewiring.

[0006] The semiconductor device provided by the present disclosure comprises a main body including a semiconductor layer, an electrode located on one side of the main body in the thickness direction of the main body and conductive to the semiconductor layer, a rewiring located on the opposite side of the main body with respect to the electrode in the thickness direction and conductive to the electrode, a first protective film located on the same side of the rewiring with respect to the electrode in the thickness direction and overlapping the rewiring when viewed in the thickness direction, and a second protective film located between the main body and the first protective film in the thickness direction, wherein the rewiring has an opposing surface facing the first protective film in the thickness direction, the opposing surface having at least one recess recessed in the thickness direction, and the first protective film extends into each of the at least one recess.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of FIG. 1 in which a number of terminals are omitted. [Figure 3] FIG. 3 is a plan view of FIG. 2 in which the first protective film is omitted. [Figure 4] FIG. 4 is a diagram showing a plurality of rewirings by imaginary lines in the plan view of FIG. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is an enlarged cross-sectional view of a main part of the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a partially enlarged view of a part of FIG. [Figure 8] FIG. 8 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] FIG. 13 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] FIG. 14 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] FIG. 15 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] FIG. 16 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] FIG. 17 is a cross-sectional view showing the semiconductor device according to the first embodiment in use, and corresponds to the cross section of FIG. [Figure 18] FIG. 18 is an enlarged cross-sectional view of a main part of a semiconductor device according to a modification of the first embodiment. [Figure 19] FIG. 19 is an enlarged cross-sectional view of a main part of a semiconductor device according to the second embodiment. [Figure 20] FIG. 20 is an enlarged cross-sectional view of a main part of a semiconductor device according to a first modification of the second embodiment. [Figure 21] FIG. 21 is an enlarged cross-sectional view of a main part of a semiconductor device according to a second modification of the second embodiment. [Figure 22] FIG. 22 is an enlarged cross-sectional view of a main part of a semiconductor device according to a third modification of the second embodiment. [Figure 23] FIG. 23 is an enlarged cross-sectional view of a main part of a semiconductor device according to a third embodiment. [Figure 24] FIG. 24 is an enlarged cross-sectional view of a main part of a semiconductor device according to a modification of the third embodiment. [Figure 25] FIG. 25 is an enlarged cross-sectional view of a main part showing another configuration example of a semiconductor device according to the present disclosure. [Figure 26] FIG. 26 is a plan view showing an example of the configuration of the recessed portion of the rewiring and the opening of the second protective film. [Figure 27] FIG. 27 is a plan view showing another example of the configuration of the recessed portion of the rewiring and the opening of the second protective film. [Figure 28] FIG. 28 is a plan view showing another example of the configuration of the recessed portion of the rewiring and the opening of the second protective film. [Figure 29] FIG. 29 is a plan view showing another example of the configuration of the recessed portion of the rewiring and the opening of the second protective film. [Figure 30] FIG. 30 is a plan view showing another example of the configuration of the recessed portion of the rewiring and the opening of the second protective film.

[0009] [Detailed explanation] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant explanations will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an object) B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an object) B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an object) B" includes "a certain object A is in contact with a certain object B and is located on (an object) B" and "a certain object A is located on (an object) B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, "object A overlaps object B when viewed from a certain direction" includes "object A overlaps the entirety of object B" and "object A overlaps part of object B." Furthermore, "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is primarily made of material C." Furthermore, unless otherwise specified, "a certain surface A faces in direction B (one side or the other)" does not necessarily mean that surface A is at a 90° angle with respect to direction B, but also includes the case where surface A is tilted relative to direction B. Furthermore, unless otherwise specified, "a certain surface A is perpendicular to surface B" does not necessarily mean that surface A is at a 90° angle with respect to surface B, but also includes the case where surface A is tilted relative to surface B.

[0011] First Embodiment 1 to 7 show a semiconductor device A10 according to a first embodiment. The semiconductor device A10 includes a semiconductor element 10, rewiring 20, a first protective film 3, a second protective film 4, and a plurality of terminals 5. For ease of understanding, FIG. 6 is an enlarged cross-sectional view of a main part of the semiconductor device A10, which is a schematic illustration and does not correspond to the cross section of FIG. 5.

[0012] For ease of explanation, reference will be made to the thickness direction z, the first direction x, and the second direction y, which are perpendicular to each other. The thickness direction z corresponds to the thickness direction of the semiconductor device A10. Furthermore, "plan view" refers to the view in the thickness direction z. The first direction x is perpendicular to the thickness direction z. The second direction y is perpendicular to the thickness direction z and the first direction x. Note that one side of the thickness direction z is sometimes referred to as "upper," and the other side of the thickness direction z is sometimes referred to as "lower." However, such terms as "upper," "lower," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component, etc. in the thickness direction z, and do not necessarily define the relationship with the direction of gravity.

[0013] The semiconductor device A10 is an LSI (Large Scale Integration) called a WL-CSP (Wafer Level Chip Size Package), etc. The semiconductor device A10 can be surface-mounted on a circuit board of an electric device, a vehicle, or the like.

[0014] As shown in FIGS. 5 and 6, the semiconductor element 10 has a body 11, a plurality of electrodes 12, and a passivation film 13.

[0015] As shown in FIGS. 5 and 6, the main body 11 includes a semiconductor substrate 111 and a semiconductor layer 112 located on one side of the semiconductor substrate 111 in the thickness direction z. The semiconductor substrate 111 is obtained from, for example, a silicon wafer. Various semiconductor circuits such as transistors and diodes are configured on the upper surface (surface facing upward in the thickness direction z) of the semiconductor layer 112 and in its vicinity. An insulating layer may be formed on the lower surface (surface facing downward in the thickness direction z) of the semiconductor layer 112. The insulating layer may contain, for example, epoxy resin.

[0016] 5 and 6, the multiple electrodes 12 are located on one side of the body 11 in the thickness direction z. The multiple electrodes 12 are in contact with the upper surface (the surface facing upward in the thickness direction z) of the body 11. The multiple electrodes 12 are each electrically connected to various semiconductor circuits configured in the semiconductor layer 112.

[0017] The passivation film 13 covers the upper surface of the main body 11 (the surface facing upward in the thickness direction z). The passivation film 13 contacts the periphery of each electrode 12 in a plan view. The passivation film 13 is a thin film containing silicon dioxide (SiO2) or silicon nitride (Si3N4), or a laminate of these thin films. As shown in Figures 5 and 6, the passivation film 13 has a plurality of openings 131. The plurality of openings 131 are individually arranged on the plurality of electrodes 12. Each of the plurality of electrodes 12 is exposed from the passivation film 13 through the corresponding opening 131.

[0018] As shown in Figures 5 and 6, the second protective film 4 is located between the main body 11 and the first protective film 3 in the thickness direction z. The second protective film 4 covers a portion of each of the multiple electrodes 12 and a portion of the passivation film 13. The second protective film 4 is an insulator containing an organic compound. The organic compound includes, but is not limited to, polyimide, for example.

[0019] The second protective film 4 includes a covered portion 41 and an exposed portion 42. The covered portion 41 is a portion of the second protective film 4 that is covered by any of the multiple rewirings 20. The exposed portion 42 is a portion of the second protective film 4 that is not covered by any of the multiple rewirings 20, i.e., a portion that is exposed from the multiple rewirings 20.

[0020] As shown in FIG. 6 , the covering portion 41 has a plurality of openings 411. In this embodiment, each of the plurality of openings 411 is a through-hole penetrating the second protective film 4 in the thickness direction z. A rewiring 20 is fitted into each of the plurality of openings 411. In this embodiment, each of the openings 411 is a rectangle (square) with rounded corners in a planar view. That is, the shape of each of the openings 411 in a planar view has curved, rounded corners. Alternatively, each of the openings 411 may be a rectangle with chamfered corners in a planar view. As shown in FIGS. 1 to 4 , each of the openings 411 is arranged such that its four sides extend along the first direction x or the second direction y in a planar view. That is, in the illustrated example, one of the two pairs of opposite sides of each of the openings 411 is aligned along the first direction x, and the other of the two pairs of opposite sides is aligned along the second direction y.

[0021] 7, the multiple openings 411 include multiple through holes 411A and multiple through holes 411B. The multiple through holes 411A are located above the multiple electrodes 12. Through the multiple through holes 411A, a portion of each of the multiple electrodes 12 is exposed from the second protective film 4. The multiple through holes 411B are located above the passivation film 13. Through the multiple through holes 411B, the passivation film 13 is partially exposed from the second protective film 4.

[0022] In the semiconductor device A10, as shown in FIG. 7, each opening 411 has an opening length L10. Hereinafter, the opening length L10 of each through hole 411A among the plurality of openings 411 is referred to as an opening length L11, and the opening length L10 of each through hole 411B among the plurality of openings 411 is referred to as an opening length L12. That is, each through hole 411A has an opening length L11, and each through hole 411B has an opening length L12. The opening length L10 is an edge on the lower side in the thickness direction z (the side closer to the main body 11 in the thickness direction z) of each opening 411, and is the length of a portion corresponding to the short side in a plan view. As described above, since the planar shape of each opening 411 is a substantially square (a square with rounded corners), the opening length L10 corresponds to the dimension in the first direction x or the dimension in the second direction y. In the present embodiment, the opening lengths L10 of each opening 411 are the same as each other. Therefore, in the present embodiment, the opening length L11 of each through hole 411A and the opening length L12 of each through hole 411B are the same.

[0023] In the semiconductor device A10, the opening length L10 of each opening 411 (the opening length L11 of each through hole 411A and the opening length L12 of each through hole 411B) is larger than twice the thickness t20 of the rewiring 20 (see FIG. 7), and is smaller than the sum of half of the thickness t4 of the second protective film 4 (see FIG. 7) and twice the thickness t20 of the rewiring 20. That is, in the semiconductor device A10, 2×t20 < L10, L11, L12 < (1 / 2×t4 + 2×t20) is satisfied. The thickness t20 is, as shown in FIG. 7, the dimension in the thickness direction z of each rewiring 20, and is the sum of the dimensions in the thickness direction z of the underlying layer 20a and the conductive layer 20b. Also, the thickness t4 is, as shown in FIG. 7, the dimension in the thickness direction z of the second protective film 4. Note that the configuration is not limited to the case where each opening length L10 (L11, L12) is within this range.

[0024] As shown in FIGS. 5 and 6, the plurality of rewirings 20 are located on the side opposite to the main body 11 with respect to the plurality of electrodes 12 in the thickness direction z. Each of the plurality of rewirings 20 is electrically connected to one of the plurality of electrodes 12.

[0025] As shown in FIGS. 6 and 7, each of the multiple rewirings 20 includes an underlayer 20a and a conductive layer 20b. The underlayer 20a includes a barrier layer that contacts any of the multiple electrodes 12 and the second protective film 4, and a seed layer that is stacked on the barrier layer. The barrier layer includes titanium (Ti). The seed layer includes copper (Cu). The conductive layer 20b is stacked on the seed layer of the underlayer 20a. The conductive layer 20b includes copper. The dimension of the conductive layer 20b in the thickness direction z is larger than the dimension of the underlayer 20a in the thickness direction z.

[0026] As shown in FIG. 6 , each of the multiple rewirings 20 includes multiple first portions 21 and multiple second portions 22. The multiple first portions 21 and multiple second portions 22 described below are common to all rewirings 20 unless otherwise specified. The multiple first portions 21 are portions of the corresponding rewirings 20 that are individually fitted into the multiple openings 411. Of the multiple first portions 21, those fitted into the multiple through holes 411A are in contact with the electrode 12 and are electrically connected to the electrode 12. The second portions 22 are stacked on the covering portion 41 that is covered by the corresponding rewirings 20. The multiple first portions 21 and the second portions 22 are connected to each other. With this configuration, each rewiring 20 is electrically connected to the corresponding electrode 12.

[0027] 6, each of the rewirings 20 has an opposing surface 201. The opposing surface 201 faces the first protective film 3 in the thickness direction z. The opposing surface 201 has a top 202 and a plurality of recesses 203.

[0028] The top portion 202 faces upward in the thickness direction z. The top portion 202 is the top surface of the opposing surface 201 and is located upward in the thickness direction z. The top portion 202 is, for example, flat. The top portion 202 may have unevenness (surface roughness) inherent to the base material of the member, or unevenness due to manufacturing errors, etc.

[0029] Each of the multiple recesses 203 is recessed from the top 202 in the thickness direction z. In a plan view, the multiple recesses 203 individually overlap with the multiple openings 411. Each of the multiple recesses 203 is formed by fitting a portion of the rewiring 20 into each opening 411. In this configuration, the shape of each recess 203 in a plan view is substantially the same as the shape of each opening 411 in a plan view. For example, the shape of each recess 203 in a plan view is similar to the shape of each opening 411 in a plan view. The periphery of each opening 411 in a plan view is contained within the periphery of each recess 203 in a plan view. In the semiconductor device A10, the shape of each of the multiple recesses 203 in a plan view is a rectangle (square) with rounded corners, similar to the shape of each opening 411 in a plan view. In the illustrated example, in each of the plurality of recesses 203, one of the two pairs of opposite sides is aligned along the first direction x, and the other of the two pairs of opposite sides is aligned along the second direction y. For these reasons, in the semiconductor device A10, the dimension of each recess 203 in the first direction x is the same as the dimension in the second direction y.

[0030] As shown in FIGS. 6 and 7 , each of the recesses 203 has a bottom surface 203a and a sidewall 203b. The bottom surface 203a faces upward in the thickness direction z. The bottom surface 203a is located closer to the main body 11 in the thickness direction z than the terminal connection surface 204. In a plan view, the periphery of the bottom surface 203a is contained within the periphery of the opening 411 located below the bottom surface 203a in the thickness direction z. The sidewall 203b connects the bottom surface 203a and the top portion 202. In a plan view, the sidewall 203b surrounds the bottom surface 203a. In the example shown in FIG. 7 , the sidewall 203b includes a portion extending substantially parallel to the bottom surface 203a in the thickness direction z and a portion curved from the portion extending substantially parallel to the bottom surface 203a and connecting to the top portion 202. The shape of the sidewall 203b is not limited to this. For example, the sidewall 203b may be configured to be inclined in the thickness direction z from the bottom surface 203a toward the top portion 202. The shape of the sidewall 203b may vary depending on the shape of each opening 411 and the method for forming the redistribution lines 20.

[0031] As shown in FIGS. 6 and 7 , the plurality of recesses 203 includes a plurality of first grooves 2031 and a plurality of second grooves 2032. The plurality of first grooves 2031 overlap with the plurality of through holes 411A, respectively, in a plan view. The plurality of first grooves 2031 can be formed by fitting parts of the rewirings 20 (some of the first portions 21) into the plurality of through holes 411A. The plurality of second grooves 2032 overlap with the plurality of through holes 411B, respectively, in a plan view. The plurality of second grooves 2032 can be formed by fitting parts of the rewirings 20 (some of the first portions 21) into the plurality of through holes 411B.

[0032] In the semiconductor device A10, the bottom distance w11 of each first groove 2031 (see FIG. 7) is the same as the bottom distance w12 of each second groove 2032 (see FIG. 7). The bottom distance w11 is the length of the short side of the bottom surface 203a of each first groove 2031 in a planar view, and the bottom distance w12 is the length of the short side of the bottom surface 203a of each second groove 2032 in a planar view. When the bottom distance w11 of each first groove 2031 and the bottom distance w12 of each second groove 2032 are not distinguished from each other and are referred to as the bottom distance w10 of each recess 203 (see FIG. 7), the bottom distances w10 of each recess 203 are the same.

[0033] In the semiconductor device A10, the depth d11 (see FIG. 7) of each first groove 2031 and the depth d12 (see FIG. 7) of each second groove 2032 are the same. The depth d11 is the distance in the thickness direction z between the top 202 and the bottom surface 203a of each first groove 2031 (i.e., the dimension of each first groove 2031 in the thickness direction z), and the depth d12 is the distance in the thickness direction z between the top 202 and the bottom surface 203a of each second groove 2032 (i.e., the dimension of each second groove 2032 in the thickness direction z). When the depth d11 of each first groove 2031 and the depth d12 of each second groove 2032 are not distinguished from each other and are referred to as the depth d10 of each recess 203 (see FIG. 7), the depths d10 of the recesses 203 are the same.

[0034] In the semiconductor device A10, the ratio of the bottom distance w10 to the depth d10 (bottom distance w10:depth d10) in each of the plurality of recesses 203 is 1:2 or greater. That is, in each of the plurality of recesses 203, the depth d10 is twice or greater than the bottom distance w10 of the bottom surface 203a. Hereinafter, the ratio of the bottom distance to the depth of each recess 203 (bottom distance:depth) will be referred to as the "aspect ratio." In the semiconductor device A10, the aspect ratio (bottom distance w11:depth d11) of each first groove 2031 is 1:2 or greater. That is, the depth d11 is twice or greater than the bottom distance w11. Furthermore, the aspect ratio (bottom distance w12:depth d12) of each second groove 2032 is 1:2 or greater. That is, the depth d12 is twice or greater than the bottom distance w12. The aspect ratio of each recess 203 (the aspect ratio of each first groove 2031 and the aspect ratio of each second groove 2032) is not limited to 1:2 or more.

[0035] In plan view, the separation distance between two adjacent recesses 203 among the plurality of recesses 203 is, for example, 10 μm or more and 50 μm or less. That is, in the region where the first protective film 3 and the rewiring 20 contact each other, the plurality of recesses 203 are provided so that the rewiring 20 does not continue continuously with a uniform thickness for longer than 50 μm. Also, in the region where the first protective film 3 and the rewiring 20 contact each other, the plurality of recesses 203 are provided so that the separation distance between the adjacent recesses 20 is, for example, 900 μm or more in plan view. 2 More than 22500μm 2 They shall be provided at a rate of one per unit area as follows:

[0036] In the semiconductor device A10, the plurality of recesses 203 form unevenness on the opposing surface 201 of each rewiring 20. For example, when the top 202 has unevenness due to the inherent unevenness of the base material of the rewiring 20 or due to manufacturing errors, the unevenness due to the plurality of recesses 203 has a greater difference in height than the unevenness on the top 202.

[0037] As shown in Fig. 6, each of the multiple rewirings 20 has a terminal connection surface 204. The terminal connection surface 204 is connected to the opposing surface 201. A plurality of terminals 5 are individually in contact with the terminal connection surfaces 204 of the multiple rewirings 20. As shown in Fig. 6, in the semiconductor device A10, the terminal connection surface 204 is located at the same height as the top 202 of the opposing surface 201 in the thickness direction z.

[0038] As shown in FIGS. 5 and 6 , the first protective film 3 is located on the same side as the rewirings 20 in the thickness direction z with respect to the electrodes 12. In a plan view, the first protective film 3 overlaps the rewirings 20 and the second protective film 4. The first protective film 3 is an insulator containing an organic compound. The first protective film 3 includes, for example, polyimide. In this example, the composition of the first protective film 3 is the same as the composition of the second protective film 4. Instead of polyimide, the first protective film 3 is made of polyamide, polybenzoxazole, phenolic resin, or the like. The dimension of the first protective film 3 in the thickness direction z is larger than the dimension of the second protective film 4 in the thickness direction z.

[0039] 5 and 6, the first protective film 3 has a plurality of openings 32. The plurality of openings 32 penetrate the first protective film 3 in the thickness direction z. From each of the plurality of openings 32, one of the terminal connection surfaces 204 of the plurality of rewirings 20 is exposed.

[0040] 6, the first protective film 3 includes a plurality of fitting portions 31. The fitting portions 31 are fitted into the recesses 203 (the plurality of first grooves 2031 and the plurality of second grooves 2032) of the rewirings 20, respectively.

[0041] As shown in FIGS. 5 and 6 , each of the multiple terminals 5 is located on the opposite side of the multiple electrodes 12 with respect to the multiple rewirings 20 in the thickness direction z. Each of the multiple terminals 5 is electrically connected to one of the multiple rewirings 20. The multiple terminals 5 are exposed from the first protective film 3. Each of the multiple terminals 5 includes a metal layer 51 and a bonding layer 52. The metal layer 51 and the bonding layer 52 described below are common to all of the terminals 5 unless otherwise specified.

[0042] The metal layer 51 is interposed between the bonding layer 52 and the multiple redistribution lines 20 in the thickness direction z. As shown in FIG. 6 , the metal layer 51 includes an underlayer 511 and a conductive layer 512. The underlayer 511 includes a barrier layer in contact with the terminal connection surface 204 of any of the redistribution lines 20, and a seed layer stacked on the barrier layer. The barrier layer includes titanium. The seed layer includes copper. The conductive layer 512 is stacked on the seed layer of the underlayer 511. The conductive layer 512 includes copper. The dimension of the conductive layer 512 in the thickness direction z is larger than the dimension of the underlayer 511 in the thickness direction z.

[0043] As shown in FIGS. 5 and 6 , the bonding layer 52 is located on the opposite side of the metal layer 51 from the plurality of rewirings 20 in the thickness direction z. The bonding layer 52 is stacked on the metal layer 51. The bonding layer 52 is, for example, solder. The composition of the bonding layer 52 includes, for example, tin (Sn), but is not limited to this. The bonding layer 52 is, for example, formed in a hemispherical shape, and the upper surface of the bonding layer 52 (the surface facing upward in the thickness direction z) is curved. Note that the shape of the bonding layer 52 is not limited to the example shown in the drawings.

[0044] Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to Figures 8 to 16. Figures 8 to 16 are enlarged cross-sectional views of a main part showing one step of the method for manufacturing the semiconductor device A10, and correspond to the cross section of Figure 6.

[0045] First, as shown in FIG. 8 , a second protective film 4 is formed on a semiconductor element 10 having a main body 11, multiple electrodes 12, and a passivation film 13. Here, the main body 11 corresponds to one element of a silicon wafer. The second protective film 4 is formed by applying photosensitive polyimide to the passivation film 13, for example, by spin coating, and then curing the applied polyimide through lithographic patterning. A plurality of openings 411 are formed in the second protective film 4 by lithographic patterning. The plurality of openings 411 include a plurality of through holes 411A and a plurality of through holes 411B. Of the plurality of openings 411, those formed on the plurality of electrodes 12 (the plurality of through holes 411A) expose portions of each electrode 12. The method for forming the second protective film 4 can be changed as appropriate depending on the material of the second protective film 4 used.

[0046] Next, as shown in FIG. 9, the base layer 20a is formed. For example, a spin coating method is used to form the base layer 20a, but this is not limitative. For example, a sputtering method may also be used. Through this process, the entire second protective film 4 and parts of the passivation film 13 and the electrodes 12 exposed by each of the multiple openings 411 in the second protective film 4 are covered with the base layer 20a. In other words, the entire upper surface (the surface facing upward in the thickness direction z) of the semiconductor device A10 in the process of being manufactured shown in FIG. 8 is covered with the base layer 20a. In forming the base layer 20a, a barrier layer containing, for example, titanium may be formed first, and then a seed layer containing copper may be formed.

[0047] Next, as shown in FIGS. 10 and 11, a plurality of conductive layers 20b are formed. To form the plurality of conductive layers 20b, first, as shown in FIG. 10, a first resist 81 is applied to the base layer 20a, and then lithographic patterning is performed on the first resist 81. As a result, a plurality of openings 811 penetrating the first resist 81 in the thickness direction z are formed in the first resist 81. Next, as shown in FIG. 11, a plurality of conductive layers 20b are deposited by electrolytic plating using the base layer 20a as a conductive path. The conductive layer 20b contains, for example, copper. As a result, a plurality of conductive layers 20b individually accommodated in the plurality of openings 811 are formed. At this time, as shown in FIG. 11, a plurality of recesses 203 are formed on the upper surface (surface facing upward in the thickness direction z) of the conductive layer 20b, consisting of regions where the second protective film 4 is formed and regions where the second protective film 4 is not formed. That is, the recess 203 is formed above each opening 411 (each through-hole 411A, 411B) in the thickness direction z.

[0048] 12, after removing the first resist 81, the areas of the base layer 20a exposed from the plurality of conductive layers 20b are removed. The base layer 20a is removed by wet etching using a mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). This completes the formation of the plurality of rewirings 20.

[0049] Next, as shown in FIG. 13 , the first protective film 3 is formed. The first protective film 3 is formed by applying a material containing photosensitive polyimide to the plurality of rewirings 20 and the second protective film 4 exposed from the plurality of rewirings 20, and then curing the material after lithographic patterning. A plurality of openings 32 are formed in the first protective film 3 by lithographic patterning. The terminal connection surfaces 204 of the rewirings 20 are exposed from the plurality of openings 32. The method for forming the first protective film 3 can be changed as appropriate depending on the material of the first protective film 3 used.

[0050] 14, an underlayer 511 is formed by sputtering. This step covers the entire first protective film 3 and the terminal connection surfaces 204 of the multiple rewirings 20 exposed from the multiple openings 32 of the first protective film 3 with the underlayer 511. That is, the entire upper surface (surface facing upward in the thickness direction z) of the semiconductor device A10 in the process of being manufactured shown in FIG. 13 is covered with the underlayer 511. In forming the underlayer 511, a barrier layer containing, for example, titanium may be formed first, and then a seed layer containing copper may be formed.

[0051] Next, as shown in FIG. 15, a plurality of conductive layers 512 are formed. To form the plurality of conductive layers 512, first, a second resist 82 is applied to the base layer 511, and then lithographic patterning is performed on the second resist 82. As a result, a plurality of openings 821 penetrating the second resist 82 in the thickness direction z are formed. Next, the plurality of conductive layers 512 are deposited by electrolytic plating using the base layer 511 as a conductive path. Each conductive layer 512 contains, for example, copper. As a result of the above, a plurality of conductive layers 512 individually accommodated in the plurality of openings 821 are formed.

[0052] 16, after removing the second resist 82, the regions of the base layer 511 exposed from the plurality of conductive layers 512 are removed. The base layer 511 is removed by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide. As a result, the plurality of metal layers 51 are formed.

[0053] Next, a plurality of bonding layers 52 are formed. To form the plurality of bonding layers 52, first, a material containing solder is placed on the plurality of metal layers 51. Then, the material is melted by reflow. Finally, the melted material is hardened. In this way, a plurality of bonding layers 52 individually placed on the plurality of metal layers 51 are formed.

[0054] Finally, the main body 11, which is one element of the silicon wafer, is divided into individual pieces by blade dicing or the like. Through the above steps, the semiconductor device A10 is manufactured. Note that the above-described manufacturing method for the semiconductor device A10 is an example, and is not limited to this.

[0055] FIG. 17 shows a state in which the semiconductor device A10 is used. In this example, the semiconductor device A10 is surface-mounted on a circuit board 91. The circuit board 91 includes, for example, a substrate 911 and multiple wiring patterns 912. The substrate 911 is an insulator, and each of the multiple wiring patterns 912 includes, for example, copper. Alternatively, the circuit board 91 may include only the wiring patterns 912, which are leads. Furthermore, the circuit board 91 may include external terminals located on the opposite side of the substrate 911 from the multiple wiring patterns 912 in the thickness direction z. The semiconductor device A10 is conductively bonded to the multiple wiring patterns 912 of the circuit board 91 by multiple terminals 5 (bonding layers 52), respectively. The semiconductor device A10 is bonded to the circuit board 91 in an orientation in which the top and bottom in the thickness direction z are reversed relative to the orientation shown in FIGS. 1 to 7. Unlike the example shown in FIG. 17, at least a part of the semiconductor device A10 (for example, the part between it and the circuit board 91) may be covered with a sealing resin such as underfill.

[0056] The functions and effects of the semiconductor device A10 are as follows.

[0057] In the semiconductor device A10, each rewiring 20 has an opposing surface 201 that faces the first protective film 3 in the thickness direction z, and the opposing surface 201 has recesses 203 recessed in the thickness direction z. The first protective film 3 is recessed into each recess 203. With this configuration, an anchoring effect is exerted on the first protective film 3 with respect to the multiple rewirings 20, thereby improving the adhesive strength between the first protective film 3 and each rewiring 20. Therefore, the semiconductor device A10 can suppress peeling of the first protective film 3 from each rewiring 20. Furthermore, even if peeling occurs at the interface between the first protective film 3 and each rewiring 20, the recesses 203 prevent the peeling from progressing. This also makes it possible to suppress peeling of the first protective film 3 from each rewiring 20.

[0058] In the semiconductor device A10, the aspect ratio of the bottom distance w10 to the depth d10 (bottom distance w10:depth d10) in each of the plurality of recesses 203 is 1:2 or greater. That is, the depth d10 in each of the plurality of recesses 203 is twice or greater than the bottom distance w10 of the bottom surface 203a. This configuration can ensure an appropriate adhesive strength between the first protective film 3 and each rewiring 20 due to the anchoring effect described above.

[0059] In the semiconductor device A10, the second protective film 4 has a plurality of openings 411. According to this configuration, the covering portion 41 of the second protective film 4 has unevenness formed on the surface that contacts each rewiring 20, and a plurality of recesses 203 are formed on the opposing surface 201 of each rewiring 20 formed on the second protective film 4. That is, at least one recess 203 can be formed in each rewiring 20.

[0060] In the semiconductor device A10, the opening length L10 of each opening 411 (the opening length L11 of each through hole 411A and the opening length L12 of each through hole 411B) is greater than twice the thickness t20 of the rewiring 20 (see FIG. 7). This configuration ensures a connection, with an appropriate thickness, between the part (first portion 21) of the rewiring 20 fitted in the opening 411 and the part (second portion 22) of the rewiring 20 disposed on the second protective film 4. In addition, in the semiconductor device A10, the opening length L10 of each opening 411 (the opening length L11 of each through hole 411A and the opening length L12 of each through hole 411B) is less than the sum of half the thickness t4 (see FIG. 7) of the second protective film 4 and twice the thickness t20 of the rewiring 20 (see FIG. 7). According to this configuration, it is possible to make the aspect ratio (bottom distance w10:depth d10) of the bottom distance w10 to the depth d10 in each recess 203 equal to or greater than 1:2. That is, in the semiconductor device A10, the opening length L10 of each opening 411 (opening length L11 of each through hole 411A and opening length L12 of each through hole 411B) is greater than twice the thickness t20 (see FIG. 7) of the rewiring 20 and is smaller than the sum of half the thickness t4 (see FIG. 7) of the second protective film 4 and twice the thickness t20 (see FIG. 7) of the rewiring 20. Therefore, it is possible to make the aspect ratio (bottom distance w10:depth d10) of the bottom distance w10 to the depth d10 in each recess 203 equal to or greater than 1:2 while ensuring a connection between the first portion 21 and the second portion 22 with an appropriate thickness.

[0061] Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other as long as no technical contradiction occurs.

[0062] 18 shows a semiconductor device A11 according to a modification of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the following respect: the opening length L11 of the through hole 411A is different from the opening length L12 of the through hole 411B.

[0063] In the illustrated example, the opening length L11 of each through hole 411A is greater than the opening length L12 of each through hole 411B. In this configuration, the bottom distance w11 of each first groove 2031 is greater than the bottom distance w12 of each second groove 2032. Here, the depth d11 of each first groove 2031 and the depth d12 of each second groove 2032 are the same, as in the semiconductor device A10. Therefore, the aspect ratio of each first groove 2031 (bottom distance w11:depth d11) and the aspect ratio of each second groove 2032 (bottom distance w12:depth d12) are different from each other. Note that in this example as well, the aspect ratio of each first groove 2031 and the aspect ratio of each second groove 2032 are each 1:2 or greater.

[0064] The semiconductor device A11 also achieves the same effects as the semiconductor device A10. Furthermore, in the semiconductor device A11, the opening length L11 of each through hole 411A is greater than the opening length L12 of each through hole 411B, which increases the contact area between each rewiring 20 and the corresponding electrode 12. In other words, the semiconductor device A11 can improve the electrical connection between each rewiring 20 and the corresponding electrode 12.

[0065] In the semiconductor device A11 described above, the opening length L11 is greater than the opening length L12. However, unlike this configuration, the opening length L11 may be smaller than the opening length L12. As can be understood from these modifications, in the semiconductor device of the present disclosure, the opening lengths L10 of the openings 411 are not limited to being the same as each other, and include, for example, a case in which the opening length L11 of the through hole 411A and the opening length L12 of the through hole 411B are different. Furthermore, in the semiconductor device of the present disclosure, the bottom distances w10 of the recesses 203 are not limited to being the same as each other, and include, for example, a case in which the bottom distance w11 of the first grooves 2031 and the bottom distance w12 of the second grooves 2032 are different.

[0066] In the above semiconductor devices A10 and A11, an example was shown in which the opening 411 in the second protective film 4 located on the passivation film 13 is a through hole 411B, but unlike this configuration, the opening 411 on the passivation film 13 may be a groove that does not penetrate the second protective film 4 in the thickness direction z.

[0067] Second Embodiment 19 shows a semiconductor device A20 according to the second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in the following respect: none of the multiple openings 411 is formed in the second protective film 4. In other words, the second protective film 4 is formed with a uniform thickness on the passivation film 13.

[0068] In the semiconductor device A20, each rewiring 20 has a metal layer 20c in addition to a base layer 20a and a conductive layer 20b. In each of the multiple rewirings 20, the metal layer 20c is stacked on the conductive layer 20b. The metal layer 20c contains, for example, copper like the conductive layer 20b, but may contain a different metal from that of the conductive layer 20b. The metal layer 20c is not formed on the entire surface of the conductive layer 20b, but is formed partially on the conductive layer 20b. With this configuration, multiple recesses 203 are formed on the opposing surface 201 of the rewiring 20. Furthermore, in the semiconductor device A20, multiple terminals 5 are formed on the metal layer 20c of each rewiring 20. Therefore, in the semiconductor device A20, a portion of the upper surface of the metal layer 20c (the surface facing upward in the thickness direction z) serves as the terminal connection surface 204.

[0069] For example, after forming the plurality of conductive layers 20b shown in FIG. 11, the first resist 81 is removed, and then a resist for forming the plurality of metal layers 20c is formed. Then, the plurality of metal layers 20c are deposited by electrolytic plating using the base layer 20a as a conductive path. The plurality of metal layers 20c include, for example, copper. Thereafter, the resist for forming the plurality of metal layers 20c is removed, and the regions of the base layer 20a exposed by the plurality of conductive layers 20b and the plurality of metal layers 20c are removed. This allows each rewiring 20 of the semiconductor device A20 to be formed.

[0070] In the semiconductor device A20, similar to the semiconductor device A10, the opposing surface 201 of each rewiring 20 has a recess 203, and the first protective film 3 extends into the recess 203. Therefore, similar to the semiconductor device A10, the semiconductor device A20 can suppress peeling of the first protective film 3 from each rewiring 20. Furthermore, even if peeling occurs at the interface between the first protective film 3 and each rewiring 20, the recess 203 prevents the peeling from progressing, which also makes it possible to suppress peeling of the first protective film 3 from each rewiring 20.

[0071] Additionally, the semiconductor device A20 has a common configuration with the semiconductor device A10 and thus achieves the same effects as the semiconductor device A10. As can be understood from the semiconductor device A20, in the semiconductor device of the present disclosure, the rewiring 20 also includes a structure in which a plurality of plating layers (conductive layer 20b and metal layer 20c in the semiconductor device A20) are stacked on an underlayer 20a.

[0072] 20 shows a semiconductor device A21 according to a first modified example of the second embodiment. The semiconductor device A21 differs from the semiconductor device A20 in the following respect: each terminal 5 is formed on the conductive layer 20b, not on the metal layer 20c.

[0073] In the semiconductor device A21, each terminal 5 is formed on the conductive layer 20b, and therefore a part of the upper surface (surface facing upward in the thickness direction z) of the conductive layer 20b serves as the terminal connection surface 204. In this configuration, the top 202 of the opposing surface 201 is located above the terminal connection surface 204 in the thickness direction z.

[0074] 21 shows a semiconductor device A22 according to a second modification of the second embodiment. The semiconductor device A22 differs from the semiconductor device A20 in the following respect: each redistribution line 20 does not have a metal layer 20c.

[0075] In the semiconductor device A22, a portion of the upper surface of the conductive layer 20b of each rewiring 20 is partially recessed. Therefore, as shown in FIG. 21, the conductive layer 20b of each rewiring 20 includes a portion (thick portion) having a relatively large dimension in the thickness direction z and a portion (thin portion) having a relatively small dimension in the thickness direction z. In the semiconductor device A22, the recessed portion of the conductive layer 20b forms multiple recesses 203. In other words, the multiple recesses 203 are formed by the step between the thick portion and the thin portion. The method for partially removing the conductive layer 20b of each rewiring 20 is not limited in any way, but may be, for example, etching. As a result, the conductive layer 20b having partially recessed portions is formed as shown in FIG. 21.

[0076] 22 shows a semiconductor device A23 according to a third modified example of the second embodiment. The semiconductor device A23 differs from the semiconductor device A22 in the following respect: each terminal 5 is in contact with the aforementioned thin portion (portion having a small dimension in the thickness direction z) of the conductive layer 20b.

[0077] In the semiconductor device A22 described above, each terminal 5 is formed to contact the thick portion (the portion having a large dimension in the thickness direction z) of the conductive layer 20b. In contrast, in the semiconductor device A23, each terminal 5 is formed to contact the thin portion (the portion having a small dimension in the thickness direction z) of the conductive layer 20b. In this configuration, as shown in FIG. 22, the top 202 of the opposing surface 201 is located above the terminal connection surface 204 in the thickness direction z, similar to the semiconductor device A21.

[0078] Like the semiconductor device A20, each of the semiconductor devices A21 to A23 described above has a recess 203 on the opposing surface 201 of each rewiring 20, and the first protective film 3 extends into the recess 203, so that, like the semiconductor device A20, it is possible to suppress peeling of the first protective film 3 from each rewiring 20. In addition, each of the semiconductor devices A21 to A23 has a configuration in common with the semiconductor device A20, and therefore exhibits the same effects as the semiconductor device A20.

[0079] <Third embodiment> 23 shows a semiconductor device A30 according to the third embodiment. The semiconductor device A30 differs from the semiconductor device A10 in the following respect: the second protective film 4 has two organic films 40a and 40b.

[0080] In the second protective film 4 of the semiconductor device A30, the two organic films 40a, 40b each contain, for example, polyimide. Alternatively, the two organic films 40a, 40b may contain different organic compounds. The organic film 40a covers the passivation film 13 and partially covers each electrode 12. The organic film 40a has a uniform thickness on the passivation film 13. The organic film 40b partially covers the organic film 40a formed on the passivation film 13. While the organic film 40a is formed on each electrode 12 in the semiconductor device A30, for example, the organic film 40b may be formed instead of the organic film 40a.

[0081] In the semiconductor device A30, the multiple openings 411 include multiple through holes 411A and multiple grooves 411C. Each of the multiple grooves 411C is located on the passivation film 13 and is recessed downward in the thickness direction z from the upper surface (the surface facing upward in the thickness direction z) of the second protective film 4. The multiple grooves 411C are formed on the passivation film 13 by regions where the organic film 40b is formed and regions where the organic film 40b is not formed. Furthermore, the multiple through holes 411A are formed on each electrode 12 by regions where the organic film 40a is formed and regions where the organic film 40a is not formed.

[0082] In the semiconductor device A30, similar to the semiconductor device A10, the opposing surface 201 of each rewiring 20 has a recess 203, and the first protective film 3 extends into the recess 203. Therefore, similar to the semiconductor device A10, the semiconductor device A30 can suppress peeling of the first protective film 3 from each rewiring 20. Furthermore, even if peeling occurs at the interface between the first protective film 3 and each rewiring 20, the recess 203 prevents the peeling from progressing, which also makes it possible to suppress peeling of the first protective film 3 from each rewiring 20.

[0083] Additionally, the semiconductor device A30 has a configuration in common with the semiconductor devices A10 and A20, and thus exhibits the same effects as the semiconductor devices A10 and A20. As can be seen from the semiconductor device A30, in the semiconductor device of the present disclosure, the opening 411 in the second protective film 4 disposed on the passivation film 13 may be a groove 411C instead of a through hole 411A.

[0084] 24 shows a semiconductor device A31 according to a modification of the third embodiment. The semiconductor device A31 differs from the semiconductor device A30 in the following respect: an organic film 40a is partially formed on the passivation film 13, and an organic film 40b has a uniform thickness on the organic film 40a.

[0085] In the semiconductor device A30 described above, the second organic film 40b on the passivation film 13 is provided with unevenness to form a plurality of grooves 411C in the second protective film 4. In contrast, in the semiconductor device A31, the first organic film 40a on the passivation film 13 is provided with unevenness to form a plurality of grooves 411C in the second protective film 4.

[0086] Like the semiconductor device A30, each of the above-described semiconductor devices A31 has a recess 203 on the opposing surface 201 of each rewiring 20, and the first protective film 3 extends into the recess 203, so that, like the semiconductor device A30, it is possible to suppress peeling of the first protective film 3 from each rewiring 20. In addition, the semiconductor device A31 has a configuration in common with the semiconductor device A30, and therefore exhibits the same effects as the semiconductor device A30.

[0087] In the semiconductor devices A30 and A31 described above, the openings 411 include the grooves 411C instead of the through holes 411B, but the openings 411 may include the through holes 411B as in the semiconductor device A10, etc. In this case, the organic film 40b is laminated over the entire upper surface of the organic film 40a.

[0088] In the above-described first to third embodiments (including their modified examples), examples have been shown in which at least one first groove 2031 is formed on each electrode 12 and at least one second groove 2032 is formed on the passivation film 13, but when the area where the rewiring 20 and the first protective film 3 contact each other on each electrode 12 or passivation film 13 is small (for example, when it is equal to or smaller than the unit area described above), the first groove 2031 or the second groove 2032 may not be formed. In such a case, for example, in a configuration in which the first groove 2031 is not formed, at least one second groove 2032 may be formed by forming irregularities in the passivation film 13, as shown in FIG.

[0089] In the first to third embodiments (including their modifications), each recess 203 has a square shape with rounded corners in plan view. Unlike this configuration, the shape of each recess 203 in plan view may be a rectangle with rounded corners as shown in FIG. 27 . Alternatively, it may be a circle as shown in FIG. 28 . Alternatively, it may be an ellipse as shown in FIG. 29 . Alternatively, it may be a polygon (a regular octagon in the illustrated example) with obtuse corners (interior angles) as shown in FIG. 30 . As described above, the shape of each recess 203 in plan view is, for example, similar to the shape of each opening 411 in plan view. Therefore, in the example shown in FIG. 26 , the openings 411 that individually overlap multiple recesses 203 have a square shape with rounded corners in plan view. In addition, in the example shown in Fig. 27, the opening is a rectangle with rounded corners in plan view, in the example shown in Fig. 28, a circle in plan view, in the example shown in Fig. 29, an ellipse, and in the example shown in Fig. 30, a polygon with obtuse corners (interior angles). Note that in the examples shown in Figs. 26 to 30, the opening length L10 of each opening 411 corresponds to the short side length shown in the figures.

[0090] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. For example, the semiconductor device according to the present disclosure includes the following embodiments. Note that, although examples of each component in the following embodiments are indicated in parentheses using the symbols in the above-described embodiment (including modified examples), the present disclosure is not limited to these. Appendix 1. a body (11) including a semiconductor layer (112); an electrode (12) located on one side (upper side) of the body (11) in the thickness direction (z) of the body (11) and conducting to the semiconductor layer (112); a rewiring (20) located on the opposite side of the main body (11) with respect to the electrode (12) in the thickness direction (z) and electrically connected to the electrode (12); a first protective film (3) that is located on the same side as the rewiring (20) with respect to the electrode (12) in the thickness direction (z) and that overlaps with the rewiring (20) when viewed in the thickness direction (z); a second protective film (4) located between the main body (11) and the first protective film (3) in the thickness direction (z); Equipped with The rewiring (20) has an opposing surface (201) that faces the first protective film (3) in the thickness direction (z), the opposing surface (201) has the at least one recess (203) recessed in the thickness direction (z), The semiconductor device (A10) is characterized in that the first protective film (3) extends into each of the at least one recess (203). Appendix 2. the second protective film (4) has a covering portion (41) covered with the rewiring (20), The semiconductor device (A10) according to appendix 1, wherein the covering portion (41) has an uneven surface formed on the surface that contacts the rewiring (20). Appendix 3. the covering portion (41) has an opening (411) that overlaps with the at least one recessed portion (203) when viewed in the thickness direction (z), The rewiring (20) includes a first portion (21) that is fitted into the opening (411) and a second portion (22) that is laminated on the covering portion (41), The semiconductor device (A10) according to Appendix 2, wherein the first portion (21) and the second portion (22) are connected to each other. Appendix 3-1. The semiconductor device (A10) according to Appendix 3, wherein the opening (411) is a through-hole that penetrates the second protective film (4) in the thickness direction (z). Appendix 3-2. The semiconductor device (A30, A31) described in Appendix 3, wherein the opening (411) is a groove recessed in the second protective film (4) from one side of the thickness direction (z) to the other side of the thickness direction (z). Appendix 4. A semiconductor device (A10) according to Appendix 3, wherein the opening length (L10) of the opening (411) is greater than twice the dimension (t20) of the rewiring (20) in the thickness direction (z) and is smaller than the sum of half the dimension (t4) of the second protective film (4) in the thickness direction (z) and twice the dimension (t20) of the rewiring (20). Appendix 5. Further provided is a terminal (5) electrically connected to the rewiring (20), The semiconductor device (A10) according to any one of Appendix 1 to Appendix 4, wherein the terminal (5) is located on the opposite side of the electrode (12) with respect to the rewiring (20) in the thickness direction (z) and is exposed from the first protective film (3). Appendix 6. The semiconductor device (A10) according to Appendix 5, wherein the terminal (5) includes a metal layer (51) in contact with the rewiring (20) and a bonding layer (52) formed on the metal layer (51). Appendix 7. The semiconductor device (A10) according to appendix 6, wherein the rewiring (20) contains the same material as the metal layer (51). Appendix 8. The rewiring (20) has a terminal connection surface (204) that contacts the terminal (5), Each of the at least one recess (203) has a bottom surface (203a), A semiconductor device (A10) according to any one of Appendix 5 to Appendix 7, wherein in each of the at least one recess (203), the bottom surface (203a) is located closer to the main body (11) than the terminal connection surface (204) in the thickness direction (z). Appendix 8-1. The rewiring (20) has a terminal connection surface (204) that contacts the terminal (5), Each of the at least one recess (203) has a bottom surface (203a), A semiconductor device (A21, A23) described in any one of Appendix 5 to Appendix 7, wherein in each of the at least one recess (203), the bottom surface (203a) is located at the same height as the terminal connection surface (204) in the thickness direction (z). Appendix 9. A semiconductor device (A10) according to Appendix 8, wherein, for each of the at least one recess (203), the dimension (d10) of the recess (203) in the thickness direction (z) is at least twice the bottom distance (w10) of the recess (203). Appendix 10. The semiconductor device (A10) according to any one of Supplementary Note 1 to Supplementary Note 9, wherein the at least one recess (203) includes a plurality of recesses (203). Appendix 11. The semiconductor device further includes a passivation film (13) located on the one side (upper side) of the thickness direction (z) of the main body (11), The electrode (12) is exposed from the passivation film (13), The semiconductor device (A10) according to Appendix 10, wherein the plurality of recesses (203) are arranged in a region spanning from the passivation film (13) to the electrode (12). Appendix 11-1. A semiconductor device (A10, A11) described in Appendix 11, wherein the plurality of recesses (203) include a first groove (2031) that overlaps with the electrode (12) when viewed in the thickness direction (z), and a second groove (2032) that overlaps with the passivation film (13) when viewed in the thickness direction (z). Appendix 11-2. A semiconductor device (A11) described in Appendix 11-1, wherein the ratio of the dimension (d11) in the thickness direction (z) of the first groove (2031) to the bottom distance (w11) and the ratio of the dimension (d12) in the thickness direction (z) of the second groove (2032) to the bottom distance (w12) are different from each other. Appendix 11-3. 12. The semiconductor device according to claim 11, wherein the passivation film (13) has projections and recesses formed thereon that overlap the plurality of recesses (203). Appendix 12. The semiconductor device (A10) according to any one of Supplementary Note 1 to Supplementary Note 11, wherein the first protective film (3) contains an organic compound. Appendix 13. The semiconductor device (A10) according to any one of Supplementary Note 1 to Supplementary Note 12, wherein the second protective film (4) contains an organic compound. Appendix 14. 14. The semiconductor device according to any one of claims 1 to 13, wherein the recess (203) is circular or elliptical when viewed in the thickness direction (z). Appendix 15. 14. The semiconductor device according to any one of claims 1 to 13, wherein the recess (203) has a rectangular shape with rounded corners or a rectangular shape with chamfered corners when viewed in the thickness direction (z). Appendix 16. 14. The semiconductor device according to any one of claims 1 to 13, wherein the recess (203) is a polygon with all corners being obtuse angles when viewed in the thickness direction (z). Appendix 16-1. The semiconductor device (A30, A31) according to any one of Supplementary Note 1 to Supplementary Note 16, wherein the second protective film (4) has two organic films (40a, 40b) stacked in the thickness direction (z). [Explanation of symbols]

[0091] A10, A11, A20 to A23, A30, A31: Semiconductor device 10: Semiconductor element 11: Main body 111: Semiconductor substrate 112: Semiconductor layer 12: Electrode 13: Passivation film 131 :Aperture 20: Rewiring 20a: Base layer 20b: Conductive layer 20c: Metal layer 201: Opposite surface 202:Top 203: Recess 203a: Bottom 203b: Side wall 2031 :1st groove 2032 :Second groove 204: Terminal connection surface 21: Part 1 22: Part 2 3: 1st protective film 31: Inset part 32:Aperture 4:Second protective film 40a,40b:Organic film 41: Covering part 411 :Aperture 411A, 411B: Through hole 411C: Groove 42:Exposed part 5: Terminal 51: Metal layer 511: Base layer 512: Conductive layer 52: Bonding layer 81: First Resist 811 :Aperture 82: Second Resist 821 :Aperture 91: Circuit board 911: Base material 912: Wiring pattern

Claims

1. a body including a semiconductor layer; an electrode located on one side of the body in the thickness direction of the body and connected to the semiconductor layer; a rewiring located on the opposite side of the main body with respect to the electrode in the thickness direction and electrically connected to the electrode; a first protective film located on the same side as the rewiring with respect to the electrode in the thickness direction and overlapping the rewiring when viewed in the thickness direction; a second protective film located between the main body and the first protective film in the thickness direction; Equipped with the rewiring has an opposing surface that faces the first protective film in the thickness direction, the opposing surface has the at least one recess recessed in the thickness direction, The semiconductor device, wherein the first protective film extends into each of the at least one recessed portion.

2. the second protective film has a covering portion covered by the rewiring, The semiconductor device according to claim 1 , wherein the covering portion has an uneven surface in contact with the rewiring.

3. the covering portion has an opening that overlaps the at least one recess when viewed in the thickness direction, the rewiring includes a first portion that is fitted into the opening and a second portion that is laminated on the covering portion; The semiconductor device according to claim 2 , wherein the first portion and the second portion are connected to each other.

4. 4. The semiconductor device according to claim 3, wherein an opening length of the opening is greater than twice the dimension of the rewiring in the thickness direction and less than the sum of half the dimension of the second protective film in the thickness direction and twice the dimension of the rewiring in the thickness direction.

5. Further, a terminal electrically connected to the rewiring is provided.

5. The semiconductor device according to claim 1, wherein the terminal is located on an opposite side of the rewiring from the electrode in the thickness direction, and is exposed from the first protective film.

6. The semiconductor device according to claim 5 , wherein the terminal includes a metal layer in contact with the rewiring, and a bonding layer formed on the metal layer.

7. The semiconductor device according to claim 6 , wherein the rewiring includes the same material as the metal layer.

8. the rewiring has a terminal connection surface that contacts the terminal, each of the at least one recess has a bottom surface; The semiconductor device according to claim 5 , wherein the bottom surface of each of the at least one recessed portion is located closer to the main body than the terminal connection surface in the thickness direction.

9. 9. The semiconductor device according to claim 8, wherein the dimension of each of said at least one recess in said thickness direction is at least twice the distance from the bottom surface of said recess.

10. 5. The semiconductor device according to claim 1, wherein said at least one recessed portion includes a plurality of recessed portions.

11. a passivation film located on the one side of the thickness direction of the body; the electrode is exposed from the passivation film, The semiconductor device according to claim 10 , wherein the plurality of recesses are arranged in a region spanning from the passivation film to the electrode.

12. 5. The semiconductor device according to claim 1, wherein the first protective film contains an organic compound.

13. 5. The semiconductor device according to claim 1, wherein the second protective film contains an organic compound.

14. 5. The semiconductor device according to claim 1, wherein said recess is circular or elliptical when viewed in said thickness direction.

15. 5. The semiconductor device according to claim 1, wherein the recess has a rectangular shape with rounded corners or a rectangular shape with chamfered corners when viewed in the thickness direction.

16. 5. The semiconductor device according to claim 1, wherein said recess is a polygon with all corners being obtuse angles when viewed in said thickness direction.

Images