Adaptive power supply ripple rejection enhancement in voltage regulator
The adaptive PSRR boost circuit in LDO regulators enhances PSRR by injecting compensation signals into the regulation loop, addressing the challenge of high frequency AC ripples while maintaining low current consumption and stability.
Patent Information
- Application Number
- JP2025057760
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-04-10
- Filing Date
- 2025-03-31
- Publication Date
- 2025-10-23
AI Technical Summary
Existing techniques for improving power supply ripple rejection (PSRR) in low-dropout voltage regulators (LDO) often require large bias currents, making it difficult to enhance PSRR without adversely affecting quiescent current consumption.
An adaptive system incorporating a PSRR boost circuit with a capacitive element and a diode-connected transistor to inject compensation signals into the regulation loop, maintaining the diode in a reverse or zero bias region to minimize current consumption while enhancing PSRR, particularly at high frequency AC ripples.
The system effectively improves PSRR without affecting the operating bandwidth or stability of the LDO regulator, providing adaptive PSRR enhancement that varies with frequency and output current, and limits maximum bias current draw.
Smart Images
Figure 2025160889000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates generally to power supply ripple rejection in voltage regulators, and more particularly to an adaptive system for improving power supply ripple rejection in low dropout voltage regulators. [Background technology]
[0002] A voltage regulator circuit is a circuit used to convert a regulated or unregulated input voltage into a regulated output voltage that can be used to power electronic devices. A low-dropout (LDO) regulator (or LDO regulator) is a type of linear voltage regulator circuit that can provide a regulated output voltage even when there is only a small difference between the input voltage and the desired output voltage. LDO regulators often utilize an open-drain topology at the output of the LDO, where the output transistor can be driven into saturation, thereby minimizing the voltage drop across the output transistor when the desired output voltage is close to the input voltage.
[0003] One performance parameter of voltage regulator circuits, including LDO regulators, is power supply ripple rejection (PSRR), also known as power supply rejection ratio. The PSRR of a voltage regulator circuit represents the ability of the voltage regulator circuit to suppress noise or other fluctuations on the input voltage supply from affecting the regulated output voltage of the voltage regulator circuit. The inventors of embodiments of the present disclosure recognized that known techniques for improving PSRR may use large bias currents. As a result, the inventors of embodiments of the present disclosure found that it can be difficult to improve PSRR without adversely affecting quiescent current consumption. Embodiments of the present disclosure may address one or more of these challenges. [Brief explanation of the drawings]
[0004] A more complete understanding of the present embodiments can be obtained by reference to the following description in conjunction with the accompanying drawings, in which like reference numerals indicate like features and in which: [Figure 1] 1 is a schematic diagram of an LDO regulator according to an example embodiment of the present disclosure. [Figure 2] FIG. 2 is a plot of operating voltages within an LDO regulator, according to an example embodiment of the present disclosure. [Figure 3A] FIG. 1 is a plot illustrating improved PSRR of an LDO regulator, according to an example embodiment of the present disclosure. [Figure 3B] FIG. 1 is a plot illustrating improved PSRR of an LDO regulator, according to an example embodiment of the present disclosure. [Figure 4] FIG. 2 is a plot illustrating bias voltage and bias current of a PSRR boost circuit as a function of output current of an LDO regulator, in accordance with an example embodiment of the present disclosure. [Figure 5] FIG. 2 is a plot of the capacitance of a varactor diode as a function of the bias voltage applied across the varactor diode terminals, according to an example embodiment of the present disclosure. [Figure 6] FIG. 1 illustrates a method for improving power supply ripple rejection in a regulator circuit, according to an example embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION
[0005] The details of one or more embodiments are set forth in the following description and the accompanying drawings. Other features will be apparent from the description and drawings, and from the claims.
[0006] 1 shows a schematic diagram of an LDO regulator 100 according to an example embodiment of the present disclosure. The LDO regulator 100 may include a first stage 110, a second stage 120, an output 130, a compensation circuit 135, and a PSRR boost circuit 150. The LDO regulator 100 generates a reference voltage V REF, a first power supply voltage VDD, and a second power supply voltage VCC. The LDO regulator 100 receives a reference voltage V REF and feedback from output 130 to produce a regulated output voltage V OUT at output 130. LDO regulator 100 may provide a regulated output voltage V OUT to an electronic device such as a load 140. The output current I OUT may depend on the amount of current drawn by load 140. The amount of current drawn by load 140 may vary depending on the operating characteristics of the electronic circuitry forming load 140. For example, when the electronic circuitry forming load 140 is in a standby or non-operating mode, the load current may be 0 μA. Conversely, when the electronic circuitry forming load 140 is operating, load 140 may draw a load current greater than 0 μA, such as 5 μA, 1 mA, 10 mA, 100 mA, 1 A, or more.
[0007] First stage 110 may be implemented in any suitable manner consistent with the operation described in this disclosure. In some embodiments, first stage 110 may include reference input 101, feedback input 102, transistors 111-114, and current source 116. As shown in FIG. 1 , the components of first stage 110 may be configured as a first amplifier stage. Transistors 111 and 112 may be P-channel metal-oxide-semiconductor field-effect transistors (“P-channel MOSFET” or “PMOS” transistors). PMOS transistors 111 and 112 may be configured as a differential pair with their respective source terminals coupled together to collectively receive a bias current from current source 116. Current source 116 may be coupled to a first power supply voltage VDD and may generate the bias current for first stage 110. The gate of transistor 111 is coupled to a reference voltage V REFThe gate of transistor 112 may be coupled to reference input 101 to receive a feedback voltage V at reference input 101. The gate of transistor 112 may be coupled to feedback input 102 to receive a feedback voltage from the output of LDO regulator 100. Thus, the differential pair formed by transistors 111 and 112 couples the reference voltage V at reference input 101 to a REF and the feedback voltage at feedback input 102 may be compared and amplified.
[0008] As shown in FIG. 1 , transistors 113 and 114 may be N-channel metal-oxide-semiconductor field-effect transistors (“N-channel MOSFETs” or “NMOS” transistors). The drain of NMOS transistor 113 may be coupled to the drain of PMOS transistor 111, and the drain of NMOS transistor 114 may be coupled to the drain of PMOS transistor 112. Furthermore, the gate of NMOS transistor 113 and the gate of NMOS transistor 114 may be coupled to the drain of NMOS transistor 113 at node A, such that NMOS transistor 114 mirrors the current of NMOS transistor 113. Thus, the components of first stage 110, including current source 116, PMOS transistors 111 and 112, and NMOS transistors 113 and 114, may collectively form a first amplifier stage with a first stage output at node 119.
[0009] Second stage 120 may be implemented in any suitable manner consistent with the operations described herein. In some embodiments, second stage 120 may include NMOS transistor 121, NMOS transistor 122, PMOS transistor 123, and PMOS transistor 124. As shown in FIG. 1 , the components of second stage 120 may be configured as a second amplifier stage with PMOS transistor 124 configured as an output transistor having an open-drain output that drives output 130 of LDO regulator 100. Second stage 120 may include a second stage input that may be coupled to the first stage output of first stage 110. For example, as shown in FIG. 1 , the gate of NMOS transistor 121 may be coupled to the first stage output at node 119, and the source of NMOS transistor 121 may be coupled to ground GND. Thus, NMOS transistor 121 may generate a drive current based on the transconductance of NMOS transistor 121 and a gate-to-source voltage applied between node 119 and ground GND.
[0010] NMOS transistor 122 may be coupled to be in the path of the drive current generated by NMOS transistor 121. As shown in FIG. 1, NMOS transistor 122 may have its gate coupled to VDD and its source coupled to the drain of NMOS transistor 121. Thus, NMOS transistor 122 may maintain a bias voltage at the drain of NMOS transistor 121 at a level equal to VDD minus the gate-to-source voltage of NMOS transistor 122. VDD may be a low power supply voltage, for example, 1.8V, 3.3V, 5.0V, or any other voltage suitable for low-voltage complementary metal-oxide semiconductor (CMOS) circuits. In some embodiments, VCC may be a low power supply voltage substantially equal to or greater than VDD; a medium power supply voltage, for example, up to 24V or 40V; or a high power supply voltage greater than 40V, for example, 50V, 60V, 70V, or higher. In embodiments in which VDD and VCC have the same voltage value, VDD and VCC may be implemented by a single voltage source. VDD and VCC may be supplied by one or more voltage regulators located upstream of LDO regulator 100. Such upstream voltage regulators may be implemented using on-chip circuitry along with the components of LDO regulator 100, or may be implemented using off-chip circuitry separate from the chip on which the components of LDO regulator 100 may be implemented.
[0011] The PMOS transistor 123 and the PMOS transistor 124 mirror the drive current generated by the NMOS transistor 121 and passing through the NMOS transistor 122 to generate the output current I OUTto the load 140. The sources of the PMOS transistors 123 and 124 may be coupled to a second power supply voltage VCC. The gates of the PMOS transistors 123 and 124 may be coupled to each other and to the drain of the PMOS transistor 123. The drain of the PMOS transistor 123 may also be coupled to the drain of the NMOS transistor 122. Thus, the drive current generated by the NMOS transistor 121 may pass through the PMOS transistor 123 and be mirrored by the PMOS transistor 124 to generate the output current I OUT to the load 140. The sizes of the PMOS transistors 123 and 124 are such that the drive current from the second power supply voltage VCC consumed by the second stage 120 is less than the output current I OUT For purposes of this disclosure, the size of an individual NMOS or PMOS transistor may refer to the ratio of the length to width of the transistor's conduction channel, and the size ratio between different transistors may refer to the ratio of the length to width of one transistor to the length to width ratio of the other transistor. The size ratio of PMOS transistor 123 to PMOS transistor 124 may be determined by the ratio of the output current I drawn by load 140. OUT , may be, for example, 1:10, 1:100, 1:1000, or less, to scale the drive current to the extent necessary to produce the output current I drawn by the load 140. OUT is zero, the bias current consumed by the second stage 120 can be zero as well, whatever the nominal semiconductor leakage current is.
[0012] Second stage 120 may also include an output capacitor 125 and feedback resistors 126 and 127. Output capacitor 125 may store charge at output 130 of LDO regulator 100. Output capacitor 125 may be configured to receive an output current I from load 140. OUTAs LDO regulator 100 responds to changes in demand, the regulated output voltage V OUT at a desired output voltage level.
[0013] Feedback resistors 126 and 127 may be coupled in series to form a resistor divider between output 130 and ground GND. The size of feedback resistors 126 and 127 is determined so that the current drawn and consumed by feedback resistors 126 and 127 from PMOS transistor 124 is less than the output current I drawn by load 140. OUT , for example, in the range of several kilohms, several megahms, or more. An intermediate node between resistor 126 and resistor 127 may be coupled to feedback input 102 of first stage 110. Thus, feedback resistors 126 and 127 are coupled to a resistor that is substantially equal to the output voltage V OUT Based on this feedback, first stage 110 and second stage 120 collectively determine the output voltage V OUT is the reference voltage V REF can be adjusted to a level proportional to
[0014] In some embodiments, output capacitor 125 and feedback resistors 126 and 127 may be implemented as part of second stage 120, as shown in FIG. 1 . In other embodiments, output capacitor 125, feedback resistors 126 and 127, or any combination thereof, may be implemented separately from second stage 120. For example, in some embodiments, transistors 121-124 of second stage 120 may be implemented as on-chip circuitry along with components of first stage 110 and PSRR boost circuit 150, while output capacitor 125 and feedback resistors 126 and 127 may be implemented separately with off-chip components. Furthermore, feedback for LDO regulator 100 may be provided by feedback resistors, such as feedback resistors 126 and 127 shown in FIG. 1 , or by feedback resistors that are connected to the output voltage V OUTmay be implemented by any other feedback circuitry suitable for providing a feedback signal representing
[0015] LDO regulator 100 may also include compensation circuit 135. Compensation circuit 135 may be configured to compensate for the frequency response of LDO regulator 100, thereby ensuring stability of LDO regulator 100. In some embodiments, compensation circuit 135 may be implemented by a capacitor coupled between ground and the first stage output at node 119. In other embodiments, compensation circuit 135 may be located in any suitable location within LDO regulator 100 and may comprise any suitable arrangement of components, such as capacitors and resistors, to ensure stability of the regulation loop. In some embodiments, compensation circuit 135 may be implemented in on-chip circuitry along with components of first stage 110, second stage 120, and PSRR boost circuit 150. In other embodiments, compensation circuit 135 may be implemented in off-chip components separate from first stage 110, second stage 120, or PSRR boost circuit 150.
[0016] 1, the LDO regulator 100 may also include a PSRR boost circuit 150. The PSRR boost circuit 150 may be implemented in any suitable manner consistent with the operation described in this disclosure. In some embodiments, the PSRR boost circuit 150 may include transistors 153, 152, and 151, and a capacitive element 160. The transistor 153 may be a PMOS transistor that matches the PMOS transistors 123 and 124. The source of the PMOS transistor 153 may be coupled to VCC, and the gate of the PMOS transistor 153 may be coupled to the gates of the PMOS transistors 123 and 124. Thus, the PMOS transistor 153 mirrors the drive current of the PMOS transistor 124 to generate the output current I OUT Similarly to generating the bias current I, the drive current through PMOS transistor 123 is mirrored to generate the bias current I biaspsrrTherefore, the bias current I generated by the PMOS transistor 153 for the PSRR boost circuit 150 can be biaspsrr is the output current I OUT In this disclosure, unless otherwise stated, both the DC component and the AC ripple of the current generated by the PMOS transistor 124 are proportional to I biaspsrr may refer to the DC component of the current generated by PMOS transistor 124. PMOS transistor 153 mirrors the drive current of PMOS transistor 124 to generate the output current I OUT Similarly to generating I, the drive current is mirrored to generate I biaspsrr , so that the PMOS transistor 153 generates an output current I OUT Based on I biaspsrr or more specifically, the output current I OUT In some embodiments, the sizes of PMOS transistor 153 and PMOS transistor 124 are such that the bias current I consumed by PSRR boost circuit 150 is biaspsrr is the output current I OUT The size ratio of the PMOS transistor 153 to the PMOS transistor 124 may be determined so that the bias current I biaspsrr I OUT to scale according to the same ratio, for example 1:10, 1:100, 1:1000, or even less.
[0017] As shown in Figure 1, the bias current I biaspsrr may pass through NMOS transistor 152 and be received by the drain of NMOS transistor 151 at node B of PSRR boost circuit 150. NMOS transistor 151 may be configured as a diode-connected transistor with the gate of NMOS transistor 151 coupled to the drain of NMOS transistor 151 and the source of NMOS transistor 151 coupled to ground GND. Thus, NMOS transistor 151 is configured to receive the bias current I biaspsrrmay function as a current-to-voltage converter to generate a bias voltage at node B based on
[0018] The capacitive element 160 may be coupled, for example, between node B of the PSRR boost circuit 150 and node A of the first stage 110. The capacitive element 160 may include a diode 161 coupled in series with a capacitor 162. The diode 161 may be positioned with its cathode facing toward node B of the PSRR boost circuit 150. For example, as shown in FIG. 1 , the diode 161 may have its anode coupled to node A of the first stage 110, while the capacitor 162 may be coupled in series between the cathode of the diode 161 and node B of the PSRR boost circuit 150. In another example, the diode 161 may have its cathode coupled to node B of the PSRR boost circuit 150, while the capacitor 162 may be coupled in series between the anode of the diode 161 and node A of the first stage 110. In other embodiments, the capacitive element 160 may include any suitable number of instances of the diode 161 and the capacitor 162 arranged in series or parallel to provide suitable capacitive coupling between node B of the PSRR boost circuit 150 and node A of the first stage 110.
[0019] The first stage 110 and PSRR boost circuit 150 may be configured such that the diode 161 is maintained in either the reverse bias region or the zero bias region of operation. For example, the DC operating point of node B may be determined by the size of the NMOS transistor 151 and the output current I OUT Bias current I mirroring biaspsrr It depends on the size of the NMOS transistor 151 and I biaspsrr I OUT may be configured so that the DC operating voltage at node B remains close to or higher than the DC operating voltage at node A of the first stage 110, thereby keeping diode 161 in either a reverse bias or zero bias operating region.
[0020] FIG. 2 illustrates an example plot of the DC operating voltages at nodes A and B, respectively, within LDO regulator 100, in accordance with an example embodiment of the present disclosure. Plot 201 illustrates the DC operating voltage at node A ("V A ") to the output current I OUT Plot 202 shows the DC operating voltage at node B of the PSRR boost circuit 150 ("V"). B ") to the output current I OUT As shown in Figure 2, the DC operating voltage at node A is a function of the output current I OUT On the other hand, the DC operating voltage of node B of the PSRR boost circuit 150 can vary from a voltage close to the voltage of node A at nominal output current, such as 1 μA, to a voltage close to the voltage of node A at output current I OUT may increase to a voltage higher than the voltage at node A as . Thus, the relative voltages at the node of first stage 110 and the node of PSRR boost circuit 150 with capacitive element 160 coupled between them maintain diode 161 in either a reverse bias or zero bias region of operation.
[0021] Since the diode 161 is maintained in either a reverse bias or zero bias region of operation, the diode 161 can function as a space charge region (depletion layer / barrier) capacitor. 160 can be expressed as follows: C 160 =(C 161 * C 162 ) / (C 161 +C 162 ) where C 161 is the capacitance of the diode 161, and C 162 is the capacitance of the capacitor 162.
[0022] 1, the PSRR boost circuit 150 can improve the PSRR of the LDO regulator 100. The PSRR boost circuit 150 reduces the PSRR of the output current I caused by high frequency AC ripple on VCC. OUT and output voltage V OUTAs described in more detail below, PSRR boost circuit 150 may be configured to generate and inject compensation into the regulation loop of LDO regulator 100, which compensates for the high frequency AC ripple on VCC that would otherwise increase the output current I of LDO regulator 100. OUT and output voltage V OUT The effect on the
[0023] As described above with reference to FIG. 1, the PMOS transistor 153 of the PSRR boost circuit 150 supplies the output current I OUT The bias current I is proportional to biaspsrr The high frequency AC ripple on VCC may be configured to generate I OUT to the same extent as adding high frequency ripple components to I biaspsrr Similarly, I biaspsrr As mentioned above, NMOS transistor 151 is configured as a diode-connected transistor, and I biaspsrr Thus, NMOS transistor 151 may be coupled to receive I biaspsrr Therefore, high frequency AC ripple from VCC can be converted to I biaspsrr to the bias voltage at node B via the capacitive element 160. The capacitive element 160 may capacitively couple node B of the PSRR boost circuit 150 to node A of the first stage 110. Thus, the capacitive element 160 may inject at least a portion of the high frequency AC ripple present at node B of the PSRR boost circuit 150 into node A of the first stage 110.
[0024] The polarity of node A of first stage 110 may be opposite to the polarity of the output of LDO regulator 100. For example, in LDO regulator 100, the signal path from node A of first stage 110 to output 130 follows three inversions, including through NMOS transistor 114, NMOS transistor 121, and PMOS transistor 124. Thus, high frequency AC ripple that may originate from VCC and be injected into node A of first stage 110 as a compensation signal is proportional to the high frequency AC ripple from VCC. OUT and output voltage V OUT This may tend to offset and compensate for the impact on
[0025] 1 , diode 161 and capacitor 162 may be sized such that their capacitance does not substantially affect the gain or phase margin of LDO regulator 100 at unity gain. Diode 161 may be sized such that its nominal zero-bias capacitance may be, for example, 4 pF, 2 pF, 1 pF, or less. Similarly, capacitor 162 may be sized such that its capacitance may be, for example, 4 pF, 2 pF, 1 pF, or less. Thus, PSRR boost circuit 150 may improve the PSRR of a regulator circuit, such as LDO regulator 100, without adversely affecting the regulator circuit's operating bandwidth or stability.
[0026] 3A and 3B illustrate plots showing improved PSRR of an example LDO regulator in accordance with an example embodiment of the present disclosure. The PSRR boost circuit 150 can improve PSRR in the frequency range above the unity-gain bandwidth of the LDO regulator. FIG. 3A shows the PSRR at an output current I of 5 μA. OUT 3A shows the PSRR of an example LDO regulator that may have a unity-gain bandwidth of approximately 3 kHz at 100 kHz. Plot 301 shows the PSRR of the example LDO regulator with PSRR boost circuit 150, and plot 302 shows the PSRR of the example LDO regulator without PSRR boost circuit 150. As shown in FIG. 3A, PSRR boost circuit 150 provides a 5 μA output current IOUT 3B shows the PSRR improvement for a frequency range of approximately 4 kHz to 40 kHz at an output current I OUT 3B shows the PSRR of an example LDO regulator that may have a unity-gain bandwidth of approximately 60 kHz at 100 mA. Plot 311 shows the PSRR of the example LDO regulator with PSRR boost circuit 150, and plot 312 shows the PSRR of the example LDO regulator without PSRR boost circuit 150. As shown in FIG. 3B, PSRR boost circuit 150 reduces the PSRR of the example LDO regulator at 100 mA of output current I OUT 3A and 3B, the PSRR improvement techniques disclosed herein result in an adaptive system whereby the PSRR improvement provided by the PSRR boost circuit 150 varies with the regulator's frequency and output current I OUT It can be a function of both.
[0027] Above, embodiments of the PSRR boost circuit 150 are described as operating with the LDO regulator 100, which includes the first stage 110 and the second stage 120. In other embodiments, the PSRR boost circuit 150 may also be implemented to improve the PSRR of other types of regulator circuits or other types of LDO regulators. For example, the PSRR boost circuit 150 may be implemented to improve the PSRR of a regulator circuit, utilizing any number and type of amplifier stages suitable for providing a regulated output voltage at the output of the regulator circuit. In some embodiments, the PSRR boost circuit 150 may generate a compensation signal based on high-frequency ripple in VCC and inject the compensation signal into a node in the regulator circuit that is opposite in polarity to the output of the regulator circuit.
[0028] Due to the characteristics of the PSRR boost circuit 150, the maximum bias current I consumed by the PSRR boost circuit 150 is biaspsrrmay be clamped to some maximum value. Thus, advantageously, the maximum current drawn from VCC consumed by the PSRR boost circuit 150 may be limited.
[0029] 1, the PMOS transistor 153 of the PSRR boost circuit 150 mirrors the drive current generated by the NMOS transistor 121, as does the PMOS transistor 124. Thus, the PMOS transistor 153 mirrors the bias current I biaspsrr , which generates the output current I OUT In some embodiments, the NMOS transistor 152 may be proportional to a maximum bias current I biaspsrr For example, it can act as a clamp or clamp transistor to limit I biaspsrr I OUT 1, node B is coupled to the source of NMOS transistor 152. Therefore, the voltage at node B can be limited to a maximum of VDD minus the gate-to-source voltage of NMOS transistor 152.
[0030] FIG. 4 illustrates the bias voltage and bias current I at node B of the PSRR boost circuit 150 according to an example embodiment of the present disclosure. biaspsrr The output current I OUT 4 illustrates plots showing the voltage at node B of the PSRR boost circuit 150 as a function of the bias current I of the PSRR boost circuit 150. Plot 401 shows VDD set to an example voltage of 1.8V. Plot 402 shows the voltage at node B of the PSRR boost circuit 150, which is coupled to the source of the NMOS transistor 152 as shown in FIG. 1. Plot 403 shows the bias current I of the PSRR boost circuit 150 as a function of the bias current I of the PSRR boost circuit 150. biaspsrr I biaspsrr is the output current I OUT is the threshold I THOUT until the output current I OUT can be increased in proportion to I THOUT Above that, the voltage at node B may be clamped to a maximum value equal to VDD minus the gate-to-source voltage of NMOS transistor 152. The output current I OUT ITHOUT When the bias current I biaspsrr can similarly be clamped to a constant or near-constant value.
[0031] Output current I OUT I THOUT When it is smaller, the bias current I biaspsrr can be expressed as follows: I biaspsrr =I OUT / N where N is the ratio of the size of the PMOS transistor 124 in the second stage 120 to the size of the PMOS transistor 153 in the PSRR boost circuit 150. The output current I OUT I THOUT When it is larger, the bias current I biaspsrr can be expressed as follows: I biaspsrr =(VDD-Vgs 152 ) * gm 151 where Vgs 152 is the gate-source voltage of the NMOS transistor 152, and gm 151 is the transconductance of the NMOS transistor 151.
[0032] Bias current I biaspsrr is clamped to the output current threshold I THOUT can be set using several design parameters. For example, I can be set by the ratio of the size of the PMOS transistor 124 in the second stage 120 to the size of the PMOS transistor 153 in the PSRR boost circuit 150. biaspsrr Output current I OUT As another example, the VDD voltage applied to the gate of NMOS transistor 152 can be increased or decreased to change the voltage level at which node B is clamped, and thus the bias current I biaspsrr1 shows that the gate of NMOS transistor 152 may be coupled to VDD, but the gate of NMOS transistor 152 also functions as a gate for NMOS transistor 152, which clamps the bias voltage at node B thereto, thus controlling the bias current I biaspsrr As a further example, the size of NMOS transistor 152 may be selected to determine the gate-to-source voltage of NMOS transistor 152 at a given current, and the size of NMOS transistor 151 may be selected to determine the transconductance (gm 151 ) may be chosen to determine
[0033] In some embodiments, the PSRR boost circuit 150 can improve the PSRR of a regulator, such as the LDO regulator 100, and further reduce the PSRR of a regulator that is sensitive to large steps in the VCC voltage or the output current I drawn by the load 140. OUT It may also prevent under- and over-peaks during large transients such as large changes in voltage.
[0034] 2, the PSRR boost circuit 150 may be configured such that the diode 161 is maintained in either a reverse bias or zero bias region of operation. Under such operating conditions, the diode 161 may function as a varactor or varactor diode, having a capacitance that can vary as a function of the bias voltage across the diode 161.
[0035] 5 illustrates a plot of the capacitance of a varactor diode, such as diode 161, as a function of the bias voltage applied across the varactor diode terminals, according to an example embodiment of the present disclosure. Plot 501 shows how the capacitance of an example embodiment of diode 161 decreases, for example, from about 1.8 pF to about 1.0 pF as the bias voltage from the cathode to the anode of diode 161 increases from 0 V to 3 V.
[0036] Because the capacitance of diode 161 decreases as the bias voltage from the cathode to the anode of diode 161 increases, the capacitive coupling that capacitive element 160 provides between node B of PSRR boost circuit 150 and node A of first stage 110 decreases as the bias voltage at node B increases relative to the bias voltage at node A. Thus, a large step in the VCC voltage supplied to LDO regulator 100 or the output current I drawn by load 140 decreases. OUT The amount of compensation that PSRR boost circuit 150 provides in response to large transient steps, such as large steps of . Thus, when LDO regulator 100 experiences a transient step in the VCC voltage of, for example, 5 V, 10 V, 20 V, or more, PSRR boost circuit 150 may improve the PSRR of LDO regulator 100 without overcompensating. Similarly ... output current I drawn by load 140, OUT When a transient step of, for example, 10 mA, 100 mA, or more occurs, the PSRR boost circuit 150 can improve the PSRR of the LDO regulator 100 without overcompensating.
[0037] FIG. 6 illustrates the operation of an example method 600 for improving power supply ripple rejection of a regulator circuit, in accordance with an example embodiment of the present disclosure. Method 600 may be performed by any suitable mechanism, such as the first stage 110, the second stage 120, and the PSRR boost circuit 150 of the LDO regulator 100, or any suitable combination thereof. Method 600 may be performed with fewer or more steps than shown in FIG. 6. Furthermore, steps of method 600 may be omitted, repeated, performed in parallel, performed in a different order than shown in FIG. 6, or performed recursively. One or more steps of method 600, while shown sequentially, may be performed simultaneously or reordered.
[0038] In step 602, a regulated output voltage may be provided at the output of the regulator circuit. For example, LDO regulator 100 may provide a regulated output voltage V OUT may be provided at output 130.
[0039] In step 604, a bias current may be generated based on the output current of the regulator circuit. For example, the PSRR boost circuit 150 may generate a bias current based on the output current I OUT The bias current I is proportional to biaspsrr In some embodiments, the PMOS transistor 153 may include a PMOS transistor 153 that may generate an output current I OUT Thus, PMOS transistor 153 may mirror the drive current through PMOS transistor 123 in the same manner as providing the output current I OUT It is also said to mirror the
[0040] In step 606, the bias current may be converted to a bias voltage at a bias voltage node. For example, the NMOS transistor 151 of the PSRR boost circuit 150 may convert the bias current I biaspsrrThe NMOS transistor 151 may be configured as a diode-connected MOSFET with its drain coupled to its gate, such that the NMOS transistor 151 receives a bias current I biaspsrr , which may function as a current-to-voltage converter that generates a bias voltage at a bias voltage node, such as node B of the PSRR boost circuit 150, based on
[0041] In step 608, the bias voltage node may be capacitively coupled to an amplifier stage of the regulator circuit. For example, as shown in FIG. 1, capacitive element 160 may capacitively couple node B of PSRR boost circuit 150 to node A of first stage 110.
[0042] In step 610, the capacitive coupling may be changed based on the bias voltage. For example, as shown in FIG. 2, nodes A and B are connected to each other when the diode 161 of the capacitive element 160 is biased to the output current I OUT , the output current I can be biased to receive either zero bias or reverse bias over a range of . Thus, the diode 161 can function as a varactor diode, with a capacitance that varies as shown in FIG. 5 based on the voltage bias applied across the diode 161 terminals. OUT As V changes, the bias voltage at node B may also change, thus changing the capacitance of diode 161 and the overall capacitance of capacitive element 160.
[0043] In step 612, the maximum value of the bias current may be clamped. For example, PMOS transistor 153 is configured such that PMOS transistor 124 mirrors PMOS transistor 123 to provide the output current I OUT In the same manner as generating the bias current I biaspsrr Therefore, the output current I of the LDO regulator 100 OUT Based on this, the bias current I of the PSRR boost circuit 150 biaspsrrFurthermore, I between the PMOS transistor 153 and node B of the PSRR boost circuit 150 biaspsrr An NMOS transistor 152 may be disposed in the path of the bias current I. The gate of the NMOS transistor 152 may be coupled to VDD. Thus, the voltage at node B may be limited to the maximum value obtained by subtracting the gate-source voltage of the NMOS transistor 152 from VDD. Therefore, the bias current I biaspsrr is the output current I OUT is the threshold I THOUT until the output current I OUT can be increased in proportion to I THOUT Above this, the voltage at node B can be clamped to a maximum value equal to VDD minus the gate-to-source voltage of NMOS transistor 152. Thus, the output current I OUT I THOUT When the bias current I biaspsrr can similarly be clamped to some maximum value.
[0044] Embodiments herein may include a regulator circuit. The regulator circuit may include a first stage including a reference input and a feedback input, the feedback input configured to receive feedback from an output of the regulator circuit. The regulator circuit may also include a second stage coupled to the first stage, the second stage including an output transistor configured to drive the output of the regulator circuit. The regulator circuit may also include a boost circuit. The boost circuit may include a first transistor configured to generate a bias current based on an output current of the output transistor. The boost circuit may further include a current-to-voltage converter configured to generate a bias voltage based on the bias current. The boost circuit may also include a capacitive element coupled between the current-to-voltage converter and a node of the first stage. The regulator circuit may have one or more of the following additional elements in any combination: Element 1: The capacitive element comprises a varactor diode; Element 2: The capacitive element comprises a capacitor coupled in series with the varactor diode; Element 3: The boost circuit includes a clamp configured to limit a maximum value of the bias current. Element 4: The first stage is configured to be powered by a first voltage source, and the second stage and the boost circuit are configured to be powered by a second voltage source. Element 5: The output transistor of the second stage is coupled to the output of the regulator circuit to provide an open-drain output. Element 6: The current-to-voltage converter of the boost circuit comprises a diode-connected transistor.
[0045] Embodiments herein may include a low-dropout regulator. The low-dropout regulator may include a first amplifier stage configured to be powered by a first voltage source. The first amplifier stage may include a reference input and a feedback input configured to receive feedback from an output of the low-dropout regulator. The low-dropout regulator may further include a second amplifier stage configured to be powered by a second voltage source. The second amplifier stage may include a second stage input coupled to the first stage output. The second amplifier stage may also include an output transistor configured to drive the output of the low-dropout regulator. The low-dropout regulator may also include a boost circuit configured to be powered by the second voltage source. The boost circuit may include a first transistor configured to mirror an output current of the output transistor to generate a bias current, a current-to-voltage converter configured to generate a bias voltage based on the bias current, and a capacitive element coupled between the current-to-voltage converter and a node of the first amplifier stage. The low-dropout regulator may also have one or more of the following additional elements in any combination: Element 1: The capacitive element comprises a varactor diode. Element 2: The capacitive element further comprises a capacitor coupled in series with the varactor diode. Element 3: The boost circuit includes a clamp configured to limit a maximum value of the bias current. Element 4: The second voltage provided by the second voltage source is greater than or equal to the first voltage provided by the first voltage source. Element 5: The output transistor of the second amplifier stage is coupled to provide an open-drain output to the output of the low-dropout regulator. Element 6: The current-to-voltage converter of the boost circuit comprises a diode-connected transistor.
[0046] Embodiments herein may include a method for improving power supply ripple rejection. The method for improving power supply ripple rejection may include providing a regulated output voltage at an output of a regulator circuit, generating a bias current based on an output current of the regulator circuit, converting the bias current to a bias voltage at a bias voltage node, and capacitively coupling the bias voltage node to an amplifier stage of the regulator circuit. The method for improving power supply ripple rejection may also include one or more of the following additional elements in any combination: Element 1: varying the capacitive coupling based on the bias voltage; Element 2: clamping the bias current to a maximum value; Element 3: clamping the bias current includes limiting the bias voltage based on at least a voltage level of a first voltage supply and a gate-to-source voltage of a clamp transistor; Element 4: generating the bias current includes mirroring the output current of the regulator circuit; and Element 5: converting the bias current to a bias voltage at the bias voltage node includes receiving the bias current with a diode-connected metal-oxide-semiconductor field-effect transistor.
[0047] Although examples have been described above, other modifications and variations may be made from this disclosure without departing from the spirit and scope of these examples. The above description of various embodiments illustrates the principles of the present invention. Numerous variations and modifications will be apparent to those skilled in the art based on the above disclosure. It is intended that the following claims be interpreted to encompass all such variations and modifications.
Claims
1. a first stage including a reference input and a feedback input, the feedback input configured to receive feedback from an output of the regulator circuit; a second stage coupled to the first stage, the second stage including an output transistor configured to drive the output of the regulator circuit; a boost circuit, The boost circuit comprises: a first transistor configured to generate a bias current based on an output current of the output transistor; a current-to-voltage converter configured to generate a bias voltage based on the bias current; and a capacitive element coupled between the current-to-voltage converter and a node of the first stage; Regulator circuit.
2. 2. The regulator circuit of claim 1, wherein the capacitive element comprises a varactor diode.
3. 2. The regulator circuit of claim 1, wherein the boost circuit includes a clamp configured to limit a maximum value of the bias current.
4. the first stage being configured to be powered by a first voltage source; the second stage and the boost circuit are configured to be powered by a second voltage source; 2. The regulator circuit of claim 1.
5. 2. The regulator circuit of claim 1, wherein the output transistor of the second stage is coupled to provide an open-drain output at the output of the regulator circuit.