Information processing apparatus and information processing method

Abstract

To provide an information processing apparatus and an information process method which can efficiently update firmware without stopping operation of the information processing apparatus.SOLUTION: The information processing apparatus comprises: a first circuit in which a first boot loader for activating a microcomputer and a second boot loader for activating the microcomputer in a state where firmware of the microcomputer can be updated are stored; and a control unit which performs control to update the firmware of the microcomputer on the basis of the second boot loader after resetting the microcomputer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to an information processing device and an information processing method. [Background technology]

[0002] Conventionally, when updating the firmware of a microcomputer built into an information processing device via a communication interface such as a USB (Universal Serial Bus) or a UART (Universal Asynchronous Receiver Transmitter), it is necessary to launch a dedicated boot loader that enables the firmware to be updated via the communication interface.

[0003] In some cases, the microcontroller also has a built-in bootloader, in which case the microcontroller can start up from the bootloader after changing the status of the bootstrap circuit.

[0004] For example, during manufacturing, the operating system (OS) of the information processing device is not running, so a dedicated boot loader that enables firmware updates can be easily started.

[0005] However, when the OS of the information processing device is running, the microcomputer starts up with the normal boot loader, so it is necessary to restart the information processing device itself and start it up again with the dedicated boot loader, which leaves room for further improvement in terms of convenience. Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide an information processing device and an information processing method that can efficiently update firmware without stopping the operation of the information processing device. [Means for solving the problem]

[0007] An information processing device according to an embodiment includes a first circuit that stores a first boot loader that starts a microcontroller and a second boot loader that starts the microcontroller in a state in which the firmware of the microcontroller can be updated, and a control unit that resets the microcontroller and then controls updating the firmware of the microcontroller based on the second boot loader. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a configuration diagram showing an example of the overall configuration of an information processing system according to an embodiment. [Figure 2] FIG. 2 is a block diagram illustrating an example of a hardware configuration of the information processing device according to the embodiment. [Figure 3] FIG. 3 is a block diagram illustrating an example of the configuration of the information processing device according to the embodiment. [Figure 4] FIG. 4 is a sequence diagram showing an example of the flow of processing executed by the information processing device according to the embodiment. [Figure 5] FIG. 5 is a block diagram showing an example of the configuration of an information processing device according to the first modified example. [Figure 6] FIG. 6 is a sequence diagram showing an example of the flow of processing executed by the information processing device according to the first modified example. [Figure 7] FIG. 7 is a block diagram showing an example of the configuration of an information processing device according to the second modification. [Figure 8] FIG. 8 is a sequence diagram showing an example of the flow of processing executed by the information processing device according to the second modification. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an information processing apparatus and an information processing method according to an embodiment will be described with reference to the drawings. Note that the present invention is not limited to the embodiment.

[0010] 1 is a configuration diagram showing an example of the overall configuration of an information processing system 1 according to an embodiment. The information processing system 1 according to this embodiment is a system for updating software installed in an information processing device 2 using an external storage device 3. The information processing system 1 includes the information processing device 2 and the external storage device 3.

[0011] The information processing device 2 is, for example, a PC (Personal Computer), a server device, a POS (Point Of Sale) terminal, an image forming device, an industrial computer, an embedded device, etc. The information processing device 2 is connected to an external storage device 3 via an interface. The information processing device 2 applies the latest firmware stored in the external storage device 3 to software installed in the information processing device 2, thereby updating the software.

[0012] The external storage device 3 is, for example, a USB (Universal Serial Bus) memory, and is a non-volatile storage device. The external storage device 3 is connected to the information processing device 2 via an interface. The external storage device 3 stores the latest firmware corresponding to the software installed in the information processing device 2. The external storage device 3 may also be a server device that can be connected via a network only under a limited environment. The limited environment is a state in which the external storage device 3 is managed under an environment where strict crime prevention and security measures are implemented.

[0013] 2 is a block diagram showing an example of a hardware configuration of an information processing device 2 according to an embodiment. As shown in FIG. 2, the information processing device 2 includes a CPU (Central Processing Unit) 21, a RAM (Random Access Memory) 22, a ROM (Read Only Memory) 23, an auxiliary storage device 24, and an external I / F (Interface) 25.

[0014] The CPU 21 is the main controller. The RAM 22 loads programs and various data. The ROM 23 stores various programs. The auxiliary storage device 24 stores various programs. The CPU 21, RAM 22, ROM 23, auxiliary storage device 24, and external I / F 25 are connected to one another via a bus 26. The CPU 21, RAM 22, and ROM 23 constitute a controller, which will be described later. That is, the controller executes control processing related to the information processing device 2, which will be described later, by the CPU 21 operating in accordance with a control program stored in the ROM 23 or the auxiliary storage device 24 and loaded in the RAM 22.

[0015] The RAM 22 is a volatile memory used as a work area for the CPU 21. The ROM 23 is a non-volatile memory. The auxiliary storage device 24 is a recording device such as an HDD (Hard Disk Drive) or an SSD (Solid State Drive), and stores, for example, an OS (Operating System), application programs, various data, etc. The external I / F 25 is an interface for connecting to, for example, the external storage device 3 or other devices or circuits.

[0016] Fig. 3 is a block diagram showing an example of the configuration of an information processing device 2 according to an embodiment. As shown in Fig. 3, the information processing device 2 includes a microcomputer 4, a host controller 5, a one-shot IC (Integrated Circuit) 6, and a USB switch 7. The host controller 5 shown in Fig. 3 corresponds to the CPU 21 shown in Fig. 2. The microcomputer 4, the one-shot IC 6, and the USB switch 7 shown in Fig. 3 are connected to the external I / F 25 shown in Fig. 2.

[0017] The microcomputer 4 includes a bootstrap circuit 41, a first input / output unit 42, and a reset unit 43.

[0018] The bootstrap circuit 41 stores a first boot loader that starts the microcomputer 4 and a second boot loader that starts the microcomputer 4 in a state where the firmware of the microcomputer 4 can be updated. The bootstrap circuit 41 is an example of a first circuit. For example, the first boot loader is a program for starting the microcomputer 4 as a normal device. For example, the second boot loader is a program for starting the microcomputer 4 as a DFU (Device Firmware Update) device. The bootstrap circuit 41 switches from the first boot loader to the second boot loader based on a signal input from the one-shot IC 6.

[0019] The microcomputer 4 functions as a normal device by loading and starting up the first boot loader set in the bootstrap circuit 41. The microcomputer 4 can also update firmware by loading and starting up the second boot loader set in the bootstrap circuit 41.

[0020] The first input / output unit 42 is an interface that performs serial communication with the USB switch 7. A DFU transition command for starting up the microcomputer 4 as a DFU device is input to the microcomputer 4 via the first input / output unit 42. When the DFU transition command is input, the microcomputer 4 updates the firmware of the microcomputer 4 based on the second boot loader. The reset unit 43 is a terminal for resetting the microcomputer 4. The reset unit 43 performs, for example, a hard reset.

[0021] The host controller 5 has a second input / output unit 51, a third input / output unit 52, and a fourth input / output unit 53. The host controller 5 is an example of a control unit. The host controller 5 performs various controls and outputs various signals to the microcomputer 4 from the second input / output unit 51, the third input / output unit 52, and the fourth input / output unit 53, thereby controlling updating of the firmware of the microcomputer 4.

[0022] The second input / output unit 51 is an interface that performs serial communication with the USB switch 7. Before resetting the microcomputer 4, the host controller 5 outputs a DFU transition command to the microcomputer 4 via the second input / output unit 51.

[0023] The host controller 5 resets the microcomputer 4 via the second input / output unit 51, and then controls the USB switch 7 to open. Specifically, the host controller 5 resets the microcomputer 4 via the second input / output unit 51, and then controls the USB switch 7 to open so that the microcomputer 4 enters a first state indicating a state in which firmware is to be updated.

[0024] In addition, the host controller 5 updates the firmware of the microcomputer 4 via the second input / output unit 51, resets the microcomputer 4, and then controls the USB switch 7 to open so that the first state becomes the second state, which indicates the state before the firmware was updated.

[0025] The third input / output unit 52 is a GPIO (General-purpose input / output) that is electrically connected to the reset unit 43 of the microcomputer 4. The third input / output unit 52 inputs a signal to the reset unit 43 to change the upper bits to a reset state and to release the reset after a predetermined time has elapsed. The reset state is a change from a high-level signal to a low-level signal.

[0026] The fourth input / output unit 53 is a GPIO that is electrically connected to the one-shot IC 6. Before resetting the microcomputer 4, the fourth input / output unit 53 inputs a signal to the one-shot IC 6 to turn on the switch.

[0027] The one-shot IC6 is electrically connected to the bootstrap circuit 41. The one-shot IC6 is electrically connected to the fourth input / output unit 53. The one-shot IC6 is an example of a second circuit. When a signal indicating that a switch is turned ON is input from the fourth input / output unit 53, the one-shot IC6 inputs a signal to the bootstrap circuit 41 to change the setting from the first boot loader to the second boot loader.

[0028] For example, the signal for changing the setting is a signal that causes the one-shot IC 6 to output a high-level signal for only a predetermined time to the bootstrap circuit 41. In other words, the one-shot IC 6 outputs a signal of a predetermined level to the bootstrap circuit 41 for a predetermined time in response to an input signal input from the host controller 5.

[0029] The USB switch 7 enables communication between the microcomputer 4 and the host controller 5. Specifically, the USB switch 7 is a device that controls the disconnection and connection of a communication line between the microcomputer 4 and the host controller 5. The USB switch 7 is an example of a connection unit. The USB switch 7 has an interface that performs serial communication with the first input / output unit 42 of the microcomputer 4. The USB switch 7 also has an interface that performs serial communication with the second input / output unit 51.

[0030] 4 is a sequence diagram showing an example of the flow of processing executed by the information processing device 2 according to the embodiment. Using FIG. 4, a process in which the host controller 5 of the information processing device 2 updates firmware for the microcomputer 4 will be described. It is assumed that the microcomputer 4 has previously acquired the latest firmware from the external storage device 3 and stored the acquired latest firmware in the auxiliary storage device 24.

[0031] In step S81, the host controller 5 outputs a DFU transition command to the first input / output unit 42 of the microcomputer 4 via the second input / output unit 51. In step S82, the host controller 5 inputs a signal to the one-shot IC 6 via the fourth input / output unit 53 to turn on the switch.

[0032] In step S83, when the one-shot IC 6 is switched on by the host controller 5, it outputs a high-level signal for a predetermined time to the bootstrap circuit 41. In step S84, the bootstrap circuit 41 of the microcomputer 4 changes its setting from the first boot loader to the second boot loader based on the signal input from the one-shot IC 6.

[0033] In step S85, the host controller 5 controls the first input / output unit 42 of the microcomputer 4 via the second input / output unit 51 to perform a soft reset of the microcomputer 4. In step S86, the microcomputer 4 performs a soft reset in accordance with the control of the host controller 5. This allows the microcomputer 4 to be initialized as a DFU device. In step S87, the host controller 5 controls the USB switch 7 to open the USB port connected to the host controller 5.

[0034] In step S88, the USB switch 7 inverts the select pin of the USB port connected to the first input / output unit 42 of the microcomputer 4, thereby controlling the microcomputer 4 to switch the connected USB port to an unconnected USB port. This allows the microcomputer 4 to initialize the connection with the USB switch 7. In step S89, the USB switch 7 controls the microcomputer 4 to connect to the USB port connected to the host controller 5. This allows the microcomputer 4 to maintain a state in which it is not USB-connected to the host controller 5.

[0035] In step S90, the microcomputer 4, whose first input / output unit 42 is now in a disconnected state, loads the second boot loader from the bootstrap circuit 41 and starts up. Also, because the microcomputer 4 has been initialized as a DFU device, it starts up by booting. In step S91, because the microcomputer 4 has started up as a DFU device, it reinitializes the first input / output unit 42 and connects it to the USB switch 7. In step S92, the microcomputer 4 updates the firmware stored in the microcomputer 4.

[0036] In step S93, after updating the firmware of the microcomputer 4, the host controller 5 hits the reset pin of the reset unit 43 of the microcomputer 4 to reset the microcomputer 4 in order to initialize the DFU device and return it to a normal device. Specifically, the host controller 5 changes the reset unit 43 of the microcomputer 4 to a reset state starting with the upper bits, and releases the reset after a predetermined time has passed. The reset state is a change from a high-level signal to a low-level signal. This causes the microcomputer 4 to transition from a DFU device state to an initialization state.

[0037] In step S94, the microcomputer 4 is reset by performing a hard reset, which allows the microcomputer 4 to be initialized as a normal device. In step S95, the host controller 5 controls the USB switch 7 to open the USB port connected to the host controller 5.

[0038] In step S96, the USB switch 7 inverts the select pin of the unconnected USB port, and performs control to switch the unconnected USB port to a USB port connected to the first input / output unit 42 of the microcomputer 4. In step S97, the USB switch 7 performs control to connect to the USB port connected to the host controller 5.

[0039] In step S98, the microcomputer 4, whose first input / output unit 42 is now connectable to the USB switch 7, loads the first boot loader from the bootstrap circuit 41 and starts up. Since the microcomputer 4 has been initialized as a normal device, it starts up by booting. In step S99, since the microcomputer 4 has started up as a normal device, it initializes the first input / output unit 42 again and connects to the USB switch 7.

[0040] As described above, the information processing device 2 of this embodiment includes a first circuit that stores a first boot loader that starts the microcomputer 4 and a second boot loader that starts the microcomputer 4 in a state where the firmware of the microcomputer 4 can be updated, and a control unit that controls updating the firmware of the microcomputer 4 based on the second boot loader after resetting the microcomputer 4.

[0041] As a result, for example, when updating firmware, the information processing device 2 can update the firmware of the microcomputer 4 without restarting the OS. Therefore, the information processing device 2 can efficiently update firmware without stopping operation.

[0042] Although an embodiment of the present invention has been described above, this embodiment is presented as an example and is not intended to limit the scope of the invention. This novel embodiment can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. This embodiment and its modifications are included within the scope and spirit of the invention, and are also included in the invention and its equivalents as defined in the claims.

[0043] (First Modification) In the above embodiment, the host controller 5 of the information processing device 2 inputs a signal to the one-shot IC 6 to turn on the switch, but this is not limiting. For example, the microcomputer 4 of the information processing device 2 may input a signal to the one-shot IC 6 to turn on the switch.

[0044] Fig. 5 is a block diagram showing an example of the configuration of an information processing device 2 according to the first modification. As shown in Fig. 5, the microcomputer 4 has a bootstrap circuit 41, a first input / output unit 42, a reset unit 43, and a fifth input / output unit 44. The host controller 5 has a second input / output unit 51 and a third input / output unit 52.

[0045] The fifth input / output unit 44 is a GPIO that is electrically connected to the one-shot IC 6. The fifth input / output unit 44 inputs a signal to the one-shot IC 6 to turn on the switch.

[0046] The one-shot IC6 is electrically connected to the fifth input / output unit 44. When a signal conveying that a switch is turned ON is input from the fourth input / output unit 53, the one-shot IC6 inputs a signal to the bootstrap circuit 41 to change the setting from the first boot loader to the second boot loader.

[0047] Fig. 6 is a sequence diagram showing an example of the flow of processing executed by the information processing device 2 according to the first modified example. In Fig. 6, the description of the same processing content as in Fig. 4 will be omitted. Fig. 6 shows a state in which step S82 shown in Fig. 4 has been deleted and replaced with a new step S101 according to the first modified example.

[0048] In step S101, the microcomputer 4 inputs a signal to the one-shot IC 6 via the fifth input / output unit 44 to turn on the switch.

[0049] As a result, the information processing device 2 according to the first modification can input a signal to the one-shot IC 6 to turn on the switch in association with the timing of the microcomputer 4 transitioning to DFU.

[0050] (Second Modification) In the above-described embodiment, the host controller 5 of the information processing device 2 controls the USB switch 7 to open a USB port, but the present invention is not limited to this. For example, the microcomputer 4 of the information processing device 2 may control the USB switch 7 to open a USB port connected to the host controller 5.

[0051] 7 is a block diagram showing an example of the configuration of an information processing device 2 according to the second modification. As shown in FIG. 5, the microcomputer 4 has a bootstrap circuit 41, a first input / output unit 42, a reset unit 43, and a sixth input / output unit 45. The host controller 5 has a second input / output unit 51, a third input / output unit 52, and a fourth input / output unit 53.

[0052] The sixth input / output unit 45 is a GPIO that is electrically connected to the USB switch 7. When the microcomputer 4 is reset, the sixth input / output unit 45 inputs a signal to the USB switch 7 to turn the switch ON.

[0053] When a signal conveying that the switch is turned ON is input from the sixth input / output unit 45, the USB switch 7 performs control so as to open the USB port connected to the host controller 5.

[0054] Fig. 8 is a sequence diagram showing an example of the flow of processing executed by the information processing device 2 according to the second modified example. In Fig. 8, the description of the same processing content as in Fig. 4 will be omitted. Fig. 8 shows a state in which step S87 and step S95 shown in Fig. 4 have been deleted and replaced with new steps S102 and S103 according to the second modified example.

[0055] In steps S102 and S103, the microcomputer 4 inputs a signal to the USB switch 7 via the sixth input / output unit 45 to turn the switch ON so as to open the USB port connected to the host controller 5.

[0056] As a result, the information processing device 2 according to the second modification can input a signal to the USB switch 7 to turn the switch ON in association with the resetting of the microcomputer 4.

[0057] The program executed by the information processing device 2 of the embodiment is provided as a file in an installable or executable format recorded on a computer-readable recording medium such as a CD-ROM, a flexible disk (FD), a CD-R, or a DVD (Digital Versatile Disk).

[0058] The program executed by the information processing device 2 of the embodiment may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. The program executed by the information processing device 2 of the embodiment may be provided or distributed via a network such as the Internet. [Explanation of symbols]

[0059] 1. Information Processing Systems 2. Information processing equipment 3 External storage device 4 Microcomputer 5 Host Controller 6 One-shot IC 7. USB Switch 41 Bootstrap Circuit 42 1st input / output section 43 Reset section 44 5th input / output section 45 6th input / output section 51 2nd input / output section 52 3rd input / output section 53 4th input / output section [Prior art documents] [Patent documents]

[0060] [Patent Document 1] Patent No. 7267692

Claims

1. a first circuit that stores a first boot loader that starts up a microcomputer and a second boot loader that starts up the microcomputer in a state where firmware of the microcomputer can be updated; a control unit that performs control to update firmware of the microcomputer based on the second boot loader after resetting the microcomputer; An information processing device comprising:

2. a second circuit electrically connected to the first circuit and outputting a signal of a predetermined level to the first circuit for a predetermined time in response to an input signal input from the control unit; the control unit inputs an input signal to the second circuit before resetting the microcomputer; the first circuit changes from the first boot loader to the second boot loader based on the signal input from the second circuit; The information processing device according to claim 1 .

3. a connection unit that enables communication between the microcomputer and the control unit, the control unit performs control to open the connection unit after resetting the microcomputer. The information processing device according to claim 2 .

4. the control unit performs control to open the connection unit so that the microcomputer is in a first state indicating a state in which the firmware is to be updated after resetting the microcomputer; The information processing device according to claim 3 .

5. the control unit updates the firmware of the microcomputer, resets the microcomputer, and then controls to open the connection unit so that the first state changes to a second state indicating a state before the firmware was updated. The information processing device according to claim 4 .

6. The first circuit is a bootstrap circuit, and the second circuit is a one-shot IC. The information processing device according to claim 2 .

7. An information processing method performed by an information processing device including a first circuit and a control unit, the first circuit stores a first boot loader that starts up a microcomputer and a second boot loader that starts up the microcomputer in a state where firmware of the microcomputer can be updated; the control unit resets the microcomputer, and then controls updating of firmware of the microcomputer based on the second boot loader. Information processing methods.

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