Method of manufacturing semiconductor device and semiconductor device

Abstract

To provide a method of manufacturing a semiconductor device capable of suppressing a charge trap in a trench bottom part, and the semiconductor device.SOLUTION: A method of manufacturing a semiconductor device includes steps of: forming a trench and a mesa part in a semiconductor layer; forming a field plate electrode inside of the trench; forming a silicon nitride film on the field plate electrode, on the mesa part and on an upper side wall of the mesa part; forming a silicon oxide film in the trench and on the mesa part by a chemical vapor deposition method after the silicon nitride film is formed; removing the silicon oxide film on the mesa part by a chemical mechanical polishing method; removing the silicon nitride film on the upper side wall of the mesa part and the silicon nitride film on the mesa part after the silicon oxide film on the mesa part is removed; and forming a gate electrode on the silicon oxide film in the trench after the silicon nitride film is removed.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In a power device, there is a configuration in which a field plate electrode is provided in a trench, and a gate electrode is provided on the field plate electrode via an insulating layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7293159 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device and a method for manufacturing the same that can suppress charge traps at the bottom of a trench. [Means for solving the problem]

[0005] According to an embodiment, a method for manufacturing a semiconductor device includes the steps of: forming a trench and a mesa portion adjacent to the trench in a semiconductor layer; forming a field plate electrode in the trench via a field insulating film; forming a silicon nitride film on the field plate electrode, on the mesa portion, and on an upper sidewall of the mesa portion above the field plate electrode and adjacent to the trench; after forming the silicon nitride film, forming a silicon oxide film in the trench and on the mesa portion by chemical vapor deposition; removing the silicon oxide film on the mesa portion by chemical mechanical polishing to expose the silicon nitride film on the mesa portion; [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 2] 5(a) and 5(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 3] 5(a) and 5(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 5(a) and 5(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 5(a) and 5(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 5(a) and 5(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 5(a) and 5(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Note that the same reference numerals are used for the same components in each drawing. In the drawings shown below, directions are indicated by the X-axis, Y-axis, and Z-axis. The direction along the X-axis is the first direction X. The direction along the Y-axis is the second direction Y, which is perpendicular to the first direction X. The direction along the Z-axis is the third direction Z, which is perpendicular to the first direction X and the second direction Y. In this specification, the thickness in a certain direction refers to the maximum thickness in that certain direction.

[0008] As shown in FIG. 1 , the semiconductor device 1 of the embodiment includes a first electrode 31, a second electrode 32, and a semiconductor layer 10 provided between the first electrode 31 and the second electrode 32 in a third direction Z. The semiconductor device 1 has, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. The first electrode 31 is a drain electrode of the MOSFET, and the second electrode 32 is a source electrode of the MOSFET. For example, a positive potential is applied to the first electrode 31, and 0 V is applied to the second electrode 32. In an on-state in which the gate voltage of a gate electrode 40 (described later) is made higher than a threshold voltage, a current flows through the semiconductor layer 10 in a vertical direction (third direction Z) between the first electrode 31 and the second electrode 32. In the third direction Z, the direction from the first electrode 31 to the second electrode 32 is defined as up or upward, and the direction from the second electrode 32 to the first electrode 31 is defined as down or downward.

[0009] The semiconductor layer 10 is, for example, a silicon layer. In this specification, the first conductivity type of the semiconductor layer 10 is defined as n-type, and the second conductivity type is defined as p-type. Note that the first conductivity type may be p-type, and the second conductivity type may be n-type.

[0010] The semiconductor layer 10 has an n-type first semiconductor layer 11, a p-type second semiconductor layer 12 provided on the first semiconductor layer 11, and an n-type third semiconductor layer 13 provided on the second semiconductor layer 12. The n-type impurity concentration of the third semiconductor layer 13 is higher than the n-type impurity concentration of the first semiconductor layer 11. The semiconductor layer 10 also has an n-type fourth semiconductor layer 14 provided between the first electrode 31 and the first semiconductor layer 11. The fourth semiconductor layer 14 is in contact with the first electrode 31 and is electrically connected to the first electrode 31.

[0011] The semiconductor device 1 may be an IGBT (Insulated Gate Bipolar Transistor) having a p-type fourth semiconductor layer 14 provided between the first electrode 31 and the first semiconductor layer 11. In the IGBT, an n-type buffer layer having a higher n-type impurity concentration than the first semiconductor layer 11 may be provided between the n-type first semiconductor layer 11 and the p-type fourth semiconductor layer 14.

[0012] The semiconductor layer 10 has a plurality of mesas 10A arranged in a first direction X. The mesas 10A extend, for example, in a second direction Y. The mesa 10A has a part of a first semiconductor layer 11, a second semiconductor layer 12 provided on a part of the first semiconductor layer 11, and a third semiconductor layer 13 provided on the second semiconductor layer 12.

[0013] The semiconductor device 1 has a plurality of trench structures 20 arranged in a first direction X. The trench structures 20 extend, for example, in a second direction Y. The trench structures 20 are adjacent to the mesa portion 10A in the first direction X.

[0014] The trench structure 20 has a gate electrode 40, a gate insulating film 80, a field plate electrode 50, a first insulating layer 60, and a field insulating film .

[0015] A side surface of the gate electrode 40 faces the second semiconductor layer 12 in the first direction X via the gate insulating film 80. The gate electrode 40 extends in the second direction Y, and, for example, an end of the gate electrode 40 in the second direction Y is connected to a gate wiring (not shown). In an on-state in which the gate voltage of the gate electrode 40 is made higher than the threshold voltage, an n-channel (inversion layer) is formed in a region of the second semiconductor layer 12 facing the gate electrode 40.

[0016] The gate insulating film 80 is located between the gate electrode 40 and the second semiconductor layer 12 in the first direction X. The gate insulating film 80 is, for example, a silicon oxide film.

[0017] The field plate electrode 50 is located below the gate electrode 40 in the third direction Z. The field plate electrode 50 extends in the second direction Y, and, for example, an end of the field plate electrode 50 in the second direction Y is connected to the second electrode 32. The field plate electrode 50 can reduce the longitudinal electric field (electric field in the third direction Z) generated in the semiconductor layer 10, thereby improving the breakdown voltage of the semiconductor device 1. The field plate electrode 50 may be electrically connected to the gate electrode 40.

[0018] The first insulating layer 60 is provided between the field plate electrode 50 and the gate electrode 40 in the third direction Z. The first insulating layer 60 has a first silicon oxide film 61, a silicon nitride film 62, and a second silicon oxide film 63.

[0019] The first silicon oxide film 61 is provided between the field plate electrode 50 and the silicon nitride film 62 in the third direction Z. The silicon nitride film 62 is provided between the first silicon oxide film 61 and the second silicon oxide film 63 in the third direction Z. The second silicon oxide film 63 is provided between the silicon nitride film 62 and the gate electrode 40 in the third direction Z. The thickness in the third direction Z of the silicon nitride film 62 located between the first silicon oxide film 61 and the second silicon oxide film 63 is thinner than the thickness in the third direction Z of the second silicon oxide film 63. The thickness in the third direction Z of the silicon nitride film 62 may be thinner than the thickness in the third direction Z of the first silicon oxide film 61.

[0020] A third silicon oxide film 81 is provided between the first insulating layer 60 and the mesa portion 10A in the first direction X. A silicon nitride film 62 is provided between the second silicon oxide film 63 and the third silicon oxide film 81 in the first direction X. The third silicon oxide film 81 is provided between the silicon nitride film 62 and the mesa portion 10A in the first direction X.

[0021] The field insulating film 70 is provided between the field plate electrode 50 and the first semiconductor layer 11 in the first direction X and the third direction Z. The field insulating film 70 is a silicon oxide film and does not contain silicon nitride. Since the bottom of the trench structure 20, where the electric field strength is likely to be high, does not contain silicon nitride, charge traps at the bottom of the trench structure 20 can be suppressed. This makes it possible to prevent deterioration of characteristics such as the breakdown voltage of the semiconductor device 1 and also to prevent deterioration of reliability over time.

[0022] In regions adjacent to both side surfaces of the first silicon oxide film 61 in the first direction X, the silicon nitride film 62 is located between the field insulating film 70 and the second silicon oxide film 63 in the third direction Z. The silicon nitride film 62 also covers both side surfaces of the first silicon oxide film 61 in the first direction X. The silicon nitride film 62 has a concave portion outside the portion on the first silicon oxide film 61 (outside in the first direction X).

[0023] The second electrode 32 is provided on the semiconductor layer 10. The second electrode 32 is in contact with the third semiconductor layer 13 by, for example, a trench contact structure. A portion (contact portion) 32A of the second electrode 32 penetrates the third semiconductor layer 13 and reaches the second semiconductor layer 12. The third semiconductor layer 13 and the second semiconductor layer 12 are in contact with the portion 32A of the second electrode 32 and are electrically connected to the second electrode 32. The p-type impurity concentration of the portion of the second semiconductor layer 12 in contact with the portion 32A of the second electrode 32 may be higher than the p-type impurity concentration of the portion of the second semiconductor layer 12 where a channel is formed. The second electrode 32 may be in contact with the upper surface of the third semiconductor layer 13.

[0024] A second insulating layer 90 is provided between the gate electrode 40 and the second electrode 32 in the third direction Z. The second insulating layer 90 mainly contains, for example, silicon oxide and may further contain, for example, boron or phosphorus.

[0025] Next, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to Figures 2(a) to 7(b). The method for manufacturing a semiconductor device according to an embodiment can include the steps described below.

[0026] As shown in FIG. 2(a), a plurality of trenches T aligned in a first direction X are formed in the semiconductor layer 10. For example, the plurality of trenches T are formed by a reactive ion etching (RIE) method. By forming the plurality of trenches T in the semiconductor layer 10, a mesa portion 10A is formed between the trenches T adjacent to each other in the first direction X.

[0027] After forming the trench T and the mesa portion 10A in the semiconductor layer 10, a field insulating film 70 is formed in the trench T as shown in FIG. 2(b). For example, a silicon oxide film can be formed as the field insulating film 70 by chemical vapor deposition (CVD). The field insulating film 70 may also be formed by thermal oxidation. The field insulating film 70 is formed continuously on the inner walls (sidewalls and bottom surface) of the trench T and the upper surface of the mesa portion 10A.

[0028] After the field insulating film 70 is formed, an electrode material that will become the field plate electrode 50 is buried in the trench T via the field insulating film 70. For example, the electrode material is buried in the trench T by a CVD method. The electrode material is also deposited on the field insulating film 70 formed on the mesa portion 10A. The upper surface of the electrode material in the trench T is recessed by isotropic or anisotropic etching. The electrode material formed on the mesa portion 10A is also removed. As a result, the electrode material remains on the bottom side of the trench T as the field plate electrode 50, as shown in FIG. 3(a).

[0029] The field plate electrode 50 can be made of, for example, polycrystalline silicon or amorphous silicon doped with phosphorus or boron. For example, the polycrystalline silicon can be doped with phosphorus or boron when it is formed in the trench T. Alternatively, after the polycrystalline silicon is formed in the trench T, phosphorus or boron can be implanted into the polycrystalline silicon by ion implantation. Alternatively, phosphorus can be diffused into the polycrystalline silicon by high-temperature heat treatment using POCl3.

[0030] After the field plate electrode 50 is formed, the upper portion of the field plate electrode 50 is oxidized as needed. For example, the upper portion of the field plate electrode 50 is oxidized by thermal oxidation. However, this step does not necessarily have to be performed.

[0031] After the field plate electrode 50 is formed, the field insulating film 70 formed on the upper sidewall 10B of the mesa portion 10A is removed. The upper sidewall 10B of the mesa portion 10A is adjacent to the upper portion of the trench T, which is located above the field plate electrode 50. For example, the field insulating film 70 formed on the upper sidewall 10B of the mesa portion 10A is removed by wet etching or isotropic dry etching. As shown in FIG. 4(a), the field insulating film 70 on the mesa portion 10A and on the field plate electrode 50 is also removed.

[0032] As shown in FIG. 4(a), the field insulating film 70 in contact with the side surface and bottom end of the field plate electrode 50 remains in the trench T.

[0033] After the step shown in FIG. 3(a), the field insulating film 70 on the upper sidewall 10B and the field insulating film 70 on the mesa portion 10A may be removed without oxidizing the upper portion of the field plate electrode 50.

[0034] If the upper portion of the field plate electrode 50 is oxidized and then the field insulating film 70 on the upper sidewall 10B and the field insulating film 70 on the mesa portion 10A are removed, the depth of the recess 110 can be reduced.

[0035] After removing the field insulating film 70 from the upper sidewall 10B, the mesa portion 10A, and the field plate electrode 50, the upper sidewall 10B is thermally oxidized to form a third silicon oxide film 81 on the upper sidewall 10B, as shown in FIG. 4(b). The upper portion of the field plate electrode 50 is also thermally oxidized to form a first silicon oxide film 61 on the field plate electrode 50. The upper surface of the mesa portion 10A is also thermally oxidized to form a third silicon oxide film 81 on the mesa portion 10A.

[0036] 5(a), a silicon nitride film 62 is formed by, for example, a CVD method. The silicon nitride film 62 is continuously formed on the upper surface of the first silicon oxide film 61 on the field plate electrode 50, on the third silicon oxide film 81 on the mesa portion 10A, on the third silicon oxide film 81 on the upper sidewall 10B, and on the inner surface of the recess 110 including both side surfaces of the first silicon oxide film 61 in the first direction X.

[0037] After the silicon nitride film 62 is formed, a second silicon oxide film 63 is formed in the trench T and on the mesa portion 10A by chemical vapor deposition, as shown in FIG. 5(b). For example, the second silicon oxide film 63 is formed by HDP-CVD (High Density Plasma Chemical Vapor Deposition) using high density plasma.

[0038] The second silicon oxide film 63 is formed on the silicon nitride film 62 on the first silicon oxide film 61, in the recess 110, on the silicon nitride film 62 on the upper sidewall 10B, and on the silicon nitride film 62 on the mesa portion 10A.

[0039] By forming the second silicon oxide film 63 by chemical vapor deposition, the film thickness (film thickness in the first direction X) of the second silicon oxide film 63 formed on the upper sidewall 10B of the mesa portion 10A can be made thinner than the film thickness (film thickness in the third direction Z) of the second silicon oxide film 63 formed on the field plate electrode 50 and the film thickness (film thickness in the third direction Z) of the second silicon oxide film 63 formed on the upper surface of the mesa portion 10A. That is, in the trench T, the film thickness of the second silicon oxide film 63 formed on the sidewall can be made thicker while suppressing the film thickness of the second silicon oxide film 63 formed on the field plate electrode 50.

[0040] During the formation of the second silicon oxide film 63, the portion of the second silicon oxide film 63 deposited on the mesa portion 10A near the opening of the trench T is susceptible to etching, and the film thickness (film thickness in the third direction Z) of the second silicon oxide film 63 deposited on the mesa portion 10A is thickest near the center of the mesa portion 10A in the first direction X.

[0041] After the second silicon oxide film 63 is formed, the second silicon oxide film 63 on the mesa portion 10A is removed by chemical mechanical polishing (CMP). As a result, the silicon nitride film 62 on the mesa portion 10A is exposed, as shown in FIG. 6(a). The silicon nitride film 62 formed on the mesa portion 10A functions as a stopper when the second silicon oxide film 63 on the mesa portion 10A is removed by CMP. When the silicon nitride film 62 on the mesa portion 10A is exposed, the CMP of the second silicon oxide film 63 is stopped. Since the silicon nitride film 62, which serves as a CMP stopper, is not formed at the bottom of the trench T, charge traps at the bottom of the trench T can be suppressed.

[0042] After the second silicon oxide film 63 on the mesa portion 10A is removed by CMP, the second silicon oxide film 63 remaining on the silicon nitride film 62 on the upper sidewall 10B is removed by, for example, wet etching or isotropic dry etching. As a result, the silicon nitride film 62 on the upper sidewall 10B is exposed, as shown in FIG. 6( a). By forming the second silicon oxide film 63 so that the film thickness of the second silicon oxide film 63 on the field plate electrode 50 is thicker than the film thickness of the second silicon oxide film 63 on the upper sidewall 10B, the second silicon oxide film 63 on the upper sidewall 10B can be removed while leaving the second silicon oxide film 63 on the field plate electrode 50.

[0043] After removing the second silicon oxide film 63 on the mesa portion 10A and the second silicon oxide film 63 on the upper sidewall 10B, the silicon nitride film 62 exposed on the mesa portion 10A and the silicon nitride film 62 exposed on the upper sidewall 10B are removed. The silicon nitride film 62 is removed by a method in which the etching rate of the silicon nitride film 62 is higher than the etching rate of the silicon oxide film. For example, the silicon nitride film 62 can be removed by wet etching using hot phosphoric acid or isotropic dry etching.

[0044] The first silicon oxide film 61 on the field plate electrode 50, the silicon nitride film 62 on the first silicon oxide film 61, the second silicon oxide film 63 on the silicon nitride film 62, the silicon nitride film 62 in the recess 110, and the second silicon oxide film 63 in the recess 110 remain.

[0045] By removing the silicon nitride film 62 on the mesa portion 10A and the silicon nitride film 62 on the upper sidewall 10B, the third silicon oxide film 81 on the mesa portion 10A and the third silicon oxide film 81 on the upper sidewall 10B are exposed, as shown in FIG. 6(b).

[0046] For example, an additional silicon oxide film is formed on the third silicon oxide film 81 on the upper sidewall 10B by the CVD method, to form a gate insulating film 80 on the upper sidewall 10B as shown in FIG. 7(a). In this case, the gate insulating film 80 includes the third silicon oxide film 81 formed by the thermal oxidation method and a silicon oxide film formed by the CVD method. The silicon oxide film formed by the CVD method is also formed on the second silicon oxide film 63.

[0047] Alternatively, the third silicon oxide film 81 remaining on the upper sidewall 10B may be used as it is as the gate insulating film 80. In this case, the gate insulating film 80 is a single layer film of the third silicon oxide film 81.

[0048] Alternatively, the third silicon oxide film 81 remaining on the upper sidewall 10B may be removed by etching, and then the gate insulating film 80 may be formed on the upper sidewall 10B by thermal oxidation.

[0049] After the gate insulating film 80 is formed, the gate electrode 40 is formed on the second silicon oxide film 63 in the trench T, as shown in FIG. 7(b).

[0050] For example, a gate electrode material is buried in the trench T by a CVD method. The gate electrode material is also deposited on the mesa portion 10A. The upper surface of the gate electrode material in the trench T is recessed by isotropic or anisotropic etching. The gate electrode material formed on the mesa portion 10A is also removed. As a result, the gate electrode 40 remains on the second silicon oxide film 63 in the trench T, as shown in FIG. 7(b).

[0051] The gate electrode 40 may be made of, for example, polycrystalline silicon or amorphous silicon doped with phosphorus or boron. For example, the polycrystalline silicon may be doped with phosphorus or boron when it is formed in the trench T. Alternatively, after the polycrystalline silicon is formed in the trench T, phosphorus or boron may be implanted into the polycrystalline silicon by ion implantation. Alternatively, phosphorus may be diffused into the polycrystalline silicon by high-temperature heat treatment using POCl3. The gate electrode 40 may also be made of a metal.

[0052] After the gate electrode 40 is formed, a step of forming a second semiconductor layer 12 and a third semiconductor layer 13 in the semiconductor layer 10 by, for example, ion implantation is performed. Then, the formation of a second insulating layer 90 and the formation of a second electrode 32 are continued.

[0053] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0054] 1...semiconductor device, 10...semiconductor layer, 10A...mesa portion, 10B...upper sidewall, 11...first semiconductor layer, 12...second semiconductor layer, 13...third semiconductor layer, 14...fourth semiconductor layer, 20...trench structure portion, 31...first electrode, 32...second electrode, 40...gate electrode, 50...field plate electrode, 60...first insulating layer, 61...first silicon oxide film, 62...silicon nitride film, 63...second silicon oxide film, 70...field insulating film, 80...gate insulating film, 81...third silicon oxide film, 90...second insulating layer, 110...recess, T...trench

Claims

1. forming a trench and a mesa portion adjacent to the trench in a semiconductor layer; forming a field plate electrode in the trench via a field insulating film; forming a silicon nitride film on the field plate electrode, on the mesa portion, and on an upper sidewall of the mesa portion adjacent to the trench above the field plate electrode; forming a silicon oxide film in the trench and on the mesa portion by chemical vapor deposition after forming the silicon nitride film; removing the silicon oxide film on the mesa portion by chemical mechanical polishing to expose the silicon nitride film on the mesa portion; removing the silicon oxide film on the mesa portion, and then removing the silicon nitride film on the upper sidewall of the mesa portion and the silicon nitride film on the mesa portion; forming a gate electrode on the silicon oxide film in the trench after removing the silicon nitride film; A method for manufacturing a semiconductor device, comprising:

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the silicon oxide film, a thickness of the silicon oxide film formed on the upper sidewall of the mesa portion is thinner than a thickness of the silicon oxide film formed on the field plate electrode.

3. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of oxidizing an upper portion of said field plate electrode before forming said silicon nitride film.

4. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of removing said field insulating film formed on said upper sidewall of said mesa portion before forming said silicon nitride film.

5. 5. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of oxidizing said upper sidewall after removing said field insulating film on said upper sidewall and before forming said silicon nitride film.

6. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of removing the silicon oxide film formed on the silicon nitride film on the upper sidewall before removing the silicon nitride film on the upper sidewall.

7. a mesa portion including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer and having a higher first conductivity type impurity concentration than the first semiconductor layer; a trench structure adjacent to the mesa portion, the trench structure including: a gate electrode; a gate insulating film provided between the gate electrode and the second semiconductor layer; a field plate electrode located below the gate electrode; an insulating layer provided between the field plate electrode and the gate electrode; and a field insulating film provided between the field plate electrode and the first semiconductor layer; Equipped with the insulating layer includes a first silicon oxide film, a silicon nitride film, and a second silicon oxide film; the first silicon oxide film is provided between the field plate electrode and the silicon nitride film, the silicon nitride film is provided between the first silicon oxide film and the second silicon oxide film, the second silicon oxide film is provided between the silicon nitride film and the gate electrode, the thickness of the silicon nitride film is thinner than the thickness of the second silicon oxide film; The semiconductor device, wherein the field insulating film does not contain silicon nitride.

8. 8. The semiconductor device according to claim 7, wherein said silicon nitride film has a thickness smaller than that of said first silicon oxide film.

9. 9. The semiconductor device according to claim 7, wherein said silicon nitride film has a recessed portion outside a portion on said first silicon oxide film.

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