Display substrate and display device

Abstract

To ensure on-state current of a thin film transistor included in a demultiplexer circuit.SOLUTION: A display substrate comprises: a plurality of gate wires 21; a plurality of source wires 22; a plurality of pixels TFT 23; a plurality of pixel electrodes 24; a driver 16; and a plurality of switches TFT 50 composing a demultiplexer circuit 19 distributing a pixel signal supplied from the driver 16 to the plurality of source wires 22. The pixel TFT 23 includes a gate electrode 23A connected to the gate wires 21, and a semiconductor part 23D arranged opposite the gate electrode 23A across the first insulator film 61. The switch TFT 50 includes: a gate electrode 50A having gate length L2 smaller than gate length L1 of the gate electrode 23A; a semiconductor part 50D arranged opposite the gate electrode 50A across the first insulator film 61; and a gate electrode 50E arranged opposite the semiconductor part 50D across a second insulator film 62.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a display substrate and a display device. [Background technology]

[0002] A conventionally known display substrate is that described in Patent Document 1. The display substrate described in Patent Document 1 includes a plurality of pixel electrodes, a signal supply unit (display signal drive circuit) that supplies image signals (display signals) to the plurality of pixel electrodes, and a plurality of source wirings for transmitting the image signals from the signal supply unit to each of the plurality of pixel electrodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-149410 Summary of the Invention [Problem to be solved by the invention]

[0004] Also, a display substrate is known that includes a demultiplexer circuit composed of multiple thin film transistors interposed between multiple source lines and a signal supply. By using the demultiplexer circuit to distribute image signals supplied from the signal supply to multiple source lines, the total number of lines connecting the signal supply and the demultiplexer circuit can be reduced compared to the total number of source lines. This facilitates wiring arrangement on the display substrate. However, when distributing image signals to multiple source lines, time-division control is used, which requires that charging and discharging of each pixel electrode be completed in a shorter time. Therefore, a higher positive bias must be applied to the thin film transistors that make up the demultiplexer circuit. This increases the threshold voltage of the thin film transistor (positive shift) and reduces the on-current obtained at a specified operating potential. The increase in the threshold voltage of the thin film transistor is thought to be due to electrons being trapped in a potential level present inside the semiconductor portion of the thin film transistor, weakening the positive electric field from the gate electrode.

[0005] The technology disclosed in this specification was developed based on the above circumstances, and aims to ensure an on-current of the thin film transistors that constitute the demultiplexer circuit. [Means for solving the problem]

[0006] As a means for solving the above-mentioned problems, a display substrate disclosed in this specification includes a plurality of first wirings extending in a first direction, a plurality of second wirings extending in a second direction intersecting the first direction, a plurality of first thin film transistors connected to any of the plurality of first wirings and any of the plurality of second wirings, a plurality of pixel electrodes arranged in a matrix in the first direction and the second direction and connected to the plurality of first thin film transistors, a signal supply unit that supplies image signals to the plurality of second wirings, and a demultiplexer that distributes the image signals supplied from the signal supply unit to the plurality of second wirings. and a plurality of second thin film transistors that constitute a circuit, wherein the first thin film transistor comprises a first gate electrode connected to the first wiring and a first semiconductor portion arranged opposite the first gate electrode with a first insulating film sandwiched therebetween, and the second thin film transistor comprises a second gate electrode having a gate length smaller than that of the first gate electrode, a second semiconductor portion arranged opposite the second gate electrode with the first insulating film sandwiched therebetween, and a third gate electrode arranged on the opposite side of the second gate electrode to the second semiconductor portion and arranged opposite the second semiconductor portion with a second insulating film sandwiched therebetween.

[0007] The semiconductor device may further include a transparent conductive film disposed on the same side of the second insulating film as the third gate electrode, and the third gate electrode may be made of the same material as the transparent conductive film.

[0008] The device may also include a position detection electrode made of a transparent conductive film and forming a capacitance with a position input element that performs position input, and a position detection wiring connected to the position detection electrode and transmitting a position detection signal, the position detection wiring being arranged on the same side of the second insulating film as the third gate electrode and being made of the same material as the third gate electrode.

[0009] The device may also include a position detection electrode made of a transparent conductive film and forming a capacitance with a position input element that performs position input, a position detection wiring connected to the position detection electrode and transmitting a position detection signal, and a gate electrode wiring connected to the third gate electrode, wherein the third gate electrode is arranged on the same side of the second insulating film as the position detection electrode and is made of the same material as the position detection electrode, and the gate electrode wiring is arranged on the same side of the second insulating film as the position detection wiring and is made of the same material as the position detection wiring.

[0010] Furthermore, as means for solving the above-mentioned problems, a display device disclosed in this specification includes the display substrate and an opposing substrate disposed opposite to the display substrate. [Effects of the Invention]

[0011] According to the technology described in this specification, it is possible to ensure the on-current of the thin film transistors that make up the demultiplexer circuit. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view of a liquid crystal panel, a driver, and a flexible substrate according to Embodiment 1. [Figure 2] 1 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a first embodiment; [Figure 3] 1 is a cross-sectional view showing an array substrate according to a first embodiment; [Figure 4] 10 is a cross-sectional view showing an array substrate according to a second embodiment. [Figure 5] 10 is a cross-sectional view showing an array substrate according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] <Embodiment 1> A first embodiment of the present invention will be described with reference to Figures 1 to 3. In this embodiment, a liquid crystal panel 10 is used as an example of a display device, and an array substrate 12 included in the liquid crystal panel 10 is used as an example of a display substrate. Note that X, Y, and Z axes are shown in some of the drawings, and each axis direction is depicted as being in the direction shown in each drawing. Note that the liquid crystal panel 10 has, for example, a rectangular shape in a plan view, with one side direction coinciding with the X axis direction, the other side direction coinciding with the Y axis direction, and the plate thickness direction coinciding with the Z axis direction.

[0014] As shown in FIG. 1, the liquid crystal panel 10 is configured by sandwiching a liquid crystal layer 13 containing liquid crystal molecules, a substance whose optical properties change when an electric field is applied, between a pair of substrates 11 and 12 made of nearly transparent glass with excellent light transmissivity. A seal portion 14 is interposed between the outer peripheral edges of the pair of substrates 11 and 12 to seal the liquid crystal layer 13. The seal portion 14 is formed in a rectangular frame shape (endless ring) so as to surround the liquid crystal layer 13. A polarizing plate 15 is attached to the outer surface of each of the substrates 11 and 12. Of the pair of substrates 11 and 12, the one disposed on the front side is the counter substrate 11, and the one disposed on the back side is the array substrate 12 (display substrate, active matrix substrate). The counter substrate 11 is disposed opposite the array substrate 12. Both the counter substrate 11 and the array substrate 12 are formed by laminating various films on the inner surfaces of glass substrates 11GS and 12GS.

[0015] The dimension of the array substrate 12 in the Y-axis direction is larger than the dimension of the counter substrate 11. The counter substrate 11 is attached to the array substrate 12 so that one end in the Y-axis direction is aligned with the array substrate 12. Therefore, the other end in the Y-axis direction of the array substrate 12 is an exposed portion 12A that protrudes laterally from the counter substrate 11 and is exposed. A driver 16 (signal supply unit) and a flexible substrate 17 are mounted on the exposed portion 12A.

[0016] The liquid crystal panel 10 is capable of displaying images using illumination light emitted from a backlight device (illumination device), not shown. As shown in FIG. 2, the liquid crystal panel 10 has a display area AA where an image is displayed and a non-display area NAA where no image is displayed. The display area AA occupies most of the central portion of the screen, while the non-display area NAA is arranged in a frame-like outer periphery surrounding the display area AA. Note that in FIG. 2, the ratio of the non-display area NAA to the display area AA is exaggerated to show the details of the demultiplexer circuit 19 in the non-display area NAA.

[0017] The driver 16 is an LSI chip with an internal drive circuit. The driver 16 is mounted on the exposed portion 12A of the array substrate 12 using COG (Chip On Glass) technology. The driver 16 processes various signals transmitted by the flexible substrate 17. The driver 16 supplies various signals to various wirings provided on the array substrate 12, such as image signals to a plurality of source wirings 22. The flexible substrate 17 is configured by forming multiple wiring patterns on a base material made of an insulating and flexible synthetic resin material (e.g., polyimide resin). As shown in FIG. 1, one end of the flexible substrate 17 is connected to the exposed portion 12A of the array substrate 12. More specifically, the flexible substrate 17 is connected to the end of the exposed portion 12A on the opposite side of the driver 16 from the display area AA in the Y-axis direction. The other end of the flexible substrate 17 is connected to an external circuit board (e.g., a control board) (not shown).

[0018] 2, a gate drive circuit 18, a demultiplexer circuit 19, and a protection circuit 20 are provided in the non-display area NAA of the array substrate 12. The gate drive circuit 18 is provided to extend along one side (Y-axis direction) of the array substrate 12. The gate drive circuit 18 is for supplying scanning signals to gate wiring 21, which will be described later, and is provided monolithically on the glass substrate 12GS that constitutes the array substrate 12.

[0019] As shown in FIG. 2, the demultiplexer circuit 19 and the protection circuit 20 are disposed in the non-display area NAA at a position sandwiched between the display area AA and the driver 16 in the Y-axis direction. The demultiplexer circuit 19 and the protection circuit 20 are both provided to extend along the other side (X-axis direction) of the array substrate 12. The demultiplexer circuit 19 is located closer to the display area AA (farther from the driver 16) than the protection circuit 20 in the Y-axis direction. The demultiplexer circuit 19 has the function of distributing image signals supplied from the driver 16 to a plurality of source lines 22, which will be described later. The specific configuration of the demultiplexer circuit 19 will be described in detail later. The protection circuit 20 is located farther from the display area AA (closer to the driver 16) than the demultiplexer circuit 19 in the Y-axis direction. The protection circuit 20 has a function of protecting each component connected to the source main line 44 (the driver 16, the source line 22, the switch TFT 50 and the pixel TFT 23 of the demultiplexer circuit 19) from surges.

[0020] As shown in Fig. 2, gate lines 21 (first lines) and source lines 22 (second lines) that intersect with each other are provided on the inner surface of the display area AA of the array substrate 12. The gate lines 21 extend in the X-axis direction (first direction) across the display area AA, and multiple lines are arranged side by side at intervals in the Y-axis direction. The source lines 22 extend in the Y-axis direction (second direction intersecting the first direction) across the display area AA, and multiple lines are arranged side by side at intervals in the X-axis direction. On the inner surface of the display area AA of the array substrate 12, pixel TFTs 23 (first thin film transistors) and pixel electrodes 24 are provided in an area surrounded by the gate lines 21 and the source lines 22.

[0021] A plurality of pixel TFTs 23 and pixel electrodes 24 are provided in a matrix (rows and columns) in the X-axis direction and the Y-axis direction, respectively. Each of the pixel TFTs 23 is connected to one of the gate lines 21 and one of the source lines 22. Each of the pixel electrodes 24 is connected to a corresponding one of the pixel TFTs 23. The pixel TFT 23 includes a gate electrode 23A connected to the gate line 21, a source electrode 23B connected to the source line 22, a drain electrode 23C connected to the pixel electrode 24, and a semiconductor portion 23D connected to the source electrode 23B and the drain electrode 23C. The pixel TFT 23 is driven based on a scanning signal supplied to the gate line 21, and a potential based on an image signal (data signal) supplied to the source line 22 is charged in the pixel electrode 24.

[0022] Additionally, the inner surface of the display area AA of the counter substrate 11 is provided with three color filters (red (R), green (G), and blue (B)) that overlap each pixel electrode 24, as well as a light-shielding portion (black matrix) that separates adjacent color filters. In the liquid crystal panel 10, the R, G, and B color filters aligned along the X-axis and three pixel electrodes 24 facing each color filter constitute three-color pixels. The pixels are the display units in the display area AA, and are arranged in groups of multiple pixels at a predetermined pitch along the X-axis and Y-axis. As shown in FIG. 3, the array substrate 12 is also provided with a common electrode 25, made of the same transparent electrode material as the pixel electrodes 24 and overlapping the pixel electrodes 24 with a gap between them. In the liquid crystal panel 10, a predetermined electric field is applied to the liquid crystal layer 13 based on the potential difference generated between the common electrode 25 and each pixel electrode 24, thereby enabling each pixel to display a predetermined gray scale.

[0023] Next, the configuration of the demultiplexer circuit 19 will be described. The demultiplexer circuit 19 is a so-called SSD (Source Shared Driving) circuit. As shown in FIG. 2, the demultiplexer circuit 19 includes a plurality of unit switch circuits 19U arranged along its length (generally in the X-axis direction) and three switch wirings 38 to 40 to which switch signals for the switches are transmitted. Each unit switch circuit 19U has three switch TFTs 50. The three switch TFTs 50 are connected to any one of the switch wirings 38 to 40 and the source wiring 22, and have the function of controlling the supply of image signals. The number of unit switch circuits 19U installed is one-third the number of source wirings 22 installed.

[0024] The three switch wirings 38 to 40 are arranged at intervals in the Y-axis direction and all extend along the X-axis direction. Although not shown, each of the switch wirings 38 to 40 is connected to a driver 16. The switch wirings 38 to 40 are designated, in order from the top of FIG. 2, as a red switch wiring 38, a green switch wiring 39, and a blue switch wiring 40. The switch TFT 50 (second thin film transistor) is, for example, an N-channel transistor.

[0025] Of the three switch TFTs 50 constituting the unit switch circuit section 19U, the switch TFT 50 arranged on the left side in Fig. 2 is a switch TFT for red, and its gate electrodes 50A and 50E (described in detail later) are connected to the red switch wiring 38, and its drain electrode 50C (see Fig. 3) is connected to the source wiring 22 that supplies image signals to the pixel electrodes 24 that constitute the red pixels. Of the three switch TFTs 50 constituting the unit switch circuit section 19U, the switch TFT 50 arranged on the center side in Fig. 2 is a switch TFT for green, and its gate electrodes 50A and 50E are connected to the green switch wiring 39, and its drain electrode 50C is connected to the source wiring 22 that supplies image signals to the pixel electrodes 24 that constitute the green pixels. Of the three switch TFTs 50 that make up the unit switch circuit section 19U, the switch TFT 50 arranged on the right side of Figure 2 is a switch TFT for blue, and its gate electrodes 50A and 50E are connected to the blue switch wiring 40, and its drain electrode 50C is connected to the source wiring 22 that supplies an image signal to the pixel electrode 24 that constitutes the blue pixel.

[0026] The source electrode 50B of the switch TFT 50 (see FIG. 3) is connected to a source trunk line 44 provided in the non-display area NAA of the array substrate 12. One end of the source trunk line 44 is connected to the driver 16, and the other end is branched into three and connected to the source electrodes of the three switch TFTs 50. The number of source trunk lines 44 installed is one-third of the number of source lines 22 installed. In this way, compared to the case where the source lines 22 are directly connected to the driver 16, the number of lines existing between the driver 16 and the demultiplexer circuit 19 can be reduced to one-third. This makes it possible to easily route the lines (source trunk lines 44) even when the frame of the liquid crystal panel 10 becomes narrower.

[0027] A red image signal for red pixels, a green image signal for green pixels, and a blue image signal for blue pixels are supplied to the source trunk line 44 in a time-division manner from the driver 16. In synchronization with this, switch signals are supplied from the driver 16 to the three switch lines 38 to 40. Specifically, at the timing when the red image signal is supplied from the driver 16 to the source trunk line 44, a switch signal is supplied from the driver 16 to the red switch line 38. As a result, the red switch TFT 50 is selectively turned on, so that the red image signal can be supplied to the pixel electrodes 24 that constitute red pixels via the selected source line 22.

[0028] Furthermore, at the timing when the driver 16 supplies a green image signal to the source trunk line 44, the driver 16 supplies a switch signal to the green switch line 39. This selectively turns on the green switch TFT 50, so that the green image signal can be supplied to the pixel electrode 24 constituting the green pixel via the selected source line 22.

[0029] Furthermore, at the timing when a blue image signal is supplied from the driver 16 to the source trunk line 44, a switch signal is supplied from the driver 16 to the blue switch line 40. This selectively turns on the blue switch TFT 50, allowing the blue image signal to be supplied to the pixel electrode 24 constituting the blue pixel via the selected source line 22. As described above, the demultiplexer circuit 19 allows the source line 22 connected to the source trunk line 44 to be switched in synchronization with the timing when the image signal is supplied from the driver 16 to the source trunk line 44.

[0030] Next, various films laminated on the glass substrate 12GS of the array substrate 12 will be described in detail with reference to Fig. 3. Fig. 3 is a diagram showing the cross-sectional configuration of the pixel TFT 23 and the switch TFT 50 in the array substrate 12. As shown in Fig. 3, on the glass substrate 12GS of the array substrate 12, a first metal film, a first insulating film 61 (gate insulating film), a semiconductor film, a second metal film, a second insulating film 62 (passivation film), a third insulating film 63, a first transparent conductive film, a fourth insulating film 64, and a second transparent conductive film are laminated in this order from the lower layer side (glass substrate 12GS side).

[0031] The first and second metal films are conductive and light-shielding, and are each made of a single layer of one type of metal material (e.g., copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), etc.), or a laminated film or alloy made of different types of metal materials. The first and second transparent conductive films are made of a transparent electrode material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0032] The first insulating film 61 and the fourth insulating film 64 are made of, for example, silicon nitride (SiNx) or silicon oxide (SiO2). The second insulating film 62 is made of, for example, an inorganic insulating film such as silicon nitride or silicon oxide, or an acrylic resin film (for example, polymethyl methacrylate resin (PMMA)). The third insulating film 63 is made of PMMA (acrylic resin), which is a type of organic material (organic resin material). The third insulating film 63 is set to have a thickness greater than the first insulating film 61, the second insulating film 62, and the fourth insulating film 64, for example.

[0033] The semiconductor film is made of an oxide semiconductor material. The semiconductor film may contain at least one metal element selected from the group consisting of In, Ga, and Zn, and may be, for example, an In-Ga-Zn-O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and examples include In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, and In:Ga:Zn=1:1:2. The In-Ga-Zn-O-based semiconductor used in the semiconductor film may be amorphous or crystalline.

[0034] The semiconductor film may contain other oxide semiconductors instead of In-Ga-Zn-O-based semiconductors. For example, it may contain In-Sn-Zn-O-based semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO). In-Sn-Zn-O-based semiconductors are ternary oxides of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer 4 may include an In-W-Zn-O-based semiconductor containing W (tungsten), an In-W-Sn-Zn-O-based semiconductor, an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O-based semiconductor, a Cd-Ge-O-based semiconductor, a Cd-Pb-O-based semiconductor, CdO (cadmium oxide), an Mg-Zn-O-based semiconductor, an In-Ga-Sn-O-based semiconductor, an In-Ga-O-based semiconductor, a Zr-In-Zn-O-based semiconductor, an Hf-In-Zn-O-based semiconductor, an Al-Ga-Zn-O-based semiconductor, a Ga-Zn-O-based semiconductor, or an In-Ga-Zn-Sn-O-based semiconductor.

[0035] The pixel TFT 23 includes a gate electrode 23A (first gate electrode) connected to the gate line 21, a source electrode 23B, a drain electrode 23C, and a semiconductor portion 23D (first semiconductor portion). The semiconductor portion 23D is made of the semiconductor film described above, and is disposed opposite the gate electrode 23A with the first insulating film 61 interposed therebetween.

[0036] The gate electrode 23A is made of a first metal film and is disposed on the glass substrate 12GS. The gate electrode 23A is disposed below the semiconductor portion 23D and overlaps the central portion of the semiconductor portion 23D in the Y-axis direction. The source electrode 23B and the drain electrode 23C are made of a second metal film. The source electrode 23B is disposed so as to be connected to one end of the semiconductor portion 23D in the Y-axis direction. The drain electrode 23C is disposed so as to be connected to the other end of the semiconductor portion 23D in the Y-axis direction.

[0037] Pixel electrodes 24 and a common electrode 25 are arranged in the display area AA. The common electrode 25 is made of a first transparent conductive film. The common electrode 25 is arranged across almost the entire display area AA. As a result, the common electrode 25 is arranged below all pixel electrodes 24 arranged in the display area AA, with a fourth insulating film 64 interposed therebetween. Furthermore, although not shown, a plurality of slits are formed in the common electrode 25 in portions that overlap multiple pixel electrodes 24. The pixel electrode 24 is made of a second transparent conductive film. A contact hole 71 is formed in the insulating films 62, 63, and 64 interposed between the pixel electrode 24 and the drain electrode 23C. The contact hole 71 is arranged at a position that overlaps the pixel electrode 24 and the drain electrode 23C. The pixel electrode 24 is connected to the drain electrode 23C through the contact hole 71.

[0038] A common potential signal serving as a common potential (reference potential) is supplied to the common electrode 25. When the pixel electrode 24 is charged to a potential based on an image signal transmitted to the source line 22 in response to the driving of the pixel TFT 23, a potential difference is generated between the pixel electrode 24 and the common electrode 25. This generates a fringe electric field (oblique electric field) between the edge of the slit opening in the common electrode 25 and the pixel electrode 24, which includes a component normal to the surface of the array substrate 12 in addition to a component along the surface of the array substrate 12. Therefore, by utilizing this fringe electric field, the orientation state of the liquid crystal molecules contained in the liquid crystal layer 13 can be controlled, and a predetermined display is produced based on the orientation state of the liquid crystal molecules. In other words, the liquid crystal panel 10 according to this embodiment operates in a FFS (Fringe Field Switching) mode.

[0039] A switch TFT 50 is disposed in the non-display area NAA. As shown in FIG. 3, the switch TFT 50 includes a gate electrode 50A (second gate electrode), a source electrode 50B, a drain electrode 50C, a semiconductor portion 50D (second semiconductor portion), and a gate electrode 50E (third gate electrode). The gate electrode 50A is made of a first metal film and is disposed on a glass substrate 12GS. Because the gate electrode 23A and the gate electrode 50A are both made of the same metal film (first metal film), the number of metal film layers can be reduced compared to a case in which the gate electrode 23A and the gate electrode 50A are made of different metal films.

[0040] The gate electrode 50A is disposed below the semiconductor portion 50D and overlaps the central portion of the semiconductor portion 50D in the Y-axis direction. The source electrode 50B and the drain electrode 50C are formed of a second metal film. The source electrode 50B is disposed so as to be connected to one end of the semiconductor portion 50D in the Y-axis direction. The drain electrode 50C is disposed so as to be connected to the other end of the semiconductor portion 50D in the Y-axis direction. The semiconductor portion 50D is also formed of a semiconductor film like the semiconductor portion 23D, and is disposed opposite the gate electrode 50A with a first insulating film 61 sandwiched therebetween. The gate electrode 50A has a gate length L2 that is smaller than the gate length L1 of the gate electrode 23A.

[0041] The gate electrode 50E is disposed on the opposite side of the semiconductor portion 50D from the gate electrode 50A, and is disposed opposite the semiconductor portion 50D with the second insulating film 62 sandwiched therebetween. The semiconductor portion 50D is sandwiched between the gate electrode 50A and the gate electrode 50E from above and below. In other words, the switch TFT 50 has a double-gate structure. In the non-display area NAA, the third insulating film 63 is not interposed between the second insulating film 62 and the fourth insulating film 64, and the gate electrode 50E is disposed on the second insulating film 62.

[0042] The gate electrode 50E is made of a first transparent conductive film. That is, the gate electrode 50E is made of the same material as the common electrode 25 (a transparent conductive film arranged on the same side of the second insulating film 62 as the gate electrode 50E). When a switch signal is supplied from the driver 16 to the gate electrode 50A and the gate electrode 50E via a switch wiring (one of the switch wirings 38 to 40) from the driver 16, an electric field acting on the semiconductor portion 50D from the gate electrode 50A and the gate electrode 50E generates channel regions in a lower layer portion (on the gate electrode 50A side) and an upper layer portion (on the gate electrode 50E side) of the semiconductor portion 50D. This allows the channel regions to be generated stably in the semiconductor portion 50D.

[0043] Next, the effects of this embodiment will be described. According to this embodiment, by distributing the image signal to a plurality of source lines 22 using the demultiplexer circuit 19, the total number of source trunk lines 44 connecting the driver 16 and the demultiplexer circuit 19 can be made smaller than the total number of source lines 22. This makes it easier to route the source trunk lines 44 on the array substrate 12.

[0044] The switch TFT 50 constituting the demultiplexer circuit 19 also includes a gate electrode 50A and a gate electrode 50E sandwiching the semiconductor portion 50D from both sides. This double-gate structure allows channel regions to be formed on both sides of the semiconductor portion 50D, thereby increasing the on-current of the switch TFT 50. Furthermore, the gate electrode 50A has a gate length L2 that is smaller than the gate length L1 of the gate electrode 23A. This allows the on-current of the switch TFT 50 to be higher than when the gate length L2 of the gate electrode 50A is the same as the gate length L1 of the gate electrode 23A. As a result, the on-current of the switch TFT 50 constituting the demultiplexer circuit 19 can be ensured.

[0045] Also, the common electrode 25 is provided on the same side of the second insulating film 62 as the gate electrode 50E, and the gate electrode 50E is made of the same material (first transparent conductive film) as the common electrode 25. By arranging the gate electrode 50E and the common electrode 25 on the same side of the second insulating film 62 and using the same material, the gate electrode 50E and the common electrode 25 can be formed simultaneously, which simplifies the manufacturing process.

[0046] <Embodiment 2> A second embodiment of the present invention will be described with reference to FIG. 4. The same parts as those in the above-described embodiment are designated by the same reference numerals, and redundant description will be omitted. The array substrate 112 of this embodiment differs from the above-described embodiment in the configuration of various films laminated on the glass substrate 12GS. The array substrate 112 has a touch panel pattern for achieving touch panel functionality. The touch panel pattern is of a so-called projected capacitive type, and its detection method is a self-capacitive type. The touch panel pattern is composed of position detection electrodes 125 shown in FIG. 4. The position detection electrodes 125 are composed of a transparent conductive film (more specifically, the first transparent conductive film described above), and a plurality of them are arranged in a matrix in the display area AA of the liquid crystal panel 10.

[0047] When a user of the liquid crystal panel 10 approaches a conductive finger to the surface of the liquid crystal panel 10 to input a position based on the image in the display area AA, a capacitance is formed between the finger (position input object) performing the position input and the position detection electrodes 125. As a result, the capacitance detected by the position detection electrodes 125 near the finger changes as the finger approaches, and becomes different from that of the position detection electrodes 125 farther from the finger, making it possible to detect the input position based on this. The position detection electrodes 125 are substantially rectangular in plan view, each larger than the pixel electrodes 24, and are arranged in a range spanning multiple pixel electrodes 24 in the planar directions (X-axis and Y-axis directions).

[0048] As shown in FIG. 4, position detection wiring 145 connected to the position detection electrodes 125 and transmitting position detection signals is formed on the second insulating film 62. Each of the position detection electrodes 125 is connected to a corresponding one of the position detection wirings 145. A contact hole 171 is provided in the third insulating film 63 interposed between the position detection electrode 125 and the position detection wiring 145. The contact hole 171 is disposed at a position where the position detection electrode 125 and the position detection wiring 145 overlap. The position detection electrode 125 is connected to the position detection wiring 145 through the contact hole 171. The position detection wiring 145 is parallel to the source wiring 22 (see FIG. 2) and is connected to the driver 16 at the end opposite to the position detection electrode 125.

[0049] A common potential signal related to the display function and a position detection signal related to the touch function are supplied at different times (in a time-divided manner) from the driver 16 to the position detection wiring 145. The timing when the common potential signal is supplied from the driver 16 to the position detection wiring 145 is the display period, and the timing when the position detection signal is supplied from the driver 16 to the position detection wiring 145 is the sensing period (position detection period). During the display period, the common potential signal is supplied to all the position detection wirings 145, so all the position detection electrodes 125 become the reference potential and function as common electrodes.

[0050] The switch TFT 150 (second thin film transistor) includes a gate electrode 50A, a source electrode 50B, a drain electrode 50C, a semiconductor portion 50D, and a gate electrode 150E (third gate electrode). The gate electrode 150E is disposed on the opposite side of the semiconductor portion 50D from the gate electrode 50A, and faces the semiconductor portion 50D across the second insulating film 62. The position detection wiring 145 is disposed on the same side of the second insulating film 62 as the gate electrode 150E and is made of the same material (third metal film) as the gate electrode 150E. The third metal film constituting the position detection wiring 145 and the gate electrode 150E is made of a single layer film made of a single type of metal material (e.g., copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), etc.) or a laminated film or alloy made of different types of metal materials.

[0051] According to this embodiment, by arranging the gate electrode 150E and the position detection wiring 145 on the same side of the second insulating film 62 and using the same material, it becomes possible to simultaneously form the gate electrode 150E and the position detection wiring 145, thereby simplifying the manufacturing process. Furthermore, unlike the position detection electrode 125, which is formed over a relatively large area, the position detection wiring 145 does not need to be made of a transparent conductive film, and therefore a material with lower electrical resistance than a transparent conductive film can be used. This makes it possible to further reduce the electrical resistance of the gate electrode 150E and suppress signal delays.

[0052] <Embodiment 3> A third embodiment of the present invention will be described with reference to FIG. 5. In an array substrate 212 of this embodiment, the configuration of a switch TFT 250 (second thin film transistor) differs from that of the above-described embodiments. As shown in FIG. 5, the switch TFT 250 includes a gate electrode 50A, a source electrode 50B, a drain electrode 50C, a semiconductor portion 50D, and a gate electrode 250E (third gate electrode). In addition, a switch wiring 246 (wiring for gate electrode) connected to the gate electrode 250E is formed on the second insulating film 62. The switch wiring 246 is used as any of the red switch wiring, green switch wiring, and blue switch wiring described in the above-described embodiments.

[0053] The gate electrode 250E is disposed on the same side of the second insulating film 62 as the position detection electrode 125, and is made of the same material as the position detection electrode 125 (the above-mentioned first transparent conductive film). The switch wiring 246 is disposed on the lower layer side of the gate electrode 250E. The switch wiring 246 is also disposed on the same side of the second insulating film 62 as the position detection wiring 145, and is made of the same material as the position detection wiring 145 (the above-mentioned third metal film). The gate electrode 50A is connected to the switch wiring 246 via a contact hole (not shown). The switch wiring 246 is provided so as not to cover the semiconductor portion 50D from the side opposite the gate electrode 50A.

[0054] An end of the switch wiring 246 opposite to the gate electrode 250E is connected to the driver 16 (see FIG. 2). When a switch signal is supplied from the driver 16 to the gate electrode 50A and the gate electrode 250E via the switch wiring 246, an electric field acting on the semiconductor portion 50D from the gate electrode 50A and the gate electrode 250E generates channel regions in a lower layer side (gate electrode 50A side) and an upper layer side (gate electrode 250E side) of the semiconductor portion 50D, respectively, and the switch TFT 250 is turned on.

[0055] According to this embodiment, the gate electrode 250E and the position detection electrode 125 can be formed simultaneously, and the position detection wiring 145 and the switch wiring 246 can be formed simultaneously. This simplifies the manufacturing process. By forming the gate electrode 250E covering the semiconductor portion 50D of the switch TFT 250 using a transparent conductive film, it is possible to prevent stray light (light generated by reflection and refraction inside the liquid crystal panel 10) that reaches the array substrate 212 from being blocked by the gate electrode 250E, allowing more light to reach the semiconductor portion 50D. This allows the threshold voltage of the switch TFT 250 to be lowered (negative shift), preventing a decrease in the on-current obtained at a specified operating potential.

[0056] Furthermore, since the position detection wiring 145 does not need to be made of a transparent conductive film like the position detection electrode 125, a material with lower electrical resistance than a transparent conductive film can be used. The switch wiring 246 is made of the same material as the position detection wiring 145, and its electrical resistance can be made lower, so that delay in the switch signal transmitted by the switch wiring 246 to the gate electrode 250E can be suppressed.

[0057] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope. (1) In the above embodiment, the electrodes (gate electrode, source electrode, drain electrode) of the pixel TFT and the switch TFT are made of a metal film. However, the present invention is not limited to this, and it is also possible to use a conductive film other than a metal film (for example, a low-resistance film obtained by subjecting a semiconductor film to a resistance-reducing treatment, a transparent conductive film, etc.). (2) The planar shape of the liquid crystal panel 10 is not limited to a square, but may be a circle, a semicircle, an oval, an ellipse, a trapezoid, or the like. (3) In the above embodiment, the liquid crystal panel 10 is used as an example of the display device. However, other than the liquid crystal panel 10, an organic EL display device, which is a self-luminous display device, may also be used. [Explanation of symbols]

[0058] 10... liquid crystal panel (display device), 11... opposing substrate, 12, 112, 212... array substrate (display substrate), 16... driver (signal supply unit), 19... demultiplexer circuit, 21... gate wiring (first wiring), 22... source wiring (second wiring), 23... pixel TFT (first thin film transistor), 23A... gate electrode (first gate electrode), 23D... semiconductor portion (first semiconductor portion), 24... pixel electrode, 25... common electrode (second insulating film and the third gate electrode transparent conductive film arranged on the same side), 50...switch TFT (second thin film transistor), 50A...gate electrode (second gate electrode), 50D...semiconductor portion (second semiconductor portion), 50E...gate electrode (third gate electrode), 61...first insulating film, 62...second insulating film, L1...gate length (gate length of first gate electrode), L2...gate length (gate length of second gate electrode), 125...position detection electrode, 145...position detection wiring, 246...switch wiring (wiring for gate electrode)

Claims

1. a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction intersecting the first direction; a plurality of first thin film transistors connected to any one of the plurality of first wirings and any one of the plurality of second wirings; a plurality of pixel electrodes arranged in a matrix in the first direction and the second direction, each connected to the plurality of first thin film transistors; a signal supply unit that supplies image signals to the plurality of second wirings; a plurality of second thin film transistors constituting a demultiplexer circuit that distributes the image signals supplied from the signal supply unit to the plurality of second wirings, The first thin film transistor is a first gate electrode connected to the first wiring; a first semiconductor portion disposed opposite the first gate electrode with a first insulating film interposed therebetween; The second thin film transistor is a second gate electrode having a gate length smaller than that of the first gate electrode; a second semiconductor portion disposed opposite the second gate electrode with the first insulating film interposed therebetween; a third gate electrode disposed on the opposite side of the second semiconductor portion from the second gate electrode and facing the second semiconductor portion with a second insulating film interposed therebetween.

2. a transparent conductive film disposed on the same side as the third gate electrode with respect to the second insulating film; 2. The display substrate according to claim 1, wherein the third gate electrode is made of the same material as the transparent conductive film.

3. a position detection electrode made of a transparent conductive film, which forms a capacitance with a position input device that performs a position input; a position detection wiring connected to the position detection electrode and transmitting a position detection signal; 2. The display substrate according to claim 1, wherein the position detection wiring is disposed on the same side of the second insulating film as the third gate electrode and is made of the same material as the third gate electrode.

4. a position detection electrode made of a transparent conductive film, which forms a capacitance with a position input device that performs a position input; a position detection wiring connected to the position detection electrode and transmitting a position detection signal; a gate electrode wiring connected to the third gate electrode, the third gate electrode is disposed on the same side of the second insulating film as the position detection electrode and is made of the same material as the position detection electrode; 2. The display substrate according to claim 1, wherein the gate electrode wiring is disposed on the same side of the second insulating film as the position detection wiring and is made of the same material as the position detection wiring.

5. A display substrate according to any one of claims 1 to 4; a counter substrate disposed opposite the display substrate.

Images