Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device with improved breakdown voltage.SOLUTION: A silicon carbide semiconductor device 100 comprises a silicon carbide substrate having a first main surface 1, a second main surface 2 opposite to the first main surface, an active region 110, and a termination region 120, the silicon carbide substrate comprises a first semiconductor region 11 of a first conductivity type and a plurality of second semiconductor regions 14 of a second conductivity type within the first semiconductor region, the plurality of second semiconductor regions have a third semiconductor region 14A within the termination region 120, the third semiconductor region has an upper end surface 14B and a lower end surface 14C, the first main surface and the upper end surface are separated from each other by the first semiconductor region, there is a first effective concentration peak of impurities contained within the second semiconductor region within a virtual plane positioned between the upper end surface and the lower end surface and parallel to the first main surface, a rate of change of the first effective concentration between the virtual plane and the lower end surface along a second axis Z perpendicular to the first main surface is smaller than a rate of change of the first effective concentration between the virtual plane and the upper end surface, and a distance between the upper end surface and the lower end surface is 1 μm or more.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to silicon carbide semiconductor devices. [Background technology]

[0002] Conventionally, semiconductor devices having a superjunction structure have been disclosed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-273355 [Patent Document 2] Japanese Patent Application Publication No. 2019-165217 [Patent Document 3] Japanese Patent Application Publication No. 2019-102761 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional semiconductor devices, it is difficult to further improve the breakdown voltage.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device that can improve breakdown voltage. [Means for solving the problem]

[0006] A silicon carbide semiconductor device according to the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region, the silicon carbide substrate having a first semiconductor region having a first conductivity type and a plurality of second semiconductor regions having a second conductivity type provided within the first semiconductor region, the plurality of second semiconductor regions being aligned along a first axis parallel to the first main surface within the active region and the termination region, the second semiconductor region having a third semiconductor region within the termination region, the third semiconductor region being between the first main surface and the second main surface and a bottom surface between the top surface and the second main surface, wherein the first main surface and the top surface are separated from each other by the first semiconductor region and are located between the top surface and the bottom surface, a peak of a first effective concentration of the second conductivity type impurity contained in the second semiconductor region exists in an imaginary plane parallel to the first main surface, an average value of a rate of change of the first effective concentration between the imaginary plane and the bottom surface is smaller than an average value of a rate of change of the first effective concentration between the imaginary plane and the top surface along a second axis perpendicular to the first main surface, and a distance between the top surface and the bottom surface is 1 μm or more. [Effects of the Invention]

[0007] According to the present disclosure, the breakdown voltage can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing the configuration of an interlayer insulating film and a first main surface in an active region of the silicon carbide semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view showing the configuration of an active region of the silicon carbide semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing the configuration of the vicinity of the boundary between the active region and the termination region of the silicon carbide semiconductor device according to the embodiment. [Figure 5]FIG. 5 is a cross-sectional view (part 1) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 2) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be denoted by the same reference numerals, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are represented by brackets [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative index in crystallography is usually represented by placing a "-" (bar) above a number, but in this disclosure, a negative sign is placed before the number. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the silicon carbide semiconductor device. An XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the -Z direction may be referred to as downward, lower side, or bottom.

[0011] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region, the silicon carbide substrate having a first semiconductor region having a first conductivity type and a plurality of second semiconductor regions having a second conductivity type provided within the first semiconductor region, the plurality of second semiconductor regions being aligned along a first axis parallel to the first main surface in the active region and the termination region, the second semiconductor region having a third semiconductor region within the termination region, the third semiconductor region being aligned along a first axis parallel to the first main surface and a bottom surface between the top surface and the second main surface, the first main surface and the top surface being separated from each other by the first semiconductor region, the second semiconductor region being located between the top surface and the bottom surface, a peak of a first effective concentration of the second conductivity type impurity contained in the second semiconductor region being present in an imaginary plane parallel to the first main surface, an average value of a rate of change of the first effective concentration between the imaginary plane and the bottom surface being smaller than an average value of a rate of change of the first effective concentration between the imaginary plane and the top surface along a second axis perpendicular to the first main surface, and a distance between the top surface and the bottom surface being 1 μm or more.

[0012] Depletion in the vicinity of the lower end surface of the second semiconductor region is likely to be promoted, and the breakdown voltage can be improved.

[0013] [2] In [1], the distance between the imaginary plane and the lower end surface may be greater than the distance between the imaginary plane and the upper end surface, in which case depletion is particularly likely to be promoted near the lower end surface of the second semiconductor region.

[0014] [3] In [1] or [2], the distance between the first main surface and the upper end surface may be 100 nm or more and 500 nm or less. In this case, the entire first semiconductor region is likely to be depleted between the first main surface and the upper end surface, and electric field concentration due to a steep change in the equipotential surface is likely to be alleviated.

[0015] [4] In any one of [1] to [3], an effective concentration of the first conductivity type impurity contained in a portion of the first semiconductor region between adjacent second semiconductor regions is 1×10 16 cm -3 5x10 or more 17 cm -3 In this case, it is easy to suppress an increase in on-resistance while improving the breakdown voltage.

[0016] [5] In any one of [1] to [4], the second semiconductor regions may be provided at a constant pitch along the first axis, which makes it easier to obtain high uniformity in breakdown voltage within the silicon carbide semiconductor device.

[0017] [6] In any one of [1] to [5], the second semiconductor regions may extend along a third axis perpendicular to the first axis and the second axis. In this case, the second semiconductor regions are easily formed uniformly.

[0018] [7] In any one of [1] to [6], any of the plurality of second semiconductor regions may be provided in both the termination region and the active region, which makes it easier to form the second semiconductor region uniformly in the termination region and the active region.

[0019] [8] In any of [1] to [7], the distance between the upper end surface and the lower end surface may be equal to or greater than half the thickness of the first semiconductor region. In this case, a high breakdown voltage can be easily obtained even if the concentration of the first impurity in the first semiconductor region is relatively high in the active region. Therefore, the on-resistance can be easily reduced.

[0020] [Embodiments of the present disclosure] An embodiment of the present disclosure relates to a so-called vertical MOS (metal oxide semiconductor) field effect transistor (FET) using silicon carbide. This MOS FET is an example of a silicon carbide semiconductor device. FIG. 1 is a schematic diagram showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a diagram showing the configuration of an interlayer insulating film and a first main surface in an active region of the silicon carbide semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view showing the configuration of an active region of the silicon carbide semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view showing the configuration near the boundary between the active region and a termination region of the silicon carbide semiconductor device according to an embodiment. FIG. 2 corresponds to region II in FIG. 1. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 1. A barrier metal film 84 is omitted in FIG. 4.

[0021] As shown in Figures 1 to 4, the silicon carbide semiconductor device 100 according to the embodiment has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier metal film 84.

[0022] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 forms the first main surface 1, and the silicon carbide single crystal substrate 50 forms the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity (first conductivity type).

[0023] As shown in FIG. 1 , silicon carbide substrate 10 has active region 110 and termination region 120. Active region 110 has, for example, a square shape with rounded corners in a plan view perpendicular to first main surface 1. Active region 110 may also have a rectangular shape with rounded corners in a plan view. Termination region 120 surrounds active region 110 in a plan view. Termination region 120 is provided around active region 110 in a plan view. Termination region 120 has a first termination region 121 that contacts active region 110 in a direction parallel to the Y-axis, a second termination region 122 that contacts active region 110 in a direction parallel to the X-axis, and a third termination region 123 that contacts first termination region 121 and second termination region 122. First termination regions 121 are provided on the +Y and −Y sides of active region 110, second termination regions 122 are provided on the +X and −X sides of active region 110, and third termination regions 123 are provided at the four corners of silicon carbide substrate 10.

[0024] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[0025] The silicon carbide epitaxial layer 40 has a drift region 11, a body region 12, a source region 13, a p-type region 14 for a superjunction, a contact region 16, a junction termination extension (JTE) 17, and a contact region 18.

[0026] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50.

[0027] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity. The body region 12 is located within the active region 110. The body region 12 is provided on the drift region 11. The lower end surface of the body region 12 and the upper end surface of the drift region 11 are in contact with each other.

[0028] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is located within the active region 110. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 constitutes the first main surface 1.

[0029] A plurality of gate trenches 5 defined by side surfaces 3 and bottom surfaces 4 are provided on the first main surface 1. The gate trenches 5 are formed in the active region 110. The gate trenches 5 extend, for example, along the Y axis. A plurality of gate trenches 5 are also provided along the X axis at regular intervals (first pitch P1). The side surfaces 3 penetrate the source region 13, the body region 12, and part of the drift region 11, and reach the drift region 11. The bottom surfaces 4 are continuous with the side surfaces 3. The bottom surfaces 4 are located in the drift region 11. For example, the bottom surfaces 4 are parallel to the first main surface 1 and the second main surface 2. In a cross-sectional view perpendicular to the Y axis, the angle θ1 of the side surfaces 3 with respect to an imaginary plane 30 including the bottom surfaces 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surfaces 3 preferably have a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

[0030] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 is located within the active region 110. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. The contact region 18 constitutes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 and the source regions 13 may be alternately provided along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 may be provided intermittently along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis.

[0031] A plurality of gate trenches 5 may be arranged at regular intervals along the Y axis. When a plurality of gate trenches 5 are arranged at regular intervals along the Y axis, a part of the contact region 18 may be located between adjacent gate trenches 5 along the Y axis. A plurality of gate trenches 5 may be provided in an array.

[0032] The contact region 16 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 16 is located within the active region 110. The contact region 16 is formed simultaneously with the contact region 18, is made of the same material as the contact region 18, and has the same depth as the contact region 18. The contact region 16 also constitutes the first main surface 1. In a plan view, the contact region 16 is provided in an annular shape, and a plurality of gate trenches 5 and a gate electrode 82, which will be described later, are located inside the contact region 16. The outer edge of the contact region 16 is the boundary between the active region 110 and the termination region 120. In this disclosure, an annular shape includes a single closed curve shape other than a circular annular shape or an elliptical annular shape, such as a rounded rectangular shape.

[0033] JTE 17 contains p-type impurities such as aluminum at an effective concentration lower than that of contact region 16, and has p-type conductivity. JTE 17 is provided in an annular shape so as to be in contact with contact region 16. In a plan view, contact region 16 is located inside JTE 17. JTE 17 is located within termination region 120. JTE 17 also constitutes first main surface 1. JTE 17 is provided inside the outer edge of silicon carbide substrate 10, and first main surface 1 at the outer edge of silicon carbide substrate 10 is constituted by drift region 11.

[0034] The p-type region 14 contains p-type impurities such as aluminum and has p-type conductivity. The p-type region 14 is in the active region 110 and the termination region 120. The p-type region 14 is provided in the drift region 11. The p-type region 14 may extend along the Y-axis. Multiple p-type regions 14 are aligned along the X-axis. Multiple p-type regions 14 may be provided at a constant pitch along the X-axis. Multiple p-type regions 14 may be provided in a stripe pattern. The effective concentration of the p-type impurity in the p-type region 14 is, for example, 1×10 16 cm -3 5x10 or more 17 cm -3 The p-type region 14 is an example of a second semiconductor region. The X-axis is an example of a first axis, the Z-axis is an example of a second axis, and the Y-axis is an example of a third axis.

[0035] As shown in FIG. 3 , a portion of the p-type region 14 is located between adjacent gate trenches 5 along the X-axis in a plan view perpendicular to the first main surface 1. A p-type region 14S, which is part of the p-type region 14 and is located between adjacent gate trenches 5 along the X-axis, is spaced apart from the gate trench 5. The body region 12 is exposed at the side surface 3 of the gate trench 5. The p-type region 14S is spaced apart from the gate trench 5 along the X-axis more than the body region 12 is. The p-type region 14S is located below the body region 12 and is in contact with the body region 12. The p-type region 14S overlaps the contact region 18 in a plan view perpendicular to the first main surface 1. The contact region 18 may penetrate the body region 12, and the p-type region 14S may be in contact with the body region 12 and the contact region 18. The contact region 18, the body region 12, and the p-type region 14S are electrically connected to one another.

[0036] As shown in FIG. 4 , p-type region 14T, which is part of p-type region 14 and is located below contact region 16, is in contact with contact region 16. A p-type region 14 is also provided in termination region 120. At least a portion of p-type region 14 in termination region 120 is not in contact with JTE 17. P-type region 14U, which is part of p-type region 14 in termination region 120, may be in contact with JTE 17. In termination region 120, p-type region 14U may be in contact with JTE 17, and the remainder of p-type region 14 may be separated from JTE 17. P-type region 14A, which is part of p-type region 14 and is separated from JTE 17 in termination region 120, is an example of a third semiconductor region.

[0037] The p-type region 14A has an upper end surface 14B and a lower end surface 14C. The upper end surface 14B faces the first major surface 1, and the lower end surface 14C faces the second major surface 2. The upper end surface 14B and the first major surface 1 are separated from each other by a drift region 11. A peak of the first effective concentration of the p-type impurity contained in the p-type region 14A exists within an imaginary plane 31 located between the upper end surface 14B and the lower end surface 14C and parallel to the first major surface 1. The average rate of change of the first effective concentration between the imaginary plane 31 and the lower end surface 14C along the Z axis is smaller than the average rate of change of the first effective concentration between the imaginary plane 31 and the upper end surface 14B. Furthermore, the distance between the upper end surface 14B and the lower end surface 14C is 1 μm or more. For example, the distance L1 between the imaginary plane 31 and the lower end surface 14C is greater than the distance L2 between the imaginary plane 31 and the upper end surface 14B. The p-type regions 14 can be formed, for example, by channeling implantation of p-type impurities into an n-type epitaxial layer. The p-type regions 14 other than the p-type region 14A may have the same impurity concentration profile as the p-type region 14A.

[0038] P-type region 14A is provided, for example, in first termination region 121, second termination region 122, and third termination region 123. P-type region 14A may be provided only in first termination region 121 and second termination region 122, or p-type region 14A may be provided only in first termination region 121 or second termination region 122.

[0039] In the active region 110, the drift region 11 is exposed to the side surface 3 and is in contact with the body region 12 and the p-type region 14. In the termination region 120, the drift region 11 forms the first main surface 1 outside the JTE 17 in a plan view. The drift region 11 may be in contact with the silicon carbide single crystal substrate 50. The effective concentration of the n-type impurity in the drift region 11 is, for example, 1×10 16 cm -3 5x10 or more 17 cm -3 The drift region 11 may include a current spreading region having a particularly high effective concentration of n-type impurities within the active region 110. The drift region 11 is an example of a first semiconductor region.

[0040] Along the Z axis, silicon carbide single crystal substrate 50 and drift region 11 are present between bottom surface 4 and second main surface 2, and the conductivity type of silicon carbide substrate 10 between bottom surface 4 and second main surface 2 is n-type. Along the Z axis, no semiconductor with p-type conductivity exists between bottom surface 4 and second main surface 2.

[0041] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may also contact the source region 13 at the first main surface 1.

[0042] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y-axis. In a plan view perpendicular to the first main surface 1, the gate electrode 82 may overlap multiple gate trenches 5.

[0043] A gate insulating film 81 is also provided on the contact region 16, and an electrode film 85 is formed thereon. The electrode film 85 is formed simultaneously with the gate electrode 82, and is made of the same material as the gate electrode 82.

[0044] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A part of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.

[0045] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged such that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0046] Above the contact region 16, an interlayer insulating film 83 is provided on the gate insulating film 81 and the electrode film 85. A contact hole 91 is formed in the interlayer insulating film 83, reaching the electrode film 85, and a contact hole 92 is formed in the interlayer insulating film 83 and the gate insulating film 81, reaching the contact region 16. The silicon carbide semiconductor device 100 has a gate runner 63 and a source runner 64. The gate runner 63 and the source runner 64 are formed simultaneously with the source electrode 60 and are made of the same material as the source electrode 60. The gate runner 63 is electrically connected to the gate electrode 82 and the electrode film 85. The source runner 64 is electrically connected to the source electrode 60 and the contact region 16. In a plan view, the source runner 64 is provided in an annular shape, and the outer edge of the source runner 64 may coincide with the outer edge of the contact region 16. The gate runner 63 is provided between the source electrode 60 and the source runner 64.

[0047] The barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0048] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 provided in a contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13, the contact region 16, and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13, the contact region 16, and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum.

[0049] Silicon carbide semiconductor device 100 further has silicon nitride film 87 and polyimide film 88. Silicon nitride film 87 covers the upper surface and side surfaces of interlayer insulating film 83, and polyimide film 88 covers the upper surface and side surfaces of silicon nitride film 87. An opening exposing a portion of source electrode 60 is formed in silicon nitride film 87 and polyimide film 88, and a source plating film 86 is formed inside this opening. Silicon nitride film 87 and polyimide film 88 also have an opening (not shown) exposing a portion of a gate electrode (not shown) connected to gate runner 63, and a gate plating film (not shown) is formed inside this opening.

[0050] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may also be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0051] A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and drift region 11. Also, a passivation film covering a portion of source electrode 60 may be provided.

[0052] The effective concentration of p-type impurities in the contact regions 16 and 18 may be higher than the effective concentration of p-type impurities in the body region 12. For example, the effective concentration of p-type impurities in the contact regions 16 and 18 may be, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The effective concentration of p-type impurities in the body region 12 is 5×10 17 cm -3 5x10 or more 18 cm -3 The following is the result.

[0053] The effective concentration of n-type impurities in the source region 13 may be higher than the effective concentration of p-type impurities in the body region 12. The effective concentration of n-type impurities in the source region 13 may be, for example, 1×10 19 cm -3 That's about it.

[0054] In the present disclosure, the effective concentration of a first conductivity type impurity is the concentration obtained by subtracting the concentration of a second conductivity type impurity from the concentration of the first conductivity type impurity, and the effective concentration of a second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentrations can be measured using, for example, a scanning capacitance microscope (SCM).

[0055] Drift region 11 has n-type conductivity, and body region 12 and p-type region 14 have p-type conductivity, so the boundary between drift region 11 and body region 12 and the boundary between drift region 11 and p-type region 14 are clear.

[0056] Next, a description will be given of a method for manufacturing the silicon carbide semiconductor device 100. Figures 5 and 6 are cross-sectional views showing the method for manufacturing the silicon carbide semiconductor device 100 according to the embodiment.

[0057] First, as shown in Fig. 5, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0058] 6 , ions are implanted into silicon carbide epitaxial layer 40 to form p-type region 14. The ion implantation for forming p-type region 14 involves channeling implantation of p-type impurities such as aluminum. At this time, the upper end surface of p-type region 14 is spaced apart from the upper surface of silicon carbide epitaxial layer 40.

[0059] Next, ions are implanted into the silicon carbide epitaxial layer 40 to form the body region 12, the source region 13, the contact region 16, the JTE 17, and the contact region 18. The remaining portion of the silicon carbide epitaxial layer 40 becomes the drift region 11. Next, a plurality of gate trenches 5 are formed. Next, a gate insulating film 81, a gate electrode 82, an electrode film 85, an interlayer insulating film 83, a barrier metal film 84, a silicon nitride film 87, a polyimide film 88, and a plating film 86 are formed (see FIGS. 3 and 4).

[0060] In this manner, silicon carbide semiconductor device 100 can be manufactured.

[0061] In silicon carbide semiconductor device 100, as described above, first main surface 1 and upper end surface 14B are separated from each other by drift region 11, and the peak of the first effective concentration of p-type impurities contained in p-type region 14A is within imaginary plane 31. Additionally, along the Z-axis, the average value of the rate of change of the first effective concentration between imaginary plane 31 and lower end surface 14C is smaller than the average value of the rate of change of the first effective concentration between imaginary plane 31 and upper end surface 14B, and the distance (L1+L2) between upper end surface 14B and lower end surface 14C is 1 μm or more. By increasing the effective concentration of p-type impurities on imaginary plane 31 in p-type region 14A and making the average value of the rate of change of n-type impurities below imaginary plane 31 smaller than the average value of the rate of change of n-type impurities above imaginary plane 31, depletion in p-type region 14A near lower end surface 14C can be promoted, and a charge compensation structure similar to a superjunction structure can be obtained. Furthermore, the breakdown voltage can be improved by alleviating electric field concentration at the pn interface at the side end of p-type region 14. The distance between upper end surface 14B and lower end surface 14C may be 1.5 μm or more, or may be 2 μm or more.

[0062] Furthermore, although the distribution of impurity concentration in p-type region 14 may deviate from the design value due to manufacturing errors, there is a wide tolerance (margin) within which a high breakdown voltage can be obtained even in such cases.

[0063] Since the distance L1 between the imaginary plane 31 and the lower end surface 14C is greater than the distance L2 between the imaginary plane 31 and the upper end surface 14B, depletion near the lower end surface 14C of the p-type region 14 is particularly likely to be promoted.

[0064] When the distance between the first main surface 1 and the upper end surface 14B is 500 nm or less, the entire drift region 11 is easily depleted between the first main surface 1 and the upper end surface 14B, which facilitates mitigating electric field concentration caused by a steep change in the equipotential surface. However, when the distance between the first main surface 1 and the upper end surface 14B is less than 100 nm, a leakage path may occur between adjacent p-type regions 14A. Therefore, the distance between the first main surface 1 and the upper end surface 14B is, for example, 100 nm to 500 nm. The distance between the first main surface 1 and the upper end surface 14B may be 150 nm to 450 nm, or may be 200 nm to 400 nm. Furthermore, the distance between the first main surface 1 and the upper end surface 14B may be smaller than the dimension of the p-type region 14A along the X-axis direction and the dimension of the drift region 11 between adjacent p-type regions 14A.

[0065] The effective concentration of n-type impurities contained in the portion between adjacent p-type regions 14 in drift region 11 is 1×10 16 cm -3 If the effective concentration of n-type impurities contained in the portion between adjacent p-type regions 14 in drift region 11 is less than 5×10 17 cm -3 If the n-type impurity concentration is greater than 1×10, it may be difficult to obtain a sufficient breakdown voltage. Therefore, the effective concentration of the n-type impurity contained in the portion between the adjacent p-type regions 14 in the drift region 11 is set to, for example, 1×10 16 cm -3 5x10 or more 17 cm -3 The effective concentration of n-type impurities contained in the portion between adjacent p-type regions 14 in drift region 11 is 2×10 16 cm -3 Over 4×10 17 cm -3 May be less than 3 x 10 16 cm -3 3x10 or more 17 cm-3 It may be the following:

[0066] When multiple p-type regions 14 are provided at a constant pitch along the X-axis, it is easy to achieve high uniformity in the breakdown voltage within silicon carbide semiconductor device 100. When multiple p-type regions 14 extend along the Y-axis, it is easy to form p-type regions 14 uniformly. Furthermore, when any of multiple p-type regions 14 is provided in both termination region 120 and active region 110, it is easy to form p-type region 14 uniformly in termination region 120 and active region 110.

[0067] When the distance between the upper end surface 14B and the lower end surface 14C is equal to or greater than half the thickness of the drift region 11, a high breakdown voltage can be easily obtained even if the concentration of n-type impurities in the drift region 11 is relatively high within the active region 110. Therefore, the on-resistance can be easily reduced.

[0068] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0069] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5 Gate trench 10 Silicon carbide substrate 11 Drift Region 12 Body Region 13 Source Region 14, 14A, 14S, 14T, 14U p-type region 14B Upper end surface 14C Lower end surface 16 Contact Area 17 Junction termination structure 18 Contact Area 30, 31 Virtual plane 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 63 Gate Runner 64 Source Runner 70 drain electrode 81 Gate insulating film 82 gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Electrode membrane 86 Plating film 87 Silicon nitride film 88 Polyimide film 90, 91, 92 contact holes 100 Silicon carbide semiconductor device 110 Active area 120 Termination area 121 1st termination area 122 Second termination area 123 Third terminal area L1, L2 distance P1 First pitch θ1 angle

Claims

1. a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region; The silicon carbide substrate is a first semiconductor region having a first conductivity type; a plurality of second semiconductor regions provided within the first semiconductor region and having a second conductivity type; and the second semiconductor regions are aligned along a first axis parallel to the first major surface in the active region and the termination region; the second semiconductor region has a third semiconductor region within the termination region; The third semiconductor region is an upper end surface between the first main surface and the second main surface; a lower end surface between the upper end surface and the second main surface; and the first main surface and the top surface are separated from each other by the first semiconductor region, a peak of a first effective concentration of the second conductivity type impurity contained in the second semiconductor region is present within an imaginary plane that is located between the upper end surface and the lower end surface and is parallel to the first main surface; an average value of a rate of change of the first effective concentration between the imaginary plane and the lower end surface along a second axis perpendicular to the first principal surface is smaller than an average value of a rate of change of the first effective concentration between the imaginary plane and the upper end surface; a distance between the upper end surface and the lower end surface being 1 μm or more.

2. The silicon carbide semiconductor device according to claim 1 , wherein a distance between said imaginary plane and said lower end surface is greater than a distance between said imaginary plane and said upper end surface.

3. 3 . The silicon carbide semiconductor device according to claim 1 , wherein a distance between said first main surface and said upper end surface is not less than 100 nm and not more than 500 nm.

4. The effective concentration of the first conductivity type impurity contained in the portion of the first semiconductor region between the adjacent second semiconductor regions is 1×10 １６ cm －３ 5x10 or more １７ cm －３ 3. The silicon carbide semiconductor device according to claim 1, wherein:

5. 3 . The silicon carbide semiconductor device according to claim 1 , wherein said plurality of second semiconductor regions are provided at a constant pitch along said first axis.

6. 3 . The silicon carbide semiconductor device according to claim 1 , wherein said plurality of second semiconductor regions extend along a third axis perpendicular to said first axis and said second axis.

7. 3 . The silicon carbide semiconductor device according to claim 1 , wherein any one of said plurality of second semiconductor regions is provided in both said termination region and said active region.

8. 3 . The silicon carbide semiconductor device according to claim 1 , wherein a distance between said upper end surface and said lower end surface is equal to or greater than half a thickness of said first semiconductor region.

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