Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device with improved breakdown voltage.SOLUTION: A silicon carbide semiconductor device 100 comprises a silicon carbide substrate having a first main surface 1, a second main surface 2, an active region 110, and a termination region 120, the silicon carbide semiconductor substrate includes a first semiconductor region 11 of a first conductivity type, a plurality of second semiconductor regions 14 of a second conductivity type and a third semiconductor region 16 of the second conductivity type shaped like a ring in plan view, a first inner edge of the first semiconductor region adjacent to the third semiconductor region, a ring-shaped fourth semiconductor region 24 in which a first outer edge 24B is located in the termination region, a fifth semiconductor region 25 in which a first impurity concentration is lower than that of the sixth semiconductor region, a sixth semiconductor region 26 between the fifth semiconductor region and the second main surface, and a seventh semiconductor region 27 between the first inner edge and the first outer edge in plan view. The seventh semiconductor region has an upper end surface 27A between the first main surface and the second main surface, and a lower end surface 27B between the upper end surface and the second main surface, and the first main surface and the upper end surface are separated by the fifth semiconductor region, and a part of the second semiconductor region is electrically connected to the third semiconductor region.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to silicon carbide semiconductor devices. [Background technology]

[0002] Conventionally, semiconductor devices having a superjunction structure have been disclosed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-273355 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional semiconductor devices, it is difficult to further improve the breakdown voltage.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device that can improve breakdown voltage. [Means for solving the problem]

[0006] A silicon carbide semiconductor device according to the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region, the silicon carbide substrate having a first semiconductor region having a first conductivity type, a plurality of second semiconductor regions having a second conductivity type provided within the first semiconductor region, and a third semiconductor region having the second conductivity type provided within the active region, constituting the first main surface and having an annular shape in the plan view, the plurality of second semiconductor regions being aligned along a first axis parallel to the first main surface in the active region and the termination region, and in the termination region, a first inner edge of the first semiconductor region is in contact with the third semiconductor region and a first outer edge is in the termination region in the plan view. the second semiconductor region includes a seventh semiconductor region located between the first inner edge and the first outer edge in the planar view, the seventh semiconductor region having an upper end surface between the first main surface and the second main surface, and a lower end surface between the upper end surface and the second main surface, the first main surface and the upper end surface being separated from each other by the fifth semiconductor region, and a portion of the second semiconductor region is electrically connected to the third semiconductor region. [Effects of the Invention]

[0007] According to the present disclosure, the breakdown voltage can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the configuration of an interlayer insulating film and a first main surface in an active region of the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 3]FIG. 3 is a cross-sectional view showing the configuration of the active region of the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing a configuration in the vicinity of the boundary between the active region and the termination region of the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 5] FIG. 5 is a first cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 2) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 3) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 4) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 9] FIG. 9 is a schematic diagram showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a configuration in the vicinity of the boundary between the active region and the termination region of the silicon carbide semiconductor device in accordance with the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a configuration in the vicinity of the boundary between the active region and the termination region of the silicon carbide semiconductor device in accordance with the third embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a configuration in the vicinity of the boundary between the active region and the termination region of the silicon carbide semiconductor device in accordance with the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be denoted by the same reference numerals, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are represented by brackets [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative index in crystallography is usually represented by placing a "-" (bar) above a number, but in this disclosure, a negative sign is placed before the number. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the silicon carbide semiconductor device. An XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the -Z direction may be referred to as downward, lower side, or bottom.

[0011] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region, the silicon carbide substrate having a first semiconductor region having a first conductivity type, a plurality of second semiconductor regions having a second conductivity type provided within the first semiconductor region, and a third semiconductor region having the second conductivity type provided within the active region, constituting the first main surface and having an annular shape in the plan view, the plurality of second semiconductor regions being aligned along a first axis parallel to the first main surface in the active region and the termination region, and in the termination region, a first inner edge of the first semiconductor region is in contact with the third semiconductor region and a first outer edge of the first semiconductor region is in contact with the termination region in the plan view. the fourth semiconductor region has a fifth semiconductor region constituting the first main surface and a sixth semiconductor region between the fifth semiconductor region and the second main surface, an effective concentration of the first impurity of the first conductivity type contained in the fifth semiconductor region is lower than an effective concentration of the first impurity contained in the sixth semiconductor region, the plurality of second semiconductor regions include seventh semiconductor regions located between the first inner edge and the first outer edge in the planar view, the seventh semiconductor region has an upper end surface between the first main surface and the second main surface and a lower end surface between the upper end surface and the second main surface, the first main surface and the upper end surface are separated from each other by the fifth semiconductor region, and some of the plurality of second semiconductor regions are electrically connected to the third semiconductor region.

[0012] Compared to when the effective concentration of the first impurity contained in the fifth semiconductor region is equal to the effective concentration of the first impurity contained in the sixth semiconductor region, the electric field applied to the second semiconductor region in contact with the third semiconductor region is reduced, thereby improving the breakdown voltage.

[0013] [2] In [1], the minimum value of the effective concentration of the first impurity in the sixth semiconductor region is 1×10 lower than the maximum value of the effective concentration of the first impurity in the fifth semiconductor region. 16 cm -3 In this case, the electric field applied to the second semiconductor region in contact with the third semiconductor region can be easily alleviated.

[0014] [3] In [1] or [2], the interface between the fifth semiconductor region and the sixth semiconductor region may be farther from the first main surface than the upper end surface and farther from the second main surface than the lower end surface, making it easier to form the fifth semiconductor region by ion implantation.

[0015] [4] In [3], the seventh semiconductor region may have an eighth semiconductor region in contact with the fifth semiconductor region and a ninth semiconductor region in contact with the sixth semiconductor region, and the effective concentration of the second impurity of the second conductivity type contained in the eighth semiconductor region may be higher than the effective concentration of the second impurity contained in the ninth semiconductor region. In this case, the fifth semiconductor region can be formed in multiple locations with the eighth semiconductor region sandwiched therebetween by a single ion implantation.

[0016] [5] In [1] or [2], the lower end surface may be farther from the second main surface than the interface between the fifth semiconductor region and the sixth semiconductor region. In this case, the effective concentration of the first conductivity type impurity can be reduced over a wide range in a direction perpendicular to the first main surface, which promotes depletion in the direction perpendicular to the first main surface when a high voltage is applied, making it easier to obtain a high breakdown voltage.

[0017] [6] In any one of [1] to [5], all of the second semiconductor regions may be located inside the first outer edge in the planar view. In this case, the effective concentration of the first conductivity type impurity can be reduced even in the vicinity of the seventh semiconductor region located at the outermost periphery, thereby promoting depletion in a direction parallel to the first main surface when a high voltage is applied, and making it easier to obtain a high breakdown voltage.

[0018] [7] In any one of [1] to [6], an insulating film may be provided covering the first main surface, and the first outer edge may be located inside a second outer edge of the insulating film in the plan view. In this case, excessive expansion of a depletion layer can be suppressed.

[0019] [8] In any one of [1] to [7], the second semiconductor regions may be provided at a constant pitch along the first axis, which makes it easier to obtain high uniformity in breakdown voltage within the silicon carbide semiconductor device.

[0020] [9] In any one of [1] to [8], the second semiconductor regions may extend along a second axis parallel to the first main surface and perpendicular to the first axis. In this case, the second semiconductor regions are easily formed uniformly.

[0021]

[10] In any of [1] to [9], the distance between the upper end surface and the lower end surface may be equal to or greater than half the thickness of the first semiconductor region. In this case, a high breakdown voltage can be easily obtained even if the concentration of the first impurity in the first semiconductor region is relatively high in the active region. Therefore, the on-resistance can be easily reduced.

[0022] [Embodiments of the present disclosure] (First embodiment) A first embodiment will be described. The first embodiment relates to a so-called vertical MOS (metal oxide semiconductor) field effect transistor (FET) using silicon carbide. This MOS FET is an example of a silicon carbide semiconductor device. FIG. 1 is a schematic diagram showing an overview of a silicon carbide substrate in the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a diagram showing the configuration of an interlayer insulating film and a first main surface in an active region of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing the configuration of the active region of the silicon carbide semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view showing the configuration near the boundary between the active region and the termination region of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 corresponds to region II in FIG. 1. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 1. A barrier metal film 84 is omitted in FIG. 4.

[0023] As shown in Figures 1 to 4, the silicon carbide semiconductor device 100 according to the first embodiment has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier metal film 84.

[0024] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 forms the first main surface 1, and the silicon carbide single crystal substrate 50 forms the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity (first conductivity type).

[0025] As shown in FIG. 1 , silicon carbide substrate 10 has active region 110 and termination region 120. Active region 110 has, for example, a square shape with rounded corners in a plan view perpendicular to first main surface 1. Active region 110 may also have a rectangular shape with rounded corners in a plan view. Termination region 120 surrounds active region 110 in a plan view. Termination region 120 is provided around active region 110 in a plan view. Termination region 120 has a first termination region 121 that contacts active region 110 in a direction parallel to the Y-axis, a second termination region 122 that contacts active region 110 in a direction parallel to the X-axis, and a third termination region 123 that contacts first termination region 121 and second termination region 122. First termination regions 121 are provided on the +Y and −Y sides of active region 110, second termination regions 122 are provided on the +X and −X sides of active region 110, and third termination regions 123 are provided at the four corners of silicon carbide substrate 10.

[0026] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[0027] The silicon carbide epitaxial layer 40 has a drift region 11, a body region 12, a source region 13, a p-type region 14 for superjunction, a contact region 16, and a contact region 18.

[0028] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50.

[0029] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity. The body region 12 is located within the active region 110. The body region 12 is provided on the drift region 11. The lower end surface of the body region 12 and the upper end surface of the drift region 11 are in contact with each other.

[0030] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is located within the active region 110. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 constitutes the first main surface 1.

[0031] A plurality of gate trenches 5 defined by side surfaces 3 and bottom surfaces 4 are provided on the first main surface 1. The gate trenches 5 are formed in the active region 110. The gate trenches 5 extend, for example, along the Y axis. A plurality of gate trenches 5 are also provided along the X axis at regular intervals (first pitch P1). The side surfaces 3 penetrate the source region 13, the body region 12, and part of the drift region 11, and reach the drift region 11. The bottom surfaces 4 are continuous with the side surfaces 3. The bottom surfaces 4 are located in the drift region 11. For example, the bottom surfaces 4 are parallel to the first main surface 1 and the second main surface 2. In a cross-sectional view perpendicular to the Y axis, the angle θ1 of the side surfaces 3 with respect to an imaginary plane 30 including the bottom surfaces 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surfaces 3 preferably have a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

[0032] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 is located within the active region 110. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. The contact region 18 constitutes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 and the source regions 13 may be alternately provided along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 may be provided intermittently along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis.

[0033] A plurality of gate trenches 5 may be arranged at regular intervals along the Y axis. When a plurality of gate trenches 5 are arranged at regular intervals along the Y axis, a part of the contact region 18 may be located between adjacent gate trenches 5 along the Y axis. A plurality of gate trenches 5 may be provided in an array.

[0034] The contact region 16 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 16 is located within the active region 110. The contact region 16 is formed simultaneously with the contact region 18, is made of the same material as the contact region 18, and has the same depth as the contact region 18. The contact region 16 also constitutes the first main surface 1. In a plan view, the contact region 16 is provided in an annular shape, and a plurality of gate trenches 5 and a gate electrode 82 (described below) are located inside the contact region 16. The outer edge of the contact region 16 is the boundary between the active region 110 and the termination region 120. The contact region 16 is an example of a third semiconductor region. In this disclosure, an annular shape includes a single closed curve shape other than a circular annular shape or an elliptical annular shape, such as a rounded rectangular shape.

[0035] The p-type region 14 contains p-type impurities such as aluminum and has p-type conductivity. The p-type region 14 is in the active region 110 and the termination region 120. The p-type region 14 is provided in the drift region 11. The p-type region 14 may extend along the Y-axis. Multiple p-type regions 14 are aligned along the X-axis. Multiple p-type regions 14 may be provided at a constant pitch along the X-axis. Multiple p-type regions 14 may be provided in a stripe pattern. The effective concentration of the p-type impurity in the p-type region 14 is, for example, 1×10 16 cm -3 5x10 or more 17 cm -3 The p-type region 14 is an example of a second semiconductor region. The X-axis is an example of a first axis, and the Y-axis is an example of a second axis.

[0036] As shown in FIG. 3 , a portion of the p-type region 14 is located between adjacent gate trenches 5 along the X-axis in a plan view perpendicular to the first main surface 1. A p-type region 14S, which is part of the p-type region 14 and is located between adjacent gate trenches 5 along the X-axis, is spaced apart from the gate trench 5. The body region 12 is exposed at the side surface 3 of the gate trench 5. The p-type region 14S is spaced apart from the gate trench 5 along the X-axis more than the body region 12 is. The p-type region 14S is located below the body region 12 and is in contact with the body region 12. The p-type region 14S overlaps the contact region 18 in a plan view perpendicular to the first main surface 1. The contact region 18 may penetrate the body region 12, and the p-type region 14S may be in contact with the body region 12 and the contact region 18. The contact region 18, the body region 12, and the p-type region 14S are electrically connected to one another.

[0037] 4, a p-type region 14T that is part of the p-type region 14 and is located below the contact region 16 is in contact with the contact region 16. The termination region 120 also has a p-type region 14.

[0038] In the active region 110, the drift region 11 is exposed to the side surface 3 and is in contact with the body region 12 and the p-type region 14. In the termination region 120, the drift region 11 forms the first main surface 1. The drift region 11 may be in contact with the silicon carbide single crystal substrate 50. The effective concentration of n-type impurities in the drift region 11 is, for example, 1×10 16 cm -3 5x10 or more 17 cm -3 The drift region 11 may include a current spreading region having a particularly high effective concentration of n-type impurities within the active region 110. The drift region 11 is an example of a first semiconductor region.

[0039] Along the Z axis, silicon carbide single crystal substrate 50 and drift region 11 are present between bottom surface 4 and second main surface 2, and the conductivity type of silicon carbide substrate 10 between bottom surface 4 and second main surface 2 is n-type. Along the Z axis, no semiconductor with p-type conductivity exists between bottom surface 4 and second main surface 2.

[0040] In the termination region 120, the drift region 11 has a fourth semiconductor region 24 that is annular in plan view. The fourth semiconductor region 24 has a first inner edge 24A and a first outer edge 24B. In plan view, the first inner edge 24A contacts the contact region 16, and the first outer edge 24B is within the termination region 120. The first outer edge 24B is located in the first termination region 121, the second termination region 122, and the third termination region 123. The fourth semiconductor region 24 has a fifth semiconductor region 25 and a sixth semiconductor region 26. The fifth semiconductor region 25 and the sixth semiconductor region 26 contact each other. The fifth semiconductor region 25 and the sixth semiconductor region 26 contact the p-type region 14. The fifth semiconductor region 25 constitutes the first main surface 1. The sixth semiconductor region 26 is located between the fifth semiconductor region 25 and the second main surface 2. The effective concentration of the n-type impurity contained in the fifth semiconductor region 25 is lower than the effective concentration of the n-type impurity contained in the sixth semiconductor region 26. For example, the effective concentration of the n-type impurity contained in the fifth semiconductor region 25 is 1×10 15 cm -3 Over 4×10 17 cm -3 The effective concentration of the n-type impurity contained in the sixth semiconductor region 26 is 1×10 16 cm -3 5x10 or more 17 cm -3 The effective concentration of n-type impurities does not need to be uniform in either the fifth semiconductor region 25 or the sixth semiconductor region 26. The effective concentration of n-type impurities contained in the fifth semiconductor region 25 is the average value of the effective concentrations of n-type impurities contained in the fifth semiconductor region 25, and the effective concentration of n-type impurities contained in the sixth semiconductor region 26 is the average value of the effective concentrations of n-type impurities contained in the sixth semiconductor region 26. The n-type impurities contained in the fifth semiconductor region 25 and the sixth semiconductor region 26 are an example of a first impurity.

[0041] The seventh semiconductor region 27, which is part of the p-type region 14 and is located between the first inner edge 24A and the first outer edge 24B in a plan view, has an eighth semiconductor region 28 and a ninth semiconductor region 29. The eighth semiconductor region 28 and the ninth semiconductor region 29 are in contact with each other. The ninth semiconductor region 29 is located between the eighth semiconductor region 28 and the second main surface 2. The eighth semiconductor region 28 is in contact with the fifth semiconductor region 25, and the ninth semiconductor region 29 is in contact with the sixth semiconductor region 26. The effective concentration of the p-type impurity contained in the eighth semiconductor region 28 is higher than the effective concentration of the p-type impurity contained in the ninth semiconductor region 29. For example, the effective concentration of the p-type impurity contained in the eighth semiconductor region 28 is 2×10 16 cm -3 More than 6 x 10 17 cm -3 The effective concentration of the p-type impurity contained in the ninth semiconductor region 29 is 1×10 16 cm -3 5x10 or more 17 cm -3 The effective concentration of p-type impurities does not need to be uniform in either the eighth semiconductor region 28 or the ninth semiconductor region 29. The effective concentration of p-type impurities contained in the eighth semiconductor region 28 is the average value of the effective concentrations of p-type impurities contained in the eighth semiconductor region 28, and the effective concentration of p-type impurities contained in the ninth semiconductor region 29 is the average value of the effective concentrations of p-type impurities contained in the ninth semiconductor region 29. The p-type impurities contained in the eighth semiconductor region 28 and the ninth semiconductor region 29 are an example of a second impurity.

[0042] The seventh semiconductor region 27 has an upper end surface 27A and a lower end surface 27B. The upper end surface 27A faces the first main surface 1, and the lower end surface 27B faces the second main surface 2. The upper end surface 27A and the first main surface 1 are separated from each other by a fifth semiconductor region 25 in the drift region 11. The distance between the upper end surface 27A and the lower end surface 27B is 1 μm or more. An interface 31 between the fifth semiconductor region 25 and the sixth semiconductor region 26 is farther from the first main surface 1 than the upper end surface 27A and farther from the second main surface 2 than the lower end surface 27B. The upper end surface of a portion of the p-type region 14 farther from the active region 110 than the seventh semiconductor region 27 in a plan view may be separated from the first main surface 1 by the drift region 11. The p-type region 14 can be formed, for example, by channeling implantation of p-type impurities into an n-type epitaxial layer.

[0043] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may also contact the source region 13 at the first main surface 1.

[0044] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y-axis. In a plan view perpendicular to the first main surface 1, the gate electrode 82 may overlap multiple gate trenches 5.

[0045] A gate insulating film 81 is also provided on the contact region 16, and an electrode film 85 is formed thereon. The electrode film 85 is formed simultaneously with the gate electrode 82, and is made of the same material as the gate electrode 82.

[0046] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A part of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.

[0047] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged such that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0048] Above the contact region 16, an interlayer insulating film 83 is provided on the gate insulating film 81 and the electrode film 85. A contact hole 91 is formed in the interlayer insulating film 83, reaching the electrode film 85, and a contact hole 92 is formed in the interlayer insulating film 83 and the gate insulating film 81, reaching the contact region 16. The silicon carbide semiconductor device 100 has a gate runner 63 and a source runner 64. The gate runner 63 and the source runner 64 are formed simultaneously with the source electrode 60 and are made of the same material as the source electrode 60. The gate runner 63 is electrically connected to the gate electrode 82 and the electrode film 85. The source runner 64 is electrically connected to the source electrode 60 and the contact region 16. In a plan view, the source runner 64 is provided in an annular shape, and the outer edge of the source runner 64 may coincide with the outer edge of the contact region 16. The gate runner 63 is provided between the source electrode 60 and the source runner 64.

[0049] The barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0050] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 provided in a contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13, the contact region 16, and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13, the contact region 16, and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum.

[0051] Silicon carbide semiconductor device 100 further includes silicon nitride film 87 and polyimide film 88. Silicon nitride film 87 covers the upper surface and side surfaces of interlayer insulating film 83, and polyimide film 88 covers the upper surface and side surfaces of silicon nitride film 87. An opening exposing a portion of source electrode 60 is formed in silicon nitride film 87 and polyimide film 88, and a source plating film 86 is formed inside this opening. Silicon nitride film 87 and polyimide film 88 also have an opening (not shown) exposing a portion of gate electrode (not shown) connected to gate runner 63, and a gate plating film (not shown) is formed inside this opening. A first outer edge 24B of fourth semiconductor region 24 is closer to active region 110 than a second outer edge 88B of polyimide film 88. That is, in a plan view, first outer edge 24B is located inside second outer edge 88B. Polyimide film 88 is an example of an insulating film.

[0052] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may also be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0053] A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and drift region 11. Also, a passivation film covering a portion of source electrode 60 may be provided.

[0054] The effective concentration of p-type impurities in the contact regions 16 and 18 may be higher than the effective concentration of p-type impurities in the body region 12. For example, the effective concentration of p-type impurities in the contact regions 16 and 18 may be, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The effective concentration of p-type impurities in the body region 12 is 5×10 17 cm -3 More than 1×10 18 cm -3 The following is the result.

[0055] The effective concentration of n-type impurities in the source region 13 may be higher than the effective concentration of p-type impurities in the body region 12. The effective concentration of n-type impurities in the source region 13 may be, for example, 1×10 19 cm -3 That's about it.

[0056] In the present disclosure, the effective concentration of a first conductivity type impurity is the concentration obtained by subtracting the concentration of a second conductivity type impurity from the concentration of the first conductivity type impurity, and the effective concentration of a second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentrations can be measured using, for example, a scanning capacitance microscope (SCM).

[0057] Drift region 11 has n-type conductivity, and body region 12 and p-type region 14 have p-type conductivity, so the boundary between drift region 11 and body region 12 and the boundary between drift region 11 and p-type region 14 are clear.

[0058] Next, a description will be given of a method for manufacturing silicon carbide semiconductor device 100. Figures 5 to 8 are cross-sectional views illustrating the method for manufacturing silicon carbide semiconductor device 100 according to the first embodiment.

[0059] First, as shown in Fig. 5, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0060] 6 , ions are implanted into silicon carbide epitaxial layer 40 to form p-type region 14. The ion implantation for forming p-type region 14 involves channeling implantation of p-type impurities such as aluminum. At this time, the upper end surface of p-type region 14 is spaced apart from the upper surface of silicon carbide epitaxial layer 40.

[0061] Next, as shown in FIG. 7, ions are implanted into the silicon carbide epitaxial layer 40 to form the body region 12, the source region 13, the contact region 16, and the contact region 18. As shown in FIG.

[0062] 8 , ions of a p-type impurity such as aluminum are implanted into the silicon carbide epitaxial layer 40 to form a fifth semiconductor region 25 in the silicon carbide epitaxial layer 40 and an eighth semiconductor region 28 in a portion of the p-type region 14. In this manner, the drift region 11 having the fourth semiconductor region 24 including the fifth semiconductor region 25 and the sixth semiconductor region 26 is obtained, and the seventh semiconductor region 27 including the eighth semiconductor region 28 and the ninth semiconductor region 29 is also obtained. As a result of the implantation of the p-type impurity, the dimension along the X-axis of the seventh semiconductor region 27 may become larger than the dimension along the X-axis of the p-type region 14 other than the seventh semiconductor region 27.

[0063] Next, a plurality of gate trenches 5 are formed. Next, a gate insulating film 81, a gate electrode 82, an electrode film 85, an interlayer insulating film 83, a barrier metal film 84, a silicon nitride film 87, a polyimide film 88, and a plating film 86 are formed (see FIGS. 3 and 4).

[0064] In this manner, silicon carbide semiconductor device 100 can be manufactured.

[0065] In silicon carbide semiconductor device 100, as described above, first inner edge 24A of fourth semiconductor region 24, which includes fifth semiconductor region 25 and sixth semiconductor region 26, contacts contact region 16. Furthermore, the effective concentration of n-type impurities contained in fifth semiconductor region 25 is lower than the effective concentration of n-type impurities contained in sixth semiconductor region 26, and first main surface 1 and upper end surface 27A of p-type seventh semiconductor region 27 are separated from each other by fifth semiconductor region 25. Therefore, the electric field applied to p-type region 14 in contact with contact region 16 is reduced compared to when the effective concentration of n-type impurities contained in fifth semiconductor region 25 is equivalent to the effective concentration of n-type impurities contained in sixth semiconductor region 26. This reduces the electric field applied to p-type region 14 in contact with contact region 16, thereby improving breakdown voltage. In particular, the electric field applied to the portion of multiple p-type regions 14 in contact with contact region 16 that is closest to termination region 120 is reduced.

[0066] The minimum effective concentration of the n-type impurity in the sixth semiconductor region 26 is 1×1016 cm -3 or more, the electric field applied to the p-type region 14 in contact with the contact region 16 is easily relaxed. The minimum value of the effective concentration of the n-type impurity in the sixth semiconductor region 26 is 5×10 16 cm -3 It can be larger than 1 x 10 17 cm -3 It may be larger than this.

[0067] When the interface 31 between the fifth semiconductor region 25 and the sixth semiconductor region 26 is farther from the first main surface 1 than the upper end surface 27A and farther from the second main surface 2 than the lower end surface 27B, the fifth semiconductor region 25 can be easily formed by ion implantation, etc. Furthermore, when the effective concentration of the p-type impurity contained in the eighth semiconductor region 28 is higher than the effective concentration of the p-type impurity contained in the ninth semiconductor region 29, the fifth semiconductor region 25 can be formed in multiple locations with the eighth semiconductor region 28 sandwiched therebetween by a single ion implantation.

[0068] When viewed from above, the first outer edge 24B is located inside the second outer edge 88B of the polyimide film 88, thereby preventing the depletion layer from expanding excessively.

[0069] When multiple p-type regions 14 are provided at a constant pitch along the X-axis, it is easy to obtain high uniformity in the breakdown voltage within silicon carbide semiconductor device 100. When multiple p-type regions 14 extend along the Y-axis, it is easy to form p-type regions 14 uniformly.

[0070] When the distance between the upper end surface 27A and the lower end surface 27B is equal to or greater than half the thickness of the drift region 11, a high breakdown voltage can be easily obtained even if the concentration of n-type impurities in the drift region 11 is relatively high within the active region 110. Therefore, the on-resistance can be easily reduced.

[0071] (Second embodiment) A second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the fourth semiconductor region. FIG. 9 is a schematic diagram showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the configuration near the boundary between the active region and the termination region of the silicon carbide semiconductor device according to the second embodiment. FIG. 10 corresponds to a cross-sectional view taken along line XX in FIG. 9. Barrier metal film 84 is omitted in FIG. 10.

[0072] As shown in FIGS. 9 and 10, in silicon carbide semiconductor device 200 according to the second embodiment, all of the plurality of p-type regions 14 are located inside first outer edge 24B of fourth semiconductor region 24 in plan view.

[0073] Other configurations of silicon carbide semiconductor device 200 are the same as those of silicon carbide semiconductor device 100. The second embodiment also provides the same effects as those of the first embodiment. Furthermore, in a plan view, all of the multiple p-type regions 14 are located inside first outer edge 24B of fourth semiconductor region 24, so that the effective concentration of n-type impurities is lower than in the first embodiment even in the vicinity of p-type region 14 located at the outermost periphery. Therefore, when a high voltage is applied between source electrode 60 and drain electrode 70, depletion is promoted in a direction parallel to first main surface 1, and a higher breakdown voltage is obtained.

[0074] (Third embodiment) A third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the fourth semiconductor region. FIG. 11 is a cross-sectional view showing the configuration of the vicinity of the boundary between the active region and the termination region of a silicon carbide semiconductor device according to the third embodiment. Like FIG. 4, FIG. 11 corresponds to a cross-sectional view taken along line IV-IV in FIG. 1. Barrier metal film 84 is omitted in FIG. 11.

[0075] 11 , in the silicon carbide semiconductor device 300 according to the third embodiment, a bottom end surface 27B of the seventh semiconductor region 27 is farther from the second main surface 2 than an interface 31 between the fifth semiconductor region 25 and the sixth semiconductor region 26. The entire seventh semiconductor region 27 is in contact with the fifth semiconductor region 25, and the seventh semiconductor region 27 is separated from the sixth semiconductor region 26 by the fifth semiconductor region 25. The entire seventh semiconductor region 27 is made up of the eighth semiconductor region 28 in the first embodiment, and the effective concentration of p-type impurities contained in the seventh semiconductor region 27 is, for example, 2×10 16 cm -3 More than 6 x 10 17 cm -3 The following is the result.

[0076] Other configurations of the silicon carbide semiconductor device 300 are the same as those of the silicon carbide semiconductor device 100. The third embodiment also provides the same effects as the first embodiment. Furthermore, because the bottom end surface 27B of the seventh semiconductor region 27 is farther from the second main surface 2 than the interface 31 between the fifth semiconductor region 25 and the sixth semiconductor region 26, the effective concentration of n-type impurities is lower than that of the first embodiment over a wide range in the direction perpendicular to the first main surface 1. Therefore, when a high voltage is applied between the source electrode 60 and the drain electrode 70, depletion is promoted in the direction perpendicular to the first main surface 1, and a higher breakdown voltage is obtained.

[0077] (Fourth embodiment) A fourth embodiment will be described. The fourth embodiment differs from the third embodiment mainly in the configuration of the fourth semiconductor region. FIG. 12 is a cross-sectional view showing the configuration of the vicinity of the boundary between the active region and the termination region of a silicon carbide semiconductor device according to the fourth embodiment. Like FIG. 10, FIG. 12 corresponds to a cross-sectional view taken along line XX in FIG. 9. Barrier metal film 84 is omitted in FIG. 12.

[0078] As shown in FIG. 12, in a silicon carbide semiconductor device 400 in accordance with the fourth embodiment, all of the plurality of p-type regions 14 are located inside a first outer edge 24B of a fourth semiconductor region 24 in plan view.

[0079] Other configurations of silicon carbide semiconductor device 400 are the same as those of silicon carbide semiconductor device 300. The fourth embodiment also provides the same effects as the second and third embodiments.

[0080] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0081] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5 Gate trench 10 Silicon carbide substrate 11 Drift Region 12 Body Region 13 Source Region 14, 14S, 14T p-type region 16, 18 Contact area 24 Fourth Semiconductor Region 24A First Inner Margin 24B First outer edge 25 5th Semiconductor Region 26 6th Semiconductor Region 27 Seventh Semiconductor Region 27A Top surface 27B Lower end surface 28 8th Semiconductor Region 29 9th Semiconductor Region 30 Virtual Plane 31 Interface 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 63 Gate Runner 64 Source Runner 70 drain electrode 81 Gate insulating film 82 gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Electrode membrane 86 Plating film 87 Silicon nitride film 88 Polyimide film 88B Second outer edge 90, 91, 92 contact holes 100, 200, 300, 400 Silicon carbide semiconductor device 110 Active area 120 Termination area 121 1st termination area 122 Second termination area 123 Third terminal area P1 First pitch θ1 angle

Claims

1. a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region; The silicon carbide substrate is a first semiconductor region having a first conductivity type; a plurality of second semiconductor regions provided within the first semiconductor region and having a second conductivity type; a third semiconductor region having the second conductivity type, being provided in the active region, constituting the first main surface, and having an annular shape in the plan view; and the second semiconductor regions are aligned along a first axis parallel to the first major surface in the active region and the termination region; In the termination region, the first semiconductor region has, in the plan view, a ring-shaped fourth semiconductor region having a first inner edge in contact with the third semiconductor region and a first outer edge in the termination region; The fourth semiconductor region is a fifth semiconductor region constituting the first major surface; a sixth semiconductor region between the fifth semiconductor region and the second major surface; and an effective concentration of the first impurity of the first conductivity type contained in the fifth semiconductor region is lower than an effective concentration of the first impurity contained in the sixth semiconductor region; the plurality of second semiconductor regions include a seventh semiconductor region located between the first inner edge and the first outer edge in the planar view, The seventh semiconductor region is an upper end surface between the first main surface and the second main surface; a lower end surface between the upper end surface and the second main surface; and the first main surface and the top surface are separated from each other by the fifth semiconductor region; a first semiconductor region electrically connected to the second semiconductor region; a second semiconductor region electrically connected to the second semiconductor region;

2. The minimum value of the effective concentration of the first impurity in the sixth semiconductor region is 1×10 lower than the maximum value of the effective concentration of the first impurity in the fifth semiconductor region. １６ cm －３ The silicon carbide semiconductor device according to claim 1 , wherein the silicon carbide semiconductor device has a capacitance of at least 100 kJ / cm 2 .

3. 3 . The silicon carbide semiconductor device according to claim 1 , wherein an interface between said fifth semiconductor region and said sixth semiconductor region is farther from said first main surface than said upper end surface and farther from said second main surface than said lower end surface.

4. The seventh semiconductor region is an eighth semiconductor region in contact with the fifth semiconductor region; a ninth semiconductor region in contact with the sixth semiconductor region; and 4 . The silicon carbide semiconductor device according to claim 3 , wherein an effective concentration of said second impurity of the second conductivity type contained in said eighth semiconductor region is higher than an effective concentration of said second impurity contained in said ninth semiconductor region.

5. 3 . The silicon carbide semiconductor device according to claim 1 , wherein said lower end surface is farther from said second main surface than an interface between said fifth semiconductor region and said sixth semiconductor region.

6. The silicon carbide semiconductor device according to claim 1 , wherein all of the second semiconductor regions are located inside the first outer edge in the plan view.

7. an insulating film covering the first main surface; The silicon carbide semiconductor device according to claim 1 , wherein the first outer edge is located inside a second outer edge of the insulating film in the plan view.

8. 3 . The silicon carbide semiconductor device according to claim 1 , wherein said plurality of second semiconductor regions are provided at a constant pitch along said first axis.

9. 3 . The silicon carbide semiconductor device according to claim 1 , wherein said plurality of second semiconductor regions extend along second axes parallel to said first main surface and perpendicular to said first axis.

10. 3 . The silicon carbide semiconductor device according to claim 1 , wherein a distance between said upper end surface and said lower end surface is equal to or greater than half a thickness of said first semiconductor region.

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