Display device and head mount display device

Abstract

To provide a head mount display device.SOLUTION: A display device and a head mount display device are provided. The display device includes: a first single crystal semiconductor substrate on which a plurality of first transistors are formed; a second single crystal semiconductor substrate which is arranged on the first single crystal semiconductor substrate, and on which a plurality of second transistors are formed; and a connection wiring layer arranged between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate. The second single crystal semiconductor substrate includes a display area where a plurality of light-emitting elements electrically connected to the second transistors are arranged, and a non-display area in the periphery of the display area. Further, the second single crystal semiconductor substrate includes a plurality of first open holes which are formed in the display area of the second single crystal semiconductor substrate, and in which first conductive vias are disposed by being connected respectively to the first transistors and the second transistors.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a display device and a head-mounted display device. [Background technology]

[0002] A head-mounted display device (HMD) is an image display device worn on a user's head in the form of glasses or a helmet, and focuses on a short distance in front of the user's eyes. The head-mounted display device can realize virtual reality (VR) or augmented reality (AR).

[0003] A head-mounted display device uses multiple lenses to magnify and display images displayed on a small display device. Therefore, the display device used in the head-mounted display device needs to provide high-resolution images, for example, images with a resolution of 3000 PPI (Pixels Per Inch) or more. For this reason, OLEDoS (Organic Light Emitting Diode on Silicon), a high-resolution small organic light-emitting display device, is used as the display device used in the head-mounted display device. OLEDoS is a device that displays images by arranging organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which CMOS (Complementary Metal Oxide Semiconductor) is arranged. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent Publication No. 2020-0123204 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide an improved display device and head-mounted display device.

[0006] The objectives of the present invention are not limited to those mentioned above, and other technical objectives not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] A display device according to one embodiment for solving the above problem includes a first single crystal semiconductor substrate having a plurality of first transistors formed thereon, a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate and having a plurality of second transistors formed thereon, and a connection wiring layer disposed between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate, wherein the second single crystal semiconductor substrate includes a display region in which a plurality of light-emitting elements electrically connected to the second transistors are disposed, and a non-display region around the display region, and includes a plurality of first through holes formed in the display region of the second single crystal semiconductor substrate and in which first conductive vias connected to the first transistors and the second transistors, respectively, are disposed.

[0008] The non-display area may include a first driving voltage wiring disposed in a common electrode contact region disposed on at least one side of the display area, and a second driving voltage wiring disposed in the display area, wherein the second transistor is connected to the second driving voltage wiring and the light-emitting element is connected to the first driving voltage wiring.

[0009] The planar area of ​​the first single crystal semiconductor substrate may be smaller than the planar area of ​​the second single crystal semiconductor substrate.

[0010] The connection wiring layer may include a plurality of first connection wirings connected to the first conductive vias, and a portion of the plurality of first connection wirings may not overlap the first single-crystal semiconductor substrate.

[0011] The second single crystal semiconductor substrate may include a pad region disposed on one side of the display region, and a plurality of second through holes disposed between the pad region and the display region.

[0012] The display device may include a first scan driver and a data driver disposed on the first single crystal semiconductor substrate and including the plurality of first transistors.

[0013] The pixel may include a first scan line disposed on the first single crystal semiconductor substrate and connected to the first transistor and the first scan driver, and a data line disposed on the first single crystal semiconductor substrate and connected to the first transistor and the data driver.

[0014] The second single crystal semiconductor substrate may include a plurality of second scan lines and a plurality of light emission control lines electrically connected to some of the plurality of second transistors.

[0015] The second single crystal semiconductor substrate may include a second scan driver disposed in the non-display area and connected to the plurality of second scan lines, and a light emitting driver disposed in the non-display area and connected to the light emitting control lines.

[0016] The second single crystal semiconductor substrate may include a plurality of third through holes in which conductive vias connected to the second scan lines are arranged, and a plurality of fourth through holes in which conductive vias connected to the light-emitting control lines are arranged, and the first single crystal semiconductor substrate may include a second scan driver connected to the second scan lines through conductive vias arranged in the third through holes, and a light-emitting driver connected to the light-emitting control lines through conductive vias arranged in the fourth through holes.

[0017] The third through holes and the fourth through holes may not overlap the first single-crystal semiconductor substrate.

[0018] The number of the third through holes may be the same as the number of the fourth through holes.

[0019] The connection wiring layer includes connection wiring connected to a plurality of conductive vias arranged in the plurality of third through holes and the plurality of fourth through holes, and a portion of each of the connection wirings may not overlap with the first single crystal semiconductor substrate.

[0020] The number of the first through holes may be the same as the number of the light emitting elements arranged in the display area.

[0021] The minimum line width of the first transistor may be smaller than the minimum line width of the second transistor.

[0022] A display device according to one embodiment for solving the above problem includes a first single crystal semiconductor substrate on which a plurality of first transistors are formed and a plurality of first scan lines and a plurality of data lines are arranged; a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate, on which a plurality of second transistors are formed and on which at least one driving voltage line connected to some of the plurality of second transistors is arranged; a display element layer disposed on the second single crystal semiconductor substrate and including a plurality of light-emitting elements; and a connection wiring layer disposed between the display element layer and the first single crystal semiconductor substrate, wherein the plurality of light-emitting elements are electrically connected to the driving voltage line, the first transistors, and the second transistors; the connection wiring layer includes a first connection wiring connected to a first conductive via disposed in a first through-hole penetrating the second single crystal semiconductor substrate, and the first conductive via is electrically connected to the first transistor and the second transistor.

[0023] The plurality of driving voltage lines may include a first driving voltage line connected to one electrode of the light emitting element, and a second driving voltage line electrically connected to the second transistor.

[0024] The display device may further include a plurality of second scan lines and a plurality of light emission control lines disposed on the second single crystal semiconductor substrate.

[0025] The planar area of ​​the first single crystal semiconductor substrate may be smaller than the planar area of ​​the second single crystal semiconductor substrate.

[0026] A head-mounted display device according to one embodiment for solving the above problem includes a frame that is worn on a user's body and corresponds to the left and right eyes, a plurality of display devices arranged on the frame, and lenses that are respectively arranged on the plurality of display devices, wherein the display devices include a first single crystal semiconductor substrate on which a plurality of first transistors are formed, a second single crystal semiconductor substrate that is arranged on the first single crystal semiconductor substrate and on which a plurality of second transistors are formed, and a connection wiring layer that is arranged between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate, and the second single crystal semiconductor substrate includes a display region in which a plurality of light-emitting elements electrically connected to the second transistors are arranged, and a non-display region around the display region, and includes a plurality of first through holes that are formed in the display region of the second single crystal semiconductor substrate and in which first conductive vias connected to the first transistors and the second transistors, respectively, are arranged.

[0027] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0028] According to the display device of one embodiment, it is possible to provide a display device and a head-mounted display device that are improved over conventional devices.

[0029] The effects of the embodiments are not limited to the above examples, and a wider variety of effects are included in this specification. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is an exploded perspective view of a display device according to an embodiment; [Figure 2] 2 is a plan view showing an example of a driving unit shown in FIG. 1. FIG. [Figure 3] FIG. 2 is a plan view showing an example of a display unit shown in FIG. [Figure 4] 1 is a block diagram illustrating a display device according to an embodiment. [Figure 5] FIG. 2 is an equivalent circuit diagram of one pixel according to an embodiment. [Figure 6] FIG. 2 is a diagram showing wiring arranged in a driving unit of a display device according to an embodiment. [Figure 7] 2 is a diagram showing connections between wiring and pixel circuits arranged in a display unit of a display device according to an embodiment; FIG. [Figure 8] 1 is a schematic cross-sectional view of a display device according to an embodiment. [Figure 9] FIG. 2 is a schematic diagram illustrating a rear view of a display device according to an embodiment. [Figure 10] 1 is a schematic cross-sectional view of a drive unit according to one embodiment; [Figure 11] 3 is a plan view illustrating first electrodes, light-emitting regions, and pixel defining layers of a plurality of sub-pixels arranged in a display area of ​​a display unit according to an embodiment; [Figure 12] 10 is a plan view illustrating first electrodes, light-emitting regions, and pixel defining layers of a plurality of sub-pixels arranged in a display area of ​​a display unit according to another embodiment. [Figure 13] FIG. 2 is a cross-sectional view showing a portion of a display unit according to an embodiment. [Figure 14] FIG. 10 is a block diagram showing an example of a display device according to another embodiment. [Figure 15] FIG. 15 is an equivalent circuit diagram of one pixel of the display device of FIG. [Figure 16] FIG. 16 is a plan view showing an example of a drive unit of the display device of FIGS. 14 and 15. [Figure 17] FIG. 16 is a plan view showing an example of a display unit of the display device of FIGS. 14 and 15. [Figure 18] 18 is a plan view showing the arrangement of a plurality of wires arranged in the display unit of FIG. 17. [Figure 19] FIG. 18 is a schematic diagram showing the back of the display device of FIGS. 16 and 17. [Figure 20] FIG. 10 is a plan view showing an example of a drive unit of a display device according to still another embodiment. [Figure 21] 21 is a plan view showing an example of a display unit of the display device of FIG. 20. FIG. [Figure 22]FIG. 22 is a schematic diagram showing the rear of the display device of FIGS. 20 and 21. [Figure 23] FIG. 22 is a schematic cross-sectional view of the display device of FIGS. 20 and 21. [Figure 24] FIG. 22 is a cross-sectional view showing a part of the display unit of the display device of FIGS. 20 and 21. [Figure 25] 1 is a perspective view showing a head-mounted display device according to an embodiment; [Figure 26] FIG. 26 is an exploded perspective view showing an example of the head-mounted display device of FIG. 25. [Figure 27] 1 is a perspective view showing a head-mounted display device according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0031] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided solely for the purpose of complete disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0032] When an element or layer is referred to as being "on" another element or layer, this includes being directly on top of or having intervening layers or elements. Similarly, when references are made to "below," "left," and "right," this includes being directly adjacent to or having intervening layers or elements. Like reference numerals throughout the specification refer to like elements.

[0033] Although terms such as "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that a "first" component referred to below may be a "second" component within the technical concept of the present invention.

[0034] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0035] FIG. 1 is an exploded perspective view of a display device according to an embodiment.

[0036] Referring to FIG. 1, a display device 10 according to an embodiment is a device for displaying moving images or still images. The display device 10 according to an embodiment may be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). For example, the display device 10 may be applied to a television, a notebook computer, a monitor, a billboard, or a display unit of an Internet of Things (IoT). Alternatively, the display device 10 may be applied to a smart watch, a watch phone, or a head-mounted display device (HMD) for implementing virtual reality and augmented reality.

[0037] The display device 10 according to one embodiment may include a driver unit 100, a display unit 200, and a circuit board 300. The display device 10 may further include a protective layer 900 disposed around the driver unit 100.

[0038] The driver 100 may have a planar shape similar to a rectangle. For example, the driver 100 may have a planar shape similar to a rectangle having one side in a first direction DR1 and another side in a second direction DR2 intersecting the first direction DR1. The driver 100 may have different lengths for the one side in the first direction DR1 and the other side in the second direction DR2. In the driver 100, the corner where the one side in the first direction DR1 intersects with the other side in the second direction DR2 may be rounded or right-angled to have a predetermined curvature. The planar shape of the driver 100 is not limited to a rectangle and may be formed in various shapes such as a polygon, a circle, or an ellipse.

[0039] The display unit 200 is disposed on the driver 100. In the display device 10, the driver 100 and the display unit 200 may be bonded to each other. In the example shown in FIG. 1 , the display unit 200 may have a shape similar to a square, unlike the driver 100. For example, the driver 100 may have a planar shape similar to a square, in which one side in a first direction DR1 and the other side in a second direction DR2 intersecting the first direction DR1 have the same length. The planar shape of the display unit 200 is not limited to a rectangle, and may be formed into various shapes such as other polygons, circles, or ellipses. The planar shape of the display device 10 may follow the planar shape of the display unit 200, but is not limited thereto.

[0040] According to an embodiment, the display device 10 may have a display unit 200 with a larger planar area than the driver unit 100. The display device 10 may include a driver unit 100 and a display unit 200 that include different substrates, and the drive unit 100 and the display unit 200 may have different areas. The elements formed in the driver unit 100 and the elements formed in the display unit 200 may be different from each other, and the elements may be formed separately on different substrates. The display device 10 may be manufactured by forming a plurality of elements with different sizes, line widths, and manufacturing processes on different substrates and then bonding them together, which has the advantage of improving product performance and manufacturing yield.

[0041] The circuit board 300 is electrically connected to the pads in the pad region of the display unit 200 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Although FIG. 1 shows the circuit board 300 unfolded, the circuit board 300 can be bent. In this case, one end of the circuit board 300 is disposed on the lower surface of the driver unit 100. The other end of the circuit board 300 can be connected to the pads in the pad region of the display unit 200 using a conductive adhesive member. In another embodiment, the circuit board 300 can be attached to the lower surface of the driver unit 100.

[0042] The protective layer 900 surrounds the driver unit 100 and is disposed on the lower surface of the display unit 200. The protective layer 900 can reduce a step due to the difference in area between the driver unit 100 and the display unit 200, and can also protect the driver unit 100 and the display unit 200. For example, the protective layer 900 is formed to surround the side and lower surface of the driver unit 100, so that the upper surface of the driver unit 100 and the upper surface of the protective layer 900 can be roughly flush with each other. This can reduce a step due to the difference in area between the driver unit 100 and the display unit 200. As a result, by placing the display unit 200, which has a larger area than the driver unit 100, on the upper surface of the protective layer 900 as well as the upper surface of the driver unit 100, the display unit 200 can be appropriately positioned on the driver unit 100 while suppressing the influence of the step.

[0043] Fig. 2 is a plan view showing an example of the drive unit shown in Fig. 1. Fig. 3 is a plan view showing an example of the display unit shown in Fig. 1.

[0044] 2 and 3, the driver 100 of the display device 10 may include driving circuit elements of the display device 10. The driver 100 may include a first single-crystalline semiconductor substrate 110 and a driving circuit 400, a gate driver 600, a data driver 700, and a first pixel circuit 810 formed on the first single-crystalline semiconductor substrate 110. The gate driver 600 may include a scan driver.

[0045] The first single-crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A plurality of first transistors may be formed on the first single-crystal semiconductor substrate 110, and the plurality of first transistors may be electrically connected to each other to form the driving circuit unit 400, the gate driver 600, the data driver 700, and the first pixel circuit unit 810. The first transistors may be formed using a semiconductor process. For example, the plurality of transistors may be formed using CMOS (Complementary Metal Oxide Semiconductor) transistors.

[0046] In the drawing, in a plan view, the first pixel circuit unit 810 is disposed on the other side of the driver 100 in the second direction DR2, that is, the upper side; the data driver 700, the driver circuit unit 400, and the signal terminal area TDA are disposed on one side of the driver 100 in the second direction DR2, that is, the lower side; and the gate driver 600 is disposed on one side of the first pixel circuit unit 810 in the first direction DR1, that is, the right side. However, this is not limited thereto. The positions of the driver 100, the driver circuit unit 400, the gate driver 600, and the data driver 700 may be variously modified depending on the design structure of the plurality of circuit elements formed on the first single-crystal semiconductor substrate 110.

[0047] The first pixel circuit unit 810 may include a plurality of first transistors, and a plurality of scan lines (GWL in FIG. 6) and data lines (DL in FIG. 6) electrically connected to the first transistors. The first transistors are electrically connected to the first scan lines GWL and data lines DL to form pixel circuits (PXC, pixel circuits in FIG. 5) for the sub-pixels SP1, SP2, and SP3.

[0048] The signal terminal area TDA has a plurality of signal terminals STD arranged in a first direction DR1. The signal terminals STD are electrically connected to the display unit 200, and thus may be electrically connected to the circuit board 300. The signal terminals STD transmit electrical signals applied from the circuit board 300 to the driving circuit unit 400, the gate driver 600, and the data driver 700.

[0049] The display unit 200 may include a second single-crystal semiconductor substrate 210, and a plurality of pixels PX and a second pixel circuit unit 820 formed on the second single-crystal semiconductor substrate 210. The display unit 200 may include a display area DAA in which the plurality of pixels PX are arranged and a non-display area NA therearound. The display unit 200 may include a first through-hole area TSA1, a pad area PDA, and a common electrode contact area CTA arranged in the non-display area NA. The common electrode contact area CTA may be arranged on both sides of the non-display area NA in a first direction DR1, i.e., on the left and right sides.

[0050] The second single-crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A plurality of second transistors may be formed on the second single-crystal semiconductor substrate 210, and the plurality of second transistors may be electrically connected to each other to form pixel circuits for emitting light from the plurality of pixels PX. The second transistors may be formed using a semiconductor process. For example, the plurality of transistors may be formed using CMOS (Complementary Metal Oxide Semiconductor) transistors.

[0051] The display area DAA is provided with a plurality of pixels PX, each including a light-emitting element. Each of the pixels PX may include three subpixels, e.g., a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. The three subpixels SP1, SP2, and SP3 constitute a pixel PX and display a color. However, without being limited thereto, a pixel PX may include three or more subpixels. The subpixels SP may be arranged in a matrix in a first direction DR1 and a second direction DR2. Each of the subpixels SP1, SP2, and SP3 may be electrically connected to a pixel circuit (the pixel circuit of FIG. 5) including a plurality of second transistors formed on the second single-crystal semiconductor substrate 210. Each of the subpixels SP1, SP2, and SP3 includes a light-emitting element, which can emit light in response to an electrical signal applied from the pixel circuit arranged in the display area DAA.

[0052] Some of the sub-pixels SP1, SP2, and SP3 arranged in the display area DAA of the display unit 200 overlap with the driver 100 in the thickness direction, and other parts do not overlap with the driver 100 (other parts do not overlap with the driver 100). The driver 100 has an area smaller than that of the display unit 200 and is arranged adjacent to one side of the display unit 200. Therefore, only some of the sub-pixels SP1, SP2, and SP3 overlap with the driver 100 in the thickness direction.

[0053] The second pixel circuit unit 820 may include a plurality of second transistors formed on the second single-crystal semiconductor substrate 210. The plurality of second transistors may be formed by a semiconductor process. For example, the plurality of second transistors may be formed of CMOS transistors. The second pixel circuit unit 820 may include a plurality of second transistors and driving voltage lines ("VDL" and "VSL" in FIG. 5) electrically connected to the second transistors. The second transistors may be electrically connected to the first transistors of the driving unit 100, the driving voltage lines VDL and VSL of the display unit 200, and the light-emitting elements, thereby forming pixel circuits (PXCs, pixel circuits in FIG. 5) to which the sub-pixels SP1, SP2, and SP3 are connected.

[0054] According to an embodiment, the display unit 200 of the display device 10 may include a plurality of first through holes TSV1 overlapping the display area DAA. The first through holes TSV1 are formed to penetrate the second single-crystal semiconductor substrate 210 of the display unit 200. The first through holes TSV1 form a connection path between the first pixel circuit unit 810 of the driving unit 100 and the second pixel circuit unit 820 of the display unit 200. The plurality of first through holes TSV1 may be formed to correspond to each of the subpixels SP1, SP2, and SP3 of the display unit 200. In some embodiments, the number of first through holes TSV1 may be the same as the number of subpixels SP1, SP2, and SP3, and the first through holes TSV1 may be formed to overlap the subpixels SP1, SP2, and SP3, respectively. Alternatively, the number of first through holes TSV1 may be the same as the number of light-emitting elements, but is not limited thereto. The plurality of first through-holes TSV1 correspond to the sub-pixels SP1, SP2, and SP3, respectively, but do not necessarily have to be formed so as to overlap each other. As will be described later, the plurality of sub-pixels SP1, SP2, and SP3 can be connected to a pixel circuit (PXC in FIG. 5) formed by elements of the first pixel circuit unit 810 and the second pixel circuit unit 820 connected via the first through-holes TSV1.

[0055] In a display device 10 according to an embodiment, transistors (T1 and T2 in FIG. 5) included in a pixel circuit PXC and some of the wiring lines connected thereto may be disposed on different single-crystal semiconductor substrates. The display device 10 includes a driver 100 and a display unit 200, each of which includes a different single-crystal semiconductor substrate, and the transistors and wiring lines of the pixel circuit PXC are disposed separately in the driver 100 and the display unit 200, respectively. By disposing some circuit elements and wiring lines of the pixel circuit PXC separately on different single-crystal semiconductor substrates, the display device 10 can eliminate the difficulty of layout design due to high integration in a small area and prevent the formation of parasitic capacitance between adjacent elements. In addition, unnecessary current paths formed in the driver 100 and the display unit 200 can be eliminated, thereby efficiently preventing voltage drops. A more detailed description will be given below with reference to other drawings.

[0056] The non-display area NA is arranged to surround the display area DAA. The non-display area NA is an area where no pixels PX are arranged and therefore no light is emitted. The non-display area NA is also arranged with a common electrode contact area CTA, a pad area PDA, and a plurality of first through-hole areas TSA1.

[0057] The common electrode contact areas CTA are disposed on both sides of the display area DAA in the first direction DR1 in the non-display area NA. For example, the common electrode contact areas CTA are disposed on the left and right sides of the display area DAA. The common electrode contact areas CTA may be areas where the second electrodes ("CAT" in FIG. 13) of the light-emitting elements disposed in the sub-pixels SP1, SP2, and SP3 of the display area DAA are electrically connected to the first driving voltage line VSL.

[0058] The first through-hole region TSA1 is disposed in the non-display area NA on one side of the display area DAA in the second direction DR2. For example, in a plan view, the first through-hole region TSA1 is disposed below the display area DAA, between the display area DAA and the pad area PDA. A plurality of second through-holes TSV2 are formed in the first through-hole region TSA1. The second through-holes TSV2 may be connection paths for signal connection wiring that electrically connects the signal terminals STD of the driver 100 to the circuit board 300. The plurality of second through-holes TSV2 are formed to correspond to the signal terminals STD of the driver 100, respectively. In some embodiments, the number of second through-holes TSV2 may be the same as the number of signal terminals STD, and the second through-holes TSV2 may be formed to overlap the signal terminals STD. However, this is not limited thereto. The circuit board 300 may be electrically connected to the signal terminals STD of the driver 100 via the signal connection wiring disposed in the plurality of pads PD and the second through-holes TSV2.

[0059] In a plan view, the pad area PDA is disposed on one side of the display area DAA in the second direction DR2, i.e., the lower side. A plurality of pads PD are disposed in the pad area PDA and are arranged in the first direction DR1. A circuit board 300 is attached to the plurality of pads PD. The pads PD are electrically connected to the circuit board 300 and transmit electrical signals applied to the circuit board 300 to the driver 100.

[0060] FIG. 4 is a block diagram showing a display device according to an embodiment.

[0061] 4, the driving circuit unit 400 may include a timing control circuit and may further include various circuits involved in driving the display device 10, such as a gamma circuit and a logic circuit. The driving circuit unit 400 may include driving circuit transistors formed on the first single crystal semiconductor substrate 110.

[0062] The driving circuit unit 400 receives digital video data and timing signals from the outside. The timing control circuit generates a scan timing control signal SCS and a data timing control signal DCS for controlling the display unit 200 in response to the timing signals. The timing control circuit outputs the scan timing control signal SCS to the gate driving unit 600. The timing control circuit outputs the digital video data DATA and the data timing control signal DCS to the data driving unit 700.

[0063] The power supply unit generates a plurality of panel driving voltages in response to an external power supply voltage. For example, the power supply circuit generates a first driving voltage VSS and a second driving voltage VDD and supplies them to the plurality of pixels PX.

[0064] The scan timing control signal SCS, the digital video data DATA, and the data timing control signal DCS of the driving circuit unit 400 are supplied to the pixels PX. The first driving voltage VSS and the second driving voltage VDD of the power supply unit are also supplied to the pixels PX.

[0065] The gate driver 600 may include a plurality of scan transistors formed on the first single crystal semiconductor substrate 110. The plurality of scan transistors may be formed by a semiconductor process. For example, the plurality of scan transistors may be formed of a CMOS transistor. The gate driver 600 receives a scan timing control signal SCS from the driver circuit unit 400. The scan driver of the gate driver 600 may generate scan signals in response to the scan timing control signal SCS from the driver circuit unit 400 and sequentially output the scan signals to the first scan lines GWL.

[0066] The data driver 700 receives digital video data DATA and a data timing control signal DCS from the driver circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage in response to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by a write scan signal from the gate driver 600, and data voltages are supplied to the selected sub-pixels SP1, SP2, and SP3.

[0067] FIG. 5 is an equivalent circuit diagram of one pixel according to one embodiment.

[0068] 5, the pixel circuits PXC of the subpixels SP1, SP2, and SP3 are connected to the first scan line GWL and the data line DL. The pixel circuits PXC may be connected to a first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied and a second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied. That is, the first driving voltage line VSL may be a low potential voltage line, and the second driving voltage line VDL may be a high potential voltage line. In this case, the first driving voltage VSS may be lower than the second driving voltage VDD.

[0069] The pixel circuits PXC of the sub-pixels SP1, SP2, and SP3 include a plurality of transistors T1 and T2, a light emitting element (LE), and a first capacitor C1.

[0070] The light-emitting element LE emits light in response to a driving current Ids flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE is proportional to the driving current Ids. The light-emitting element LE is disposed between the first transistor T1 and the first driving voltage line VSL. A first electrode of the light-emitting element LE may be connected to the drain electrode of the first transistor T1, and a second electrode of the light-emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be, but is not limited to, an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0071] The first transistor T1 is a drive transistor that controls a source-drain current (Ids, hereinafter referred to as a "drive current") flowing between its source electrode and drain electrode in response to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the light-emitting element LE.

[0072] The second transistor T2 is disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal on the first scan line GWL to connect one electrode of the first capacitor C1 to the data line DL, thereby allowing the data voltage of the data line DL to be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the first scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0073] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 has one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1. The first node N1 is the junction of the gate electrode of the first transistor T1, the source electrode of the second transistor T2, and the other electrode of the first capacitor C1.

[0074] According to an embodiment, in the display device 10, the first transistor T1, the light-emitting element LE, the first driving voltage line VSL, and the second driving voltage line VDL are arranged in the display unit 200, and the second transistor T2 is arranged in the driving unit 100. The second transistor T2 is formed on the first single-crystal semiconductor substrate 110 of the driving unit 100, and the first transistor T1 is formed on the second single-crystal semiconductor substrate 210 of the display unit 200. The second transistor T2 may be connected to the first node N1 through a first through-hole TSV1 formed in the second single-crystal semiconductor substrate 210. Accordingly, the data line DL and the first scan line GWL are arranged in the first pixel circuit unit 810 of the driving unit 100, and the driving voltage lines VSL and VDL are arranged in the second pixel circuit unit 820 of the display unit 200.

[0075] Each of the first and second transistors T1 and T2 may be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first and second transistors T1 and T2 may be a P-type MOSFET, but is not limited thereto. Each of the first and second transistors T1 and T2 may be an N-type MOSFET. Alternatively, some of the first and second transistors T1 and T2 may be P-type MOSFETs, and the remaining transistors may be N-type MOSFETs.

[0076] Although Fig. 5 shows that the pixel circuits PXC of the subpixels SP1, SP2, and SP3 include two transistors T1 and T2 and one capacitor C1, the equivalent circuit diagram of the subpixels SP is not limited to that shown in Fig. 5. For example, the number of transistors and the number of capacitors in the pixel circuit PXC may be greater than those shown in Fig. 5.

[0077] Fig. 6 is a diagram showing wiring arranged in a drive unit of a display device according to an embodiment, and Fig. 7 is a diagram showing connections between wiring arranged in a display unit of a display device according to an embodiment and pixel circuits.

[0078] 6 and 7, the driver 100 of the display device 10 includes a plurality of first scan lines GWL and a plurality of data lines DL.

[0079] The plurality of first scan lines GWL extend in a first direction DR1 and are spaced apart in a second direction DR2, and the plurality of data lines DL extend in the second direction DR2 and are spaced apart in the first direction DR1. The plurality of data lines DL extend from a data driver 700 disposed below the display area DAA, and the plurality of first scan lines GWL extend from a gate driver 600 disposed on the right side of the display area DAA. Each of the plurality of first scan lines GWL and data lines DL may be connected to a second transistor T2 formed in the first pixel circuit unit 810.

[0080] The display unit 200 of the display device 10 has a first drive voltage line VSL and a second drive voltage line VDL arranged therein.

[0081] The first driving voltage line VSL may include a trunk line arranged in the common electrode contact area CTA and a plurality of horizontal lines branching from the trunk line in the first direction DR1 and arranged in the display area DAA. The trunk line of the first driving voltage line VSL may be connected to pads PD in the pad area PDA. The second driving voltage line VDL may include a plurality of vertical lines arranged in the display area DAA and horizontal lines connected to the plurality of vertical lines in the non-display area NA. The vertical lines of the second driving voltage line VDL may be connected to pads PD in the pad area PDA. In the display area DAA, the plurality of horizontal lines of the first driving voltage line VSL and the plurality of vertical lines of the second driving voltage line VDL are arranged in a mesh shape.

[0082] The second pixel circuit unit 820 arranged in the display area DAA includes a plurality of first transistors T1 and first capacitors C1. The first transistors T1 and the first capacitors C1 may be electrically connected to the second transistors T2 of the driving unit 100 via first through-holes TSV1. The first transistors T1 may be electrically connected to the light-emitting elements LE arranged in a display element layer ("EML" in FIG. 13) described later. The first transistors T1 may be electrically connected to the second driving voltage line VDL, and the light-emitting elements LE may be electrically connected to the first driving voltage line VSL. The first transistors T1, the second transistors T2, and the first capacitors C1 may form pixel circuits PXC corresponding to the sub-pixels SP1, SP2, and SP3 of the display device 10, which may be connected to the driving voltage lines VSL and VDL, respectively.

[0083] Fig. 8 is a schematic cross-sectional view of a display device according to an embodiment. Fig. 9 is a schematic diagram showing the back surface of a display device according to an embodiment. Fig. 8 shows a schematic connection relationship of routing wiring RM1, RM2 that electrically connects between the display unit 200 and the driver unit 100, and Fig. 9 shows the arrangement of through-holes TSV1, TSV2 and routing wiring RM1, RM2 as viewed from the back surface of the display device 10.

[0084] 8 and 9 in addition to Figures 2 and 3, a display device 10 according to an embodiment may include a driving unit 100 including a first single crystal semiconductor substrate 110 and a driving circuit layer 120 disposed on the first single crystal semiconductor substrate 110, and a display unit 200 including a second single crystal semiconductor substrate 210 and a second pixel circuit unit 820 and a display layer 230 disposed on the second single crystal semiconductor substrate 210. The display device 10 may include two different single crystal semiconductor substrates 110 and 210 overlapping each other in a third direction DR3, which is a thickness direction of the display device 10.

[0085] The driver 100 may include circuit elements necessary for emitting light from the light-emitting elements included in the display layer 230 of the display unit 200. As described above, the driver circuit layer 120 of the driver 100 may include the driver circuit 400, the gate driver 600, the data driver 700, the first pixel circuit 810, etc., and the circuit elements constituting these, for example, the second transistor T2 and the scan transistor, may be formed using CMOS on the first single-crystal semiconductor substrate 110. In addition, the driver circuit layer 120 is provided with a plurality of first scan lines GWL and data lines DL.

[0086] The display unit 200 may include some circuit elements necessary for the light emitting element to emit light and a plurality of light emitting elements that emit light to display an image on the display device 10. The display unit 200 may include a second pixel circuit unit 820 in which circuit elements constituting a pixel circuit PXC are arranged. The second pixel circuit unit 820 includes some circuit elements constituting the pixel circuit, for example, the first transistor T1 and the first capacitor C1 of FIG. 5, and is also provided with a plurality of driving voltage lines VSL and VDL. The first transistor T1 may be formed using CMOS on the second single-crystal semiconductor substrate 210. The light emitting element is electrically connected to the driving circuit layer 120 of the driving unit 100 or the circuit elements formed in the first pixel circuit unit 810 and the second pixel circuit unit 820 of the display unit 200 to emit light.

[0087] According to an embodiment, in the display device 10, the planar area of ​​the driver 100 or the first single crystalline semiconductor substrate 110 may be smaller than the planar area of ​​the display unit 200 or the second single crystalline semiconductor substrate 210. The plurality of transistors formed in the driver 100 may be formed using a semiconductor microfabrication process and may have very small sizes and line widths. The driver 100 can accommodate a large number of circuit elements with high integration, which has the advantage of reducing power consumption due to the miniaturization of the elements.

[0088] Furthermore, since the driver unit 100 includes only circuit elements formed using CMOS on the first single crystal semiconductor substrate 110 and does not include light emitting elements, it is sufficient to provide only enough space to accommodate elements formed using a microfabrication process. The first single crystal semiconductor substrate 110 has a sufficient area even though it is smaller than the second single crystal semiconductor substrate 210, and therefore multiple driver units 100 can be manufactured on a single wafer substrate on which the process of forming the driver circuit layer 120 is performed, thereby improving manufacturing yield. In particular, since the driver unit 100 is manufactured using expensive semiconductor processes, improving manufacturing yield of the driver unit 100 can also have a cost-reducing effect. Furthermore, the display unit 200 can have multiple light emitting elements formed on the second single crystal semiconductor substrate 210, which has a relatively large area, thereby realizing a high-resolution display device.

[0089] The display device 10 may include a connection wiring layer 500 disposed between the second single-crystal semiconductor substrate 210 of the display unit 200 and the drive circuit layer 120 of the drive unit 100. The connection wiring layer 500 is disposed on the lower surface of the second single-crystal semiconductor substrate 210. The connection wiring layer 500 has portions of a plurality of routing wires RM1 and RM2 disposed thereon, and the routing wires RM1 and RM2 connect the second pixel circuit unit 820 of the display unit 200 and the circuit board 300 to the drive unit 100. The drive circuit layer 120 of the drive unit 100 is electrically connected to the display unit 200 and the circuit board 300 via the routing wires RM1 and RM2 of the connection wiring layer 500, and transmits an electrical signal for light emission.

[0090] The first routing wiring RM1 may be connected to the second pixel circuit unit 820 of the display unit 200 and the first pixel circuit unit 810 of the driving unit 100. In one embodiment, the display device 10 includes a plurality of first through-holes TSV1 arranged corresponding to the subpixels SP1, SP2, and SP3 of the display unit 200, and the first routing wiring RM1 may be arranged in the first through-holes TSV1 to connect the first pixel circuit unit 810 and the second pixel circuit unit 820. For example, the first routing wiring RM1 may connect the second transistor T2 of the first pixel circuit unit 810 and the first transistor T1 of the second pixel circuit unit 820. The first through-holes TSV1 may be arranged throughout the second pixel circuit unit 820 of the display unit 200, which has a large area, while the first pixel circuit unit 810 of the driving unit 100 may have a relatively small area. The first routing wiring RM1 may include conductive vias ("RVA1" in FIG. 13) arranged throughout the large-area display unit 200 and connection wiring ("RML1" in FIG. 13) that connects these to the small-area first pixel circuit unit 810. The distance between the first routing wiring RM1 and other adjacent first routing wiring RM1 in a plan view may be narrower in the portion overlapping with the drive unit 100 than in the display area DAA.

[0091] In some embodiments, some of the multiple first through holes TSV1 overlap with the driving unit 100 in the thickness direction, and other parts do not overlap with the driving unit 100 in the thickness direction. The first routing wiring RM1 arranged in the first through holes TSV1 that do not overlap with the driving unit 100 has a portion of the connection wiring ("RML1" in FIG. 13) that does not overlap with the driving unit 100. However, the arrangement of the first through holes TSV1 may change depending on the position of the layer in which the connection wiring RML1 of the first routing wiring RM1 is arranged.

[0092] According to one embodiment, the number of first through holes TSV1 may be the same as the number of subpixels SP1, SP2, and SP3 arranged in the display area DAA. For example, the subpixels SP1, SP2, and SP3 are arranged in the first direction DR1 and the second direction DR2 in the display area DAA, and the first through holes TSV1 are also arranged in the first direction DR1 and the second direction DR2, corresponding to each of the subpixels SP1, SP2, and SP3 in a one-to-one relationship. The first through holes TSV1 are formed to overlap each of the subpixels SP1, SP2, and SP3. The number of first routing wirings RM1 may also be the same as the number of subpixels SP1, SP2, and SP3.

[0093] The plurality of second through holes TSV2 are arranged in the first through hole area TSA1 of the display unit 200 and are formed to overlap the signal terminal area TDA of the driver 100. Second routing wiring RM2 connected to the signal terminals STD of the driver 100 is arranged in the second through holes TSV2. Unlike the first through holes TSV1, the second through holes TSV2 may be formed to overlap the signal terminals STD of the driver 100, respectively. Therefore, the second routing wiring RM2 may also correspond to the signal terminals STD, respectively, and be arranged to overlap therewith. The second routing wiring RM2 may be wiring that transmits signals applied from the circuit board 300 to the driver 100.

[0094] Hereinafter, the structures of the driving circuit layer 120 of the driving unit 100 and the display layer 230 of the display unit 200 will be described in detail with reference to other drawings.

[0095] FIG. 10 is a schematic cross-sectional view of a drive unit according to one embodiment.

[0096] Referring to FIG. 10, the driver 100 may include a first single-crystal semiconductor substrate 110 and a driver circuit layer 120 disposed thereon.

[0097] The first single crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first single crystal semiconductor substrate 110 may be a substrate doped with a first type impurity. A plurality of well regions WA are disposed on the upper surface of the first single crystal semiconductor substrate 110. The plurality of well regions WA may be regions doped with a second type impurity. The second type impurity may be different from the first type impurity. For example, if the first type impurity is a p-type impurity, the second type impurity may be an n-type impurity. Alternatively, if the first type impurity is an n-type impurity, the second type impurity may be a p-type impurity.

[0098] Each of the plurality of well regions WA includes a source region SA corresponding to the source electrode of the first transistor PTR1, a drain region DA corresponding to the drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0099] A lower insulating film BINS is disposed between the gate electrode GE and the well region WA. A side insulating film SINS is disposed on the side of the gate electrode GE. The side insulating film SINS is disposed on the lower insulating film BINS.

[0100] The source region SA and the drain region DA may each be a region doped with a first-type impurity. The gate electrode GE of the first transistor PTR1 overlaps the well region WA in the third direction DR3. The channel region CH overlaps the gate electrode GE in the third direction DR3. The source region SA is disposed on one side of the gate electrode GE, and the drain region DA is disposed on the other side of the gate electrode GE.

[0101] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2 may increase the distance between the source region SA and the drain region DA. Therefore, the length of the channel region CH of each first transistor PTR1 may be increased, thereby preventing punch-through and hot carrier phenomena due to a short channel.

[0102] The first single crystal semiconductor substrate 110 may include a plurality of first transistors PTR1 that constitute a plurality of circuit elements of the driver 100. The first transistors PTR1 formed on the first single crystal semiconductor substrate 110 may constitute the driver circuit 400, the gate driver 600, the data driver 700, and the first pixel circuit 810.

[0103] After the driving circuit layer 120 is formed on the silicon wafer substrate, a process for reducing the thickness of the first single crystal semiconductor substrate 110 is performed. The first single crystal semiconductor substrate 110 may have a thickness thinner than that of the wafer substrate on which the semiconductor process for forming the driving circuit layer 120 is performed. In some embodiments, the thickness of the first single crystal semiconductor substrate 110 may be 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0104] The drive circuit layer 120 may include a first semiconductor insulating layer SINS1, a second semiconductor insulating layer SINS2, a plurality of contact electrodes CTE, a first interlayer insulating layer INS1, a second interlayer insulating layer INS2, a plurality of conductive layers ML1 to ML8, and a plurality of vias VA1 to VA8. The drive circuit layer 120 may include wiring electrically connected to a plurality of first transistors PTR1 included in the first single crystal semiconductor substrate 110.

[0105] The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 are disposed on the first single crystal semiconductor substrate 110. The first semiconductor insulating layer SINS1 is an insulating layer disposed on the first single crystal semiconductor substrate 110, and the second semiconductor insulating layer SINS2 may be an insulating layer disposed on the gate electrode GE of the first transistor PTR1 and the first semiconductor insulating layer SINS1. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be formed of silicon carbon nitride (SiCN) or silicon oxide (SiO x Although the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 are shown in the drawings as being formed as single layers each having a predetermined thickness, the present invention is not limited thereto. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may have a structure in which at least one layer is stacked on top of each other.

[0106] The plurality of contact electrodes CTE are disposed on the first single crystal semiconductor substrate 110. The plurality of contact electrodes CTE may be connected to one of the gate electrode GE, source region SA, and drain region DA of each first transistor PTR1 formed on the first single crystal semiconductor substrate 110 via holes penetrating the semiconductor insulating layers SINS1 and SINS2. The plurality of contact electrodes CTE may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. The upper surfaces of the plurality of contact electrodes CTE may be exposed and not covered by the semiconductor insulating layers SINS1 and SINS2.

[0107] The first interlayer insulating layer INS1 is disposed on the contact electrodes CTE and the semiconductor insulating layers SINS1 and SINS2. The second interlayer insulating layer INS2 is disposed on the first interlayer insulating layer INS1. The first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 are each made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film, but is not limited thereto. In the drawings, the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 are each shown formed as a single layer, but are not limited thereto. The first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may each have a structure in which at least one layer is stacked on top of each other, and these may be disposed between a plurality of first to eighth conductive layers ML1 to ML8 described below.

[0108] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are electrically connected to the plurality of contact electrodes CTE to form the driving circuit unit 400 or the data driver 700 of the driver 100. The plurality of first transistors PTR1 formed on the first single crystal semiconductor substrate 110 are electrically connected to each other via the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 to form the driving circuit unit 400 and the data driver 700 of the driver 100.

[0109] The first conductive layer ML1 is connected to the contact electrode CTE through a first via VA1. The first conductive layer ML1 is disposed on the contact electrode CTE, and the first via VA1 is disposed between the first conductive layer ML1 and the contact electrode CTE and may be in contact with them, respectively. The second conductive layer ML2 is connected to the first conductive layer ML1 through a second via VA2. The second conductive layer ML2 is disposed on the first conductive layer ML1, and the second via VA2 is disposed between the first conductive layer ML1 and the second conductive layer ML2 and may be in contact with them, respectively.

[0110] The third conductive layer ML3 is connected to the second conductive layer ML2 through the third via VA3. The fourth conductive layer ML4 is connected to the third conductive layer ML3 through the fourth via VA4, the fifth conductive layer ML5 is connected to the fourth conductive layer ML4 through the fifth via VA5, and the sixth conductive layer ML6 is connected to the fifth conductive layer ML5 through the sixth via VA6. The third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 are sequentially arranged on the second conductive layer ML2, with the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 arranged between them. The third to sixth vias VA6 may contact different metal layers arranged above and below them, respectively. The seventh via VA7 is arranged on the sixth conductive layer ML6. The seventh via VA7 may contact the seventh conductive layer ML7 and the sixth conductive layer ML6 arranged above it, respectively.

[0111] The first to sixth conductive layers ML1 to ML6 and the first to seventh vias VA1 to VA7 are arranged on the first interlayer insulating layer INS1. The first to sixth conductive layers ML1 to ML6 and the first to seventh vias VA1 to VA7 can form a first drive circuit layer of the drive circuit layer 120 that is arranged on the first interlayer insulating layer INS1.

[0112] The seventh conductive layer ML7 may be connected to the sixth conductive layer ML6 through a seventh via VA7. The seventh conductive layer ML7 is disposed on the first interlayer insulating layer INS1 and the sixth conductive layer ML6, and the seventh via VA7 may be disposed between the sixth conductive layer ML6 and the seventh conductive layer ML7 and may be in contact with them, respectively. The eighth conductive layer ML8 may be connected to the seventh conductive layer ML7 through an eighth via VA8. The eighth conductive layer ML8 is disposed on the seventh conductive layer ML7, and the eighth via VA8 may be disposed between the seventh conductive layer ML7 and the eighth conductive layer ML8 and may be in contact with them, respectively. The top surface of the eighth conductive layer ML8 may be exposed without being covered by the second interlayer insulating layer INS2, and may be electrically connected to the routing wiring RM disposed in the display unit 200 described above.

[0113] The seventh conductive layer ML7, the eighth via VA8, and the eighth conductive layer ML8 are disposed on the second interlayer insulating layer INS2. The seventh conductive layer ML7, the eighth via VA8, and the eighth conductive layer ML8 can form a second drive circuit layer of the drive circuit layer 120 that is disposed on the second interlayer insulating layer INS2.

[0114] Although the drawings show a structure in which the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are sequentially stacked on one another, their arrangement and connection may be modified in various ways depending on the circuits of the driving circuit unit 400 and the data driver 700 of the driver 100. The connection structure shown in the drawings is one example, and the connection of the driving circuit layer 120 arranged in the driving unit 100 of the display device 10 is not limited thereto. In addition, the driving circuit layer 120 does not necessarily have to include the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8, and some of these layers may be omitted, or more layers may be arranged.

[0115] The first through eighth conductive layers ML1 through ML8 and the first through eighth vias VA1 through VA8 are made of substantially the same material, for example, copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these materials.

[0116] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately 1360 Å, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 may each be approximately 1440 Å, and the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6 may each be approximately 1150 Å.

[0117] The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8. The thickness of the seventh via VA7 and the thickness of the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be substantially the same. For example, the thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately 9000 Å. The thickness of the seventh via VA7 and the eighth via VA8 may each be approximately 6000 Å.

[0118] FIG. 11 is a plan view illustrating first electrodes, light-emitting regions, and pixel defining layers of a plurality of sub-pixels arranged in a display area of ​​a display unit according to an embodiment.

[0119] 11, each of the pixels PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first to third sub-pixels SP1, SP2, and SP3 may include light-emitting regions EA1, EA2, and EA3, respectively. For example, the first sub-pixel SP1 may include a first light-emitting region EA1, the second sub-pixel SP2 may include a second light-emitting region EA2, and the third sub-pixel SP3 may include a third light-emitting region EA3.

[0120] Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have a quadrilateral planar shape such as a rectangle, a square, or a diamond. For example, the first light-emitting region EA1 may have a rectangular planar shape with a short side in the first direction DR1 and a long side in the second direction DR2. Also, each of the second light-emitting region EA2 and the third light-emitting region EA3 may have a rectangular planar shape with a long side in the first direction DR1 and a short side in the second direction DR2.

[0121] Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be a region defined by a pixel defining film PDL. For example, each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be a region defined by a first pixel defining film PDL1.

[0122] The length in the first direction DR1 of the third light-emitting region EA3 may be smaller than the length in the first direction DR1 of the first light-emitting region EA1 and may be smaller than the length in the first direction DR1 of the second light-emitting region EA2. The length in the first direction DR1 of the first light-emitting region EA1 and the length in the first direction DR1 of the second light-emitting region EA2 may be substantially the same.

[0123] In each of the multiple pixels PX, the first light-emitting region EA1 and the second light-emitting region EA2 are adjacent to each other in the second direction DR2. The first light-emitting region EA1 and the third light-emitting region EA3 are adjacent to each other in the first direction DR1. The second light-emitting region EA2 and the third light-emitting region EA3 are adjacent to each other in the first direction DR1. The areas of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be different.

[0124] Although the drawings show that the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 each have a rectangular planar shape, the planar shape is not limited thereto. For example, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may each have a polygonal, circular, or elliptical planar shape other than a rectangular shape.

[0125] The first light-emitting region EA1 emits light of a first color, the second light-emitting region EA2 emits light of a second color, and the third light-emitting region EA3 emits light of a third color. Here, the first light may be light in the red wavelength band, the second light may be light in the green wavelength band, and the third light may be light in the blue wavelength band. For example, the blue wavelength band refers to light whose main peak wavelength is in the wavelength band of approximately 370 nm to 460 nm, the green wavelength band refers to light whose main peak wavelength is in the wavelength band of approximately 480 nm to 560 nm, and the red wavelength band refers to light whose main peak wavelength is in the wavelength band of approximately 600 nm to 750 nm.

[0126] The first electrode AND of the light-emitting element has a rectangular planar shape. The planar shapes of the first electrode AND of the light-emitting element may be different among the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. For example, the first electrode AND of the first subpixel SP1 and the first electrode AND of the second subpixel SP2 may have a rectangular planar shape with a longer side in a first direction DR1 and a shorter side in a second direction DR2. The first electrode AND of the third subpixel SP3 may have a rectangular planar shape with a shorter side in the first direction DR1 and a longer side in the second direction DR2. The length in the first direction DR1 of the first electrode AND of the third subpixel SP3 may be shorter than the length in the second direction DR2 of the first electrode AND of the first subpixel SP1 and the second subpixel SP2. The length in the second direction DR2 of the first electrode AND of the first subpixel SP1 may be longer than the length in the second direction DR2 of the first electrode AND of the second subpixel SP2.

[0127] 13, the first electrode AND of the light-emitting element may be connected to the reflective electrode layer (RL in FIG. 13) through an electrode via VAP. The electrode via VAP overlaps the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 in the third direction DR3.

[0128] The at least one trench TRC may be a structure for separating at least one charge generation layer of the light emitting stack IL between adjacent light emitting regions EA1, EA2, and EA3. At least one trench TRC is disposed between the first light emitting region EA1 and the second light emitting region EA2, between the first light emitting region EA1 and the third light emitting region EA3, and between the second light emitting region EA2 and the third light emitting region EA3. More specifically, the at least one trench TRC is disposed between the first electrode AND of the first subpixel SP1 and the first electrode AND of the second subpixel SP2, between the first electrode AND of the first subpixel SP1 and the first electrode AND of the third subpixel SP3, and between the first electrode AND of the second subpixel SP2 and the first electrode AND of the third subpixel SP3.

[0129] FIG. 12 is a plan view showing first electrodes, light-emitting regions, and pixel defining layers of a plurality of sub-pixels arranged in a display area of ​​a display unit according to another embodiment.

[0130] Referring to Figure 12, the planar shapes of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are different from those of the embodiment of Figure 11, and are therefore substantially similar to the embodiment of Figure 11, and therefore, explanations overlapping with the embodiment of Figure 11 will be omitted.

[0131] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be arranged in a hexagonal structure having a hexagonal planar shape. In this case, the first light-emitting region EA1 and the second light-emitting region EA2 are adjacent to each other in a first direction DR1, the second light-emitting region EA2 and the third light-emitting region EA3 are adjacent to each other in a first diagonal direction DD1, and the first light-emitting region EA1 and the third light-emitting region EA3 are adjacent to each other in a second diagonal direction DD2. The first diagonal direction DD1 is a direction between the first direction DR1 and the second direction DR2 and is tilted 45 degrees relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 may be perpendicular to the first diagonal direction DD1.

[0132] 11 and 12 show that each of the plurality of pixels PX includes three light-emitting areas EA1, EA2, and EA3, but this is not limiting, that is, each of the plurality of pixels PX may include four light-emitting areas.

[0133] The arrangement of the light emitting regions of the pixels PX is not limited to that shown in the drawings. For example, the light emitting regions of the pixels PX may be arranged in a stripe structure in which the light emitting regions are arranged in a first direction DR1, a PenTile (registered trademark) structure in which the light emitting regions are arranged in a diamond shape, or a hexagonal structure in which light emitting regions having a hexagonal planar shape are arranged.

[0134] 13 is a cross-sectional view showing a part of a display unit according to an embodiment, which shows a schematic cross-sectional structure of a display area DAA and a first through-hole area TSA1 of a non-display area NA.

[0135] Referring to FIG. 13 , the display unit 200 may include a semiconductor backplane SBP, a pixel circuit backplane EBP, a display element layer EML, an encapsulation layer TFE, an adhesive layer ADL, an optical layer OPL, and a cover layer DCL. The semiconductor backplane SBP and pixel circuit backplane EBP of the display unit 200 may constitute a second pixel circuit unit 820. The display element layer EML, the encapsulation layer TFE, the adhesive layer ADL, and the optical layer OPL of the display unit 200 may constitute a display layer 230. Although not shown in the drawing, the display unit 200 may further include a polarizer disposed on the cover layer DCL. The connection wiring layer 500 is disposed between the second single-crystal semiconductor substrate 210 and the first single-crystal semiconductor substrate 110 of the semiconductor backplane SBP. Alternatively, the connection wiring layer 500 may be disposed between the display element layer EML and the first single-crystal semiconductor substrate 110.

[0136] The semiconductor backplane SBP includes a second single-crystal semiconductor substrate 210 including a plurality of second transistors PTR2, a plurality of semiconductor insulating films disposed on the plurality of second transistors PTR2, and a plurality of contact electrodes CTE electrically connected to the plurality of pixel transistors, respectively. The plurality of second transistors PTR2 may be the first transistors T1 constituting the pixel circuit of FIG. 5.

[0137] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The second single crystal semiconductor substrate 210 may be a substrate doped with impurities. A plurality of well regions WA are disposed on the upper surface of the second single crystal semiconductor substrate 210. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities are different from the first-type impurities described above. For example, if the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. Alternatively, if the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0138] The second single crystal semiconductor substrate 210 may include a plurality of second transistors PTR2, similar to the first single crystal semiconductor substrate 110. The structure of the second transistor PTR2 is similar to that of the first transistor PTR1, and therefore a detailed description thereof will be omitted.

[0139] In the display device 10, the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 of the driver unit 100 and the second transistor PTR2 formed on the second single crystal semiconductor substrate 210 of the display unit 200 may be formed on different wafer substrates. According to an embodiment, in the display device 10, the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 and the second transistor PTR2 formed on the second single crystal semiconductor substrate 210 may have different sizes and line widths.

[0140] For example, in the display device 10, the minimum line width of the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 may be smaller than the minimum line width of the second transistor PTR2 formed on the second single crystal semiconductor substrate 210. The semiconductor process performed on the first wafer substrate to form the first transistor PTR1 has a higher resolution than the semiconductor process performed on the second wafer substrate to form the second transistor PTR2, and therefore the size of the manufactured elements such as transistors is smaller. In other words, the semiconductor process performed on the first wafer substrate may be a finer process than the semiconductor process performed on the second wafer substrate.

[0141] As described above, the first single crystal semiconductor substrate 110 of the driver unit 100 has a smaller planar area than the second single crystal semiconductor substrate 210 of the display unit 200, allowing small-sized elements to be arranged with a high degree of integration, thereby reducing power consumption and improving manufacturing yield. Meanwhile, the second single crystal semiconductor substrate 210 of the display unit 200 has a larger planar area than the first single crystal semiconductor substrate 110, and is fabricated using a process that results in a relatively large line width. The second transistor PTR2 disposed on the second single crystal semiconductor substrate 210 may be formed with a larger area than when formed on the first single crystal semiconductor substrate 110, and the second transistor PTR2 constituting the pixel circuit does not require a high degree of integration. Therefore, the semiconductor process performed on the first wafer substrate is a high-cost process that results in a small line width, and the semiconductor process performed on the second wafer substrate is a low-cost process that results in a relatively large line width.

[0142] In an exemplary embodiment, the plurality of transistors PTR1 and PTR2 may have different lengths of their channel regions CH, and the minimum line width or length of the channel region CH of the first transistor PTR1 may be smaller than the minimum line width or length of the channel region CH of the second transistor PTR2. The minimum line width or length of the channel region CH of the first transistor PTR1 may be 100 nm or less, or may range from 2 nm to 80 nm. The minimum line width or length of the channel region CH of the second transistor PTR2 may be 100 nm or more, or may range from 100 nm to 5 μm.

[0143] The second single crystal semiconductor substrate 210 may include a plurality of first through holes TSV1 spaced apart from one another. The first through holes TSV1 penetrate from the top surface to the bottom surface of the second single crystal semiconductor substrate 210. A first conductive via RVA1 of the first routing wiring RM1 is disposed in the first through holes TSV1. The first through holes TSV1 may form a connection path of the first routing wiring RM1 that electrically connects the first pixel circuit unit 810 of the driving unit 100 and the second pixel circuit unit 820 of the display unit 200.

[0144] The second single-crystal semiconductor substrate 210 includes a plurality of second through holes TSV2 formed in the non-display area NA, and a second conductive via RVA2 of the second routing wiring RM2 is disposed in each of the second through holes TSV2. The circuit board 300 and the signal terminals STD of the driver 100 may be electrically connected to each other through the second routing wiring RM2. The second conductive via RVA2 may form a connection path of the second routing wiring RM2 connecting the circuit board 300 and the signal terminals STD of the driver 100.

[0145] In some embodiments, the through holes TSV1 and TSV2 of the second single crystal semiconductor substrate 210 may be formed by a TSV (Through Silicon Via) process for forming holes that penetrate a wafer substrate. The display layer 230 and the driver 100 may be electrically connected to each other via routing wires RM1 and RM2 through the through holes TSV1 and TSV2 formed in the second single crystal semiconductor substrate 210 without using separate wires.

[0146] The second single crystal semiconductor substrate 210 undergoes a process of reducing its thickness after the actuator 100 is bonded to the silicon wafer substrate. The second single crystal semiconductor substrate 210 may have a thickness thinner than that of the wafer substrate on which the process for forming the conductive layer is performed. In some embodiments, the thickness of the second single crystal semiconductor substrate 210 may be 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0147] The semiconductor backplane SBP and the pixel circuit backplane EBP are disposed on the second single-crystal semiconductor substrate 210. The semiconductor backplane SBP and a part of the pixel circuit backplane EBP can form the second pixel circuit unit 820 of the display unit 200.

[0148] The third semiconductor insulating film SINS3 is disposed on the second single crystal semiconductor substrate 210. The third semiconductor insulating film SINS3 is made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0149] The fourth semiconductor insulating film SINS4 is disposed on the third semiconductor insulating film SINS3. The fourth semiconductor insulating film SINS4 is made of silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0150] Each of the plurality of contact electrodes CTE may be connected to one of the gate electrode GE, source region SA, and drain region DA of each of the second transistors PTR2 through a hole penetrating the third semiconductor insulating film SINS3 and the fourth semiconductor insulating layer INS4. The plurality of contact electrodes CTE may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these.

[0151] The pixel circuit backplane EBP may include third to seventh interlayer insulating layers INS3, INS4, INS5, INS6, and INS7 and a plurality of connecting conductive layers RMT. The connecting conductive layers RMT may include wiring electrically connected to a plurality of second transistors PTR2 formed on the second single-crystal semiconductor substrate 210. The pixel circuit backplane EBP may include driving voltage lines VSL and VDL arranged in the display unit 200.

[0152] The third interlayer insulating layer INS3 is disposed on the plurality of contact electrodes CTE and the semiconductor insulating layers SINS3 and SINS4. The fourth interlayer insulating layer INS4 is disposed on the third interlayer insulating layer INS3. The fifth interlayer insulating layer INS5, the sixth interlayer insulating layer INS6, and the seventh interlayer insulating layer INS7 are disposed in sequence on the fourth interlayer insulating layer INS4. The plurality of connecting conductive layers RMT are disposed between the fifth interlayer insulating layer INS5 to the seventh interlayer insulating layer INS7. The third interlayer insulating layer INS3 to the seventh interlayer insulating layer INS7 are each formed of silicon carbon nitride (SiCN) or silicon oxide (SiO x)-based inorganic film, but is not limited thereto. In the drawings, the third interlayer insulating layer INS3 to the seventh interlayer insulating layer INS7 are each shown as being formed as a single layer, but are not limited thereto. The third interlayer insulating layer INS3 to the seventh interlayer insulating layer INS7 may each have a structure in which at least one layer is stacked on top of each other, and these may be disposed between a plurality of first to eighth conductive layers ML1 to ML8, which will be described later.

[0153] The connection conductive layer RMT may have a structure similar to the plurality of conductive layers ML1-ML8 and vias VA1-VA8 of the drive circuit layer 120. The connection conductive layer RMT may include at least one conductive layer and vias disposed between them, and may constitute wiring, such as the drive voltage lines VSL and VDL, disposed in the display unit 200. For example, the connection conductive layer RMT disposed in the display area DAA may be electrically connected to the second transistor PTR2 to constitute the pixel circuit of FIG. 5. The connection conductive layer RMT may serve as connection wiring that connects the second transistor PTR2 to other circuit elements.

[0154] The connection wiring layer 500 is disposed on the lower surface of the second single crystal semiconductor substrate 210. The connection wiring layer 500 may include an interlayer insulating layer RINS and a plurality of connection wirings RML1, RML2.

[0155] The interlayer insulating layer RINS is disposed on the lower surface of the second single crystal semiconductor substrate 210. The interlayer insulating layer RINS is made of silicon carbon nitride (SiCN) or silicon oxide (SiO x Although the drawings show that the interlayer insulating layers RINS are formed as a single layer, the present invention is not limited thereto and the interlayer insulating layers RINS may have a structure in which at least one layer is stacked on top of each other, and these may be disposed between the connecting wires RML1 and RML2.

[0156] The connection wirings RML1, RML2, together with the conductive vias RVA1, RVA2, form routing wirings RM1, RM2. The connection wirings RML1, RML2 may include at least one conductive layer and one or more vias connecting these to each other. The connection and structure of the connection wirings RML1, RML2 are similar to those described above for the plurality of conductive layers ML1 to ML8 and vias VA1 to VA8. The connection wirings RML are electrically connected to the second pixel circuit unit 820 or the circuit board 300 via the conductive vias RVA, RVA2 arranged in the through-holes TSV1, TSV2 of the second single-crystal semiconductor substrate 210, and can electrically connect these to the drive circuit layer 120 of the drive unit 100, respectively.

[0157] A first conductive via RVA1 of the first routing wiring RM1 is disposed in the first through hole TSV1. The first through hole TSV1 penetrates the second single crystal semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3, INS4, and INS5. The first conductive via RVA1 of the first routing wiring RM1 is disposed in the first through hole TSV1 and extends from the lower surface of the sixth interlayer insulating layer INS6 to the lower surface of the second single crystal semiconductor substrate 210, and may be connected to the first connection wiring RML1. The first conductive via RVA1 may be connected to the second transistor PTR2 via the connection conductive layer RMT of the pixel circuit backplane EBP, and may be connected to the first pixel circuit unit 810 of the driving unit 100 via the first connection wiring RML1. The first connection wiring RML1 may be the wiring shown on the back surface of the display unit 200 in FIG. 9.

[0158] A second conductive via RVA2 of the second routing wiring RM2 is disposed in the second through hole TSV2. The second through hole TSV2 penetrates the second single crystal semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3, INS4, and INS5. The second conductive via RVA2 of the second routing wiring RM2 is disposed in the second through hole TSV2 and is disposed from the lower surface of the sixth interlayer insulating layer INS6 to the lower surface of the second single crystal semiconductor substrate 210, and can be connected to the second connection wiring RML2. The second conductive via RVA2 is connected to the write signal terminal GTD of the pixel circuit backplane EBP, and can be connected to the signal terminal STD of the driver 100 via the second connection wiring RML2.

[0159] In the display device 10, the circuit unit formed in the driver 100 can be formed using a costly micro-semiconductor process, allowing for high integration density on the small-area first single-crystal semiconductor substrate 110. The manufacturing process for the driver 100 can achieve a high yield per wafer substrate, and the small size of the circuit elements (e.g., first transistors) can reduce power consumption. In addition, elements constituting pixel circuits for emitting light from the light-emitting elements are separately arranged in the driver 100 and the display unit 200, preventing excessive integration density on the first single-crystal semiconductor substrate 110. Furthermore, the driving voltage lines VSL and VDL, to which voltages for driving the light-emitting elements are applied, are arranged in the display unit 200 and do not need to pass through the driver 100, eliminating unnecessary current paths and efficiently preventing voltage drops.

[0160] The display layer 230 is disposed on the second single-crystal semiconductor substrate 210 and the pixel circuit backplane EBP. The display layer 230 may include a display element layer EML, a sealing layer TFE, an adhesive layer ADL, an optical layer OPL, and a cover layer DCL. The display layer 230 may include a light-emitting element electrically connected to the driver 100 to emit light.

[0161] The display element layer EML is disposed on the pixel circuit backplane EBP. The display element layer EML may include a reflective electrode layer RL, eighth and ninth interlayer insulating layers INS8 and INS9, an electrode via VAP, a light-emitting element, a pixel defining film PDL, and a plurality of trenches TRC. The light-emitting element may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0162] The reflective electrode layer RL is disposed on the seventh interlayer insulating layer INS7. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL may include first to fourth reflective electrodes RL1, RL2, RL3, and RL4.

[0163] Each of the first reflective electrodes RL1 may be disposed on the seventh interlayer insulating layer INS7 and connected to a via penetrating the seventh interlayer insulating layer INS7. The first reflective electrodes RL1 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0164] Each of the second reflective electrodes RL2 is disposed on the first reflective electrode RL1. The second reflective electrodes RL2 are made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the second reflective electrodes RL2 may include aluminum (Al).

[0165] Each of the third reflective electrodes RL3 is disposed on the second reflective electrode RL2. The third reflective electrodes RL3 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the third reflective electrodes RL3 may include titanium nitride (TiN).

[0166] Each of the fourth reflective electrodes RL4 is disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0167] The second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element, and the thickness of the second reflective electrode RL2 may be greater than the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may each be approximately 100 Å, and the thickness of the second reflective electrode RL2 may be approximately 850 Å.

[0168] The eighth interlayer insulating layer INS8 is disposed on the seventh interlayer insulating layer INS7. The eighth interlayer insulating layer INS8 is disposed between adjacent reflective electrode layers RL. The eighth interlayer insulating layer INS8 is disposed on the reflective electrode layer RL in the first sub-pixel SP1. The eighth interlayer insulating layer INS8 is made of silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0169] The ninth interlayer insulating layer INS9 is disposed on the eighth interlayer insulating layer INS8 and the reflective electrode layer RL. The ninth interlayer insulating layer INS9 is made of silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0170] In at least one of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9 may not be arranged below the first electrode AND, taking into account the resonance distance of the light emitted from the light-emitting element LE.

[0171] For example, the first electrode AND of the third subpixel SP3 is disposed directly on the fourth reflective electrode RL4, and the first electrode AND of the third subpixel SP3 does not overlap the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9. The first electrode AND of the second subpixel SP2 is disposed on the ninth interlayer insulating layer INS9, but the ninth interlayer insulating layer INS9 can be disposed directly on the fourth reflective electrode RL4. That is, the first electrode AND of the second subpixel SP2 does not overlap the eighth interlayer insulating layer INS8. The first electrode AND of the first subpixel SP1 is disposed on the ninth interlayer insulating layer INS9 and may overlap the eighth interlayer insulating layer INS8.

[0172] In one embodiment, the distance between the first electrode AND and the reflective electrode layer RL may be different in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. To adjust the distance from the reflective electrode layer RL to the second electrode CAT depending on the main wavelength of the light emitted from each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, the presence or absence of an eighth interlayer insulating layer INS8 and a ninth interlayer insulating layer INS9 may be determined for each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. For example, in FIG. 13 , the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3. However, the present invention is not limited to this, and the distance between the first electrode AND and the reflective electrode layer RL in each of the sub-pixels SP1, SP2, and SP3 can be variously modified and designed.

[0173] Although the drawings show the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9, a tenth interlayer insulating layer may also be disposed below the first electrode AND of the subpixel SP. In this case, the ninth interlayer insulating layer INS9 and the tenth interlayer insulating layer may be disposed below the first electrode AND of the second subpixel SP2, and the eighth interlayer insulating layer INS8, the ninth interlayer insulating layer INS9, and the tenth interlayer insulating layer may be disposed below the first electrode AND of the first subpixel SP1.

[0174] Each of the electrode vias VAP may be connected to the fourth reflective electrode RL4 exposed through the eighth interlayer insulating layer INS8 and / or the ninth interlayer insulating layer INS9 in the first subpixel SP1 and the second subpixel SP2. The electrode vias VAP may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. The thickness of the electrode via VAP in the second subpixel SP2 may be smaller than the thickness of the electrode via VAP in the first subpixel SP1.

[0175] The first electrode AND of each light-emitting element LE may be disposed on the ninth interlayer insulating layer INS9 or the reflective electrode layer RL and connected to the electrode via VAP. The first electrode AND of each light-emitting element LE may be connected to the second transistor PTR2 via the electrode via VAP, the first to fourth reflective electrodes RL1 to RL4, the connecting conductive layer RMT, and the contact electrode CTE. The first electrode AND of each light-emitting element LE may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the first electrode AND of each light-emitting element may be titanium nitride (TiN).

[0176] The pixel defining layer PDL is disposed on a portion of the first electrode AND of each light emitting element. The pixel defining layer PDL may cover the edge of the first electrode AND of each light emitting element. The pixel defining layer PDL serves to divide the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3.

[0177] The first light-emitting region EA1 is defined as the region in the first sub-pixel SP1 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light. The second light-emitting region EA2 is defined as the region in the second sub-pixel SP2 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light. The third light-emitting region EA3 is defined as the region in the third sub-pixel SP3 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light.

[0178] The pixel defining film PDL may include first to third pixel defining films PDL1, PDL2, and PDL3. The first pixel defining film PDL1 is disposed on the edge of the first electrode AND of each light-emitting element LE, the second pixel defining film PDL2 is disposed on the first pixel defining film PDL1, and the third pixel defining film PDL3 is disposed on the second pixel defining film PDL2. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 are made of silicon oxide (SiO x The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each have a thickness of approximately 500 Å.

[0179] When the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 are formed as an integrated pixel defining film, the height of the integrated pixel defining film increases, and the first inorganic encapsulating layer TFE1 may be separated due to step coverage. Step coverage refers to the ratio of the degree to which the thin film is coated on sloped portions to the degree to which the thin film is coated on flat portions. In other words, step coverage, also known as step coverage, is the ratio of the deposited film thickness at the bottom and top of steps on the substrate, and is the ratio of the film thickness at the thinnest portion to the film thickness at the flat portion. The lower the step coverage, the greater the possibility that the thin film will be separated on sloped portions.

[0180] To prevent the first inorganic sealing layer TFE1 from being divided by step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may have a cross-sectional structure with a staircase-like step. For example, the width of the first pixel defining layer PDL1 may be greater than the widths of the second pixel defining layer PDL2 and the third pixel defining layer PDL3, and the width of the second pixel defining layer PDL2 may be greater than the width of the third pixel defining layer PDL3. The width of the first pixel defining layer PDL1 refers to the horizontal length of the first pixel defining layer PDL1 defined by the first direction DR1 and the second direction DR2.

[0181] Each of the plurality of trenches TRC penetrates the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. In each of the plurality of trenches TRC, a portion of the eighth interlayer insulating layer INS8 is recessed, and the ninth interlayer insulating layer INS9 penetrates through the trench.

[0182] At least one trench TRC is disposed between adjacent sub-pixels SP1, SP2, and SP3. Although the drawing shows two trenches TRC disposed between adjacent sub-pixels SP1, SP2, and SP3, the present invention is not limited to this.

[0183] The light emitting stack IL may include multiple stacks. Although the drawings show the light emitting stack IL having a three-tandem structure including a first light emitting stack IL1, a second light emitting stack IL2, and a third light emitting stack IL3, the light emitting stack IL is not limited thereto. For example, the light emitting stack IL may have a two-tandem structure including two light emitting stacks.

[0184] In the three-tandem structure, the light-emitting stack IL may have a tandem structure including multiple light-emitting stacks IL1, IL2, and IL3 that emit different light from each other. For example, the light-emitting stack IL may include a first light-emitting stack IL1 that emits light of a first color, a second light-emitting stack IL2 that emits light of a third color, and a third light-emitting stack IL3 that emits light of a second color. The first light-emitting stack IL1, the second light-emitting stack IL2, and the third light-emitting stack IL3 may be stacked sequentially.

[0185] The first light-emitting stack IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer that emits light of a first color, and a first electron transport layer are sequentially stacked. The second light-emitting stack IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer that emits light of a third color, and a second electron transport layer are sequentially stacked. The third light-emitting stack IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer that emits light of a second color, and a third electron transport layer are sequentially stacked.

[0186] A first charge generation layer may be disposed between the first light emitting stack IL1 and the second light emitting stack IL2 to supply electrons to the second light emitting stack IL2 and to supply electrons to the first light emitting stack IL1. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first light emitting stack IL1 and a P-type charge generation layer that supplies holes to the second light emitting stack IL2. The N-type charge generation layer may include a metal dopant.

[0187] A second charge generation layer may be disposed between the second light-emitting stack IL2 and the third light-emitting stack IL3 to supply electrons to the third light-emitting stack IL3 and to supply electrons to the second light-emitting stack IL2. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second light-emitting stack IL2 and a P-type charge generation layer that supplies holes to the third light-emitting stack IL3.

[0188] The first light-emitting stack IL1 is disposed on the first electrode AND and the pixel defining layer PDL, and is disposed on the bottom surface of each trench TRC. The trench TRC may separate the first light-emitting stack IL1 between adjacent sub-pixels SP1, SP2, and SP3. The second light-emitting stack IL2 is disposed on the first light-emitting stack IL1. The trench TRC may separate the second light-emitting stack IL2 between adjacent sub-pixels SP1, SP2, and SP3. A cavity or empty space is disposed between the first light-emitting stack IL1 and the second light-emitting stack IL2. The third light-emitting stack IL3 is disposed on the second light-emitting stack IL2. The third light-emitting stack IL3 is not separated by the trench TRC, and is disposed so as to cover the second light-emitting stack IL2 in each trench TRC. That is, in the three-tandem structure, each of the trenches TRC may be a structure for separating the first and second light-emitting stacks IL1 and IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between the adjacent subpixels SP1, SP2, and SP3. Also, in the two-tandem structure, each of the trenches TRC may be a structure for separating the charge generation layer and the lower light-emitting stack disposed between the lower light-emitting stack and the upper light-emitting stack.

[0189] To stably separate the first through second light-emitting stacks IL1, IL2 of the display element layer EML between adjacent subpixels SP1, SP2, and SP3, the height of each of the trenches TRC may be greater than the height of the pixel defining layer PDL. The height of each of the trenches TRC refers to the length of each of the trenches TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. To separate the first through third light-emitting stacks IL1, IL2, and IL3 of the display element layer EML between adjacent subpixels SP1, SP2, and SP3, other structures may be present instead of the trenches TRC. For example, instead of the trenches TRC, a reverse-tapered barrier rib may be disposed on the pixel defining layer PDL.

[0190] The number of light-emitting stacks IL1, IL2, and IL3 that emit different light rays is not limited to that shown in the drawings. For example, the light-emitting stack IL may include two light-emitting stacks. In this case, one of the two light-emitting stacks may be substantially identical to the first light-emitting stack IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer may be disposed between the two light-emitting stacks to supply electrons to one of the light-emitting stacks and the other light-emitting stack.

[0191] Although the drawings illustrate that the first to third light-emitting stacks IL1, IL2, and IL3 are all disposed in the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, this is not limiting. For example, the first light-emitting stack IL1 may be disposed in the first light-emitting region EA1, but not in the second light-emitting region EA2 or the third light-emitting region EA3. The second light-emitting stack IL2 may be disposed in the second light-emitting region EA2, but not in the first light-emitting region EA1 or the third light-emitting region EA3. The third light-emitting stack IL3 may be disposed in the third light-emitting region EA3, but not in the first light-emitting region EA1 or the second light-emitting region EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL may be omitted.

[0192] The second electrode CAT is disposed on the third light-emitting stack IL3. The second electrode CAT is disposed on the third light-emitting stack IL3 in each of the trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) such as ITO or IZO, or a semi-transmissive metal material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive metal material, the microcavities increase the light output efficiency of each of the first to third sub-pixels SP1, SP2, and SP3. The second electrode CAT may be electrically connected to the first driving voltage line VSL at the common electrode contact region CTA of the non-display area NA.

[0193] The encapsulating layer TFE is disposed on the display element layer EML. The encapsulating layer TFE may include at least one inorganic encapsulating layer TFE1, TFE3 to prevent oxygen or moisture from penetrating into the display element layer EML. The encapsulating layer TFE may also include at least one organic film to protect the display element layer EML from foreign matter such as dust. For example, the encapsulating layer TFE may include a first inorganic encapsulating layer TFE1, an organic encapsulating layer TFE2, and a second inorganic encapsulating layer TFE3.

[0194] The first inorganic sealing layer TFE1 is disposed on the second electrode CAT, the organic sealing layer TFE2 is disposed on the first inorganic sealing layer TFE1, and the second inorganic sealing layer TFE3 is disposed on the organic sealing layer TFE2. The first inorganic sealing layer TFE1 and the second inorganic sealing layer TFE3 are made of silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ), and an aluminum oxide layer (AlO xThe organic encapsulation layer TFE2 may be formed of a multi-layer structure in which one or more inorganic layers such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. are alternately stacked. The organic encapsulation layer TFE2 may be a monomer. Alternatively, the organic encapsulation layer TFE2 may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0195] The adhesive layer ADL is disposed on the sealing layer TFE. The adhesive layer ADL may be a layer for adhering the sealing layer TFE to a layer disposed thereon. The adhesive layer ADL may be a double-sided adhesive member. The adhesive layer ADL may also be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0196] The optical layer OPL may include a color filter layer CFL, a plurality of lenses LNS, and a filler layer FIL. The color filter layer CFL may include first, second, and third color filters CF1, CF2, and CF3. The first, second, and third color filters CF1, CF2, and CF3 are disposed on the adhesive layer ADL.

[0197] The first color filter CF1 overlaps the first light-emitting area EA1. The first color filter CF1 transmits light of a first color, i.e., light in the red wavelength band. The red wavelength band may be approximately 600 nm to 750 nm. The first color filter CF1 transmits light of the first color emitted from the first light-emitting area EA1.

[0198] The second color filter CF2 overlaps the second light-emitting area EA2. The second color filter CF2 transmits light of a second color, i.e., light in the green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm. The second color filter CF2 transmits light of the second color emitted from the second light-emitting area EA2.

[0199] The third color filter CF3 overlaps the third light-emitting area EA3. The third color filter CF3 transmits light of a third color, i.e., light in the blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm. The third color filter CF3 transmits light of the third color emitted from the third light-emitting area EA3.

[0200] Each of the lenses LNS is disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the lenses LNS may be a structure for increasing the proportion of light directed toward the front of the display device 10. Each of the lenses LNS may have a cross-sectional shape that is convex upward.

[0201] The filler layer FIL is disposed on the lenses LNS. The filler layer FIL may have a predetermined refractive index so that light travels in the third direction DR3 at the interface between the lenses LNS and the filler layer FIL. The filler layer FIL may also be a planarization layer. The filler layer FIL may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0202] The cover layer DCL is disposed on the filler layer FIL. The cover layer DCL can be a glass substrate or a polymer resin such as resin. If the cover layer DCL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can serve to adhere the cover layer DCL. If the cover layer DCL is a glass substrate, it can serve as a sealing substrate. If the cover layer DCL is a polymer resin such as resin, it can be directly applied on the filler layer FIL.

[0203] Although not shown in the drawings, the display unit 200 may further include a polarizer disposed on the cover layer DCL. The polarizer is disposed on one surface of the cover layer DCL. The polarizer may be a structure for preventing a decrease in visibility due to external light reflection. The polarizer may include a linear polarizer and a phase retardation film. For example, the phase retardation film may be, but is not limited to, a λ / 4 plate. However, if the visibility due to external light reflection is sufficiently improved by the first to third color filters CF1, CF2, and CF3, the polarizer may be omitted.

[0204] Various embodiments of the display device 10 will now be described with reference to other drawings.

[0205] Fig. 14 is a block diagram showing an example of a display device according to another embodiment, and Fig. 15 is an equivalent circuit diagram of one pixel of the display device of Fig. 14.

[0206] 14 and 15, in the display device 10 according to an embodiment, the pixel circuit PXC of each of the subpixels SP1, SP2, and SP3 may include a larger number of transistors T1 to T6. Therefore, the display device 10 may include additional gate drivers and signal lines disposed in the display unit 200.

[0207] 14, the block diagram of the display device 10 will be described. The driving circuit unit 400 may include a timing control circuit. The driving circuit unit 400 may further include various circuits involved in driving the display device 10, such as a gamma circuit and a logic circuit. The driving circuit unit 400 may include driving circuit transistors formed on the first single crystal semiconductor substrate 110.

[0208] The driver circuit 400 receives digital video data and timing signals from an external device. The timing control circuit generates a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS to control the display unit 200 in response to the timing signals. The timing control circuit outputs the scan timing control signal SCS to the first scan driver 610 and the second scan driver 620 of the gate driver 600, and outputs the light emission timing control signal ECS to the light emission driver 630 of the gate driver 600. The timing control circuit outputs the digital video data and the data timing control signal DCS to the data driver 700.

[0209] The power supply unit generates a plurality of panel driving voltages in response to an external power supply voltage. For example, the power supply circuit generates a first driving voltage VSS, a second driving voltage VDD, and an initialization voltage VINT and supplies them to the plurality of pixels PX.

[0210] The scan timing control signal SCS, the light emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the driving circuit unit 400 are supplied to the pixels PX. The first driving voltage VSS, the second driving voltage VDD, the reference voltage VREF, and the initialization voltage VINT of the power supply unit may also be supplied to the pixels PX.

[0211] The gate driver 600 may include a first scan driver 610, a second scan driver 620, and an emission driver 630. The first scan driver 610 may include a plurality of scan transistors formed on the first single crystal semiconductor substrate 110, the second scan driver 620 may include a scan transistor formed on the second single crystal semiconductor substrate 210, and the emission driver 630 may include a plurality of emission transistors formed on the second single crystal semiconductor substrate 210. The plurality of scan transistors and the plurality of emission transistors may be formed using a semiconductor process. For example, the plurality of scan transistors and the plurality of emission transistors may be formed using CMOS transistors.

[0212] The first scan driver 610 may include a first scan signal output unit 611, and the second scan driver 620 may include a second scan signal output unit 612 and a third scan signal output unit 613. Each of the first scan signal output unit 611, the second scan signal output unit 612, and the third scan signal output unit 613 receives a scan timing control signal SCS from the driver circuit unit 400. The first scan signal output unit 611 generates write scan signals in response to the scan timing control signal SCS of the driver circuit unit 400 and sequentially outputs the write scan signals to the first scan lines GWL. The second scan signal output unit 612 generates control scan signals in response to the scan timing control signal SCS and sequentially outputs the control scan signals to the second scan lines GCL. The third scan signal output unit 613 generates bias scan signals in response to the scan timing control signal SCS and sequentially outputs the bias scan signals to the third scan lines GBL.

[0213] The light emission driving unit 630 may include a first light emission signal output unit 621 and a second light emission signal output unit 622. Each of the first light emission signal output unit 621 and the second light emission signal output unit 622 receives a light emission timing control signal ECS from the driving circuit unit 400. The light emission driving unit 630 generates a light emission control signal in response to the light emission timing control signal ECS and outputs the signal to the first and second light emission control lines EL1 and EL2 in sequence.

[0214] The data driver 700 receives digital video data DATA and a data timing control signal DCS from the driver circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage in response to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by a write scan signal from the first scan driver 610, and data voltages are supplied to the selected sub-pixels SP1, SP2, and SP3.

[0215] Referring to FIG. 15, the pixel circuit PXC may be connected to a first scan line GWL, a second scan line GCL, a third scan line GBL, a first light-emitting control line EL1, a second light-emitting control line EL2, and a data line DL. The pixel circuit PXC may also be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL may be a low potential voltage line, the second drive voltage line VDL may be a high potential voltage line, and the third drive voltage line VIL may be an initialization voltage line. In this case, the first drive voltage VSS may be lower than the third drive voltage VINT. The second drive voltage VDD may be higher than the third drive voltage VINT.

[0216] The pixel circuit PXC includes a plurality of transistors T1 to T6, a light emitting element (LE), a first capacitor C1, and a second capacitor C2.

[0217] The light-emitting element LE emits light in response to the driving current Ids flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE is proportional to the driving current Ids. The light-emitting element LE is disposed between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode.

[0218] The first transistor T1 may be a drive transistor that controls a source-drain current (Ids, hereinafter referred to as a "drive current") flowing between its source electrode and drain electrode in response to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0219] The second transistor T2 is disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal on the first scan line GWL to connect one electrode of the first capacitor C1 to the data line DL, thereby allowing the data voltage of the data line DL to be applied to one electrode of the first capacitor C1. The second transistor ST2 includes a gate electrode connected to the first scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0220] The third transistor T3 is disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a write control signal from the second scan line GCL to connect the first node N1 to the second node N2. This connects the gate electrode and source electrode of the first transistor T1, allowing the first transistor T1 to operate as a diode. The third transistor T3 includes a gate electrode connected to the second scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0221] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first light-emitting control signal from the first light-emitting control line EL1 to connect the second node N2 to the third node N3, so that the driving current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first light-emitting control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0222] The fifth transistor T5 is disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal of the third scan line GBL to connect the third node N3 to the third driving voltage line VIL. This allows the third driving voltage VINT of the third driving voltage line VIL to be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the third scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0223] The sixth transistor T6 is disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by a second light-emitting control signal from the second light-emitting control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. This allows the second driving voltage VDD from the second driving voltage line VDL to be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second light-emitting control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0224] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2, and includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0225] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL, and includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second drive voltage line VDL.

[0226] The first node N1 is a junction of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a junction of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0227] According to an embodiment, in the display device 10, the second transistor T2 may be formed on the first single crystal semiconductor substrate 110 of the driver 100, and the first transistor T1 and the third to sixth transistors T3 to T6 may be formed on the second single crystal semiconductor substrate 210 of the display unit 200. The second transistor T2 may be connected to one electrode of the first capacitor C1 through a first through-hole TSV1 formed in the second single crystal semiconductor substrate 210. Accordingly, the data line DL and the first scan line GWL are disposed in the first pixel circuit unit 810 of the driver 100, and the second scan line GCL, the third scan line GBL, the light emitting control lines EL1 and EL2, and the driving voltage lines VSL, VDL, and VIL are disposed in the second pixel circuit unit 820 of the display unit 200.

[0228] Each of the first to sixth transistors T1 to T6 may be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but is not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs, and the remaining transistors may be N-type MOSFETs.

[0229] Fig. 16 is a plan view showing an example of a drive section of the display device of Fig. 14 and Fig. 15. Fig. 17 is a plan view showing an example of a display section of the display device of Fig. 14 and Fig. 15.

[0230] 16 and 17, the driver 100 of the display device 10 according to an embodiment may include a first single crystalline semiconductor substrate 110 and a driver circuit unit 400, a first scan driver 610, a data driver 700, and a first pixel circuit unit 810 formed on the first single crystalline semiconductor substrate 110. The description of each component of the driver 100 is the same as that described above with reference to FIGS. 2 and 3, and therefore, some overlapping descriptions will be omitted below.

[0231] The first single-crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A plurality of first transistors may be formed on the first single-crystal semiconductor substrate 110, and the plurality of first transistors may be electrically connected to each other to form the driving circuit unit 400, the gate driver 600, the data driver 700, and the first pixel circuit unit 810.

[0232] In the drawing, in a plan view, the first pixel circuit unit 810 is disposed on the other side of the driver 100 in the second direction DR2, i.e., the upper side, and the data driver 700, the driver circuit unit 400, and the signal terminal area TDA are disposed on one side of the driver 100 in the second direction DR2, i.e., the lower side, and the first scan driver 610 is disposed on one side of the first pixel circuit unit 810 in the first direction DR1, i.e., the right side. However, this is not limiting. The first pixel circuit unit 810 may include a plurality of first transistors and a plurality of first scan lines GWL and data lines DL electrically connected to the first transistors.

[0233] The display unit 200 may include a second single-crystal semiconductor substrate 210, a second pixel circuit unit 820, a second scan driver 620, and an emission driver 630. The display unit 200 may include a display area DAA in which a plurality of pixels PX are arranged and a non-display area NA therearound. The display unit 200 may include the second scan driver 620, the emission driver 630, a first through-hole area TSA1, a pad area PDA, and a common electrode contact area CTA arranged in the non-display area NA.

[0234] The second scan driver 620 and the light emitting driver 630 are respectively disposed on the left and right sides of the non-display area NA in the first direction DR1 of the display area DAA. A common electrode contact area CTA is disposed on the outermost side of the non-display area NA in the first direction DR1 of the display area DAA, and the second scan driver 620 and the light emitting driver 630 are disposed between the common electrode contact area CTA and the display area DAA.

[0235] The second single-crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A plurality of second transistors may be formed on the second single-crystal semiconductor substrate 210, and the plurality of second transistors may be electrically connected to each other to form pixel circuits for emitting light from the plurality of pixels PX. Some of the second transistors may form scan transistors or light-emitting transistors of the second scan driver 620 and the light-emitting driver 630. The second transistors may be formed using a semiconductor process. For example, the plurality of transistors may be formed using CMOS (Complementary Metal Oxide Semiconductor) transistors.

[0236] The second pixel circuit unit 820 may include a plurality of second transistors formed on the second single crystal semiconductor substrate 210. The second pixel circuit unit 820 may also include a second scan line GCL and a third scan line GBL connected to the second scan driver 620, and light emitting control lines EL1 and EL2 connected to the light emitting driver 630. The second pixel circuit unit 820 may also include a plurality of driving voltage lines VDL, VSL, and VIL.

[0237] Fig. 18 is a plan view showing the arrangement of a plurality of wires arranged in the display section of Fig. 17. Fig. 19 is a schematic view showing the rear surface of the display device of Figs.

[0238] 18 and 19, the display unit 200 may include a plurality of second scan lines GCL and third scan lines GBL connected to the second scan driver 620. The second scan lines GCL and third scan lines GBL extend in a first direction DR1 and are spaced apart from each other in a second direction DR2. The display unit 200 may include a plurality of light-emitting control lines EL (EL1, EL2) connected to the light-emitting driver 630. The first light-emitting control line EL1 and second light-emitting control line EL2 extend in the first direction DR1 and are spaced apart from each other in a second direction DR2. Although not shown in the drawings, the display unit 200 may further include a third driving voltage line VIL disposed in the display area DAA. The third driving voltage line VIL may have a wiring configuration extending in the first direction DR1 and the second direction DR2, similar to the first driving voltage line VDL.

[0239] The display unit 200 differs from the embodiment of FIG. 6 in that it further includes a second scan driver 620, a light emitting driver 630, signal wiring GL including second scan lines GCL and third scan lines GBL, light emitting control lines EL, and a third driving voltage line VIL.

[0240] As the pixel circuit PXC of the display device 10 includes a larger number of transistors T1 to T6, the display device 10 can include a larger number of signal wirings and driving voltage lines. In the display device 10, the elements constituting the pixel circuit PXC are separately arranged in a driver 100 and a display unit 200, which include different single-crystal semiconductor substrates 110 and 210. For example, the second transistor T2 of the pixel circuit PXC is arranged in the driver 100, and the first transistor T1, the third through sixth transistors T3 to T6, and the light-emitting element LE are arranged in the display unit 200. The second transistor T2 can be electrically connected to other transistors via a first through-hole TSV1. Depending on the arrangement of the transistors, the first scan driver 610 and the data driver 700 are arranged in the driver 100, and the second scan driver 620 and the light-emitting driver 630 are arranged in the display unit 200. The first scan lines GWL and data lines DL are arranged in the driver 100, and the second scan lines GCL, third scan lines GBL, light emitting control lines EL1 and EL2, and drive voltage lines VSL, VDL, and VIL are arranged in the display section 200.

[0241] In the display device 10 according to an embodiment, even if the pixel circuit PXC for driving the light emitting element LE includes a large number of transistors, the difficulty of layout design due to high integration can be eliminated by disposing these transistors separately on different single crystal semiconductor substrates 110 and 210. Furthermore, the driving voltage lines VSL, VDL, and VIL can be disposed in the display unit 200 having a relatively large area, ensuring a sufficient wiring width, and eliminating unnecessary current paths can efficiently prevent voltage drops.

[0242] Fig. 20 is a plan view showing an example of a drive unit of a display device according to still another embodiment. Fig. 21 is a plan view showing an example of a display unit of the display device of Fig. 20.

[0243] 20 and 21, according to one embodiment, in the display device 10, a gate driver 600 is disposed in the driver 100, and some of the signal lines (GL: GCL, GBL) of the display unit 200 and the light-emitting control lines EL1, EL2 may be electrically connected to the gate driver 600 via through-holes (TSV3, TSV4). This embodiment differs from the embodiments of FIGS. 16 and 17 in the arrangement of the second scan driver and the light-emitting driver and the connection with the pixel circuit PXC.

[0244] The driver 100 may include a scan driver 610 and an emission driver 620 as the gate driver 600. The scan driver 610 includes a first scan driver 610 and a second scan driver 620 in the embodiment of Figures 16 and 17, and the emission driver 620 is the same as the emission driver 630 in the embodiment of Figures 16 and 17. The scan driver 610 and the emission driver 620 may be disposed on both sides of the first pixel circuit unit 810 in the first direction DR1, respectively.

[0245] However, similarly to the above-described embodiment, only the second transistor T2 of the multiple transistors constituting the pixel circuit PXC may be arranged in the driving unit 100, and the other transistors may be arranged in the display unit 200. Therefore, the first scan line GWL and the data line DL may be arranged in the driving unit 100, and the second scan line GCL, the third scan line GBL, the light emitting control lines EL1 and EL2, and the driving voltage lines VSL, VDL, and VIL may be arranged in the display unit 200.

[0246] According to an embodiment, the display unit 200 may include a plurality of through-hole regions TSA1, TSA2, and TSA3 formed in the non-display area NA. The first through-hole region TSA1 is disposed on the lower side, which is one side of the display area DAA in the second direction DR2. The second through-hole region TSA2 is disposed on the left side, which is one side of the display area DAA in the first direction DR1, and the third through-hole region TSA3 is disposed on the right side, which is the other side of the display area DAA in the first direction DR1. The second through-hole region TSA2 and the third through-hole region TSA3 do not overlap with the driver 100.

[0247] The display unit 200 may include a plurality of first through-holes TSV1 arranged in the display area DAA and a plurality of through-holes TSV2, TSV3, and TSV4 arranged in the non-display area NA. The first through-holes TSV1 are arranged corresponding to the plurality of sub-pixels SP1, SP2, and SP3, respectively, as described above. The first through-holes TSV1 can electrically connect transistors arranged on different single-crystal semiconductor substrates 110 and 210 among the plurality of transistors constituting the pixel circuit PXC. For example, the second transistor T2 can be arranged on the first single-crystal semiconductor substrate 110 and connected to other transistors via the first through-holes TSV1 to constitute the pixel circuit PXC.

[0248] The second through holes TSV2 are arranged in the first through hole area TSA1 of the non-display area NA. The second through holes TSV2 may be connection paths for signal connection wiring that electrically connects the signal terminals STD of the driver 100 and the circuit board 300.

[0249] 23, the plurality of third through holes TSV3 are arranged in the second through hole region TSA2, and the fourth through holes TSV4 are arranged in the third through hole region TSA3. The third through holes TSV3 and the fourth through holes TSV4 are each arranged in the non-display area NA and do not overlap with the first single crystal semiconductor substrate 110 of the driving unit 100. The third through holes TSV3 are arranged to correspond to the plurality of second scan lines GCL (see FIG. 18, etc.) and third scan lines GBL (see FIG. 18, etc.) arranged in the display area DAA, respectively, and the fourth through holes TSV4 are arranged to correspond to the plurality of light-emitting control lines EL1 and EL2 (see FIG. 18, etc.) arranged in the display area DAA, respectively. The number of the third through holes TSV3 may be the same as the number of the second scan lines GCL and the third scan lines GBL, and the number of the fourth through holes TSV4 may be the same as the number of the light-emitting control lines EL1 and EL2. For example, one pixel circuit PXC may be electrically connected to one second scan line GCL and one third scan line GBL. Thus, the number of third through-holes TSV3 may be equal to twice the number of pixel rows of the subpixels SP1, SP2, and SP3 arranged in the display area DAA. Furthermore, one pixel circuit PXC may be electrically connected to one first light-emitting control line EL1 and one second light-emitting control line EL2. Thus, the number of fourth through-holes TSV4 may be equal to twice the number of pixel rows of the subpixels SP1, SP2, and SP3 arranged in the display area DAA.

[0250] Each of the plurality of second scan lines GCL and third scan lines GBL corresponds to the third through-hole TSV3 and may be electrically connected to the connection wiring arranged in the third through-hole TSV3. Each of the second scan lines GCL and third scan lines GBL may be connected to the scan driver 610 of the driver 100 via the connection wiring arranged in the third through-hole TSV3. Each of the plurality of first light-emitting control lines EL1 and second light-emitting control lines EL2 corresponds to the fourth through-hole TSV4 and may be electrically connected to the connection wiring arranged in the fourth through-hole TSV4. Each of the first light-emitting control line EL1 and second light-emitting control line EL2 may be connected to the light-emitting driver 620 of the driver 100 via the connection wiring arranged in the fourth through-hole TSV4.

[0251] Fig. 22 is a schematic cross-sectional view of the display device of Fig. 20 and Fig. 21. Fig. 23 is a schematic view showing the back surface of the display device of Fig. 20 and Fig. 21. Fig. 24 is a cross-sectional view showing a part of the display unit of the display device of Fig. 20 and Fig. 21.

[0252] 22 to 24 , the display device 10 may include a connection wiring layer 500 disposed between the second single-crystal semiconductor substrate 210 of the display unit 200 and the driving circuit layer 120 of the driving unit 100. The connection wiring layer 500 is disposed on the lower surface of the second single-crystal semiconductor substrate 210. The connection wiring layer 500 may include portions of a plurality of routing wires RM1, RM2, RM3, and RM4 disposed thereon, and the routing wires RM1, RM2, RM3, and RM4 may connect the second pixel circuit unit 820 of the display unit 200 and the circuit board 300 to the driving unit 100. The driving circuit layer 120 of the driving unit 100 is electrically connected to the display unit 200 and the circuit board 300 via the routing wires RM1, RM2, RM3, and RM4 of the connection wiring layer 500 to transmit an electrical signal for light emission.

[0253] The first routing wiring RM1 connects the pixel circuit PXC arranged in the display unit 200 to the first pixel circuit unit 810 of the drive unit 100. The first routing wiring RM1 may include a first conductive via RVA1 arranged in the first through-hole TSV1 and a first connection wiring RML1 arranged in the connection wiring layer 500. The first routing wiring RM1 may be arranged in the display area DAA to connect the second transistor T2 of the pixel circuit PXC to other transistors. The description regarding this is the same as that described above, and the description regarding the second routing wiring RM2 is also the same as that described above.

[0254] The third routing wiring RM3 may connect the second and third scan lines GCL, GBL arranged in the display unit 200 to the scan driver 610 arranged in the driver 100. The third routing wiring RM3 may include a third conductive via RVA3 arranged in a third through hole TSV3 formed in the second single-crystal semiconductor substrate 210 and a third connection wiring RML3 arranged in the connection wiring layer 500. The third conductive via RVA3 may be connected to a terminal GTD of the display unit 200, and the terminal GTD may be connected to one of the second and third scan lines GCL, GBL. The multiple third through holes TSV3 are arranged in a second through hole region TSA2 of the non-display region NA of the display unit 200 and do not overlap the driver 100 in the thickness direction. The third routing wiring RM3 may connect the third through holes TSV3 that do not overlap the driver 100 to the scan driver 610. The third routing wire RM3 or the third connection wire RML3 partially overlaps with the driving section 100.

[0255] The fourth routing wiring RM4 may connect the first and second light-emitting control lines EL1 and EL2 arranged in the display unit 200 to the light-emitting driver 620 arranged in the driver 100. The fourth routing wiring RM4 may include a fourth conductive via RVA4 arranged in a fourth through-hole TSV4 formed in the second single-crystal semiconductor substrate 210 and a fourth connection wiring RML4 arranged in the connection wiring layer 500. The multiple fourth through-holes TSV4 are arranged in a third through-hole region TSA3 of the non-display area NA of the display unit 200 and do not overlap the driver 100 in the thickness direction. The fourth routing wiring RM4 connects the fourth through-hole TSV4 that does not overlap the driver 100 to the light-emitting driver 620. The fourth routing wiring RM4 or the fourth connection wiring partially overlaps the driver 100.

[0256] The plurality of second scan lines GCL and third scan lines GBL extend in the first direction DR1 and may be connected to the third through-holes TSV3 in parallel without bending even in the non-display area NA. The plurality of first light-emitting control lines EL1 and second light-emitting control lines EL2 also extend in the first direction DR1 and may be connected to the fourth through-holes TSV4 in parallel without bending even in the non-display area NA. The display device 10 maintains constant spacing between signal lines in the display area DAA and the non-display area NA of the display unit 200, eliminating the need for a fan-out structure in which signal lines are bent and narrowed in the non-display area NA. The spacing between the third through-holes TSV3 and the fourth through-holes TSV4 may also be constant, similar to the spacing between the signal lines. However, routing lines arranged on the back surface of the display unit 200, such as the connection wirings RML3 and RML4 of the third routing wiring RM3 and the fourth routing wiring RM4, connect the driver unit 100, which has a small area, from the edge of the display unit 200, and therefore the spacing becomes narrower as they approach the driver unit 100. In the case of the first routing wiring RM1 as well, the pixel circuits PXC arranged in the display area DAA having a large area are connected to the driving unit 100 having a small area, so the closer to the driving unit 100, the narrower the gap.

[0257] Fig. 25 is a perspective view showing a head-mounted display device according to an embodiment, and Fig. 26 is an exploded perspective view showing an example of the head-mounted display device of Fig. 25.

[0258] Referring to Figures 25 and 26, a head-mounted display device 1000 according to one embodiment includes a first display device 11, a second display device 12, a display device storage section 1100, a storage section cover 1200, a first eyepiece lens 1210, a second eyepiece lens 1220, a head-mounted band 1300, a middle frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and a connector.

[0259] The first display device 11 provides an image to the user's left eye, and the second display device 12 provides an image to the user's right eye. Each of the first display device 11 and the second display device 12 is substantially similar to the display device 10 described with reference to FIG. 1, and therefore, a description of the first display device 11 and the second display device 12 will be omitted.

[0260] The first optical member 1510 is disposed between the first display device 11 and the first eyepiece 1210. The second optical member 1520 is disposed between the second display device 12 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0261] The middle frame 1400 is disposed between the first display device 11 and the control circuit board 1600, and between the second display device 12 and the control circuit board 1600. The middle frame 1400 serves to support and fix the first display device 11, the second display device 12, and the control circuit board 1600.

[0262] The control circuit board 1600 is disposed between the middle frame 1400 and the display device receiving portion 1100. The control circuit board 1600 can be connected to the first display device 11 and the second display device 12 via connectors. The control circuit board 1600 converts an externally input video source into digital video data DATA and transmits the digital video data DATA to the first display device 11 and the second display device 12 via the connectors.

[0263] The control circuit board 1600 transmits digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 11, and transmits digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 12. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 11 and the second display device 12.

[0264] The display device housing 1100 houses the first display device 11, the second display device 12, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and a connector. The housing cover 1200 is disposed to cover one open side of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for receiving the user's left eye and a second eyepiece 1220 for receiving the user's right eye. Although the drawings show the first eyepiece 1210 and the second eyepiece 1220 as being separately disposed, the present invention is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be integrated.

[0265] The first eyepiece 1210 is aligned with the first display device 11 and the first optical member 1510, and the second eyepiece 1220 is aligned with the second display device 12 and the second optical member 1520. Thus, the user can view the image of the first display device 11 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and the image of the second display device 12 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0266] The head mounting band 1300 serves to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 can be maintained in a state where they are positioned over the user's left and right eyes, respectively. If the display device housing 1100 is realized to be lightweight and compact, the head mounted display device 1000 may include an eyeglass frame instead of the head mounting band 1300.

[0267] The head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, an external connection port for receiving a video source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0268] FIG. 27 is a perspective view showing a head mounted display device according to an embodiment.

[0269] 27, a head mounted display device 1000_1 according to an embodiment may be a display device in the form of glasses, in which a lightweight and compact display device housing 1200_1 is realized. The head mounted display device 1000_1 according to an embodiment may include a display device 13, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path converting member 1070, and the display device housing 1200_1.

[0270] The display device housing 1200_1 may include a display device 13, an optical member 1060, and an optical path converting member 1070. An image displayed on the display device 13 is enlarged by the optical member 1060, and the optical path is converted by the optical path converting member 1070, and the image is provided to the right eye of the user via the right eye lens 1020. This allows the user to view an augmented reality image, which is a combination of a virtual image displayed on the display device 13 and a real image seen through the right eye lens 1020, via the right eye.

[0271] Although the drawings show that the display device housing 1200_1 is disposed at the right end of the support frame 1030, the present invention is not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, in which case an image from the display device 13 may be provided to the left eye of the user. Alternatively, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, in which case the user may view an image displayed on the display device 13 through both the left and right eyes.

[0272] According to the above-described embodiment, one of the problems to be solved by the present invention can be said to be to provide an ultra-small display device including a plurality of single crystal semiconductor substrates different from one another, and a head-mounted display device including the same.

[0273] Furthermore, according to the above embodiment, one of the problems to be solved by the present invention is to provide an ultra-small display device realized by an efficient layout design of wiring arranged on two different semiconductor substrates.

[0274] According to the above embodiment, the display device may include two single-crystal semiconductor substrates, and pixel circuits for emitting light from light-emitting elements may be disposed separately on the two single-crystal semiconductor substrates. Furthermore, the display device may have wiring connected to the separated pixel circuits disposed on the two single-crystal semiconductor substrates. Furthermore, since the wiring is disposed separately on the two single-crystal semiconductor substrates, the display device may be able to design an efficient current path and prevent a voltage drop depending on the pixel position.

[0275] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0276] 10 Display device 100 Drive unit 110 First single crystal semiconductor substrate 120 Drive Circuit Layer 200 Display section 210 Second single crystal semiconductor substrate 230 Display layer 300 Circuit Boards 400 Drive circuit section 500 connection wiring layers 600 Gate driver 700 Data Drive Unit 810,820 Pixel circuit section 1000 Head-mounted display device EML display element layer TFE sealing layer OPL optical layer INS Interlayer insulation layer SINS Semiconductor insulating layer

Claims

1. a first single crystal semiconductor substrate on which a plurality of first transistors are formed; a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate and having a plurality of second transistors formed thereon; a connection wiring layer disposed between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate; the second single-crystal semiconductor substrate includes a display region in which a plurality of light-emitting elements electrically connected to the second transistor are arranged, and a non-display region around the display region; a display device including a plurality of first through holes formed in the display region of the second single crystal semiconductor substrate and in which first conductive vias connected to the first transistor and the second transistor, respectively, are arranged.

2. a first driving voltage wiring disposed in a common electrode contact region of the non-display region that is disposed on at least one side of the display region, and a second driving voltage wiring disposed in the display region, the second transistor is connected to the second driving voltage wiring; The display device according to claim 1 , wherein the light emitting element is connected to the first driving voltage wiring.

3. The display device according to claim 1 , wherein a planar area of ​​the first single crystal semiconductor substrate is smaller than a planar area of ​​the second single crystal semiconductor substrate.

4. the connection wiring layer includes a plurality of first connection wirings connected to the first conductive vias; The display device according to claim 3 , wherein a portion of each of the plurality of first connection wirings does not overlap with the first single-crystal semiconductor substrate.

5. The display device of claim 1 , wherein the second single-crystal semiconductor substrate includes a pad region disposed on one side of the display region, and a plurality of second through holes disposed between the pad region and the display region.

6. The display device of claim 1 , further comprising: a first scan driver and a data driver disposed on the first single-crystal semiconductor substrate and including the plurality of first transistors.

7. a first scan line disposed on the first single crystal semiconductor substrate and connected to the first transistor and the first scan driver; The display device according to claim 6 , further comprising a data line disposed on the first single-crystal semiconductor substrate and connected to the first transistor and the data driver.

8. The display device according to claim 1 , wherein the second single-crystal semiconductor substrate includes a plurality of second scan lines and a plurality of light-emission control lines electrically connected to some of the plurality of second transistors.

9. 9. The display device of claim 8, wherein the second single-crystal semiconductor substrate includes a second scan driver disposed in the non-display area and connected to the plurality of second scan lines, and a light-emitting driver disposed in the non-display area and connected to the light-emitting control lines.

10. the second single crystal semiconductor substrate includes a plurality of third through holes in which conductive vias connected to the second scan lines are disposed, and a plurality of fourth through holes in which conductive vias connected to the light emission control lines are disposed, 9. The display device of claim 8, wherein the first single crystal semiconductor substrate includes a second scan driver connected to the second scan line via a conductive via arranged in the third through hole, and a light emission driver connected to the light emission control line via a conductive via arranged in the fourth through hole.

11. The display device according to claim 10 , wherein the third through holes and the fourth through holes do not overlap with the first single-crystal semiconductor substrate.

12. The display device of claim 10 , wherein the number of the third through holes is the same as the number of the fourth through holes.

13. the connection wiring layer includes connection wiring connected to a plurality of conductive vias arranged in the plurality of third through holes and the plurality of fourth through holes; The display device according to claim 10 , wherein a portion of each of the connection wirings does not overlap with the first single-crystal semiconductor substrate.

14. The display device according to claim 1 , wherein the number of the first through holes is the same as the number of the light-emitting elements arranged in the display region.

15. The display device according to claim 1 , wherein the minimum line width of the first transistor is smaller than the minimum line width of the second transistor.

16. a first single-crystal semiconductor substrate on which a plurality of first transistors are formed and on which a plurality of first scan lines and a plurality of data lines are arranged; a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate, on which a plurality of second transistors are formed and on which at least one driving voltage line connected to a portion of the plurality of second transistors is disposed; a display element layer disposed on the second single crystal semiconductor substrate and including a plurality of light emitting elements; a connection wiring layer disposed between the display element layer and the first single-crystal semiconductor substrate; the plurality of light-emitting elements are electrically connected to the driving voltage line, the first transistor, and the second transistor; the connection wiring layer includes a first connection wiring connected to a first conductive via disposed in a first through hole penetrating the second single-crystal semiconductor substrate, The first conductive via is electrically connected to the first transistor and the second transistor.

17. 17. The display device according to claim 16, wherein the plurality of driving voltage lines include a first driving voltage line connected to one electrode of the light-emitting element, and a second driving voltage line electrically connected to the second transistor.

18. The display device of claim 16 , further comprising a plurality of second scan lines and a plurality of light-emitting control lines disposed on the second single-crystal semiconductor substrate.

19. The display device according to claim 16 , wherein a planar area of ​​the first single crystal semiconductor substrate is smaller than a planar area of ​​the second single crystal semiconductor substrate.

20. a frame attached to a user's body and corresponding to the left and right eyes; a plurality of display devices disposed on the frame; a lens disposed on each of the plurality of display devices; The display device includes a first single-crystal semiconductor substrate having a plurality of first transistors formed thereon; a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate and having a plurality of second transistors formed thereon; a connection wiring layer disposed between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate; the second single-crystal semiconductor substrate includes a display region in which a plurality of light-emitting elements electrically connected to the second transistor are arranged, and a non-display region around the display region; A head-mounted display device including a plurality of first through holes formed in the display region of the second single crystal semiconductor substrate and in which first conductive vias connected to the first transistor and the second transistor, respectively, are arranged.

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