Semiconductor device

Abstract

To prevent reduction in short-circuit resistance of a semiconductor device and delay of a gate signal.SOLUTION: A semiconductor device includes an emitter electrode (6) disposed on a cell region, a gate wiring (51) disposed outside the emitter electrode (6), and a gate finger wiring (61) having one end connected to the gate wiring (51) and extending on the cell region. The emitter electrodes (6) adjacent to each other with the gate finger wiring (61) interposed between them are connected by an emitter electrode connection portion (71) disposed in a region between the other end of the gate finger wiring (61) and the gate wiring (51). In a semiconductor substrate, a first active trench gate (111) intersecting the gate finger wiring (61) and a second active trench gate (112) drawing out the first active trench gate (111) positioned under the emitter electrode connection portion (71) to under the gate finger wiring (61) are formed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Vertical semiconductor devices are known that have electrodes on both the front and back sides and conduct electricity in the vertical direction, i.e., the direction connecting the front and back sides. For example, Patent Document 1 listed below discloses a configuration in which the electrode on the front side of a vertical semiconductor device (hereinafter referred to as the "front electrode") is divided into multiple parts by gate liners, which are control wiring for transmitting gate signals to the gate electrodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-210519 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device in which the surface electrode is divided into multiple parts by a gate liner, as in Patent Document 1, the flowing current becomes unbalanced and the short-circuit resistance is likely to decrease. However, if the gate liner is bypassed so that the surface electrode is not divided, there is a concern that the gate signal may be delayed.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device that can prevent a decrease in short-circuit resistance and a delay in a gate signal. [Means for solving the problem]

[0006] a gate finger wiring electrically connected to the gate wiring and extending over the cell region, one end of the gate finger wiring being connected to the gate wiring and the other end of the gate finger wiring not reaching the gate wiring, and adjacent emitter electrodes sandwiching the gate finger wiring being electrically connected through an emitter electrode connecting portion being arranged in a region between the other end of the gate finger wiring and the gate wiring; and the active trench gate including: a first active trench gate extending in a first direction intersecting the extension direction of the gate finger wiring; and a second active trench gate connected to the first active trench gate located below the emitter electrode connecting portion, extending in a second direction parallel to the extension direction of the gate finger wiring, and drawn out to below the gate finger wiring or the gate wiring. [Effects of the Invention]

[0007] According to the semiconductor device according to the present disclosure, it is possible to prevent a decrease in short-circuit resistance and a delay in gate signals. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view of a chip of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a chip of a semiconductor device according to a first embodiment. [Figure 3] 1 is a plan view of an IGBT region of a semiconductor device according to a first embodiment. [Figure 4] 2 is a cross-sectional view of an IGBT region of the semiconductor device according to the first embodiment. [Figure 5] 2 is a cross-sectional view of an IGBT region of the semiconductor device according to the first embodiment. [Figure 6]2 is a plan view of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 7] 2 is a cross-sectional view of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 8] 2 is a cross-sectional view of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 9] 2 is a cross-sectional view of the boundary between an IGBT region and a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 10] 1 is a plan view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a first embodiment. [Figure 11] 1 is a cross-sectional view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a first embodiment. [Figure 12] 10 is a plan view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a second embodiment. FIG. [Figure 13] 10 is a diagram showing the shape of an emitter electrode coupling portion of a semiconductor device according to a second embodiment. FIG. [Figure 14] FIG. 11 is a plan view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a third embodiment. [Figure 15] FIG. 10 is a plan view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a fourth embodiment. [Figure 16] FIG. 11 is a plan view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a fifth embodiment. [Figure 17] FIG. 11 is a cross-sectional view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a fifth embodiment. [Figure 18] FIG. 13 is a plan view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a sixth embodiment. [Figure 19] FIG. 13 is a cross-sectional view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a sixth embodiment. [Figure 20] FIG. 13 is a plan view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a seventh embodiment. [Figure 21] FIG. 13 is a cross-sectional view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a seventh embodiment. [Figure 22]FIG. 13 is a plan view of the vicinity of an emitter electrode connecting region of a semiconductor device according to an eighth embodiment. [Figure 23] FIG. 20 is a cross-sectional view of the vicinity of an emitter electrode connecting region of a semiconductor device according to an eighth embodiment. [Figure 24] FIG. 20 is a plan view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a ninth embodiment. [Figure 25] FIG. 23 is a plan view of the vicinity of an emitter electrode connecting region of a semiconductor device according to a tenth embodiment. [Figure 26] FIG. 22 is a cross-sectional view of the vicinity of an emitter electrode connecting region of a semiconductor device according to an eleventh embodiment. [Figure 27] FIG. 23 is a plan view of a chip of a semiconductor device according to a twelfth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] In the following description, n and p indicate the conductivity types of semiconductors, and in this disclosure, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. - indicates that the impurity concentration is lower than n, and n + indicates that the impurity concentration is higher than n. Similarly, p - indicates that the impurity concentration is lower than p, and p + indicates that the impurity concentration is higher than p.

[0010] The impurity concentration of each region is defined by its peak concentration, i.e., a region with a high (or low) impurity concentration means a region with a high (or low) peak impurity concentration.

[0011] <First Embodiment> The following describes the configuration of the semiconductor device according to embodiment 1. The semiconductor device may include a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), an RC-IGBT (Reverse Conducting IGBT), or the like as a semiconductor element, but the following description will be given assuming that the semiconductor element is an RC-IGBT.

[0012] The material of the semiconductor element may be silicon (Si) or a wide bandgap semiconductor such as silicon carbide (SiC). A semiconductor device formed using a wide bandgap semiconductor is superior to a semiconductor device using silicon in terms of operation at high voltages, large currents, and high temperatures. In addition to silicon carbide, wide bandgap semiconductors include gallium nitride (GaN)-based materials and diamond.

[0013] FIG. 1 is a plan view showing a semiconductor device that is an RC-IGBT. FIG. 2 is a plan view showing a semiconductor device that is an RC-IGBT with another configuration. The semiconductor device 100 shown in FIG. 1 has IGBT regions 10 and diode regions 20 arranged side by side in a stripe pattern, and may be simply called a "stripe type." The semiconductor device 100 shown in FIG. 2 has a plurality of diode regions 20 arranged vertically and horizontally, and the IGBT regions 10 are arranged around the diode regions 20, and may be simply called an "island type."

[0014] (1) Stripe-type overall planar structure In FIG. 1 , a semiconductor device 100 includes an IGBT region 10 and a diode region 20 within the semiconductor device. The IGBT region 10 and the diode region 20 extend from one end to the other end of the semiconductor device 100 and are arranged in alternating stripes in a direction perpendicular to the extension direction of the IGBT region 10 and the diode region 20. In FIG. 1 , three IGBT regions 10 and two diode regions are shown, and all of the diode regions 20 are sandwiched between the IGBT regions 10. However, the number of IGBT regions 10 and the diode region 20 is not limited to this. The number of IGBT regions 10 may be three or more or less, and the number of diode regions 20 may be two or more or less. Furthermore, the positions of the IGBT regions 10 and the diode regions 20 in FIG. 1 may be interchanged, or all of the IGBT regions 10 may be sandwiched between the diode regions 20. Furthermore, one IGBT region 10 and one diode region 20 may be provided adjacent to each other.

[0015] 1, a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. As will be described later, an emitter electrode of an RC-IGBT is arranged on the cell region of the semiconductor device 100.

[0016] In this embodiment, a gate wiring region 50 is provided around the cell region, in which gate wiring is arranged to transmit gate signals that control the flow of current through the semiconductor device 100. In addition, a gate finger wiring region 60 is provided in which gate finger wiring connected to the gate wiring is arranged, extending from one side of the gate wiring region 50 (the side closer to the pad region 40) into the cell region. The tip of the gate finger wiring region 60 does not reach the opposite side of the gate wiring region 50 (the side farther from the pad region 40). In other words, one end of the gate finger wiring 61 is connected to the gate wiring 51, but the other end is not connected to the gate wiring 51.

[0017] Therefore, the gate finger wiring region 60 does not completely divide the IGBT region 10, and a gap exists between the tip of the gate finger wiring region 60 and the gate wiring region 50. Because the gate finger wiring is formed in the same layer as the emitter electrode, the emitter electrode is separated by the gate finger wiring. However, adjacent emitter electrode portions sandwiching the gate finger wiring are connected to each other via an emitter electrode connection region 70, which is the region between the tip of the gate finger wiring region 60 and the gate wiring region 50. The gate wiring and gate finger wiring will be described in detail later in "(6) Structure of Gate Wiring and Gate Finger Wiring."

[0018] A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A known breakdown voltage maintaining structure can be appropriately selected and provided in the termination region 30. The breakdown voltage maintaining structure may be configured, for example, by providing a field limiting ring (FLR) on the first main surface side, which is the front surface side of the semiconductor device 100, in which the combined region of the cell region and the pad region 40 is surrounded by a p-type termination well layer of a p-type semiconductor, or a variation of lateral doping (VLD) in which the combined region of the cell region and the pad region 40 is surrounded by a p-type termination well layer with a concentration gradient. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. Alternatively, a p-type termination well layer may be provided over substantially the entire pad region 40, or an IGBT cell or a diode cell may be provided in the pad region 40.

[0019] The control pad 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or temperature sense diode pads 41d and 41e. The current sense pad 41a is a control pad for detecting a current flowing in a cell region of the semiconductor device 100, and is electrically connected to a portion of the IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the semiconductor device 100, a current that is one-several to one-tens-of-thousandth of the current flowing in the entire cell region flows.

[0020] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 100. The Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. + The Kelvin emitter pad 41b and the p-type base layer are electrically connected to the p-type emitter layer, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. + The temperature sensing diode pads 41d and 41e may be electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 100 via a mold contact layer. The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the cell region, and the temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0021] (2) Island-type overall planar structure 2, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 within a single semiconductor device. A plurality of diode regions 20 are arranged side by side in both the vertical and horizontal directions within the semiconductor device, and the diode regions 20 are surrounded by the IGBT region 10. In other words, a plurality of diode regions 20 are arranged in an island shape within the IGBT region 10. In FIG. 2, the diode regions 20 are shown arranged in a matrix shape with four columns in the left-right direction of the page and two rows in the upper-right direction of the page, but the number and arrangement of the diode regions 20 are not limited to this. It is sufficient that one or a plurality of diode regions 20 are arranged in a scattered manner within the IGBT region 10, and each diode region 20 is surrounded by the IGBT region 10.

[0022] 2, a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided. The IGBT region 10 and the diode region 20 are collectively called a cell region.

[0023] Even when the RC-IGBT has an island-type structure, a gate wiring region 50 in which gate wiring is arranged is provided around the cell region. In addition, a gate finger wiring region 60 in which gate finger wiring is arranged is provided so as to extend from one side of the gate wiring region 50 into the cell region. An emitter electrode connecting region 70 is provided in the gap between the tip of the gate finger wiring region 60 and the gate wiring region 50.

[0024] A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A known breakdown voltage maintaining structure can be appropriately selected and provided in the termination region 30. The breakdown voltage maintaining structure may be configured, for example, by providing a field limiting ring (FLR) on the first main surface side, which is the front surface side of the semiconductor device 100, in which the combined region of the cell region and the pad region 40 is surrounded by a p-type termination well layer of a p-type semiconductor, or a variation of lateral doping (VLD) in which the combined region of the cell region and the pad region 40 is surrounded by a p-type termination well layer with a concentration gradient. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. Alternatively, a p-type termination well layer may be provided over substantially the entire pad region 40, or an IGBT cell or a diode cell may be provided in the pad region 40.

[0025] The control pad 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or temperature sense diode pads 41d and 41e. The current sense pad 41a is a control pad for detecting a current flowing in a cell region of the semiconductor device 100, and is electrically connected to a portion of the IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the semiconductor device 100, a current that is one-several to one-tens-of-thousandth of the current flowing in the entire cell region flows.

[0026] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 100. The Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. + The Kelvin emitter pad 41b and the p-type base layer are electrically connected to the p-type emitter layer, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. +The temperature sensing diode pads 41d and 41e may be electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 100 via a mold contact layer. The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the cell region, and the temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0027] (3) Example of the structure of the IGBT region 10 Fig. 3 is a partially enlarged plan view showing the configuration of an IGBT region of a semiconductor device that is an RC-IGBT. Figs. 4 and 5 are cross-sectional views showing the configuration of the IGBT region of a semiconductor device that is an RC-IGBT. Fig. 3 is an enlarged view of the region surrounded by dashed line 82 in semiconductor device 100 shown in Fig. 1 or 2. Fig. 4 is a cross-sectional view of semiconductor device 100 shown in Fig. 3 taken along dashed line AA, and Fig. 5 is a cross-sectional view of semiconductor device 100 shown in Fig. 3 taken along dashed line BB.

[0028] As shown in Fig. 3, active trench gates 11 and dummy trench gates 12 are provided in a striped pattern in the IGBT region 10. In the semiconductor device 100 of Fig. 1, the active trench gates 11 and dummy trench gates 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 is the longitudinal direction of the active trench gates 11 and dummy trench gates 12. On the other hand, in the semiconductor device 100 of Fig. 2, there is no particular distinction between the longitudinal direction and the lateral direction of the IGBT region 10, but the longitudinal direction of the active trench gates 11 and dummy trench gates 12 may be the left-right direction on the paper, or the vertical direction on the paper may be the longitudinal direction of the active trench gates 11 and dummy trench gates 12.

[0029] The active trench gate 11 is configured by providing a gate trench electrode 11a in a trench formed in the semiconductor substrate with a gate trench insulating film 11b interposed therebetween. The dummy trench gate 12 is configured by providing a dummy trench electrode 12a in a trench formed in the semiconductor substrate with a dummy trench insulating film 12b interposed therebetween. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100.

[0030] n + The n-type emitter layer 13 is provided on both sides of the active trench gate 11 in the width direction so as to contact the gate trench insulating film 11b. + The emitter layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+17 / cm 3 ~1.0E+20 / cm 3 n + The emitter layer 13 is p + The contact layer 14 is formed alternately with the contact layer 14. + The contact layer 14 is also provided between two adjacent dummy trench gates 12. + The contact layer 14 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 is.

[0031] As shown in FIG. 3 , the IGBT region 10 of the semiconductor device 100 is configured such that three active trench gates 11 are lined up next to three dummy trench gates 12, and three active trench gates 11 are lined up next to three dummy trench gates 12. In this manner, the IGBT region 10 is configured such that sets of active trench gates 11 and sets of dummy trench gates 12 are alternately arranged. In FIG. 3 , the number of active trench gates 11 included in one set of active trench gates 11 is three, but it may be one or more. Furthermore, the number of dummy trench gates 12 included in one set of dummy trench gates 12 may be one or more, and the number of dummy trench gates 12 may be zero. In other words, all of the trenches provided in the IGBT region 10 may be active trench gates 11.

[0032] 4 is a cross-sectional view of the semiconductor device 100 taken along the dashed line AA in FIG. 3, and is a cross-sectional view of the IGBT region 10. The semiconductor device 100 is an n-type semiconductor device made of a semiconductor substrate. - The n-type drift layer 1 is - The drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 In FIG. 4, the semiconductor substrate is + type emitter layer 13 and p + The range is from the p-type contact layer 14 to the p-type collector layer 16. + type emitter layer 13 and p + The upper end of the p-type contact layer 14 on the paper surface is called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper surface is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. In the IGBT region 10, which is the cell region, the semiconductor device 100 has an n-type contact layer between the first main surface and the second main surface opposite to the first main surface. - The semiconductor device has a type drift layer 1.

[0033] As shown in FIG. 4, in the IGBT region 10, n- On the first main surface side of the n-type drift layer 1, - The n-type carrier accumulation layer 2 has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+13 / cm 3 ~1.0E+17 / cm 3 In the semiconductor device 100, the n-type carrier accumulation layer 2 is not provided, and the n-type carrier accumulation layer 2 shown in FIG. - The n-type drift layer 1 may be provided. By providing the n-type carrier accumulation layer 2, it is possible to reduce the current loss when a current flows through the IGBT region 10. - The combined layer and the type drift layer 1 may be called a drift layer.

[0034] The n-type carrier accumulation layer 2 is - n-type impurities are ion-implanted into the semiconductor substrate that constitutes the n-type drift layer 1, and then annealed to convert the implanted n-type impurities into n-type impurities. - The dopant is formed by diffusing it into the semiconductor substrate, which is the type drift layer 1.

[0035] A p-type base layer 15 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, there is provided an n-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11. + A type emitter layer 13 is provided, and a p + A contact layer 14 is provided. + type emitter layer 13 and p + The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15.+ When it is necessary to distinguish between the p-type contact layer 14 and the p-type base layer 15, they may be referred to individually. + The p-type contact layer 14 and the p-type base layer 15 may be collectively referred to as a p-type base layer.

[0036] In addition, the semiconductor device 100 has n - On the second main surface side of the n-type drift layer 1, - The n-type buffer layer 3 has a higher concentration of n-type impurities than the p-type drift layer 1. The n-type buffer layer 3 is provided to prevent a depletion layer extending from the p-type base layer 15 toward the second main surface from punching through when the semiconductor device 100 is in an off state. The n-type buffer layer 3 is doped with, for example, phosphorus (P) or protons (H + ) may be injected to form phosphorus (P) and protons (H + The n-type buffer layer 3 may be formed by implanting both n-type impurities. 3 ~1.0E+18 / cm 3 is.

[0037] The semiconductor device 100 does not have the n-type buffer layer 3, and the n-type buffer layer 3 shown in FIG. - The n-type buffer layer 3 and the n-type drift layer 1 may be provided. - The combined layer and the type drift layer 1 may be called a drift layer.

[0038] In the semiconductor device 100, a p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. - A p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0E+16 / cm 3 ~1.0E+20 / cm 3The p-type collector layer 16 forms the second main surface of the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region 30, and the portion of the p-type collector layer 16 provided in the termination region 30 forms a p-type termination collector layer 16a. Furthermore, the p-type collector layer 16 may be provided so that a portion thereof protrudes from the IGBT region 10 into the diode region 20.

[0039] As shown in FIG. 4, the semiconductor device 100 includes a first main surface of the semiconductor substrate, a p-type base layer 15, and an n-type - A trench is formed in the n-type drift layer 1. A gate trench electrode 11a is provided in the trench via a gate trench insulating film 11b, thereby forming an active trench gate 11. The gate trench electrode 11a is connected to the n-type drift layer 1 via the gate trench insulating film 11b. - The n-type drift layer 1 is opposed to the n-type drift layer 1. A dummy trench electrode 12a is provided in the trench via a dummy trench insulating film 12b, thereby forming a dummy trench gate 12. The dummy trench electrode 12a is connected to the n-type drift layer 1 via the dummy trench insulating film 12b. - The gate trench insulating film 11b of the active trench gate 11 faces the p-type base layer 15 and the n-type drift layer 1. + The active trench gate 11 is in contact with the p-type emitter layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0040] As shown in FIG. 4, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi, which is an alloy of titanium and silicon (Si). As shown in FIG. 4, the barrier metal 5 is formed of n + type emitter layer 13, p +ohmic contact with the contact layer 14 and the dummy trench electrode 12a, + type emitter layer 13, p + The barrier metal 5 is electrically connected to the contact layer 14 and the dummy trench electrode 12a. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 may be formed of an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or may be an electrode made of a multi-layer metal film formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film. Furthermore, if there are fine regions, such as between adjacent interlayer insulating films 4, where the emitter electrode 6 cannot be satisfactorily embedded, tungsten, which has better embedding properties than the emitter electrode 6, may be disposed in the fine regions, and the emitter electrode 6 may be provided on the tungsten. Note that, in the case where the barrier metal 5 is not provided, n + type emitter layer 13, p + An emitter electrode 6 may be provided on the contact layer 14 and the dummy trench electrode 12a. + The barrier metal 5 may be provided only on an n-type semiconductor layer such as the n-type emitter layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as an emitter electrode. Although FIG. 4 shows a diagram in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, the interlayer insulating film 4 may be formed on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a may be electrically connected in another cross section.

[0041] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. The collector electrode 7 may be made of an aluminum alloy or an aluminum alloy and a plating film, similar to the emitter electrode 6. The collector electrode 7 may also have a different structure from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0042] 5 is a cross-sectional view of the semiconductor device 100 taken along dashed line BB in FIG. 3, and is a cross-sectional view of the IGBT region 10. The cross-sectional view taken along dashed line AA in FIG. 4 is a cross-sectional view of the n-type IGBT region 10 provided on the first main surface side of the semiconductor substrate in contact with the active trench gate 11. + The difference is that the n-type emitter layer 13 is not visible in the cross section taken along the dashed line BB in FIG. + The p-type emitter layer 13 is selectively provided on the first main surface side of the p-type base layer. + The p-type contact layer 14 is collectively called the p-type base layer.

[0043] (4) Example of the structure of the diode region 20 Fig. 6 is a partially enlarged plan view showing the configuration of a diode region of a semiconductor device that is an RC-IGBT. Figs. 7 and 8 are cross-sectional views showing the configuration of a diode region of a semiconductor device that is an RC-IGBT. Fig. 6 is an enlarged view of a region surrounded by a dashed line 83 in the semiconductor device 100 shown in Fig. 1. Fig. 7 is a cross-sectional view taken along dashed line CC of the semiconductor device 100 shown in Fig. 6. Fig. 8 is a cross-sectional view taken along dashed line DD of the semiconductor device 100 shown in Fig. 6.

[0044] The diode trench gate 21 extends from one end side of the diode region 20, which is a cell region, to the other opposing end side along the first main surface of the semiconductor device 100. The diode trench gate 21 is configured by providing a diode trench electrode 21a via a diode trench insulating film 21b in a trench formed in the semiconductor substrate of the diode region 20. The diode trench electrode 21a is connected to the n-type MOS transistor 100 via the diode trench insulating film 21b. - The p-type drift layer 1 is opposed to the p-type drift layer 1. + A p-type contact layer 24 and a p-type anode layer 25 are provided. + The contact layer 24 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0E+15 / cm3 ~1.0E+20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 p + The p-type contact layers 24 and the p-type anode layers 25 are alternately provided in the longitudinal direction of the diode trench gate 21 .

[0045] 7 is a cross-sectional view of the semiconductor device 100 taken along the dashed line CC in FIG. 6, and is a cross-sectional view of the diode region 20. The semiconductor device 100 has an n-type semiconductor substrate in the diode region 20 as well as in the IGBT region 10. - The n-type drift layer 1 is formed in the diode region 20. - n-type drift layer 1 and IGBT region 10 - The p-type drift layer 1 is formed integrally and continuously from the same semiconductor substrate. + Type contact layer 24 to n + The area extends to the cathode layer 26. + The upper end of the n-type contact layer 24 in the drawing corresponds to the first main surface of the semiconductor substrate. + The lower end of the cathode layer 26 in the drawing is called the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are flush with each other, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are flush with each other.

[0046] As shown in FIG. 7, in the diode region 20, similarly to the IGBT region 10, n - An n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, -An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the diode region 20 have the same configuration as the n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the IGBT region 10. Note that it is not always necessary to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20, and even if the n-type carrier accumulation layer 2 is provided in the IGBT region 10, the diode region 20 may not have the n-type carrier accumulation layer 2. Also, like the IGBT region 10, - The n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as a drift layer.

[0047] A p-type anode layer 25 is provided on the first major surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is - The p-type anode layer 25 is provided between the first main surface and the first drift layer 1. The p-type anode layer 25 may have the same p-type impurity concentration as the p-type base layer 15 of the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously. Alternatively, the p-type impurity concentration of the p-type anode layer 25 may be set lower than the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10, thereby reducing the number of holes injected into the diode region 20 during diode operation. Reducing the number of holes injected during diode operation can reduce recovery loss during diode operation.

[0048] The first main surface side of the p-type anode layer 25 is + A contact layer 24 is provided. + The concentration of the p-type impurity in the contact layer 24 is + The concentration of the p-type impurity in the contact layer 14 may be the same as or different from the p-type impurity in the contact layer 14. + The p-type contact layer 24 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 24 is a region having a higher concentration of p-type impurities than the p-type anode layer 25. +When it is necessary to distinguish between the p-type contact layer 24 and the p-type anode layer 25, they may be referred to individually. + The p-type contact layer 24 and the p-type anode layer 25 may be collectively referred to as a p-type anode layer.

[0049] In the diode region 20, an n-type buffer layer 3 is provided on the second main surface side thereof. + A cathode layer 26 is provided. + The cathode layer 26 is an n-type - The n-type drift layer 1 is provided between the n-type drift layer 1 and the second main surface. + The cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+16 / cm 3 ~1.0E+21 / cm 3 As shown in Figure 2, n + The cathode layer 26 is provided on part or all of the diode region 20. + The cathode layer 26 forms the second main surface of the semiconductor substrate. + The p-type impurity is further selectively implanted into the region where the p-type cathode layer 26 is formed, + A part of the region where the p-type cathode layer 26 is formed may be made into a p-type semiconductor to provide a p-type cathode layer.

[0050] As shown in FIG. 7, the diode region 20 of the semiconductor device 100 includes an n-type anode layer 25 extending from the first main surface of the semiconductor substrate. - A trench is formed in the diode region 20, reaching the n-type drift layer 1. A diode trench electrode 21a is provided in the trench of the diode region 20 via a diode trench insulating film 21b, thereby forming a diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. - The semiconductor layer 1 faces the semiconductor layer 2 .

[0051] As shown in FIG. 7, the diode trench electrode 21a and p +A barrier metal 5 is provided on the contact layer 24. The barrier metal 5 is formed between the diode trench electrode 21a and the p + ohmic contact with the contact layer 24, and the diode trench electrode and p + The barrier metal 5 is electrically connected to the diode trench electrode 21a and the p-type contact layer 24. The barrier metal 5 may have the same configuration as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. As in the case of the IGBT region 10, the barrier metal 5 is not provided and the diode trench electrode 21a and the p-type contact layer 24 are electrically connected to the diode trench electrode 21a and the p-type contact layer 24. + The contact layer 24 and the emitter electrode 6 may be in ohmic contact. Although FIG. 7 shows a diagram in which the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in another cross section.

[0052] n + A collector electrode 7 is provided on the second main surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is an n-type + ohmic contact with the n-type cathode layer 26, + The cathode layer 26 is electrically connected to the cathode layer 26 .

[0053] 8 is a cross-sectional view of the semiconductor device 100 taken along dashed line DD in FIG. 6, and is a cross-sectional view of the diode region 20. The cross-sectional view taken along dashed line CC in FIG. 7 is a cross-sectional view of the semiconductor device 100 taken along dashed line CC in FIG. 7, and is a cross-sectional view of the diode region 20. + The difference is that the p-type contact layer 24 is not provided, and the p-type anode layer 25 constitutes the first main surface of the semiconductor substrate. +The p-type contact layer 24 is selectively provided on the first major surface side of the p-type anode layer 25 .

[0054] (5) Boundary region between the IGBT region 10 and the diode region 20 9 is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT. FIG. 9 is a cross-sectional view taken along dashed line GG in the semiconductor device 100 shown in FIG.

[0055] 9, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided so as to protrude into the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20. By providing the p-type collector layer 16 so as to protrude into the diode region 20, the n-type collector layer 16 of the diode region 20 + The distance between the cathode layer 26 and the active trench gate 11 can be increased, and even when a gate drive voltage is applied to the gate trench electrode 11a during freewheeling diode operation, n + This can prevent current from flowing through the cathode layer 26. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 100, which is an RC-IGBT, the distance U1 may be zero or a distance less than 100 μm.

[0056] (6) Gate wiring and gate finger wiring structure Fig. 10 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 shown in Fig. 1 or 2. Fig. 11 is a cross-sectional view taken along line A1-A2 shown in Fig. 10. Figs. 10 and 11 show the emitter electrode 6, which is a surface electrode arranged in the cell region, the gate wiring 51 arranged in the gate wiring region 50, the gate finger wiring 61 arranged in the gate finger wiring region 60, the emitter electrode connecting portion 71 arranged in the emitter electrode connecting region 70, and the first active trench gate 111 and the second active trench gate 112 formed in the semiconductor substrate.

[0057] The first active trench gate 111 and the second active trench gate 112 are parts of the active trench gate 11. That is, the active trench gate 11 includes the first active trench gate 111 and the second active trench gate 112. The first active trench gate 111 extends in a first direction perpendicular to the extension direction of the gate finger wiring 61. The second active trench gate 112 is electrically connected to the first active trench gate 111 and extends in a second direction parallel to the extension direction of the gate finger wiring 61. The second active trench gate 112 extends to below the gate finger wiring 61. The first active trench gate 111 is a main part of the active trench gate 11, and the active trench gate 11 shown in FIGS. 3, 4, 5, and 9 corresponds to the first active trench gate 111.

[0058] As shown in FIG. 11, the gate wiring 51 and the gate finger wiring 61 are formed on the interlayer insulating film 4, similar to the emitter electrode 6 (the barrier metal 5 is not shown in FIG. 11). The gate wiring 51 electrically connects the active trench gate 11 and the gate pad 41c. The gate finger wiring 61 is provided so as to be electrically connected to the gate wiring 51. Therefore, a gate signal input to the gate pad 41c is transmitted to the gate finger wiring 61 via the gate wiring 51.

[0059] Furthermore, the gate finger wiring 61 is connected to the first active trench gate 111 and the second active trench gate 112 through contact holes formed in the interlayer insulating film 4 (the rectangles with diagonal lines drawn in FIG. 10 indicate the positions of the contact holes). Therefore, the gate signal is transmitted to the active trench gate 11 not only through the gate wiring 51 but also through the gate finger wiring 61, thereby suppressing delay of the gate signal.

[0060] Here, the gate finger wiring 61 cannot be directly connected to the first active trench gate 111 below the emitter electrode connecting portion 71. In this embodiment, the second active trench gate 112, which is drawn out to below the gate finger wiring 61, is connected to the first active trench gate 111 below the emitter electrode connecting portion 71, and the gate finger wiring 61 is connected to the second active trench gate 112. As a result, the gate finger wiring 61 is also electrically connected to the first active trench gate 111 below the emitter electrode connecting portion 71. For this reason, the emitter electrode connecting portion 71 is arranged to overlap at least a portion of the second active trench gate 112.

[0061] The gate finger wiring 61 is, for example, an aluminum wiring. The material of the gate finger wiring 61 may be the same as that of the emitter electrode 6. In this case, the gate finger wiring 61 can be formed simultaneously with the emitter electrode 6. However, since the gate finger wiring 61 and the emitter electrode 6 are set to different potentials, the gate finger wiring 61 and the emitter electrode 6 are separated from each other.

[0062] 11 , the gate finger wiring 61 is formed in the same layer as the emitter electrode 6. Therefore, the emitter electrode 6 is separated by the gate finger wiring 61. However, adjacent emitter electrodes 6 sandwiching the gate finger wiring 61 are not completely separated. Adjacent emitter electrodes 6 sandwiching the gate finger wiring 61 are connected by an emitter electrode connecting portion 71 disposed in an emitter electrode connecting region 70. The material of the emitter electrode connecting portion 71 may be the same as the material of the emitter electrode 6, or the emitter electrode 6 and the emitter electrode connecting portion 71 may be formed uniformly.

[0063] In this way, adjacent emitter electrodes 6 sandwiching the gate finger wiring 61 are electrically connected through the emitter electrode connecting portion 71, thereby improving the current imbalance and improving the short-circuit resistance of the semiconductor device 100.

[0064] <Embodiment 2> Fig. 12 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the second embodiment. Fig. 13 also shows the shape of the emitter electrode connecting portion 71. The configuration shown in Fig. 12 is the same as that in Fig. 10.

[0065] 12 and 13, the length of the emitter electrode connecting portion 71 in a first direction (a direction perpendicular to the extension direction of the gate finger wiring 61) is denoted by x, the length of the emitter electrode connecting portion 71 in a second direction (the extension direction of the gate finger wiring 61) is denoted by y, and the thickness of the emitter electrode connecting portion 71 is denoted by z. Hereinafter, x will be referred to as the "length" of the emitter electrode connecting portion 71, and y will be referred to as the "width" of the emitter electrode connecting portion 71.

[0066] Assuming that the emitter electrode connector 71 is a straight conductor made of metal and having a rectangular cross section, as shown in FIG. 13, the inductance L [μH] of the emitter electrode connector 71 is given by L=0.002x[ln(2x / (y+z))+0.2235((y+z) / x)+0.5] The resistance R [mΩ] of the emitter electrode connecting portion 71 can be expressed as follows: R=ρx / yz (ρ: resistivity) It can be expressed as:

[0067] In the semiconductor device 100 according to the second embodiment, when the pitch of the first active trench gates 111 is 2.4 μm, 0.002x[ln(2x / (y+z))+0.2235((y+z) / x)+0.5]<5.0[μH], and ρx / yz<7.5[mΩ] The length x, width y, and thickness z of the emitter electrode connecting portion 71 are set so that the following relationship is satisfied.

[0068] In this way, by reducing the resistance and inductance of the emitter electrode coupling portion 71, the effect of correcting the current imbalance in the emitter electrode 6 is improved.

[0069] Furthermore, if the pitch of the first active trench gates 111 is 4.0 μm, 0.002x[ln(2x / (y+z))+0.2235((y+z) / x)+0.5]<2.5[μH], and ρx / yz<3.0[mΩ] The length x, width y, and thickness z of the emitter electrode connecting portion 71 may be set so that the following relationship is satisfied.

[0070] <Third Embodiment> FIG. 14 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the third embodiment.

[0071] The semiconductor device 100 in the third embodiment includes third active trench gates 113 extending in the second direction and electrically connecting adjacent first active trench gates 111 below the emitter electrode connectors 71. In the example of Fig. 14, a plurality of third active trench gates 113 are provided, and the active trench gates 11 passing below the emitter electrode connectors 71 form a ladder shape in plan view.

[0072] By connecting the first active trench gates 111 below the emitter electrode connecting portions 71 by the third active trench gates 113, gate signals can be more easily transmitted from the gate finger wiring 61 to the first active trench gates 111 below the emitter electrode connecting portions 71, thereby improving the effect of suppressing gate delay.

[0073] <Fourth Embodiment> FIG. 15 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the fourth embodiment.

[0074] The semiconductor device 100 according to the fourth embodiment has a structure (a gate thinning structure) in which the active trench gates 11 are thinned out by arranging dummy trench gates 12 between the first active trench gates 111. The dummy trench gates 12 extend parallel to the first active trench gates 111 (i.e., in the first direction).

[0075] 15, the dummy trench gate 12 may be disposed below the emitter electrode connector 71. However, if the dummy trench gate 12 intersects with the second active trench gate 112, insulation between the dummy trench gate 12 and the second active trench gate 112 cannot be ensured, and therefore the dummy trench gate 12 has a pattern that is interrupted where the second active trench gate 112 is disposed.

[0076] In this embodiment, the same effects as those in the first embodiment can be obtained.

[0077] <Fifth Embodiment> Fig. 16 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the fifth embodiment, and Fig. 17 is a cross-sectional view taken along the line A1-A2 shown in Fig. 16.

[0078] In the semiconductor device 100 according to the fifth embodiment, the second active trench gate 112 connected to the first active trench gate 111 below the emitter electrode connecting portion 71 is extended to below the gate wiring 51. The gate wiring 51 is connected to the second active trench gate 112 through a contact hole formed in the interlayer insulating film 4.

[0079] Therefore, in this embodiment, the first active trench gate 111 below the emitter electrode connector 71 is connected to the gate wiring 51 through the second active trench gate 112. Therefore, a gate signal is transmitted from the gate wiring 51 to the first active trench gate 111 below the emitter electrode connector 71 without passing through the gate finger wiring 61.

[0080] In this embodiment, the same effects as those in the first embodiment can be obtained.

[0081] <Sixth Embodiment> Fig. 18 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the sixth embodiment, and Fig. 19 is a cross-sectional view taken along the line A1-A2 shown in Fig. 18.

[0082] The sixth embodiment is a combination of the first and fifth embodiments. That is, in the semiconductor device 100 of the sixth embodiment, some of the first active trench gates 111 below the emitter electrode coupling portion 71 are connected to second active trench gates 112 drawn out to below the gate finger wiring 61, as in the first embodiment, and other parts of the first active trench gates 111 are connected to second active trench gates 112 drawn out to below the gate wiring 51, as in the sixth embodiment.

[0083] Therefore, in this embodiment, a gate signal is transmitted from the gate wiring 51 to some of the first active trench gates 111 below the emitter electrode connecting portion 71 through the gate finger wiring 61, and a gate signal is transmitted from the gate wiring 51 to other parts of the first active trench gates 111 without passing through the gate finger wiring 61.

[0084] With this structure, gate signals are transmitted from both the gate wiring 51 and the gate finger wiring 61 to the first active trench gate 111 below the emitter electrode connector 71, thereby improving the effect of suppressing gate delay.

[0085] <Seventh Embodiment> Fig. 20 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the seventh embodiment, and Fig. 21 is a cross-sectional view taken along the line A1-A2 shown in Fig. 20.

[0086] In the semiconductor device 100 according to the seventh embodiment, a p-type layer 91 deeper than the first active trench gate 111 and the second active trench gate 112 is formed in a region including the emitter electrode connecting region 70 in which the emitter electrode connecting portion 71 is arranged. When the p-type layer 91 is applied to the third embodiment, the p-type layer 91 is formed deeper than the first active trench gate 111, the second active trench gate 112, and the third active trench gate 113.

[0087] This structure makes it possible to prevent the electric field from concentrating near the end of the first active trench gate 111, the second active trench gate 112, or the third active trench gate 113 located below the emitter electrode connecting portion 71.

[0088] <Embodiment 8> Fig. 22 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the eighth embodiment. Also, Fig. 23 is a cross-sectional view taken along the line A1-A2 shown in Fig. 22.

[0089] In the semiconductor device 100 according to the eighth embodiment, the emitter electrode connecting portion 71 is connected to the p + The metal layer 14 is connected to the metal contact layer 14 .

[0090] This structure provides a hole extraction effect in the emitter electrode connecting region 70, thereby improving the SOA (Safety Operation Area) tolerance of the semiconductor device 100.

[0091] <Ninth Embodiment> FIG. 24 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the ninth embodiment.

[0092] In the semiconductor device 100 according to the ninth embodiment, the width of the active trench gate 11 (the first active trench gate 111, the second active trench gate 112, or the third active trench gate 113) disposed below the emitter electrode connector 71 is wider than the width in other regions. In other words, the width of the active trench gate 11 is locally wider in the portion disposed below the emitter electrode connector 71.

[0093] This structure reduces the gate resistance of the semiconductor device 100, thereby improving the effect of suppressing gate delay.

[0094] <Tenth Embodiment> FIG. 25 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the tenth embodiment.

[0095] In the semiconductor device 100 of embodiment 10, the corners of the active trench gate 11 (the first active trench gate 111, the second active trench gate 112, or the third active trench gate 113) arranged below the emitter electrode connecting portion 71 are rounded (R-shaped).

[0096] This structure prevents the electric field from concentrating at the corners of the trench of the active trench gate 11, thereby improving the breakdown voltage and SOA resistance of the semiconductor device 100.

[0097] <Embodiment 11> FIG. 26 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the eleventh embodiment.

[0098] The semiconductor device 100 according to the eleventh embodiment includes a plurality of gate finger wiring regions 60 in which gate finger wirings 61 are arranged. In the gap between the tip of each of the plurality of gate finger wirings 61 and the gate wiring region 50, an emitter electrode connecting region 70 in which an emitter electrode connecting portion 71 is arranged is provided.

[0099] The emitter electrode 6 is divided into three or more sections by the multiple gate finger wirings 61, but these sections are electrically connected via the emitter electrode connecting portion 71.

[0100] Since gate signals are transmitted to the active trench gate 11 from a plurality of gate finger wirings 61, the effect of suppressing gate delay is improved.

[0101] <Embodiment 12> FIG. 27 is a plan view of the vicinity of the emitter electrode connecting region 70 of the semiconductor device 100 according to the twelfth embodiment.

[0102] Similar to the 11th embodiment, the semiconductor device 100 according to the 12th embodiment includes a plurality of gate finger wiring regions 60 in which gate finger wirings 61 are arranged. However, unlike the 11th embodiment, the plurality of gate finger wirings 61 are arranged side by side so that the directions in which they extend from the gate wiring 51 alternate. In other words, the plurality of gate finger wirings 61 are arranged side by side so that the connection points with the gate wiring 51 are in a zigzag (staggered) pattern.

[0103] 27, for example, the gate finger wiring 61 in the left gate finger wiring region 60 extends upward from the side of the gate wiring 51 that is closer to the pad region 40, and the gate finger wiring 61 in the right gate finger wiring region 60 extends downward from the side of the gate wiring 51 that is farther from the pad region 40. As a result, the multiple emitter electrode connecting regions 70 are arranged in a zigzag (staggered) pattern.

[0104] Compared to the twelfth embodiment, the current balance in the semiconductor device 100 is uniform, and therefore the SOA tolerance is improved.

[0105] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0106] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0107] (Appendix 1) a plurality of active trench gates formed in a cell region of a semiconductor substrate; an emitter electrode disposed on the cell region; a gate wiring disposed outside the emitter electrode and electrically connected to the plurality of active trench gates; a gate finger wiring electrically connected to the gate wiring and extending over the cell region; Equipped with one end of the gate finger wiring is connected to the gate wiring, and the other end of the gate finger wiring does not reach the gate wiring; the emitter electrodes adjacent to each other across the gate finger wiring are electrically connected to each other through an emitter electrode connection portion disposed in a region between the other end of the gate finger wiring and the gate wiring, The active trench gate is a first active trench gate extending in a first direction intersecting the extension direction of the gate finger wiring; a second active trench gate connected to the first active trench gate located below the emitter electrode connection portion, extending in a second direction parallel to the extending direction of the gate finger wiring, and drawn out to below the gate finger wiring or the gate wiring; Including, Semiconductor device.

[0108] (Appendix 2) The pitch of the first active trench gate is 2.4 μm; When the length of the emitter electrode connecting portion in the first direction is x, the length of the emitter electrode connecting portion in the second direction is y, the thickness of the emitter electrode connecting portion is z, and the resistivity of the emitter electrode connecting portion is ρ, 0.002x[ln(2x / (y+z))+0.2235((y+z) / x)+0.5]<5.0[μH], and ρx / yz<7.5[mΩ] The relationship is satisfied, 2. The semiconductor device according to claim 1.

[0109] (Appendix 3) The pitch of the first active trench gate is 4.0 μm; When the length of the emitter electrode connecting portion in the first direction is x, the length of the emitter electrode connecting portion in the second direction is y, the thickness of the emitter electrode connecting portion is z, and the resistivity of the emitter electrode connecting portion is ρ, 0.002x[ln(2x / (y+z))+0.2235((y+z) / x)+0.5]<2.5[μH], and ρx / yz<3.0[mΩ] The relationship is satisfied, 2. The semiconductor device according to claim 1.

[0110] (Appendix 4) a third active trench gate extending in the second direction and electrically connecting adjacent first active trench gates below the emitter electrode connector; 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0111] (Appendix 5) a dummy trench gate disposed between the first active trench gates; the dummy trench gate has a pattern that extends in the first direction and is interrupted at a location where the second active trench gate is disposed; 5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0112] (Appendix 6) the second active trench gate is extended to below the gate finger wiring, and the second active trench gate is extended to below the gate wiring; 6. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0113] (Appendix 7) a p-type layer deeper than the active trench gate is formed in the semiconductor substrate below the emitter electrode connecting portion; 7. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0114] (Appendix 8) the emitter electrode connector is connected to a p-type contact layer formed on the semiconductor substrate. 8. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0115] (Appendix 9) the width of the active trench gate is locally widened below the emitter electrode connection portion; 9. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0116] (Appendix 10) a corner of the active trench gate disposed under the emitter electrode connector has a rounded shape; 10. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0117] (Appendix 11) a plurality of the gate finger wirings; 11. The semiconductor device according to claim 1.

[0118] (Appendix 12) the plurality of gate finger wirings are arranged so that connection points with the gate wirings are staggered; 12. The semiconductor device according to claim 11. [Explanation of symbols]

[0119] 1n -1. N-type drift layer, 2. n-type carrier accumulation layer, 3. n-type buffer layer, 4. interlayer insulating film, 5. barrier metal, 6. emitter electrode, 7. collector electrode, 8. trench, 9. oxide film, 10. IGBT region, 11. active trench gate, 11a. gate trench electrode, 11b. gate trench insulating film, 12. dummy trench gate, 12a. dummy trench electrode, 12b. dummy trench insulating film, 13. n + Type emitter layer, 14p + 16a p-type collector termination layer; 20 diode region; 21 diode trench gate; 21a diode trench electrode; 21b diode trench insulating film; 24 p + p-type contact layer, 25 p-type anode layer, 26 n + a gate electrode connecting portion, ...

Claims

1. a plurality of active trench gates formed in a cell region of a semiconductor substrate; an emitter electrode disposed on the cell region; a gate wiring disposed outside the emitter electrode and electrically connected to the plurality of active trench gates; a gate finger wiring electrically connected to the gate wiring and extending over the cell region; Equipped with one end of the gate finger wiring is connected to the gate wiring, and the other end of the gate finger wiring does not reach the gate wiring; the emitter electrodes adjacent to each other across the gate finger wiring are electrically connected to each other through an emitter electrode connection portion disposed in a region between the other end of the gate finger wiring and the gate wiring, The active trench gate is a first active trench gate extending in a first direction intersecting the extension direction of the gate finger wiring; a second active trench gate connected to the first active trench gate located below the emitter electrode connector, extending in a second direction parallel to the extending direction of the gate finger wiring, and drawn out to below the gate finger wiring or the gate wiring; Including, Semiconductor device.

2. The pitch of the first active trench gate is 2.4 μm; Let x be the length of the emitter electrode connecting portion in the first direction, y be the length of the emitter electrode connecting portion in the second direction, z be the thickness of the emitter electrode connecting portion, and ρ be the resistivity of the emitter electrode connecting portion. 0.002x [ln(2x / (y+z)) + 0.2235((y+z) / x) + 0.5] < 5.0 [μH], and ρx / yz<7.5 [mΩ] The relationship is satisfied, The semiconductor device according to claim 1 .

3. The pitch of the first active trench gate is 4.0 μm; Let x be the length of the emitter electrode connecting portion in the first direction, y be the length of the emitter electrode connecting portion in the second direction, z be the thickness of the emitter electrode connecting portion, and ρ be the resistivity of the emitter electrode connecting portion. 0.002x [ln(2x / (y+z)) + 0.2235((y+z) / x) + 0.5] < 2.5 [μH], and ρx / yz<3.0[mΩ] The relationship is satisfied, The semiconductor device according to claim 1 .

4. a third active trench gate extending in the second direction and electrically connecting adjacent first active trench gates below the emitter electrode connector; The semiconductor device according to claim 1 .

5. a dummy trench gate disposed between the first active trench gates; the dummy trench gate has a pattern that extends in the first direction and is interrupted at a location where the second active trench gate is disposed; The semiconductor device according to claim 1 .

6. the second active trench gate is extended to below the gate finger wiring, and the second active trench gate is extended to below the gate wiring; The semiconductor device according to claim 1 .

7. a p-type layer deeper than the active trench gate is formed in the semiconductor substrate below the emitter electrode connecting portion; The semiconductor device according to claim 1 .

8. the emitter electrode connector is connected to a p-type contact layer formed on the semiconductor substrate. The semiconductor device according to claim 1 .

9. the width of the active trench gate is locally widened below the emitter electrode connection portion; The semiconductor device according to claim 1 .

10. a corner of the active trench gate disposed under the emitter electrode connector has a rounded shape; The semiconductor device according to claim 1 .

11. a plurality of the gate finger wirings; The semiconductor device according to claim 1 .

12. the plurality of gate finger wirings are arranged so that connection points with the gate wirings are staggered; The semiconductor device according to claim 11.

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