Imaging apparatus

Abstract

To provide an imaging apparatus and an imaging module, capable of performing wide-dynamic-range photography.SOLUTION: The imaging module includes the imaging apparatus and a signal processing circuit. The imaging apparatus includes a semiconductor substrate, a first photoelectric conversion part in the semiconductor substrate, a capacitive element electrically connected to the first photoelectric conversion part, and a second photoelectric conversion part in the semiconductor substrate. In a plan view, the capacitive element at least partially overlaps with the second photoelectric conversion part and the signal processing circuit processes a signal from the imaging apparatus.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device and an imaging module, typified by a CMOS image sensor. [Background technology]

[0002] In nature, there are subjects with large differences in brightness. For example, an in-vehicle imaging device is required to simultaneously capture bright and dark subjects (high dynamic range) in order to handle subjects whose brightness changes from moment to moment. To achieve a high dynamic range, Patent Documents 1 and 2 propose the following methods.

[0003] The imaging devices disclosed in Patent Documents 1 and 2 use silicon photodiodes. In Patent Document 1, a wide dynamic range can be obtained by combining images with different exposure times (hereinafter sometimes referred to as "accumulation times"). This technique has already been put to practical use. In Patent Document 2, the dynamic range is expanded by combining images obtained from multiple imaging cells with different sensitivities arranged within one pixel. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 62-108678 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-99073 Summary of the Invention [Problem to be solved by the invention]

[0005] In the conventional imaging devices described above, there has been a demand for further improvement in high dynamic range imaging. [Means for solving the problem]

[0006] In order to solve the above problem, an imaging device according to one embodiment of the present disclosure includes a semiconductor substrate, a first imaging cell including a first photoelectric conversion unit in the semiconductor substrate and a first capacitive element having one end electrically connected to the first photoelectric conversion unit, and a second imaging cell including a second photoelectric conversion unit in the semiconductor substrate, wherein, in a planar view, the area of ​​the second photoelectric conversion unit is larger than the area of ​​the first photoelectric conversion unit.

[0007] The general or specific aspects may be realized as an element, a device, a system, an integrated circuit, or a method, or as any combination of an element, a device, a system, an integrated circuit, and a method.

[0008] Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and / or advantages are provided individually by the various embodiments and features disclosed in the specification and drawings, and not all are required to obtain one or more of them. [Effects of the Invention]

[0009] According to one aspect of the present disclosure, it is possible to provide an imaging device and an imaging module capable of capturing images in a wide dynamic range. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram schematically showing conventional imaging cell characteristics and desirable imaging cell characteristics. [Figure 2] FIG. 2 is a diagram schematically showing conventional imaging cell characteristics and more desirable imaging cell characteristics. [Figure 3] FIG. 3 is a block diagram schematically illustrating an example of the structure of the imaging device 100 according to the first exemplary embodiment. [Figure 4] FIG. 4 is a circuit diagram of a unit pixel 30 according to the first exemplary embodiment. [Figure 5] FIG. 5 is a cross-sectional view schematically illustrating the device structure of a unit pixel 30 in the imaging device 100 according to the first exemplary embodiment. [Figure 6] FIG. 6 is a cross-sectional view schematically showing another device structure of the unit pixel 30 in the imaging device 100 according to the first exemplary embodiment. [Figure 7] FIG. 7 is a cross-sectional view schematically showing another device structure of the unit pixel 30 in the imaging device 100 according to the first exemplary embodiment. [Figure 8] FIG. 8 is a cross-sectional view schematically showing another device structure of the unit pixel 30 in the imaging device 100 according to the first exemplary embodiment. [Figure 9] FIG. 9 is a cross-sectional view schematically showing yet another device structure of the unit pixel 30 in the imaging device 100 according to the first exemplary embodiment. [Figure 10] FIG. 10 is a bird's-eye view of the layout of the unit pixel 30 in the image pickup device 100 according to the first exemplary embodiment. [Figure 11] FIG. 11 is a circuit diagram schematically showing a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 12] FIG. 12 is a circuit diagram schematically showing a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 13] FIG. 13 is a circuit diagram schematically showing a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 14] FIG. 14 is a circuit diagram schematically showing a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 15] FIG. 15 is a circuit diagram schematically illustrating a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 16] FIG. 16 is a circuit diagram schematically showing a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 17] FIG. 17 is a circuit diagram schematically showing a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 18] FIG. 18 is a circuit diagram schematically illustrating a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 19] FIG. 19 is a circuit diagram schematically illustrating a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 20] FIG. 20 is a circuit diagram schematically illustrating a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 21] FIG. 21 is a circuit diagram schematically illustrating a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 22] FIG. 22 is a circuit diagram schematically illustrating a variation of the unit pixel 30 according to the first exemplary embodiment. [Figure 23] FIG. 23 is a timing chart showing the timing of exposure and readout operations during one cycle (one frame) in the imaging device 100 according to the illustrative first embodiment. [Figure 24] FIG. 24 is a schematic diagram showing functional blocks of an imaging module 200 incorporating the imaging device 100. As shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] First, the problems of the prior art that the inventors of the present invention have considered will be explained.

[0012] In the image synthesis disclosed in Patent Document 1, multiple image data are acquired in chronological order. Therefore, obtaining one synthesized image requires several times the normal imaging time. Furthermore, since images with a time lag are synthesized, the simultaneity of the images is lost, resulting in distortion in images of moving subjects.

[0013] Patent Document 2 uses multiple photodiodes of the same size with the same sensitivity and saturation electron count. It is equipped with an on-chip top lens that divides the amount of light incident on each photodiode into two types: large and small. This configuration effectively makes it appear that the sensitivity differs between multiple imaging cells. Since two cells are mounted on one pixel, simultaneous imaging is possible, ensuring image simultaneity.

[0014] On the other hand, since two cells must be placed within one pixel, the area of ​​the photodiode must be reduced to half or less compared to conventional devices. The area of ​​the photodiode and the sensitivity or number of saturation electrons are roughly proportional. As a result, if the area of ​​the photodiode is reduced to half or less, the sensitivity and number of saturation electrons will also be reduced to half or less compared to conventional devices.

[0015] FIG. 1 shows a schematic diagram of conventional imaging cell characteristics and desirable imaging cell characteristics. While a normal cell (hereinafter referred to as a "normal cell") has one imaging cell within a single pixel, high dynamic range imaging (HDR) uses two imaging cells within a single pixel. These two imaging cells preferably have (a) imaging cell characteristics with sensitivity and saturation electron count similar to those of a normal cell, and (b) imaging cell characteristics with saturation electron count similar to those of a normal cell but lower sensitivity than that of a normal cell. "a" and "b" in the diagram indicate the desirable combinations.

[0016] "a'" and "b'" in FIG. 1 indicate the combination of two imaging cells in Patent Document 2. As mentioned above, the area of ​​each imaging cell (photodiode) is half or less that of a normal cell. This reduces the sensitivity of each imaging cell, and also reduces the number of saturated electrons. This means that the characteristics deviate from the desired characteristics. Thus, the characteristics of the imaging cell in Patent Document 2 are significantly inferior to the required characteristics.

[0017] Figure 2 shows a schematic diagram of conventional and more desirable imaging cell characteristics. As shown in "b" in Figure 2, reducing the sensitivity alleviates saturation, which can occur when the amount of incident light is high. In addition, if the number of saturation electrons can be increased, the dynamic range can be further expanded.

[0018] An overview of one aspect of the present disclosure is as follows:

[0019] [Item 1] a semiconductor substrate; a first imaging cell including a first photoelectric conversion unit in the semiconductor substrate and a first capacitance element having one end electrically connected to the first photoelectric conversion unit; a second imaging cell including a second photoelectric conversion unit in the semiconductor substrate; Equipped with An imaging device, wherein, in a plan view, the area of ​​the second photoelectric conversion unit is larger than the area of ​​the first photoelectric conversion unit.

[0020] [Item 2] the first imaging cell further includes a first charge detection circuit electrically connected to the first photoelectric conversion unit; 2. The imaging device according to item 1, wherein the second imaging cell further includes a second charge detection circuit electrically connected to the second photoelectric conversion unit.

[0021] [Item 3] the first charge detection circuit includes a first reset transistor, one of a source and a drain of which is electrically connected to the first photoelectric conversion unit; 3. The imaging device according to item 2, wherein the first charge detection circuit includes a second reset transistor having one of a source and a drain electrically connected to the second photoelectric conversion unit.

[0022] [Item 4] the first imaging cell has a first transfer transistor, one of a source and a drain of which is electrically connected to the first photoelectric conversion unit; The first charge detection circuit includes: a first floating diffusion electrically connected to the other of the source and the drain of the first transfer transistor; a first reset transistor, one of a source and a drain of which is electrically connected to the first floating diffusion; 3. The imaging device according to item 2, comprising:

[0023] [Item 5] the second imaging cell has a second transfer transistor, one of a source and a drain of which is electrically connected to the second photoelectric conversion unit; The second charge detection circuit includes: a second floating diffusion electrically connected to the other of the source and the drain of the second transfer transistor; a second reset transistor, one of a source and a drain of which is electrically connected to the second floating diffusion; 5. The imaging device according to item 4, comprising:

[0024] [Item 6] The second imaging cell includes: a transfer transistor, one of a source and a drain of which is electrically connected to the second photoelectric conversion unit; a floating diffusion electrically connected to the other of the source and the drain of the transfer transistor; Item 2. The imaging device according to item 1, comprising:

[0025] [Item 7] the first imaging cell further includes a first transfer transistor, one of a source and a drain of which is electrically connected to the first photoelectric conversion unit; the second imaging cell further includes a second transfer transistor, one of a source and a drain of which is electrically connected to the second photoelectric conversion unit; The first imaging cell and the second imaging cell are 2. The imaging device of claim 1, further comprising a floating diffusion electrically connected to both the other of the source and the drain of the first transfer transistor and the other of the source and the drain of the second transfer transistor.

[0026] [Item 8] The first imaging cell and the second imaging cell further include a reset transistor, one of a source and a drain of which is electrically connected to the floating diffusion. An imaging device as described in item 7.

[0027] [Item 9] 9. The imaging device according to any one of items 1 to 8, wherein the second imaging cell does not have a capacitance element.

[0028] [Item 10] 10. The imaging device according to any one of items 1 to 9, wherein the shape of the second photoelectric conversion section is different from the shape of the first photoelectric conversion section in a plan view.

[0029] [Item 11] the first imaging cell further includes a first microlens located on a light incident side of the first photoelectric conversion unit, the second imaging cell further includes a second microlens located on a light incident side of the second photoelectric conversion unit, 11. The imaging device according to any one of items 1 to 10, wherein the light-collecting area of ​​the second microlens is larger than the light-collecting area of ​​the first microlens.

[0030] [Item 12] the first imaging cell and the second imaging cell are disposed adjacent to each other; the first imaging cell and the second imaging cell further include a common microlens located on the light incident side of the first photoelectric conversion unit and the second photoelectric conversion unit, 12. The imaging device according to any one of items 1 to 11, wherein the second photoelectric conversion unit is located on the optical axis of the microlens.

[0031] [Item 13] the first capacitance element includes a lower electrode, an upper electrode, and an insulator sandwiched between the lower electrode and the upper electrode; 13. The imaging device according to any one of items 1 to 12, wherein one of the lower electrode and the upper electrode is electrically connected to the first photoelectric conversion unit.

[0032] [Item 14] the first imaging cell and the second imaging cell are disposed adjacent to each other; 14. The imaging device according to claim 1, wherein the first capacitive element is located between the first photoelectric conversion unit and the second photoelectric conversion unit in a plan view.

[0033] [Item 15] the first imaging cell and the second imaging cell are disposed adjacent to each other; 15. The imaging device according to any one of items 1 to 14, wherein the first capacitive element at least partially overlaps one or both of the first photoelectric conversion unit and the second photoelectric conversion unit in a plan view.

[0034] [Item 16] the first imaging cell accumulates a first charge generated by the first photoelectric conversion unit for a first accumulation time; the second imaging cell accumulates the second charge generated by the second photoelectric conversion unit for a second accumulation time; 16. The imaging device according to any one of items 1 to 15, wherein the second accumulation time is longer than the first accumulation time.

[0035] [Item 17] 17. The imaging device according to any one of items 2 to 16, wherein the first charge detection circuit reads out the first charge generated by the first photoelectric conversion unit at least twice in one frame period without resetting the first charge.

[0036] [Item 18] a first photoelectric conversion unit that converts incident light into a first charge; a first storage capacitor electrically connected to the first photoelectric conversion unit and configured to store the first charge; a first charge detection circuit connected to the first storage capacitor and configured to read out the first charge stored in the first storage capacitor; a first imaging cell including: a second photoelectric conversion unit that converts incident light into a second charge; a second storage capacitor connected to the second photoelectric conversion unit and configured to store the second charge; a second charge detection circuit connected to the second storage capacitor and configured to read out the second charge stored in the second storage capacitor; a second imaging cell including: Equipped with the second photoelectric conversion unit is configured to receive more light than the first photoelectric conversion unit; An imaging device, wherein the capacitance value of the first storage capacitor is greater than the capacitance value of the second storage capacitor.

[0037] [Item 19] Item 19. The imaging device according to item 18, wherein the first storage capacitor includes a capacitive element, and the second storage capacitor does not include a capacitive element.

[0038] [Item 20] the first imaging cell and the second imaging cell are disposed adjacent to each other; the first and second imaging cells further include a common microlens located on the light incident side of the first and second photoelectric conversion units, 20. The imaging device according to item 18 or 19, wherein the second photoelectric conversion unit is located on the optical axis of the microlens.

[0039] [Item 21] the first imaging cell and the second imaging cell are disposed adjacent to each other; the first and second imaging cells further include a common microlens located on the light incident side of the first photoelectric conversion unit and the second photoelectric conversion unit, 12. The imaging device according to any one of items 1 to 11, wherein the second photoelectric conversion unit is disposed in a region where light is collected by the microlens.

[0040] [Item 22] a plurality of the first imaging cells and a plurality of the second imaging cells; 22. The imaging device according to any one of items 1 to 21, wherein the plurality of first and second imaging cells are arranged one-dimensionally or two-dimensionally in plan view.

[0041] [Item 23] 3. The imaging device according to item 2, wherein, in a plan view, the area of ​​the second charge detection circuit is larger than the area of ​​the first charge detection circuit.

[0042] [Item 24] the first imaging cell further comprises a first feedback loop; the first feedback loop includes a first inverting amplifier circuit, the first reset transistor, and the first charge detection circuit; the second imaging cell further comprises a second feedback loop; 4. The imaging device of item 3, wherein the second feedback loop includes a second inverting amplifier circuit, the second reset transistor, and the second charge detection circuit.

[0043] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the present disclosure is not limited to the following embodiments. Furthermore, appropriate modifications are possible within the scope of the effects of the present invention. Furthermore, one embodiment can be combined with another embodiment. In the following description, identical or similar components are designated by the same reference numerals. Furthermore, duplicated descriptions may be omitted.

[0044] (First embodiment) FIG. 3 schematically illustrates an example of the structure of an imaging device 100. The imaging device 100 includes a plurality of unit pixels 30 arranged two-dimensionally. In reality, several million unit pixels 30 may be arranged two-dimensionally, but FIG. 3 illustrates unit pixels 30 arranged in a matrix of two rows and two columns. The imaging device 100 may be a line sensor. In this case, the plurality of unit pixels 30 are arranged one-dimensionally (in the row direction or the column direction).

[0045] The unit pixel 30 includes a first imaging cell 31 and a second imaging cell 31'. The first imaging cell 31 is an imaging cell that supports high saturation. The second imaging cell 31' is an imaging cell that supports low noise. Typically, the first imaging cell 31 functions as an imaging cell for low sensitivity, and the second imaging cell 31' functions as an imaging cell for high sensitivity. The imaging device 100 includes, for the first imaging cell 31, a reset signal line 47 and an address signal line 48 arranged for each row, and a vertical signal line 45 and a power supply line 46 arranged for each column. The imaging device 100 also includes, for the second imaging cell 31', a reset signal line 47' and an address signal line 48' arranged for each row, and a vertical signal line 45' and a power supply line 46' arranged for each column.

[0046] The imaging device 100 includes a first peripheral circuit that processes signals from the first imaging cell 31 and a second peripheral circuit that processes signals from the second imaging cell 31'. The first peripheral circuit includes a first vertical scanning circuit 52, a first horizontal scanning circuit 53, and a first column AD conversion circuit 54. The second peripheral circuit includes a second vertical scanning circuit 52', a second horizontal scanning circuit 53', and a second column AD conversion circuit 54'. However, the address signal lines for the first imaging cell 31 and the second imaging cell 31' may be common, depending on the pixel configuration.

[0047] Focusing on the first imaging cell 31, the first vertical scanning circuit 52 controls a plurality of reset signal lines 47 and a plurality of address signal lines 48. The vertical signal lines 45 are connected to the first horizontal scanning circuit 53 and transmit pixel signals to the first horizontal scanning circuit 53. The power supply wiring 46 supplies a power supply voltage to all the unit pixels 30.

[0048] (Circuit configuration of the first imaging cell 31 and the second imaging cell 31′) Next, an example of the circuit configuration of the first imaging cell 31 and the second imaging cell 31' will be described with reference to FIG.

[0049] 4 is a circuit diagram of the unit pixel 30, and schematically shows the circuit configuration of the first imaging cell 31 and the second imaging cell 31'. The first imaging cell 31 includes a first photoelectric conversion unit PDS and a first charge detection circuit 51. The second imaging cell 31' includes a second photoelectric conversion unit PDL and a second charge detection circuit 51'. The first photoelectric conversion unit PDS and the second photoelectric conversion unit PDL are light receiving elements, typically photodiodes (PD). The first photoelectric conversion unit PDS may have a different planar shape from the second photoelectric conversion unit PDL. In plan view, the area of ​​the second charge detection circuit 51' is larger than the area of ​​the first charge detection circuit 51.

[0050] In the first imaging cell 31 and the second imaging cell 31', the first photoelectric conversion unit PDS provided on the semiconductor substrate is arranged to be smaller than the second photoelectric conversion unit PDL provided on the semiconductor substrate. Therefore, the second photoelectric conversion unit PDL generates a larger amount of charge for the same amount of light than the first photoelectric conversion unit PDS, and therefore has high sensitivity.

[0051] In the first imaging cell 31, the first photoelectric conversion unit PDS is electrically connected to the capacitance element Csat, and the connection point between the first photoelectric conversion unit PDS and the capacitance element Csat is connected to the source electrode of the reset transistor RSS and the gate electrode of the amplifier transistor SFS, which serves as the input of the source follower circuit. The reset transistor RSS resets (initializes) the charge accumulated in the first photoelectric conversion unit PDS. In other words, the reset transistor RSS resets the potential of the gate electrode of the amplifier transistor SFS.

[0052] The first imaging cell 31 has a so-called three-transistor CMOS image sensor pixel configuration. Conventionally, in a three-transistor pixel configuration, thermal noise known as reset noise occurs due to the on-off operation of the reset transistor RSS. However, the first imaging cell 31 has high saturation characteristics that enable it to receive a larger amount of light thanks to the capacitance element Csat connected to the first photoelectric conversion unit PDS. When the amount of light is large, optical shot noise becomes dominant in the captured image. In other words, because optical shot noise is larger than circuit noise, the impact of reset noise on the first imaging cell 31 is small.

[0053] In this way, the first imaging cell 31 can function as a high-saturation cell. Because the first imaging cell 31 does not require a transfer transistor, which is required in conventional CMOS image sensors, space corresponding to the transfer transistor is freed up on the silicon substrate. As a result, this space can be used to ensure the area of ​​the second photoelectric conversion unit PDL of the second imaging cell 31'.

[0054] The second imaging cell 31' has a second photoelectric conversion unit PDL, a transfer transistor TX, and a floating diffusion FD. The second photoelectric conversion unit PDL is connected to the floating diffusion (hereinafter referred to as "FD") via the transfer transistor TX. The second imaging cell 31' has a so-called four-transistor pixel circuit configuration. Since the charge generated in the second photoelectric conversion unit PDL is completely transferred to the FD via the transfer transistor TX, noise generated by the reset transistor RSL can also be subtracted by correlated double sampling (CDS) operation.

[0055] In this way, the photodiode area is reduced to make the first cell 31 low sensitivity, while providing a saturated charge storage unit with a capacitance element Csat using the wiring layer makes the first cell 31 a highly saturated cell. Because the noise requirement is not so high, it is possible to reduce the number of elements, such as noise reduction transistors, fabricated using a silicon substrate and increase the area of ​​the second photoelectric conversion unit PDL of the second imaging cell 31'.

[0056] Since the second imaging cell 31' is a high-sensitivity cell, a sufficient photodiode area is ensured. Furthermore, by adopting a conventional transistor configuration, the second imaging cell 31' can have low noise characteristics.

[0057] A high-illuminance subject is imaged by the first imaging cell 31, and at the same time, a low-illuminance subject is imaged by the second imaging cell 31'. This makes it possible to achieve a wide dynamic range while simultaneously capturing images simultaneously.

[0058] Hereinafter, the circuit configuration of the unit pixel 30 will be described with reference to FIGS. 3 and 4, focusing on the first imaging cell 31.

[0059] The first charge detection circuit 51 includes an amplification transistor SFS, a reset transistor RSS, and an address transistor SELS.

[0060] The first photoelectric conversion unit PDS is electrically connected to the source electrode of the reset transistor RSS and the gate electrode of the amplification transistor SFS. The first photoelectric conversion unit PDS converts light (incident light) incident on the first imaging cell 31 into electric charges. The first photoelectric conversion unit PDS generates signal charges according to the amount of incident light. The generated signal charges are accumulated by the charge accumulation node 44.

[0061] The power supply wiring 46 is connected to the drain electrode of the amplification transistor 40. The power supply wiring 46 is wired in the column direction for the following reason: the first imaging cells 31 are selected row by row. Therefore, if the power supply wiring 46 were wired in the row direction, all of the pixel drive current for one row would flow through one power supply wiring 46, resulting in a large voltage drop. A common source follower power supply voltage is applied to the amplification transistors SFS in all of the first imaging cells 31 in the imaging device 100 by the power supply wiring 46.

[0062] The amplifier transistor SFS amplifies a signal voltage corresponding to the amount of signal charge stored in the charge storage node 44. The gate electrode of the address transistor SELS is connected to a first vertical scanning circuit 52 via an address signal line 48. The drain electrode of the address transistor SELS is connected to a first horizontal scanning circuit 53 via a vertical signal line VSIGS. The vertical signal lines VSIGS and VSIGL correspond to the vertical signal lines 45 and 45' shown in FIG. 3, respectively. The address transistor SELS selectively outputs the output voltage of the amplifier transistor SFS to the vertical signal line VSIGS.

[0063] The first vertical scanning circuit 52 applies a row selection signal, which controls the on / off of the address transistor SELS, to the gate electrode of the address transistor SELS. This causes the row to be read out to be scanned in the vertical direction (column direction), and the row to be read out is selected. A signal voltage is read out to the vertical signal line VSIGS from the first imaging cells 31 of the unit pixels 30 in the selected row. The first vertical scanning circuit 52 also applies a reset signal, which controls the on / off of the reset transistor RSS, to the gate electrode of the reset transistor RSS. This selects the row of the first imaging cells 31 of the unit pixels 30 that are the target of the reset operation.

[0064] The first column AD conversion circuit 54 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion), on the signals read out from the first imaging cells 31 to the vertical signal lines VSIGS for each row. The first horizontal scanning circuit 53 reads out the signals processed by the first column AD conversion circuit 54.

[0065] In the imaging device 100, random noise may occur when transferring or resetting signal charges. However, in this specification, the reset noise that occurs when resetting signal charges is described as random noise. If random noise remains at the time of resetting, the remaining random noise may be added to the signal charges that are next accumulated in the charge accumulation node 44. In that case, when the signal charges are read out, a signal on which random noise is superimposed is output. can be.

[0066] (Device structure of unit pixel 30) FIG. 5 is a schematic cross-sectional view of the device structure of a unit pixel 30 in the imaging device 100 according to this embodiment.

[0067] In the unit pixel 30, the first imaging cell 31 and the second imaging cell 31' are arranged adjacent to each other. The unit pixel 30 typically includes an N-type silicon substrate 300, the first imaging cell 31, the second imaging cell 31', a first photoelectric conversion unit PDS, a second photoelectric conversion unit PDL, a color filter 305, and microlenses 302A and 302B. However, if only monochrome imaging is performed, the color filter 305 may not be provided. Furthermore, if light collection by a microlens is not performed, the microlenses 302A and 302B may not be provided. The first and second photoelectric conversion units PDS and PDL are generally formed by implanting impurities into a silicon substrate, and their depths and extents are not limited to those shown in FIG. 5.

[0068] In this embodiment, the sensitivity of the first imaging cell 31 is lower than the sensitivity of the second imaging cell 31'. The microlens 302A is formed so as to cover the entire first photoelectric conversion unit PDS. The microlens 302B is formed so as to cover the entire second photoelectric conversion unit PDL. In a plan view, the area of ​​the first photoelectric conversion unit PDS is different from the area of ​​the second photoelectric conversion unit PDL. Specifically, the area of ​​the first photoelectric conversion unit PDS is smaller than the area of ​​the second photoelectric conversion unit PDL.

[0069] 6 and 7 schematically show cross sections of other device structures of the unit pixel 30 in the imaging device 100 according to this embodiment. As shown in FIG. 6, the first imaging cell 31 and the second imaging cell 31′ may have a common microlens 302. The microlens 302 focuses light incident on the unit pixel 30 onto each photoelectric conversion unit. As shown in FIG. 7, the microlens 302 may be disposed only in the second imaging cell 31′, which is a high-sensitivity cell. The second photoelectric conversion unit PDL may be located on the optical axis of the microlens 302.

[0070] The first photoelectric conversion unit PDS and the second photoelectric conversion unit PDL may be separated by an STI (Shallow Trench Isolation) separation layer 303 formed in the silicon substrate. This reduces electrical color mixing. However, depending on the purpose of miniaturization, it is also possible to select a configuration without the STI layer 303.

[0071] In this embodiment, the difference in sensitivity is achieved by the difference in size between the first photoelectric conversion unit PDS and the second photoelectric conversion unit PDL. A capacitance element Csat formed in the wiring layer 301 is electrically connected to the charge storage node 44 (see FIG. 4) of the first imaging cell 31 via a contact 304. By increasing the charge storage capacitance using the capacitance element Csat, the number of saturated electrons in the first imaging cell 31 can be increased. The first imaging cell 31 functions as an imaging cell capable of high saturation. It is possible to acquire more highly saturated charges with low sensitivity. In other words, it is possible to capture brighter subjects without saturating them. In this disclosure, "storage capacitance" refers to all capacitance components connected to the PD.

[0072] In a plan view, the capacitance element Csat is located between the first photoelectric conversion section 31 and the second photoelectric conversion section 31'. In a plan view, the capacitance element Csat at least partially overlaps with one or both of the first photoelectric conversion section 31 and the second photoelectric conversion section 31'. As the capacitance element Csat, a MIM (Metal Insulator Metal) capacitor having a parallel plate capacitor configuration between different wiring layers as shown in FIG. 5 can be used. In this case, the capacitance element Csat includes a lower electrode 311, an upper electrode 310, and an insulator 312 sandwiched between the lower electrode 311 and the upper electrode 310. Either the lower electrode 311 or the upper electrode 310 is electrically connected to the first photoelectric conversion unit PDS.

[0073] 8 is a schematic cross-sectional view of another device structure of the unit pixel 30 in the image pickup device 100 according to this embodiment. As the capacitance element Csat, a MOM (Metal Oxide Metal) capacitance forming a capacitance between wirings in the same layer as shown in FIG. 6 may be used. Furthermore, as the capacitance element Csat, a DMOS (Depletion Metal Oxide Semiconductor) using a silicon substrate 300 may be used. Metal Oxide Semiconductor type capacitors can also be selected.

[0074] The device structures shown in Figures 6 to 8 are generally called "back side illumination (BSI)" structures. The back side illumination structure has the advantage that it is possible to use the wiring area as a capacitance, and that a wide aperture ratio can be ensured even when a capacitance element Csat is placed.

[0075] 9 is a schematic cross-sectional view of yet another device structure of a unit pixel 30 in the image pickup device 100 according to this embodiment. The device structure shown in the figure is generally called a "front side illumination (FSI)" structure. In this structure, a photoelectric conversion layer is disposed on the front side of a silicon substrate 300, and incident light from the front side is detected. The image pickup device of the present disclosure also falls within the category of a front side illumination device structure.

[0076] FIG. 10 schematically illustrates an example of a bird's-eye view layout of unit pixels 30 in the imaging device 100 according to this embodiment. Three rows and three columns of unit pixels 30 are illustrated in FIG. 5 or 8. Each of the unit pixels 30 is illustrated in FIG. 5 or 8. The on-chip microlens 302A is configured to focus light on the first photoelectric conversion unit PDS. The on-chip microlens 302B is configured to focus light on the second photoelectric conversion unit PDL. The light-focusing area of ​​the on-chip microlens 302B is larger than that of the on-chip microlens 302A. Alternatively, as illustrated in FIG. 7, the first photoelectric conversion unit PDS may be provided with no microlens 302A, thereby providing the first imaging cell 31 with lower sensitivity. Furthermore, as shown in FIG. 6, a common microlens may be disposed in the first photoelectric conversion unit PDS and the second photoelectric conversion unit PDL, and the pitch of the microlens may be widened to improve the light-collecting characteristics.

[0077] As the materials for the unit pixel 30, materials generally used in the manufacture of silicon semiconductor devices can be widely used.

[0078] Hereinafter, various variations of the circuit configuration of the unit pixel 30 will be described with reference to FIGS.

[0079] 11 to 22 schematically show various variations of the circuit configuration of the unit pixel 30 according to this embodiment (specifically, the circuit configuration of each imaging cell). As shown in the figures, there are various variations of the circuit configuration of the unit pixel 30 according to this embodiment. In addition to the configurations shown in the figures, it is also possible to combine, for example, the variations.

[0080] (First variation) 11 shows a first variation of the circuit configuration of the unit pixel 30. The first imaging cell 31 differs from the configuration of the first imaging cell 31 shown in FIG. 4 in that it does not include a capacitance element Csat connected to the charge storage node 44 as a charge storage capacitance. Reference numeral 1 denotes a three-transistor cell composed of a reset transistor RSS, an amplifying transistor SFS, an address transistor SELS, and a first photoelectric conversion unit PDS. The configuration of the second imaging cell 31′ is the same as the configuration shown in FIG.

[0081] According to the first variation, the parasitic capacitance seen from the source electrode of the reset transistor RSS and the gate capacitance of the amplification transistor are associated with the first photoelectric conversion unit PDS, and therefore, these parasitic capacitances can be utilized instead of providing a separate capacitive element.

[0082] (2nd variation) FIG. 12 shows a second variation of the circuit configuration of the unit pixel 30. Unlike the configuration of the first imaging cell 31 shown in FIG. 4, the first imaging cell 31 further includes a feedback loop (column feedback circuit). The column feedback circuit includes an amplifier transistor SFS, an address transistor SELS, an inverting amplifier circuit FBAMP1, and a reset transistor RSS. The column feedback circuit feedback-resets the first imaging cell 31. The configuration of the second imaging cell 31′ is the same as the configuration shown in FIG. 4.

[0083] In the first imaging cell 31, during a reset operation, the reset transistor RSS is turned on to fix the charge storage node 44 to the voltage of the drain terminal of the reset transistor RSS. The charge storage node 44 is connected to the gate electrode of the amplification transistor SFS, and the signal voltage of the charge storage node 44 is output to the vertical signal line VSIGS via the turned-on address transistor SELS. The signal output to the vertical signal line VSIGS is input to a first inverting amplifier circuit FBAMP1 of a column feedback circuit provided in the column. The voltage multiplied by a negative gain in the first inverting amplifier circuit FBAMP1 is applied to the drain terminal of the reset transistor RSS via the column feedback signal line FBS.

[0084] According to the second variation, negative feedback can reduce reset noise, which is fluctuations in the reset voltage of the charge storage node 44. Furthermore, in a back-illuminated sensor such as that shown in FIG. 5, the transfer transistor TX does not need to be formed on the silicon substrate 300, which allows for an increased aperture ratio.

[0085] During negative feedback, a tapered reset method can be used, in which a tapered voltage that gradually increases or decreases over time is applied to the gate of the reset transistor RSS. It is also possible to use a driving method commonly used to reduce reset noise in three-transistor CMOS image sensors, such as a flash reset method that combines strong inversion reset and weak inversion reset.

[0086] (Third variation) FIG. 13 shows a third variation of the circuit configuration of the unit pixel 30. Unlike the configuration of the first imaging cell 31 shown in FIG. 4, the first imaging cell 31 includes a transfer transistor TXS. The configuration of the second imaging cell 31' is the same as the configuration shown in FIG. 4. In this configuration, both the first imaging cell 31 and the second imaging cell 31' include transfer transistors, resulting in a four-transistor configuration. Only the first imaging cell 31 includes a high-saturation capacitance element Csat.

[0087] According to the third variation, the charges generated in all pixel cells are temporarily transferred to the charge storage unit, that is, the floating diffusions FDS and FDL, thereby enabling a global shutter operation.

[0088] The first imaging cell 31 may further include a column feedback circuit, as in the second variation. That is, a feedback circuit shown in Fig. 12 may be provided for the reset transistors RSS and RSL to reduce reset noise.

[0089] (Fourth variation) 14 shows a fourth variation of the circuit configuration of the unit pixel 30. Unlike the circuit configuration shown in Fig. 4, both the first imaging cell 31 and the second imaging cell 31' have a three-transistor configuration and include a column feedback circuit including an inverting amplifier circuit FBAMPS or an inverting amplifier circuit FBAMPL.

[0090] According to the fourth variation, since neither the first imaging cell 31 nor the second imaging cell 31' has a transfer transistor, it is possible to increase the area of ​​the second photoelectric conversion unit PDL of the second imaging cell 31', which requires high sensitivity.

[0091] (5th and 6th variations) FIG. 15 shows a fifth variation of the circuit configuration of the unit pixel 30. The configuration of the first imaging cell 31 is different from the configuration shown in FIG. 12. The first imaging cell 31 further includes a capacitance element Cc, a capacitance element Cs, and a feedback control transistor FBS. It is desirable that the capacitance value of the capacitance element Cc is smaller than the capacitance value of the capacitance element Cs. The first imaging cell 31 does not include the capacitance element Csat shown in FIG. 12.

[0092] 16 shows a modification of the fifth variation of the circuit configuration of the unit pixel 30. In the modification of the fifth variation, a capacitance element Csat is connected to the first photoelectric conversion unit PDS.

[0093] According to the fifth variation and its modifications, noise can be attenuated according to the ratio between the capacitance value of the capacitive element Cs and the capacitance value of the capacitive element Cc. As a result, a greater effect of reducing reset noise can be expected compared to the configuration shown in FIG.

[0094] 17 shows a sixth variation of the circuit configuration of the unit pixel 30. In the sixth variation, the connection destination of the source or drain of the reset transistor RSS is different from that in the fifth variation. The sixth variation can be expected to achieve the same effect as the fifth variation.

[0095] (7th and 8th variations) Fig. 18 shows a seventh variation of the circuit configuration of the unit pixel 30. Compared to the configuration shown in Fig. 15, the first imaging cell 31 includes an in-pixel feedback circuit that performs negative feedback within the pixel. The in-pixel feedback circuit includes an amplifier transistor SFS, a feedback control transistor FBS, a capacitor Cs, and a capacitor Cc. A plurality of reference voltages are applied to the drain VB10 of the amplifier transistor SFS depending on the operation mode.

[0096] According to the seventh variation, noise is attenuated in accordance with the ratio between the capacitance value of the capacitance element Cs and the capacitance value of the capacitance element Cc, and high-speed driving is possible because there is no speed reduction when a column feedback circuit is used.

[0097] 19 shows an eighth variation of the circuit configuration of the unit pixel 30. In the eighth variation, the connection destination of the source or drain of the reset transistor RSS differs from that of the seventh variation. Like the seventh variation, the eighth variation also enables reset noise reduction and high-speed operation through intra-pixel feedback reset.

[0098] (9th and 10th variations) Fig. 20 shows a ninth variation of the circuit configuration of the unit pixel 30. Compared to the configuration shown in Fig. 4, the second imaging cell 31' also includes a capacitance element CsatL connected to the second photoelectric conversion unit PDL, similar to the first imaging cell 31. A signal line VPUMP is connected to the capacitance element CsatL.

[0099] According to the ninth variation, the voltage level of the second photoelectric conversion unit PDL of the high-sensitivity cell can be increased by driving the signal line VPUMP with a pulse voltage via the capacitance element CsatL. As a result, a sufficient signal range can be ensured even during low-voltage operation. Furthermore, the second imaging cell 31', which is a high-sensitivity cell, may be equipped with a feedback circuit. In this case, in addition to low-voltage driving, low-noise driving is possible due to reduced reset noise. The feedback circuit can perform negative feedback with higher gain by including multiple capacitance elements, resistance elements, and transistor elements in addition to the reset transistor RSL.

[0100] FIG. 21 shows a tenth variation of the circuit configuration of the unit pixel 30. The second imaging cell 31′, which is a high-sensitivity cell, may be provided with a column feedback circuit. With this configuration, it is possible to selectively reduce noise in the second imaging cell 31, thereby achieving high sensitivity. The reset method in this case may be the high-gain column feedback reset shown in FIGS. 16 and 17, or the intra-pixel feedback reset method shown in FIGS. 18 and 19.

[0101] (11th variation) FIG. 22 shows an eleventh variation of the circuit configuration of the unit pixel 30. The first imaging cell 31 and the second imaging cell 31′ share a charge detection circuit including an amplifier transistor SFL and an address transistor SELL. A reset transistor RSL is shared between the two imaging cells as a reset transistor. Transfer transistors TXS and TXL are used to select which of the first imaging cell 31 and the second imaging cell 31′ to reset or read.

[0102] According to the eleventh variation, it is possible to reduce the number of transistors used in the entire unit pixel 30. As a result, it is possible to ensure a larger area for the second photoelectric conversion unit PDL in the unit pixel 30.

[0103] (Method of driving the imaging device 100) An example of an operation sequence of the imaging device 100 will be described with reference to FIG.

[0104] FIG. 23 schematically shows exposure and readout operations for one cycle (one frame) period in the imaging device 100. The horizontal axis indicates time, and the vertical axis indicates readout rows. FIG. 23 shows so-called rolling shutter readout. In the imaging device 100, the dynamic range can be expanded by performing exposure and readout operations at the same timing using the first imaging cell 31 and the second imaging cell 31′.

[0105] 5, a sensitivity difference of approximately one order of magnitude is created between the first imaging cell 31 and the second imaging cell 31'. This allows the dynamic range to be improved by approximately one order of magnitude compared to normal pixels, even when the same exposure and readout are performed.

[0106] In this embodiment, in order to further expand the dynamic range, the first imaging cell 31 and the second imaging cell 31' have independent exposure and readout timings. In one cycle of imaging operation, the second imaging cell 31' is exposed for the first accumulation time T1, and the first imaging cell 31 is exposed for the second accumulation times T2 and T3 which are shorter than the first accumulation time T1. This will be explained in detail below.

[0107] In this embodiment, one cycle is, for example, 1 / 60 seconds. First, the second imaging cells 31' are exposed for an accumulation time T1 that is close to one cycle, and after the accumulation time has elapsed, the charges in the second imaging cells 31' are read out row by row (readout 1). When the row-by-row readout is completed, the charges accumulated in the second imaging cells 31' in all of the readout-target rows are reset.

[0108] In the first imaging cell 31, so-called non-destructive readout is performed at least twice per cycle. For example, a first exposure is performed with an accumulation time T2 of 1 / 30 (1 / 1800 seconds) of one cycle period, and readout is performed after the exposure is complete (readout 2). Then, without resetting the accumulated charge, a second exposure is performed with an accumulation time T3 of 1 / 2 (1 / 120 seconds) of one cycle period, and readout is performed after the exposure is complete (readout 3). This operational sequence allows three sets of imaging data with different exposure times to be acquired in one cycle period. Performing the same exposure and readout operation would have improved the dynamic range by approximately one order of magnitude, but combining these imaging data allows for an image with a higher dynamic range by approximately one and a half orders of magnitude, for a total of approximately two and a half orders of magnitude.

[0109] As described above, the first imaging cell 31 functions as an imaging region for capturing an image of a bright subject with a large amount of light. A desirable characteristic required for the first imaging cell 31 is a high number of saturated electrons (high saturation). On the other hand, the second imaging cell 31' functions as an imaging region for capturing an image of a dark subject with a low amount of light. A desirable characteristic required for the second imaging cell 31' is low random noise. The second imaging cell 31' may have a small number of saturated electrons, i.e., low saturation. According to this embodiment, an imaging device 100 that can satisfy these characteristics is provided.

[0110] (Second embodiment) An imaging module 200 according to this embodiment will be described with reference to FIG.

[0111] FIG. 24 is a schematic diagram showing functional blocks of an imaging module 200 incorporating the imaging device 100. As shown in FIG.

[0112] The imaging module 200 includes the imaging device 100 according to the first embodiment and a DSP (Digital Signal Processor) 400. The imaging module 200 processes the signal obtained by the imaging device 100 and outputs the processed signal to the outside.

[0113] The DSP 400 functions as a signal processing circuit that processes an output signal from the image capture device 100. The DSP 400 receives a digital pixel signal output from the image capture device 100. The DSP 400 performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The DSP 400 may be a microcomputer that controls the image capture device 100 in accordance with various settings specified by a user and integrates the overall operation of the image capture module 200.

[0114] The DSP 400 processes the digital pixel signals output from the image pickup device 100 to calculate optimal reset voltages (VRG, VRB, and VRR). The DSP 400 feeds back the reset voltages to the image pickup device 100. Here, VRG, VRB, and VRR indicate the reset voltages for the G pixels, the B pixels, and the R pixels, respectively. The reset voltages are fed back via a feedback signal line 49 or a vertical It may be a feedback signal transmitted from the direct signal line 45. The imaging device 100 and the DSP 400 can also be manufactured as a single semiconductor device (a so-called SoC (System on a Chip)). This allows electronic devices using the imaging device 100 to be miniaturized.

[0115] It is of course possible to commercialize only the imaging device 100 without modularizing it. In that case, a signal processing circuit may be externally connected to the imaging device 100, and signal processing may be performed outside the imaging device 100.

[0116] The imaging device according to the present disclosure is useful for image sensors used in cameras such as digital cameras and vehicle-mounted cameras. [Industrial Applicability]

[0117] The imaging device according to the present disclosure can be used in a variety of camera systems and sensor systems, such as digital still cameras, medical cameras, surveillance cameras, vehicle-mounted cameras, digital single-lens reflex cameras, and digital mirrorless single-lens cameras. [Explanation of symbols]

[0118] 30 unit pixels 31 First imaging cell 31' Second imaging cell 45, 45' vertical signal line 46, 46' power wiring 47, 47' Reset signal line 48, 48' address signal lines 49, 49' Feedback signal line 51 First charge detection circuit 51' Second charge detection circuit 52 First vertical scanning circuit 52' Second vertical scanning circuit 53 First horizontal scanning circuit 53' Second horizontal scanning circuit 54 First column AD conversion circuit 54' Second column AD conversion circuit 100 Imaging device 200 Imaging Module 300 Semiconductor substrate 301 Wiring layer 302A, 302B Micro Lenses 303 STI 304 Contacts 305 Color Filter 13, 13' MIM capacitor element 310 Lower electrode 311 Upper electrode 312 Insulator 400 DSP RSS, RSSL, RSSS reset transistor TX, TXL, TXS transfer transistors SFS, SFSS, SFSL amplifier transistors SEL, SELS, SELL address transistor PDS, PDL photodiodes Csat, CsatS, CsatL, Cc, Cs Capacitive elements FBAMPS, FMAPL Inverting amplifier circuit

Claims

1. a semiconductor substrate; a first photoelectric conversion unit in the semiconductor substrate; a capacitive element electrically connected to the first photoelectric conversion unit; a second photoelectric conversion portion in the semiconductor substrate; a first microlens located on the light incident side of the first photoelectric conversion unit; a second microlens located on the light incident side of the second photoelectric conversion unit; Equipped with In a plan view, the capacitive element at least partially overlaps with the second microlens.

2. a semiconductor substrate; a first photoelectric conversion unit in the semiconductor substrate; a capacitive element electrically connected to the first photoelectric conversion unit; a second photoelectric conversion portion in the semiconductor substrate; a first microlens located on the light incident side of the first photoelectric conversion unit; a second microlens located on the light incident side of the second photoelectric conversion unit; Equipped with In a plan view, the capacitive element at least partially overlaps with a region between the first microlens and the second microlens.

3. The imaging device according to claim 1 , wherein a light-collecting area of ​​the second microlens is larger than a light-collecting area of ​​the first microlens.

4. a semiconductor substrate; a first photoelectric conversion unit in the semiconductor substrate; a capacitive element electrically connected to the first photoelectric conversion unit; a second photoelectric conversion portion in the semiconductor substrate; a microlens located on the light incident side of the second photoelectric conversion unit; Equipped with In a plan view, the microlens overlaps the second photoelectric conversion unit but does not overlap the first photoelectric conversion unit; There is no other microlens on the light incident side of the first photoelectric conversion unit, In a plan view, the capacitive element at least partially overlaps with the microlens.

5. The imaging device according to claim 1 , wherein an area of ​​the second photoelectric conversion unit is larger than an area of ​​the first photoelectric conversion unit in a plan view.

6. the capacitance element is located on the opposite side of the semiconductor substrate from the light incident side; The imaging device according to claim 1 .

7. The imaging device according to claim 1 , further comprising a transistor that detects the signal charges generated in the first photoelectric conversion unit and the signal charges generated in the second photoelectric conversion unit.

8. a first transistor that detects signal charges generated in the first photoelectric conversion unit; a second transistor that detects signal charges generated in the second photoelectric conversion unit; The imaging device according to claim 1 , further comprising:

9. The imaging device according to claim 1 , wherein the capacitive element is a metal-insulator-metal (MIM) capacitor.

10. The imaging device according to any one of claims 1 to 9; a signal processing circuit; Equipped with The signal processing circuit processes a signal from the imaging device.

11. The imaging device according to any one of claims 1 to 9; a signal processing circuit; Equipped with The signal processing circuit processes a signal from the imaging device.

Images