Display device

Abstract

To improve reliability of transistors without increasing the number of photomasks used for manufacturing process of a display device including the transistors.SOLUTION: A display device is manufactured while eliminating a photolithography process and an etching process for forming an island-shaped semiconductor layer without increasing the number of photomasks. Specifically, a liquid crystal display device is manufactured by five photolithography processes including a process of forming a gate electrode, a process of forming a protective layer for reducing damage caused by etching process or the like, a process of forming a source electrode and a drain electrode, a process of forming a contact hole, and a process of forming a pixel electrode. The liquid crystal display device according to one aspect of the invention includes a groove part for segmenting the semiconductor layer formed simultaneously with the process for forming the contact hole.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a liquid crystal display device, an EL display device, and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to transistors, semiconductor circuits, memory devices, imaging devices, display devices, and electro-optical devices and electronic devices are all semiconductor devices. [Background technology]

[0003] Active matrix liquid crystal display devices and EL (Electroluminescence) devices using transistors Display devices such as luminescence display devices have been put to practical use. Not only display devices, but also electronic devices such as ICs (Integrated Circuits) It is widely applied in devices.

[0004] In recent years, there has been an increasing demand for larger screen sizes, higher definition, and higher aperture ratios for display devices. Furthermore, display devices are required to have high reliability and low production costs.

[0005] In liquid crystal display devices and EL display devices, transistors are used as switching elements or driving transistors. Therefore, in order to ensure high reliability of the display device, It is important to improve the reliability of the laser. Therefore, in order to simplify the manufacturing process of a display device, it is necessary to simplify the manufacturing process of a transistor. It is effective to do so.

[0006] One effective way to improve the reliability of transistors is to use technology that reduces the degradation of semiconductor layers. The deterioration of the semiconductor layer is caused by damage during the etching process in the photolithography process. This is caused by the diffusion of impurity elements from other layers into the semiconductor layer. To reduce the deterioration of the conductor layer, it is necessary to reduce damage caused by the manufacturing process such as photolithography. It is also possible to provide a layer that reduces the amount of impurity in the semiconductor layer, or to provide a blocking layer to prevent the diffusion of impurity elements from other layers into the semiconductor layer. Techniques such as providing a coating layer are effective.

[0007] In addition, the manufacturing process of a transistor can be simplified by reducing or simplifying the photolithography process. For example, if one photolithography process is added, the resist coating The coating is done in the processes of fabrication, pre-baking, exposure, development, post-baking, etc., and in the processes before and after these. This requires processes such as forming a resist and etching, as well as processes such as removing the resist, cleaning, and drying. Therefore, just adding one photolithography step to the manufacturing process significantly reduces the number of steps. increases to.

[0008] As an example, a bottom-gate transistor is used as a switching element in a large liquid crystal display device. The transistor manufacturing process involves photolithography using at least five photomasks. Specifically, the transistors of the pixels of a liquid crystal display device are generally manufactured through the following process. In other words, the process of forming the gate electrode (including the wiring formed in the same layer), the process of forming the island-shaped semiconductor forming a layer, forming a source electrode and a drain electrode (including wiring formed in the same layer); forming an opening (contact hole) (including removing the insulating layer other than the opening) The five photo processes are: the process of forming the pixel electrode (including wiring formed in the same layer) Therefore, the transistor manufacturing process requires a single photomass The effect of shortening the process by reducing the cost or simplifying the photolithography process is significant. stomach.

[0009] Another example is a bottom gate EL display device used as a switching element in a large EL display device. The manufacturing process of a phototransistor involves photolithography using at least six photomasks. Specifically, the pixel transistors of an EL display device are In the case of a transistor, the process of forming the gate electrode (including the wiring formed in the same layer), a step of forming a semiconductor layer, a step of forming a source electrode and a drain electrode (including wiring formed in the same layer), forming an opening (contact hole) (including forming an insulating layer other than the opening); a step of forming one electrode of the EL element (including wiring formed in the same layer), and forming a partition layer to paint the EL layer by color. Therefore, in the transistor manufacturing process, one photomask is removed. The effect of shortening the process by reducing the number of steps or simplifying the photolithography process is significant.

[0010] Therefore, the photolithography process in the manufacturing process of the transistor can be reduced or simplified. Many technologies have been developed to simplify the photolithography process. The techniques for simplifying this process include backside exposure, resist reflow, and lift-off. In addition, in order to simplify the photolithography process in the manufacturing process of the transistor, To achieve this, a multi-tone mask (also called a half-tone mask or gray-tone mask) is used. The technology that reduces the manufacturing process by using a multi-tone mask is, for example, For example, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-179069 Summary of the Invention [Problem to be solved by the invention]

[0012] However, in order to reduce production costs, the photolithography process is reduced or simplified. When the semiconductor layer is etched, a part of the semiconductor layer is etched. During the etching process of the drain electrode (also called the second electrode), This can lead to problems such as the semiconductor layer being deteriorated due to exposure to etching solutions. do.

[0013] In addition, in order to reduce the deterioration of the semiconductor layer, the damage caused by the etching process, etc. However, if a protective layer is provided on the semiconductor layer, the protective layer The protective layer has a frame for providing openings for connecting the first electrode and the second electrode to the semiconductor layer. This increases the number of photomasks required. Considering bottom-gate transistors as pixel transistors of display devices, at least The number of photomasks will be six. In addition, due to this increase in the number of photomasks, Considering bottom-gate transistors as pixel transistors in EL display devices, at least In either case, the number of photomasks required is seven. Therefore, in a configuration in which a protective layer is provided to reduce damage caused by an etching process, etc. This causes a problem that the number of photolithography steps and etching steps increases.

[0014] In view of this, one embodiment of the present invention is to increase the number of photolithography steps in a manufacturing process of a transistor. Another object is to prevent deterioration of a semiconductor layer without increasing the temperature.

[0015] Another embodiment of the present invention is a photomask used in a manufacturing process of a display device including a transistor. An object of the present invention is to improve the reliability of transistors without increasing the number of transistors. [Means for solving the problem]

[0016] One aspect of the present invention is a photolithography process and an etching process for forming an island-shaped semiconductor layer. A semiconductor that can be manufactured without increasing the number of photomasks by omitting the etching process. Specifically, the process of forming a gate electrode (including wiring formed in the same layer) a step of forming a protective layer to reduce damage caused by etching steps, etc.; a step of forming a first electrode and a step of forming a first electrode (including wiring formed in the same layer); forming an opening (opening (including removal of insulating layers other than the part), pixel electrodes (including wiring formed in the same layer) The five photolithography processes are used to form semiconductor devices for liquid crystal displays. The semiconductor device according to one embodiment of the present invention is fabricated at the same time as the step of forming the opening. The semiconductor device according to one embodiment of the present invention has a semiconductor layer. An opening is provided in the protective layer on the conductor layer, and the first electrode, the second electrode, and the semiconductor layer are exposed through the opening. and a structure for reducing deterioration of the semiconductor layer superimposed on the protective layer other than the opening. This is what is done.

[0017] One aspect of the present invention is a semiconductor device including a gate electrode, a semiconductor layer, a protective layer, a first electrode, and a second electrode. a first wiring electrically connected to the gate electrode; a second wiring connected to the second electrode; a pixel electrode electrically connected to the second electrode; a capacitance wiring; and a groove portion. a protective layer is provided on the semiconductor layer in contact therewith, and the semiconductor layer and the protective layer are The first wiring, the second wiring, the pixel electrode, and the capacitance wiring are provided so as to overlap each other. The first electrode and the second electrode are electrically connected to the semiconductor layer through an opening formed in the protective layer, and the groove is formed on the first wiring so as to cross the first wiring in the line width direction, and the trench is formed on the capacitance wiring The trench is formed on the second wiring in a line width direction of the capacitor wiring. In the liquid crystal display device, the polarizer is formed beyond the edge of the pixel electrode in a direction parallel to the polarizer.

[0018] In one embodiment of the present invention, a liquid crystal display device in which no semiconductor layer is present on the bottom surface of the groove is preferred.

[0019] In one embodiment of the present invention, a liquid crystal display device having a semiconductor layer on the side surface of the groove is preferable.

[0020] In one aspect of the present invention, the liquid crystal display device preferably has the groove portion overlapping with the alignment film.

[0021] In one aspect of the present invention, there is provided a liquid crystal display device in which at least a part of the groove portion overlaps with the pixel electrode. Positioning is preferred.

[0022] In one embodiment of the present invention, the semiconductor layer in the liquid crystal display device is preferably an oxide semiconductor.

[0023] In one embodiment of the present invention, the protective layer is preferably an oxide having insulating properties. stomach.

[0024] In one embodiment of the present invention, the insulating oxide contains indium, gallium, and zinc. In the oxide, part of the gallium is replaced with titanium, zirconium, hafnium, or germanium. In the liquid crystal display device, the material is preferably substituted with at least one element selected from the group consisting of ammonium, ammonium, tungsten ...

[0025] In one embodiment of the present invention, a gate electrode is formed on a substrate by a first photolithography process. a gate insulating layer is formed on the gate electrode; a semiconductor layer is formed on the gate insulating layer; A protective layer having an opening is formed on the semiconductor layer by a photolithography process. A first electrode and a second electrode are formed on the protective layer by a lithography process, the first electrode and the second electrode being in contact with the semiconductor layer at the opening. forming an insulating layer on the first electrode and the second electrode; and a fourth photolithography process. By this, a part of the insulating layer overlapping with the second electrode is selectively removed to form an opening, and the insulating layer Then, a groove is formed by removing a part of the semiconductor layer and the gate insulating layer, and a fifth photolithography is performed. This is a method for manufacturing a liquid crystal display device in which pixel electrodes are formed on an insulating layer by a lithography process.

[0026] In one embodiment of the present invention, a liquid crystal display device is provided in which an underlayer is formed between the substrate and the gate electrode. The method of preparation is preferred.

[0027] In one embodiment of the present invention, a method for manufacturing a liquid crystal display device in which a semiconductor layer includes an oxide semiconductor is preferably used. I wish.

[0028] In one embodiment of the present invention, after the opening is formed, the surface of the semiconductor layer exposed in the opening of the protective layer The method for manufacturing a liquid crystal display device preferably includes a step of washing the substrate.

[0029] Further, one embodiment of the present invention is a photolithography process for forming an island-shaped semiconductor layer. It can be manufactured without increasing the number of photomasks by omitting the etching process. Specifically, a semiconductor device is formed on the substrate. a step of forming a protective layer to reduce damage caused by etching steps, etc.; a process for forming a source electrode and a drain electrode (including wiring formed in the same layer); (including removing the insulating layer other than the opening), one electrode of the EL element (formed in the same layer) A process for forming a partition wall layer to paint the EL layer by color. The semiconductor device used in the EL display device is manufactured through six photolithography processes. The semiconductor device according to one embodiment of the present invention is formed simultaneously with the step of forming the opening. The semiconductor device according to one embodiment of the present invention includes a semiconductor An opening is provided in the protective layer on the semiconductor layer, and the source electrode and the drain electrode are connected to the opening. and a structure for reducing deterioration of the semiconductor layer superimposed on the protective layer other than the opening. This is what we do.

[0030] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first transistor. a first wiring electrically connected to the gate electrode of the first transistor; A second wiring electrically connected to one of the electrodes serving as the input of the second transistor and a second wiring electrically connected to the source of the second transistor. a third wiring electrically connected to one of the electrodes serving as the gate or drain of the first transistor; The other of the electrodes serving as the source or drain is electrically connected to the gate electrode of the second transistor. The fourth wiring is connected to the other of the electrodes that will be the source or drain of the second transistor. The EL element is electrically connected to the electrode serving as the source or drain of the first transistor. The first transistor has a capacitance element formed in a region where the other wiring and the third wiring overlap, and a trench. a protective layer is provided on and in contact with the semiconductor layers of the first transistor and the second transistor; The semiconductor layer and the protective layer include a first wiring, a second wiring, a third wiring, a fourth wiring, and an E The L element is provided so as to overlap the first transistor and the second transistor. The source or drain electrode is electrically connected to the semiconductor layer through an opening formed in the protective layer. The groove is formed on the first wiring so as to cross the first wiring in the line width direction. The portion is formed so as to be parallel to the direction in which the second wiring and the third wiring extend. The EL display device is formed across the gate electrode of the transistor in the line width direction.

[0031] In one embodiment of the present invention, an EL display device in which no semiconductor layer is present on the bottom surface of the groove is preferred.

[0032] In one embodiment of the present invention, an EL display device having a semiconductor layer on the side surface of the groove is preferred.

[0033] In one embodiment of the present invention, the EL display device is preferably one in which the groove portion overlaps with the partition layer.

[0034] In one embodiment of the present invention, one electrode of the EL element and the fourth wiring are formed in the same layer. An EL display device in which the above-described structure is used is preferred.

[0035] In one embodiment of the present invention, the semiconductor layer in the EL display device is preferably an oxide semiconductor.

[0036] In one embodiment of the present invention, the protective layer is preferably an oxide having insulating properties. stomach.

[0037] In one embodiment of the present invention, the insulating oxide contains indium, gallium, and zinc. In oxides containing gallium, part of the gallium is replaced with titanium, zirconium, hafnium, or germanium. Preferably, the EL display device is made of a material in which at least one element selected from the group consisting of ammonium, ammonium, tungsten ... .

[0038] In one embodiment of the present invention, a gate electrode is formed on a substrate by a first photolithography process. a gate insulating layer is formed on the gate electrode; a semiconductor layer is formed on the gate insulating layer; A protective layer having an opening is formed on the semiconductor layer by the photolithography process of the third By a photolithography process, a source contacting the semiconductor layer at the opening of the protective layer is formed on the protective layer. a source electrode and a drain electrode are formed, an insulating layer is formed on the source electrode and the drain electrode, and a fourth forming an opening by selectively removing a portion of the insulating layer through a photolithography process; A groove is formed by removing a part of the insulating layer, the semiconductor layer, and the gate insulating layer. By a lithography process, an opening in the insulating layer and one electrode of the EL element are formed on the insulating layer. Then, a part of one electrode of the EL element and the insulating layer are removed by a sixth photolithography process. On top of that, a partition layer is formed to paint the EL layer of the EL element by color. It is a method.

[0039] In one embodiment of the present invention, an EL display device in which an underlayer is formed between the substrate and the gate electrode The method of preparation is preferred.

[0040] In one embodiment of the present invention, a method for manufacturing an EL display device in which a semiconductor layer includes an oxide semiconductor is preferably used. I wish.

[0041] In one embodiment of the present invention, after the opening is formed, the surface of the semiconductor layer exposed in the opening of the protective layer The method for producing an EL display device preferably includes a step of washing the substrate. [Effects of the Invention]

[0042] According to one aspect of the present invention, the number of photolithography steps in the manufacturing process of a transistor is increased. This can prevent the semiconductor layer from being damaged and reduce deterioration of the semiconductor layer.

[0043] According to one embodiment of the present invention, a photodiode used in a manufacturing process of a display device including a transistor The reliability of the transistor can be improved without increasing the number of masks. [Brief explanation of the drawings]

[0044] [Figure 1] FIG. 1 is a top view illustrating one embodiment of the present invention. [Figure 2] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 3] FIG. 1 is a top view illustrating one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 5] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 6] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 8] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 9] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 12] 1A to 1C illustrate examples of electronic devices. [Figure 13] FIG. 1 is a top view illustrating one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 15] FIG. 1 is a top view illustrating one embodiment of the present invention. [Figure 16] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 17] FIG. 1 is a top view illustrating one embodiment of the present invention. [Figure 18] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 20] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 21] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 22] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 23] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0045] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents of the description. The same reference numerals are used in different drawings to denote the same parts or parts having similar functions. A repeated explanation will be omitted.

[0046] In addition, ordinal numbers such as "first," "second," and "third" in this specification are used to indicate a mixture of constituent elements. The numbers are added to avoid confusion and are not intended to limit the number.

[0047] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual device for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0048] Also, the functions of the "source" and "drain" of a transistor are different when transistors of different polarities are used. This may be reversed when using a current source or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It shall be possible to use it.

[0049] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0050] (Embodiment 1) In this embodiment, a liquid crystal display device in which the number of photomasks and the number of photolithography steps are reduced is provided. An example of a pixel configuration and a manufacturing method of the device will be described with reference to FIGS.

[0051] An example of the structure of a semiconductor device 100 used in a liquid crystal display device is shown in FIG. The device 100 has a pixel region 102 and m terminals 10 (m is an integer of 1 or more) on a substrate 101. and a terminal section 103 having n terminals 106 (n is an integer of 1 or more). The semiconductor device 100 has a terminal portion 104 connected to the terminal portion 103. The wiring 212, n wirings 216 connected to the terminal portion 104, and wiring 203. The pixel region 102 is arranged in a matrix of m vertical rows by n horizontal columns. It has a plurality of pixels 110. The pixel 110 (i, j) in the i-th row and j-th column (i is 1 or more and m or less) j is an integer between 1 and n) are connected to the wiring 212_i and the wiring 216_j, respectively. Each pixel is connected to a wiring 203 that functions as a capacitance electrode or a capacitance wiring. The wiring 203 is connected to the terminal 107. The wiring 212_i is connected to the terminal 105_i. and the wiring 216_j is connected to the terminal 106_j.

[0052] The terminals 103 and 104 are external input terminals, and are connected to an externally provided control circuit and an FP. It is connected using a flexible printed circuit (C) or other external A signal supplied from a control circuit provided in the semiconductor device is transmitted to the semiconductor device via terminals 103 and 104. 6A, the terminal portions 103 are provided on the left and right sides of the pixel region 102. The terminal section 104 is formed on the side of the pixel area, and signals are input from two points. The configuration is shown in which signals are input from two points. By inputting a signal, the signal supply capacity is increased, and the semiconductor device 100 can operate at high speed. Furthermore, the increase in wiring resistance due to the increase in size and high definition of the semiconductor device 100 can be prevented. The influence of signal delay can be reduced. This makes it possible to improve the reliability of the semiconductor device 100. In (A), the terminal portion 103 and the terminal portion 104 are provided at two locations. It is also possible to provide one of each.

[0053] 6B shows the circuit configuration of the pixel 110. The pixel 110 includes a transistor 111 The transistor 111 includes a gate electrode, a liquid crystal element 112, and a capacitor element 113. is connected to the wiring 212_i, and is connected to one of the source and drain electrodes of the transistor 111. (hereinafter referred to as the first electrode) is connected to the wiring 216_j. The other electrode of the first source or drain (hereinafter referred to as the second electrode) is The other electrode of the liquid crystal element 112 is connected to one electrode of the capacitor 113. The electrode is connected to the electrode 114. The potential of the electrode 114 is 0V, GND, or a common potential. The other electrode of the capacitor 113 is connected to the wiring 203. It is being done.

[0054] The transistor 111 receives an image signal supplied from a wiring 216_j to the liquid crystal element 112. The wiring 212_i has a function of selecting whether to turn on the transistor 111. When a signal is supplied to the wiring 216_j, an image signal is supplied to the wiring 216_j through the transistor 111. The liquid crystal element 112 changes the voltage in response to the image signal (potential) supplied. The light transmittance is controlled. The capacitor 113 holds the potential supplied to the liquid crystal element 112. The capacitor 113 functions as a storage capacitor (also referred to as a Cs capacitor) for storing the Although it is not necessary to provide the capacitor element 113, the transistor 111 can be turned on. The liquid crystal element 11 is in an OFF state and is caused by a current (OFF current) that flows between the first electrode and the second electrode. This can suppress fluctuations in the potential applied to 2.

[0055] The semiconductor layer in which the channel of the transistor 111 is formed may be a single crystal semiconductor, a polycrystalline semiconductor, or a Examples of the semiconductor material include: Silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. In addition, the display device described in this embodiment has a semiconductor Since the layer remains, the display device using the semiconductor is used as a transmission type display device. In this case, it is preferable to increase the transmittance of visible light by making the semiconductor layer as thin as possible.

[0056] An oxide semiconductor is used for a semiconductor layer in which a channel of the transistor 111 is formed. Oxide semiconductors have a large energy gap of 3.0 eV or more, and The transmittance to visible light is high. In addition, the transistor obtained by processing the oxide semiconductor under appropriate conditions In a transistor, the off-state current is 10 0zA(1×10 -19 A) or less, or 10zA (1 x 10 -20 A) The following further is 1zA(1×10 -21 A) or less. The potential applied to the liquid crystal element 112 can be maintained without the need for a power supply. Therefore, a liquid crystal display device with a high image quality can be realized.

[0057] Next, an example of the configuration of the pixel 110 shown in FIG. 6 will be described with reference to FIGS. 1 and 2. 2 is a cross-sectional view showing the layered structure of the pixel 110. It should be noted that the chains A1-A2, B1-B2, C1-C2, and D1-D2 in FIG. The lines correspond to cross sections A1-A2, B1-B2, and C1- in FIGS. 2(A) to 2(D). C2, corresponding to cross section D1-D2.

[0058] The transistor 111 described in this embodiment has a first electrode 206A and a second electrode 206B facing each other at regular intervals. The shapes of the first electrode 206A and the second electrode 206B are the same as those of the other electrodes. For example, the second electrode 206B may be U-shaped (C-shaped, U-shaped) Alternatively, the first electrode 206A may be in a shape such that the first electrode 206A is surrounded by a first electrode 206A having a rectangular or horseshoe shape.

[0059] The wiring 203 functions as a capacitance electrode or a capacitance wiring. and the second electrode 206B are overlapped to form a capacitor element 113.

[0060] In addition, the semiconductor device described in this embodiment mode is formed with island-shaped semiconductor layers to simplify the process. Since no photolithography process or etching process is performed to form the entire pixel region 102, As a result, the wiring 212_i functions as a gate electrode. The wiring 216_j functions as one of the source and drain electrodes, and the wiring 216_ j+1 acts as the other electrode of the source or drain. Jiru.

[0061] The wiring 203 functions as a gate electrode, and the wiring 216_j functions as a source or drain. The wiring 216_j+1 functions as the other electrode of the source or drain. A second parasitic transistor is created that functions in conjunction with the

[0062] The pixel electrode 210 functions as a gate electrode, and the insulating layer 207 functions as a gate insulating layer. The wiring 216_j functions as one of the source and drain electrodes, and the wiring 216_ A third parasitic transistor is generated in which j+1 acts as the other electrode of the source or drain. Jiru.

[0063] Parasitic transistors are formed in areas of the semiconductor layer other than the area where the transistor is formed. A channel is formed to create a transistor.

[0064] In the configuration of this embodiment, the photolithography process and etching process for forming the island-shaped semiconductor layer are performed. By omitting the etching process, damage to the semiconductor layer can be reduced, and deterioration of the semiconductor layer can be prevented. can be reduced.

[0065] The first parasitic transistor applies a potential to the wiring 212_i that turns on the transistor 111. When the voltage Vcc is supplied, the first parasitic transistor is also turned on, and the wiring 216_j and the wiring 21 6_j+1 is electrically connected. If the wiring 216_j and the wiring 216_j+1 are electrically connected, the image signals of both will interfere with each other, resulting in an inaccurate image. It becomes difficult to supply the image signal to the liquid crystal element 112.

[0066] In addition, when the second parasitic transistor functions as an n-channel transistor, The potential of the wiring 216_j or the wiring 216_j+1 is lower than the potential supplied to the wiring 203. When the absolute value of the potential difference becomes larger than the threshold voltage of the second parasitic transistor, A channel is formed in the semiconductor layer 205 located under the pixel electrode 210, and a second parasitic transistor The transistor is turned on.

[0067] When the second parasitic transistor is turned on, the wiring 216_j and the wiring 216_j+1 are electrically connected. The second parasitic transistor electrically connects the wiring 216_j and the wiring 21 When 6_j+1 are electrically connected, the image signals from both sides interfere with each other, and the correct image signal is not transmitted to the LCD pixel. It becomes difficult to supply the power to the child 112.

[0068] In addition, when the third parasitic transistor functions as an n-channel transistor, The potential of the wiring 216_j or the wiring 216_j is higher than the potential supplied to or held by the electrode 210. The potential of 6_j+1 becomes lower, and the absolute value of the potential difference is the threshold value of the third parasitic transistor. When the voltage becomes larger than the threshold voltage, a channel is formed in the semiconductor layer 205 located under the pixel electrode 210. This generates a third parasitic transistor, which is turned on.

[0069] When the third parasitic transistor is turned on, the wiring 216_j and the wiring 216_j+1 are electrically connected. The third parasitic transistor electrically connects the wiring 216_j and the wiring 21 When 6_j+1 are electrically connected, the image signals from both sides interfere with each other, and the correct image signal is not transmitted to the LCD pixel. In addition, it becomes difficult to supply the pixel 112 with a large aperture ratio. Therefore, when the pixel electrode 210 is brought closer to the wiring 216_j or the wiring 216_j+1, a third parasitic transistor The influence of transistors becomes stronger.

[0070] Therefore, in this embodiment, a groove portion 230 is provided in the pixel 110 by removing the semiconductor layer 205. The groove 230 is formed to have a width equal to or smaller than the width of the wiring 212_i, so that the parasitic transistor described above does not occur. By providing the wiring so as to cross over both ends of the direction, the generation of the first parasitic transistor can be prevented. In addition, the groove 230 is designed to cross over both ends of the wiring 203 in the line width direction. By doing so, it is possible to prevent the generation of the second parasitic transistor. A plurality of upper grooves 230 or grooves 230 on the wiring 203 may be provided.

[0071] In addition, the groove 230 is formed between the wiring 216_j and the pixel electrode 210, or between the wiring 216_j+1 and the pixel electrode 210, the wiring 216_j or the wiring 216 The end 231 and the end 232 of the pixel electrode 210 are aligned in a direction parallel to the direction in which the pixel electrode 210 extends. 32. This prevents the formation of a third parasitic transistor. The groove 230 is provided parallel to the wiring 216_j or the wiring 216_j+1. The conductor need not be bent or curved, and may have bends or curves.

[0072] In FIG. 1, the groove 230 is interrupted in the region sandwiched between the wiring 212_i and the wiring 203. However, the groove 230 provided beyond the end of the wiring 212_i in the line width direction is extended, and the wiring 2 Alternatively, the groove 230 may be connected to the end of the groove 230 in the width direction of the groove 230.

[0073] Furthermore, the groove 230 is not provided on the wiring 203, and the potential of the wiring 203 is is set to a potential lower than the potential supplied to the wiring 216_j+1, However, in this case, the potential is applied to the wiring 203. A separate power source must be provided to supply the power.

[0074] There is no particular limitation on the size of the groove 230 where the semiconductor layer 205 is removed. In order to reliably prevent the generation of a resistor, the direction in which the wiring 216_j or the wiring 216_j+1 extends is The distance of the portion where the semiconductor layer in the groove 230 is removed in the direction perpendicular to the direction of the groove 230 is 1 μm or less. It is preferable that the thickness is 1 μm or more, and more preferable that the thickness is 2 μm or more.

[0075] In the transistor 111 of this embodiment, a protective layer 351 is provided over the semiconductor layer 205. This structure is designed to reduce deterioration of the semiconductor layer 205. An opening 301 and an opening 302 are provided in a part of the protective layer 351 on the conductor layer 205, and a semiconductor layer 205 is connected to the first electrode 206A and the second electrode 206B. Therefore, a part of the semiconductor layer 205 may be damaged during the etching process of the semiconductor layer 205 or during the etching process of the first electrode 206A. and exposed to etching gas or etching solution during the etching process of the second electrode 206B. This can reduce deterioration of the semiconductor layer 205.

[0076] In the layout of the pixel 110 shown in FIG. 1, the opening 301 and the opening 302 are OPC ( Optical Proximity Correction It is preferable to process the first electrode 206A of the transistor 111 and the An opening 301 and an opening 302 are formed to connect the second electrode 206B and the semiconductor layer 205. By forming the aperture using a photomask with OPC, deformation of the aperture shape due to light diffraction can be prevented. This can reduce variations in the channel width and channel length of the transistor.

[0077] The cross section A1-A2 shows the stacked structure of the transistor 111 and the capacitor 113. The transistor 111 is a transistor with a bottom gate structure. A stacked structure from the wiring 216_j to the wiring 216_j+1, including the electrode 210 and the groove portion 230 The cross section C1-C2 shows the intersection of the wiring 216_j and the wiring 212_i. The cross section D1-D2 shows the stacked structure in the groove 230 and the wiring 216_ j+1 and the wiring 212_i.

[0078] In the cross section A1-A2 shown in FIG. 2(A), an underlayer 201 is formed on a substrate 200. A gate electrode 202 and a wiring 203 are formed on the earth layer 201. A gate insulating layer 204 and a semiconductor layer 205 are formed on the gate electrode 202 and the wiring 203. A protective layer 351 is formed on the semiconductor layer 205. A first protective layer 351 is formed on the protective layer 351. The semiconductor layer 205 is formed on the first electrode 206A and the second electrode 206B. The first electrode 206A and the second electrode 206B are formed in the openings 301 and 302. Also, the first electrode 206A and the second electrode 206B are connected to a part of the protective layer 351. An insulating layer 207 is formed on the insulating layer 207. A pixel electrode 210 is formed on the insulating layer 207. The pixel electrode 210 is formed in the opening 208 formed in the insulating layer 207. It is connected to 206B.

[0079] The wiring 203 and the second electrode 206B are overlapped with the gate insulating layer 204 and the semiconductor layer 205 sandwiched therebetween. The portion where the gate insulating layer 204 and the semiconductor layer 205 are formed functions as a capacitor element 113. The dielectric layer formed between the wiring 203 and the pixel electrode 210 functions as a dielectric layer. By using a layered structure, even if a pinhole occurs in one dielectric layer, the pinhole is not dissipated in the other dielectric layers. Since the capacitor 113 is covered with the oxide semiconductor layer, the capacitor 113 can function normally. Since the relative dielectric constant of a conductor is as high as 14 to 16, when an oxide semiconductor is used for the semiconductor layer 205, Therefore, the capacitance value of the capacitance element 113 can be increased.

[0080] In the cross section B1-B2 shown in FIG. 2(B), an underlayer 201 is formed on a substrate 200. A gate insulating layer 204 is formed on the earth layer 201, and a semiconductor layer 205 is formed on the gate insulating layer 204. A protective layer 351 is formed on the semiconductor layer 205. The wiring 216_j and the wiring 216_j+1 are formed on the protective layer 351. An insulating layer 207 is formed on the wiring 216_j+1. A pixel electrode 210 is formed.

[0081] Between the wiring 216_j+1 and the pixel electrode 210, a part of the gate insulating layer 204, the semiconductor layer 20 5, a part of the protective layer 351, and a part of the insulating layer 207 are removed to form a groove 230. The groove 230 has a structure in which at least the bottom surface does not have a semiconductor layer. It has become.

[0082] In the cross section C1-C2 shown in FIG. 2(C), a base layer 201 is formed on a substrate 200. A wiring 212_i is formed on the earth layer 201. A gate insulating film is formed on the wiring 212_i. An insulating layer 204 and a semiconductor layer 205 are formed on the insulating layer 204. A protective layer 35 is formed on the semiconductor layer 205. Further, a wiring 216_j is formed on the protective layer 351, and the wiring 216_ An insulating layer 207 is formed on the substrate j.

[0083] In the cross section D1-D2 shown in FIG. 2(D), an underlayer 201 is formed on a substrate 200. A wiring 212_i is formed on the earth layer 201. A gate insulating film is formed on the wiring 212_i. An insulating layer 204 and a semiconductor layer 205 are formed on the insulating layer 204. A protective layer 35 is formed on the semiconductor layer 205. In addition, a wiring 216_j+1 is formed on the protective layer 351, and the wiring 21 An insulating layer 207 is formed on the gate insulating layer 204. A groove portion 23 is formed by removing a part of the body layer 205, a part of the protective layer 351, and a part of the insulating layer 207. 0 is formed.

[0084] Next, examples of pixel configurations different from the configuration shown in FIG. 1 will be described with reference to FIGS. 3 and 4. 3 is a top view showing the planar configuration of the pixel 120. The cross sections A1-A2, E1-E2, and F1-F2 correspond to the cross sections A1-A2 and E1- The pixel 120 shown in FIG. 3 corresponds to the cross section of the portion indicated by the chain lines E2 and F1-F2. The pixel 110 shown in FIG. 3 has a different configuration from the pixel 110 shown in FIG. 3. The configuration of the portion indicated by is the same as the configuration described in FIG. 1 and FIG. 2(A).

[0085] The pixel 120 has a groove 230 between the wiring 216_j and the pixel electrode 210, and between the wiring 216_ j+1 and the pixel electrode 210. 2_i and the wiring 203 so as to cross over the widthwise ends thereof, and 2_i and the wiring 203. By arranging the gates closer together, the formation of parasitic transistors can be more reliably prevented.

[0086] Next, an example of a pixel configuration different from the configurations shown in FIGS. 1 to 4 will be described with reference to FIG. 5. 5A is a top view showing the planar configuration of the pixel 130. -G2 corresponds to the cross section of the region indicated by the chain line G1-G2 in FIG. 5(A). The pixel 130 uses a conductive layer with high light reflectivity for the pixel electrode 210, and thus the pixel 130 is a reflective liquid crystal display. 1 shows an example of a pixel configuration that can be applied to a display device.

[0087] In the pixel 130, the grooves 251 and 252 where the semiconductor layer 205 has been removed are connected to the wiring 212 The wiring 212_i is provided so as to extend across both ends of the wiring 212_i in the line width direction. By providing a plurality of grooves that cross over both ends, the adjacent wiring 212_i is formed to overlap with the wiring 212_i. The influence of the live channel can be more reliably suppressed.

[0088] In addition, the photolithography process and etching process for forming the island-shaped semiconductor layer are not performed. Therefore, in the semiconductor layer remaining outside the region where the transistor is formed, The channel formed by the potential supplied to the pixel electrode etc. superimposed on the layer is called a parasitic channel. say.

[0089] In addition, in the pixel 130, the grooves 253 and 254 where the semiconductor layer 205 has been removed are connected to the wiring 2. The wiring 203 is provided so as to extend across both ends of the wiring 203 in the line width direction. By providing a plurality of grooves that cross over the end, parasitic channels formed overlapping with the wiring 203 are prevented. This can more reliably suppress the effects of the filter.

[0090] In addition, in the pixel 130, the grooves 255 and 256 where the semiconductor layer 205 has been removed are connected to the wiring 2. The pixel electrode 21 The wiring 216_j or the wiring 21 The end 231 and the end 6_j+1 of the pixel electrode 210 are aligned in a direction parallel to the direction in which the pixel electrode 210 extends. By providing a plurality of grooves beyond 232, the parasitic channel formed overlapping with the pixel electrode 210 can be prevented. The grooves 255 and 256 are formed so that the influence of the wiring 21 can be more reliably suppressed. 6_j or wiring 216_j+1, and It may have a part.

[0091] The grooves 255 and 256 of the pixel 130 have curved portions, and a part of the grooves 255 and 256 is connected to the pixel electrode 210. The pixel 130 is formed to overlap with the pixel electrode 210. The pixel electrode 210 includes a groove 257 and a groove 258. By providing the grooves 258 to 55, it is possible to provide unevenness on the surface of the pixel electrode 210. By providing the surface of the pixel electrode 210 with irregularities, incident external light is diffused and a better display is achieved. Therefore, the visibility of the display is improved.

[0092] The grooves 255 to 258 formed to overlap the pixel electrode 210 have side surfaces A tapered shape is preferable because it improves coverage of the pixel electrode 210 .

[0093] Next, an example of the configuration of the terminal 105 and the terminal 106 will be described with reference to FIG. 7 (A1 7(A) and 7(A2) respectively show a top view and a cross-sectional view of the terminal 105. The chain line J1-J2 in 1) corresponds to the cross section J1-J2 in FIG. 7(B1) and 7(B2) are a top view and a cross-sectional view of the terminal 106, respectively. The chain line K1-K2 in FIG. 7(B1) corresponds to the cross section K1-K2 in FIG. 7(B2). In the cross sections J1-J2 and K1-K2, J2 and K2 correspond to the substrate. It corresponds to the end.

[0094] In the cross section J1-J2, an underlayer 201 is formed on a substrate 200, and a layer 202 is disposed on the underlayer 201. A wiring 212 is formed on the gate insulating layer 204 and the semiconductor layer 20 5, a protective layer 351 and an insulating layer 207 are formed. An electrode 221 is formed on the insulating layer 207. The electrode 221 is formed by the gate insulating layer 204, the semiconductor layer 205, the protective layer 351, and the insulating layer 206. It is connected to the wiring 212 through an opening 219 formed in the layer 207 .

[0095] In the cross section K1-K2, a substrate 200 is provided with an underlayer 201, a gate insulating layer 204, a semiconductor The layer 205 and the protective layer 351 are formed on the insulating layer 205. The wiring 216 is formed on the protective layer 351. An insulating layer 207 is formed on the wiring 216. An electrode 222 is formed on the insulating layer 207. The electrode 222 is connected to the wiring 216 through an opening 220 formed in the insulating layer 207. are.

[0096] The configuration of the terminal 107 may be the same as that of the terminal 105 or the terminal 106. do.

[0097] The pixel area 102 and the terminal section 104 are connected by n wires 216. In the routing of the wiring 216 from 102 to the terminal 106 of the terminal portion 104 When the adjacent wirings 216 are close to each other, the potential difference between the adjacent wirings 216 A parasitic channel is formed in the semiconductor layer 205 between the adjacent wirings 216. There is a risk that 16 may be electrically connected to each other.

[0098] This phenomenon occurs throughout the entire area from the pixel area 102 to the terminal area 104 through the insulating layer. Alternatively, a conductive layer is provided between the adjacent wirings 216, and the potential of the conductive layer is applied to the semiconductor layer 205. This can be prevented by setting the potential at which no parasitic channel is formed.

[0099] For example, when an oxide semiconductor is used for the semiconductor layer 205, most oxide semiconductors have an n-channel Since the potential of the conductive layer is easily changed to a lower potential than the potential supplied to the wiring 216, It should be left as that.

[0100] In the groove forming step described below, the semiconductor layer 205 between the adjacent wirings 216 is By removing the wirings 216, electrical connection between adjacent wirings 216 can also be prevented.

[0101] 8, a structure in which a groove 240 is formed between adjacent wirings 216 and the semiconductor layer 205 is removed is shown. 8A is a top view showing the planar configuration of the wiring 216 connected to the terminal 106. The cross section L1-L2 shown in FIG. 8(B) is the part indicated by the chain line L1-L2 in FIG. 8(A). In FIG. 8A, the wiring 216_j is connected to the terminal 106_j. , the wire 216_j+1 is connected to the terminal 106_j+1, and the wire 216_j+2 is connected to the terminal 106_j+2. 6_j+2. The groove 240 can be formed in the same manner as the groove 230. can.

[0102] A groove portion where the semiconductor layer 205 is removed is formed between the adjacent wirings 216_j and 216_j+1. 240 is formed. In addition, between the adjacent wiring 216_j+1 and wiring 216_j+2 In this way, a groove 240 is formed by removing the semiconductor layer 205. By providing a groove 240 where the semiconductor layer 205 is removed between the lines 216, the adjacent wiring 21 This prevents electrical connections between the 6s.

[0103] There is no particular limitation on the size of the groove 240 where the semiconductor layer 205 is removed. In order to reliably prevent the generation of a loop, the direction in which the wiring 216_j or the wiring 216_j+1 extends is The distance of the portion where the semiconductor layer in the groove 240 is removed in the perpendicular direction is 1 μm or more. It is preferable that the thickness is 2 μm or more, and more preferable that the thickness is 2 μm or more.

[0104] Next, the method for manufacturing the pixel portion of the liquid crystal display device described with reference to FIG. 1 will be described with reference to FIGS. 9 and 1. 9 and 10, the cross sections A1-A2, J1-J2, and cross section K1-K2 correspond to A1-A2, J1-J2, and K1-K2 in FIGS. 1 and 7. 9 and 10. It should be noted that the explanation of the manufacturing method in FIGS. A structure in which an oxide semiconductor is used for a semiconductor layer will be described. The advantages of using it are as described above.

[0105] First, an insulating layer to be the underlayer 201 is formed on the substrate 200 to a thickness of preferably 50 nm to 300 nm. The substrate 200 is formed to a thickness of 100 nm or more and 200 nm or less. In addition to the micro substrate, a plastic substrate with heat resistance that can withstand the processing temperature of this manufacturing process is also available. Examples of glass substrates include barium borosilicate glass and Uses alkali-free glass substrates such as aluminoborosilicate glass or aluminosilicate glass. In this embodiment, aluminoborosilicate glass is used for the substrate 200.

[0106] The underlayer 201 is made of aluminum nitride, aluminum oxynitride, silicon nitride, silicon oxide, or the like. a layer of one or more insulating layers selected from silicon, silicon oxide nitride, or silicon oxynitride; It can be formed by a layer structure, and has the function of preventing the diffusion of impurity elements from the substrate 200. In this specification, silicon nitride oxide refers to a material containing more oxygen than silicon dioxide. It has a high nitrogen content, and is preferably measured by Rutherford backscattering spectroscopy (RBS). Therford Backscattering Spectrometry and water Hydrogen Forward Scattering (HFS) When measured using a SiO2 sensor, the composition range is 5 atomic % to 30 atomic % of oxygen and 20 atomic % of nitrogen. % or more and 55 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen is 10 atomic % or more and 30 atomic % or less. CVD method, coating method, printing method, etc. can be used as appropriate.

[0107] In this embodiment, the base layer 201 is a stack of silicon nitride and silicon oxide. Specifically, silicon nitride is formed on the substrate 200 to a thickness of 50 nm, and Silicon oxide is formed on the silicon substrate to a thickness of 150 nm.

[0108] Next, a 100% silicon dioxide film is formed on the underlayer 201 by sputtering, vacuum deposition, or plating. The conductive layer is formed to a thickness of 200 nm to 300 nm, preferably 200 nm to 300 nm. A resist mask is formed by a first photolithography process, and a conductive layer is selectively formed. The gate electrode 202, the wiring 203, and the wiring 212 are formed by etching.

[0109] The conductive layer for forming the gate electrode 202, the wiring 203, and the wiring 212 is made of molybdenum (M o), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), Metallic materials such as copper (Cu), chromium (Cr), neodymium (Nd), scandium (Sc) The layer can be formed as a single layer or a multilayer using an alloy material containing these as a main component.

[0110] In this embodiment, a Ti layer having a thickness of 5 nm is formed on the underlayer 201 as a conductive layer. A 250 nm thick Cu layer is then formed on the substrate by a first photolithography process. The conductive layer is selectively etched away to form a gate electrode 202, a wiring 203, and a wiring 212. (See FIG. 9(A)). The formed gate electrode 202, wiring 203, and wiring 212 If the end portion has a tapered shape, the covering property of the insulating layer and the conductive layer to be laminated later is improved, and therefore it is preferable. I wish.

[0111] Unless otherwise specified, the photolithography process referred to in this specification includes a resist mask. a step of forming a resist mask, a step of etching a conductive layer or an insulating layer, and a step of removing the resist mask. It shall be included.

[0112] Next, a gate insulating layer 204 is formed on the gate electrode 202, the wiring 203, and the wiring 212 to a thickness of 50 nm. The thickness of the gate electrode is preferably 100 nm to 600 nm. The insulating layer 204 may be made of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride. Aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride tantalum oxide, gallium oxide, yttrium oxide, lanthanum oxide, hafnium oxide, Hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-introduced hafnium hafnium silicate, hafnium aluminate with nitrogen introduced, etc. can be used. The gate insulating layer 204 can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer A is not limited to a single layer, and may be a laminate of different layers. Silicon nitride layer (SiN y (y>0)) is formed on the gate insulating layer A. A silicon oxide layer (SiO x (x>0) to form a gate insulating layer 204 It is also possible to do so.

[0113] The gate insulating layer 204 can be formed by a sputtering method, a plasma CVD method, or a microwave (e.g. Applying a film formation method such as high density plasma CVD using a frequency of 2.45 GHz It is possible.

[0114] In this embodiment, a stack of silicon nitride and silicon oxide is used as the gate insulating layer 204. Specifically, silicon nitride is formed on the gate electrode 202 to a thickness of 50 nm. Silicon oxide is formed on the silicon dioxide to a thickness of 100 nm.

[0115] The gate insulating layer 204 is made of an insulating material containing the same component as the oxide semiconductor to be formed later. When the gate insulating layer 204 is a stack of different layers, an oxide semiconductor The layer in contact with the oxide semiconductor may be made of an insulating material containing the same kind of component as the oxide semiconductor. The gate insulating layer 204 is compatible with an oxide semiconductor. This is because the state of the interface with the oxide semiconductor can be maintained in a good condition. The term "component" refers to one or more elements selected from the constituent elements of an oxide semiconductor.

[0116] Specifically, the same type of oxide semiconductor that can be used for the gate insulating layer 204 and will be formed later As an insulating material containing the above components, an oxide containing In, Ga, and Zn as an oxide semiconductor layer is When the oxide semiconductor is made of a material, Ga in In, Ga, and Zn, which are elements contained in the oxide semiconductor, is replaced with It is a material in which at least one element selected from elements that become tetravalent cations has been substituted. It is preferable that:

[0117] Examples of elements that become tetravalent cations include Ti, Zr, Hf, and Alternatively, Ge, which is a group 14 element, can be used. The group elements are trivalent cations in In-Ga-Zn oxide semiconductors (hereinafter referred to as IGZO). By substituting Ga, which becomes an ion, the bonding strength with oxygen, which constitutes the oxide semiconductor, is increased. As a result, it is possible to obtain a gate insulating layer 204 having higher insulating properties than IGZO. .

[0118] In addition, the lanthanide cerium (Ce) may also be used as a tetravalent cation. By substituting Ce for Ga, a gate insulating layer 204 having higher insulating properties than IGZO can be obtained. It is possible.

[0119] In addition, an insulating material containing the same component as an oxide semiconductor that can be used for the gate insulating layer 204 When an oxide material containing In, Ga, and Zn is used for the oxide semiconductor layer, The oxide semiconductor contains In, Ga, and Zn, and Ga is replaced with yttrium (Y). Yttrium is less electronegative than Ga, so it is an oxidizer. The electronegativity difference between the oxide and the oxygen can be increased, and the ionic bond with oxygen in the oxide semiconductor can be formed. The gate insulating layer 2 has better insulating properties than IGZO. You can get 04.

[0120] In addition, when the gate insulating layer 204 has a stacked structure, a layer containing the same kind of component as the oxide semiconductor is used. It may have a laminated structure of a film made of an insulating material and a film containing a material different from the component material of the film. .

[0121] In addition, when an oxide semiconductor layer is used as the semiconductor layer, hydrogen, hydroxide, etc. are contained in the oxide semiconductor layer. In order to minimize the inclusion of bases and moisture, a pretreatment for forming the oxide semiconductor layer was performed. The substrate 200 is preheated in a preheating chamber of the sputtering device, and the substrate 200 and the gate insulating film are It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the insulating layer 204. The evacuation means provided in the preheating chamber is preferably a cryopump. This pre-heating can be omitted. The same process may be carried out on the substrate 200 on which the pole 202, the wiring 203, and the wiring 212 are formed. .

[0122] The oxide semiconductor used for the semiconductor layer 205 is at least indium (In) or It is preferable that the alloy contains zinc (Zn). It is particularly preferable that the alloy contains In and Zn. As a stabilizer to reduce variations in the electrical characteristics of transistors that use conductive layers In addition to these, it is preferable to have gallium (Ga). It is preferable to have tin (Sn) as a stabilizer. ) as a stabilizer. It is preferable.

[0123] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0124] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide You can be there.

[0125] The oxide semiconductor layer is preferably an oxide semiconductor containing In, more preferably In, The oxide semiconductor layer is an oxide semiconductor containing Ga. Dehydration or dehydrogenation is effective.

[0126] Here, for example, the In-Ga-Zn oxide is a compound containing indium (In), gallium (Ga ), and zinc (Zn)-containing oxides, regardless of the ratio of In, Ga, and Zn. Furthermore, metal elements other than In, Ga, and Zn may be contained.

[0127] Oxide semiconductors can be in a single crystal, polycrystalline (also called polycrystalline), or amorphous state. Preferably, the oxide semiconductor is CAAC-OS (C Axis Aligned Oxide Semiconductor). Crystalline Oxide Semiconductor).

[0128] CAAC-OS is neither completely single crystalline nor completely amorphous. The oxide semiconductor has a crystalline-amorphous mixed phase structure in which a crystalline portion is present in the amorphous phase. The part is often small enough to fit inside a cube with a side of less than 100 nm. Transmission Electron Microscope (TEM) In the observation image by pe), the boundary between the amorphous and crystalline parts in CAAC-OS is clear. In addition, grain boundaries (also called grain boundaries) were observed in the CAAC-OS by TEM. Therefore, the decrease in electron mobility due to grain boundaries in CAAC-OS is not observed. be suppressed.

[0129] The crystalline part of the CAAC-OS has a c-axis that is perpendicular to the normal vector of the CAAC-OS surface. or parallel to the normal vector of the surface and triangular when viewed from the direction perpendicular to the ab plane. Or it has a hexagonal atomic arrangement, and the metal atoms are layered or metallic when viewed from the direction perpendicular to the c-axis. The a-axis and oxygen atoms are arranged in layers between different crystal parts. The direction of the b axis may be different. In this specification, when simply referring to vertical, it means 85°. Also, when simply describing it as parallel, it means that the angle is less than -5°. This also includes a range of up to 5°.

[0130] In the CAAC-OS, the distribution of the crystal parts does not have to be uniform. In the process of forming an OS, when crystal growth is performed from the surface side of the oxide semiconductor layer, The proportion of crystalline parts near the surface may be higher than that near the bottom. By adding impurities to the -OS, the crystalline portion in the impurity-doped region becomes amorphous. This may also occur.

[0131] The c-axis of the crystalline part of the CAAC-OS is the normal vector of the surface on which the CAAC-OS is formed. The shape of the CAAC-OS (cross section of the surface on which it is formed) is Depending on the surface shape or cross-sectional shape of the surface, the directions may be different from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS is formed or The direction is parallel to the normal vector of the surface. The film is formed by subjecting the film to a crystallization treatment such as heat treatment.

[0132] The electrical characteristics of transistors using CAAC-OS are stable when exposed to visible or ultraviolet light. small.

[0133] Next, sputtering, evaporation, PCVD, PLD, ALD, MBE, etc. The semiconductor layer 205 is formed using the above.

[0134] The semiconductor layer 205 is preferably formed by sputtering at a substrate temperature of 100° C. or higher and 600° C. ° C. or less, preferably 150° C. or more and 550° C. or less, and more preferably 200° C. or more and 500° C. The semiconductor layer 205 is formed in an oxygen gas atmosphere with a thickness of 1 nm to 40 nm. The higher the substrate temperature during film formation, the greater the thickness of the resulting film. The impurity concentration of the semiconductor layer 205 is reduced. In addition, the atomic arrangement in the semiconductor layer 205 is improved. The densification increases, and polycrystals or CAAC-OS tend to form. Since the film is formed by vapor deposition, it does not contain any extra atoms such as rare gases, so it is not polycrystalline or CAA. However, a mixed atmosphere of oxygen gas and rare gas may also be used. In this case, the proportion of oxygen gas is 30% by volume or more, preferably 50% by volume or more, and more preferably The thinner the semiconductor layer 205, the shorter the channel width of the transistor. However, if the thickness is too thin, the influence of interface scattering becomes strong and the field effect migration A decrease in intensity may occur.

[0135] When an In-Ga-Zn oxide material is formed as the semiconductor layer 205 by a sputtering method Preferably, the atomic ratio of In:Ga:Zn is 1:1:1, 4:2:3, 3:1:2, 1 In-Ga-Zn oxide targets shown in :1:2, 2:1:3, or 3:1:4 An In-Ga-Zn oxide target having the above atomic ratio is used. By forming the organic layer 205, polycrystal or CAAC-OS is easily formed.

[0136] In this embodiment, an In-Ga-Zn-based oxide target is used for the oxide semiconductor layer. The oxide semiconductor layer is formed to a thickness of 30 nm by a sputtering method. Typically, under an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas and oxygen. The film can be formed by sputtering.

[0137] Examples of targets for forming an oxide semiconductor layer by sputtering include those having the following composition: As a metal oxide substrate, In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] Using the target, an In-Ga-Zn-O layer is deposited.

[0138] The sputtering gas used in forming the oxide semiconductor layer is hydrogen, water, a hydroxyl group, a hydride, or the like. It is preferable to use a high-purity gas from which impurities such as fluorine and fluorine are removed. When using argon, the purity must be 9N, the dew point must be -121°C, and the H2O content must be 0.1 ppb or less. The H2 content should be 0.5 ppb or less. If oxygen is used, the purity should be 8N and the dew point should be -112. °C, H2O content of 1 ppb or less, and H2 content of 1 ppb or less are preferred.

[0139] The oxide semiconductor layer was formed by holding a substrate in a deposition chamber kept under reduced pressure and raising the substrate temperature to 1000 K. The heating is carried out at a temperature of 00°C or higher and 600°C or lower, preferably 300°C or higher and 500°C or lower.

[0140] By forming the oxide semiconductor layer while heating the substrate, hydrogen and moisture contained in the formed oxide semiconductor layer can be reduced. The concentration of impurities such as hydrides and hydroxides can be reduced. Damage caused by the ring is reduced. Also, residual moisture in the film formation chamber is removed while hydrogen and moisture are removed. A sputtering gas from which the oxide semiconductor layer is removed is introduced, and an oxide semiconductor layer is formed using the target. .

[0141] To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, such as a cryopump, is used. It is preferable to use an ion pump or a titanium sublimation pump. The stage may be a turbomolecular pump with a cold trap added. The deposition chamber is evacuated using a pump, and contains hydrogen atoms, water (H2O), and other gases. Compounds containing carbon atoms (and more preferably compounds containing carbon atoms) are exhausted from the deposition chamber. The concentration of impurities contained in the formed oxide semiconductor layer can be reduced.

[0142] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. , DC power supply power 0.5kW, oxygen as sputtering gas (oxygen flow rate 100%) When a pulsed DC power supply is used, the powder generated during film formation is This is preferable because it reduces the amount of particles and dust and also makes the film thickness distribution uniform.

[0143] Next, first heat treatment is performed. By the first heat treatment, excess SiO 2 in the oxide semiconductor layer is removed. Hydrogen (including water and hydroxyl groups) is removed (dehydration or dehydrogenation) to remove impurities in the oxide semiconductor layer. The concentration of substances can be reduced.

[0144] The first heat treatment is performed under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, or an oxygen gas atmosphere. Ambient or ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy) method) The moisture content measured using a dew point meter is preferably 20 ppm or less (-55°C in dew point equivalent). In an atmosphere of 250°C or more and 750°C or less, preferably 1 ppm or less, and preferably 10 ppb or less, air, The heating is carried out at a temperature of 400°C or lower, or at a temperature of 400°C or higher but lower than the distortion point of the substrate.

[0145] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. is a rare gas such as argon or nitrogen, which does not react with the object to be treated by heat treatment. A suitable inert gas is used.

[0146] For example, in the first heat treatment, the substrate is moved into an inert gas heated to a high temperature, After heating for several minutes, the substrate is moved and taken out of the heated inert gas atmosphere for GRTA. It is also possible.

[0147] Heat treatment is carried out under an atmosphere of inert gas such as nitrogen or rare gas, oxygen, or ultra-dry air. In this case, it is preferable that the atmosphere does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gas introduced into the treatment equipment is preferably 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., 1 ppm or less, preferably It is preferable to keep the concentration below 0.1 ppm.

[0148] The first heat treatment is performed in a reduced pressure atmosphere or an inert atmosphere, and then the temperature is maintained. It is preferable to switch to an oxidizing atmosphere and then further heat treatment. When heat treatment is performed in an inert atmosphere, the impurity concentration in the oxide semiconductor layer can be reduced. However, oxygen vacancies are also generated at the same time. This can be reduced by heat treatment in a chemical atmosphere.

[0149] In this way, the hydrogen concentration is sufficiently reduced to achieve high purity, and oxygen deficiency is prevented by supplying sufficient oxygen. In oxide semiconductors where the defect levels in the energy gap due to carrier depletion are reduced, Concentration is 1×10 12 / cm 3 Less than 1×10 11 / cm 3 Less than, more desirable 1.45 x 10 10 / cm 3 For example, the off-state current ( Here, the value per unit channel width (1 μm) is 100 zA (1 zeptoampere A) is 1 x 10 -21 A) or less, preferably 10zA or less. Also, at 85°C, 100zA(1×10 -19 A) or less, preferably 10zA (1 x 10 -20 A) The following In this way, an i-type (intrinsic) or substantially i-type oxide semiconductor is used. As a result, the transistor 111 can have excellent off-state current characteristics.

[0150] Furthermore, a transistor including a highly purified oxide semiconductor has low threshold voltage, on-state current, and other properties. There is almost no temperature dependency in any of the electrical characteristics. There is little gender variation.

[0151] In this way, the oxide is highly purified and made i-type (intrinsic) by reducing oxygen vacancies. Transistors using compound semiconductors have suppressed fluctuations in electrical characteristics and are electrically stable. Therefore, a highly reliable liquid crystal display device using an oxide semiconductor with stable electrical characteristics can be achieved. can be provided.

[0152] Next, a protective layer 351 is formed on the semiconductor layer 205. The protective layer 351 is a gate insulating layer. It can be formed from the same materials and in the same manner as the edge layer 204 .

[0153] If the protective layer 351 in contact with the semiconductor layer 205 contains a large amount of oxygen, the semiconductor layer 2 It can function as a source of oxygen to supply 05.

[0154] In this embodiment, a silicon oxide layer having a thickness of 200 nm is used as the protective layer 351. Then, a resist mask is formed on the protective layer 351 by a second photolithography process. , a portion of the protective layer 351 on the semiconductor layer 205 is selectively removed, and the openings 301 and 3 9B, the openings 301 and 302 are formed. The shape of the protective layer on the semiconductor layer 205 is a trapezoid or a triangle in cross section. The taper angle θ of the lower end is 60° or less, preferably 45° or less, and more preferably 30° or less. As an example, in this embodiment, silicon oxide is formed by a photolithography process. A resist mask is formed on the layer, and selective etching is performed to define the cross-sectional shape of the protective layer 351. The protective layer 351 has a trapezoidal shape, and the taper angle θ of the lower end portion thereof is set to about 30°.

[0155] After the protective layer 351 is formed, heat treatment may be performed. Heat treatment is carried out at 0°C for 1 hour.

[0156] The protective layer 351 may be made of an insulating material containing the same components as the semiconductor layer 205 . When the protective layer 351 is a laminate of different layers, the layer in contact with the oxide semiconductor is the oxide semiconductor. Such a material has good compatibility with oxide semiconductors. By using this as the protective layer 351, the state of the interface with the oxide semiconductor can be maintained in a good condition. Here, the term "component of the same kind as an oxide semiconductor" refers to a component of an oxide semiconductor. It means one or more elements selected from the elements.

[0157] Specifically, an insulating material containing the same components as an oxide semiconductor that can be used for the protective layer 351 When an oxide material containing In, Ga, and Zn is used for the oxide semiconductor layer, The elements contained in the compound semiconductor are In, Ga, and Zn, and Ga is converted into a tetravalent cation. It is preferable that the material be a material in which at least one element selected from the group consisting of substituted elements is used.

[0158] Examples of elements that become tetravalent cations include Ti, Zr, Hf, and Alternatively, Ge, which is a group 14 element, can be used. The group elements are used to construct oxide semiconductors by substituting Ga, which becomes a trivalent cation in IGZO. This increases the bonding strength with oxygen, resulting in a protective layer with higher insulating properties than IGZO. You can get 351.

[0159] In addition, the lanthanide cerium (Ce) may also be used as a tetravalent cation. By substituting Ce for Ga, a protective layer 351 having higher insulating properties than IGZO can be obtained. It is possible.

[0160] In addition, an insulating material containing the same component as an oxide semiconductor that can be used for the protective layer 351 is In the case where an oxide material containing In, Ga, and Zn is used as the oxide semiconductor layer, The semiconductor contains elements In, Ga, and Zn, and Ga is replaced with yttrium (Y). Yttrium is less electronegative than Ga, so it reacts well with oxygen. The electronegativity difference can be increased, and the electronegativity can be increased by ionic bonding with oxygen in the oxide semiconductor. The bond can be made stronger, and a protective layer 351 having higher insulating properties than IGZO can be obtained. This can be done.

[0161] In addition, when the protective layer 351 has a laminated structure, an insulating material containing the same component as the oxide semiconductor is used. It may also be a laminated structure of a film made of a material and a film containing a material different from the component material of the film.

[0162] The semiconductor exposed by etching to form the openings 301 and 302 is Impurities are likely to adhere to the surface of the layer 205. These impurities include the etchants used in the etching. The elements that make up the etching gas or etching solution, or those present in the processing chamber where etching is performed The impurities include elements such as boron, chlorine, fluorine, and carbon. Examples of suitable materials include silicon and aluminum.

[0163] Next, a cleaning process is performed on the surfaces of the semiconductor layer 205 and the protective layer 351. The cleaning process is performed using TMA. This can be done using an alkaline solution such as H solution, water, or diluted hydrofluoric acid. Alternatively, the cleaning process may be carried out using oxygen, nitrous oxide, or a rare gas (typically argon). The cleaning process can be carried out by a plasma treatment. The impurities attached to the surface of 51 can be removed.

[0164] Dilute hydrofluoric acid is 50% by weight hydrofluoric acid diluted 100 to 100,000 times with water. It is desirable to use diluted hydrofluoric acid for the cleaning process. Impurities adhering to the semiconductor layer 205 can be removed together with a portion of the semiconductor layer 205.

[0165] Next, on the semiconductor layer 205 in the openings 301 and 302 and on the protective layer 351, A conductive layer that will become the first electrode 206A, the second electrode 206B, and the wiring 216 is formed. The conductive layers used for the first electrode 206A, the second electrode 206B, and the wiring 216 are the same as those used for the gate electrode 202. The first electrode 206A and the second electrode 206 can be formed using the same material and method. The conductive layer used for B and the wiring 216 may be formed of a conductive metal oxide. The reactive metal oxides are indium oxide (In2O3), tin oxide (SnO2), and zinc oxide. Lead (ZnO), indium oxide tin oxide (In2O3-SnO2, abbreviated as ITO), Indium oxide zinc oxide (In2O3-ZnO) or these metal oxide materials It is possible to use one containing a recombinant.

[0166] In this embodiment, the semiconductor layer 205 in the openings 301 and 302 and the protective layer 3 A 5 nm thick Ti layer is formed on the substrate 51 as a conductive layer, and a 250 nm thick Cu layer is formed on the Ti layer. Then, a resist mask is formed by a third photolithography process. The conductive layer is selectively etched away to leave the first electrode 206A, the second electrode 206B, and the wiring. 216 is formed (see FIG. 9(C)).

[0167] Next, an insulating film is formed on the first electrode 206A, the second electrode 206B, the protective layer 351, and the wiring 216. The insulating layer 207 is formed on the gate insulating layer 204 or the gate insulating layer 205 (see FIG. 10A). It can be formed using the same material and method as the underlayer 201. The sputtering method is preferable in that the insulating layer 207 is not easily damaged. When the oxide semiconductor layer contains hydrogen, the hydrogen may penetrate into the oxide semiconductor layer or the hydrogen may penetrate into the oxide semiconductor layer. Oxygen extraction may occur, causing the oxide semiconductor layer to have a low resistance (become n-type). It is important that the insulating layer 207 is formed using a method that does not contain hydrogen or impurities containing hydrogen. It is essential.

[0168] The insulating layer 207 is typically made of silicon oxide, silicon oxynitride, hafnium oxide, Inorganic insulating materials such as aluminum oxide and gallium oxide can be used. Since silicon is a material that is difficult to charge, the threshold voltage fluctuation due to charge-up in the insulating layer can be prevented. When an oxide semiconductor is used for the semiconductor layer 205, the insulating layer 207 or a metal oxide containing the same component as the oxide semiconductor, stacked with the insulating layer 207. A layer may be formed.

[0169] In this embodiment, silicon oxide having a thickness of 200 nm is deposited as the insulating layer 207 by sputtering. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide layer is formed by sputtering using a rare gas. (typically argon) atmosphere, oxygen atmosphere, or a mixture of rare gas and oxygen atmosphere The target can be silicon oxide or silicon. For example, silicon can be used as a target and sputtered in an atmosphere containing oxygen. By carrying out the above, silicon oxide can be formed.

[0170] In order to remove the residual moisture in the film-forming chamber during the formation of the insulating layer 207, an adsorption type vacuum pump is used. It is preferable to use a pump (such as a cryopump). The insulating layer 207 formed in the film formation chamber has a reduced concentration of impurities contained therein. In addition, it can be used as an exhaust means for removing residual moisture in the film formation chamber of the insulating layer 207. may be a turbomolecular pump plus a cold trap.

[0171] The sputtering gas used in forming the insulating layer 207 is hydrogen, water, a hydroxyl group, a hydride, or the like. It is preferable to use a high-purity gas from which impurities have been removed.

[0172] Then, the mixture is heated under a reduced pressure, an inert gas atmosphere, an oxygen gas atmosphere, or an ultra-dry air atmosphere. A second heat treatment is carried out under atmospheric pressure (preferably at 200°C or higher and 600°C or lower, for example, at 250°C or higher and 55°C or lower). 0°C or less). However, the first photolithography process or the third photolithography process may be performed. When Al is used in the wiring layer formed by the lithography process, the heat treatment The temperature is set to 380°C or less, preferably 350°C or less, and Cu is used for the wiring layer. In this case, the temperature of the heat treatment is set to 450°C or less. For example, in a nitrogen atmosphere, the temperature is set to 450°C or less. The second heat treatment may be performed for 1 hour. The temperature is raised while a part of the insulating layer 207 (channel formation region) is in contact with the insulating layer 207, and the insulating layer 207 containing oxygen is Oxygen can be supplied from O7 to the semiconductor layer 205. It is preferable that the following are not included.

[0173] Next, a resist mask is formed by a fourth photolithography process, and the second electrode 20 A portion of the insulating layer 207 on the cross section K is selectively removed to form an opening 208. A portion of the insulating layer 207 on the wiring 216 in the 1-K2 cross section is selectively removed to form an opening 22 0 is formed. In addition, on the wiring 212 in the cross section J1-J2, the insulating layer 207, the protective layer The protective layer 351, the semiconductor layer 205, and a portion of the gate insulating layer 204 are selectively removed to form an opening. 219 is formed (see FIG. 10(B)). Although not shown, this photolithography In the etching process, the groove 230 is also formed in the same manner as the opening 219. The insulating layer 207, the protective layer 351, the semiconductor layer 205, and the gate insulating layer 204 are exposed on the side surface. It is being released.

[0174] The insulating layer 207, the protective layer 351, the semiconductor layer 205, and the gate insulating layer 204 are etched as follows: Either dry etching or wet etching may be used, or both may be used. The etching gas used in etching is a gas containing chlorine (chlorine-based gas, for example, chlorine (C l2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4) etc.) can be used.

[0175] As dry etching, parallel plate type RIE (Reactive Ion Etching) ng) method and ICP (Inductively Coupled Plasma) In addition, the underlayer 201 is formed from the substrate 200. In order to prevent the diffusion of impurity elements from the underlayer 2 during the etching, It is preferable to adjust the etching conditions so that O1 is not etched as much as possible. stomach.

[0176] Generally, etching of the semiconductor layer and forming of the openings are performed using different photolithography and etching processes. However, according to the manufacturing process shown in this embodiment, the etching process can be performed in one step. The photolithography and etching processes can be performed simultaneously. This not only reduces the number of photomasks, but also the photolithography process itself. This allows for a reduction in the number of subsequent etching steps. By using a graphic process, a liquid crystal display device can be manufactured at low cost and with high productivity.

[0177] Furthermore, according to the manufacturing process described in this embodiment, a photoresist is directly formed on the oxide semiconductor layer. In addition, the channel formation region of the oxide semiconductor layer is protected by the insulating layer 207. Therefore, the oxide semiconductor layer can be easily removed even in the subsequent photoresist stripping and cleaning process. Since moisture does not adhere to the channel forming region, the characteristics of the transistor 111 are not varied. This reduces noise and improves reliability.

[0178] Next, a pixel electrode 210 is formed on the second electrode 206B in the opening 208 and on the insulating layer 207. The conductive layer that becomes the pixel electrode 210 is formed by sputtering, vacuum deposition, or the like. A light-transmitting conductive layer (also called a transparent conductive layer) is preferably formed to a thickness of 30 nm or more and 200 nm or less. The transistor 111 is formed to a thickness of 50 nm or more and 100 nm or less by the above process. A semiconductor device including the capacitor 113 can be obtained (see FIG. 10C).

[0179] Examples of the light-transmitting conductive layer include indium oxide containing tungsten oxide, tungsten oxide, and Indium zinc oxide containing stainless steel, indium oxide containing titanium oxide, titanium oxide Indium tin oxide (hereinafter referred to as ITO), indium zinc Conductive materials with transparency, such as lead oxide and indium tin oxide with silicon oxide added, are used. It is also possible to use a material consisting of 1 to 10 graphene sheets. good.

[0180] In addition, although the present embodiment has exemplified a method for manufacturing a pixel portion of a transmission type liquid crystal display device, The present invention is not limited to the transmissive type, but can also be applied to the pixel portion of a reflective or semi-transmissive liquid crystal display device. When obtaining a pixel portion of a reflective liquid crystal display device, a conductive layer with high light reflectivity (reflective layer) is used as the pixel electrode. (also called conductive layer), for example, aluminum, titanium, silver, rhodium, nickel, etc. Metals with high reflectivity of visible light, or alloys containing at least one of these metals, or When obtaining a pixel portion of a semi-transmissive liquid crystal display device, one pixel electrode The electrode is formed of a transparent conductive layer and a reflective conductive layer, and has a transmissive portion and a reflective portion.

[0181] In this embodiment, an ITO layer having a thickness of 80 nm is formed as a light-transmitting conductive layer. A resist mask is formed by the photolithography process, and a light-transmitting conductive layer is selected. The pixel electrode 210, the electrode 221, and the electrode 222 are formed by selective etching.

[0182] The pixel electrode 210 is connected to the second electrode 206B through the opening 208. The electrode 222 is connected to the wiring 212 through the opening 219. The electrode 222 is connected to the wiring 216 through the opening 220. is connected to.

[0183] In addition, in the openings 219 and 220 formed in the terminal portions 103 and 104, The wiring 212 and the wiring 216 are not left exposed, but are made of conductive oxide such as ITO. It is important to cover the wiring 212 and wiring 216 with a material. If the wiring 216 and the wiring 216 are left exposed, the exposed surfaces will be oxidized and the connection to the FPC etc. will be difficult. The contact resistance increases. The increase in contact resistance causes delays in the signals input from the outside and distortion of the waveform. This causes external signals to be transmitted imprecisely, resulting in a decrease in the reliability of the semiconductor device. 212 and the exposed surfaces of the wiring 216 are covered with an oxide conductive material such as ITO. An increase in contact resistance can be prevented, and the reliability of the semiconductor device can be improved.

[0184] According to this embodiment, a semiconductor device can be fabricated using fewer photolithography steps than in the past. This makes it possible to manufacture the semiconductor layer at low cost and reduce the deterioration of the semiconductor layer. Therefore, a highly reliable liquid crystal display device can be manufactured with high productivity.

[0185] In this embodiment, a bottom-gate transistor has been described as an example. It is also possible to apply this to transistors with a gate structure.

[0186] This embodiment mode can be freely combined with other embodiment modes.

[0187] (Embodiment 2) In this embodiment, an EL display device in which the number of photomasks and the number of photolithography steps are reduced is provided. An example of a pixel configuration and a manufacturing method of the device will be described with reference to FIGS.

[0188] FIG. 18A illustrates an example of the structure of a semiconductor device 400 used in an EL display device. The device 400 has a pixel region 402 on a substrate 401 and m terminals 404 (m is an integer of 1 or more). 405, and a terminal section 403 having a terminal 407, and n terminals 406 (n is an integer of 1 or more). and a terminal portion 404 having a terminal 408. m wires 512 connected to the terminal section 403, and n wires 516 connected to the terminal section 404, The pixel region 402 has a wiring 503 and a wiring 563. The pixel region 402 has m vertical rows and n horizontal rows. The pixel 410 is arranged in a matrix of rows and columns. 10(i, j) (i is an integer between 1 and m, and j is an integer between 1 and n) is a wiring 512_ Each pixel is connected to a wiring 516_i and a wiring 516_j, which serves as a common electrode. 03, and the wiring 503 is connected to the terminal 407. In addition, each pixel The wiring 563 is connected to the terminal 408. 512_i is connected to the terminal 405_i, and the wiring 516_j is connected to the terminal 406_j. There are.

[0189] The terminals 403 and 404 are external input terminals, and are connected to an externally provided control circuit and an FP. It is connected using a flexible printed circuit (C) or other external A signal supplied from a control circuit provided in the semiconductor device is transmitted to the semiconductor device via terminals 403 and 404. 18A, the terminal portions 403 are connected to the left and right sides of the pixel region 402. The terminal portion 404 is formed on the outside of the pixel, and signals are input from two points. The structure is shown in which signals are input from two points, formed on the upper and lower outer sides of the region 402. By inputting signals from the semiconductor device 400, the signal supply capacity is improved, and the semiconductor device 400 can operate at high speed. In addition, the increase in wiring resistance due to the increase in size and high definition of the semiconductor device 400 In addition, the semiconductor device 400 has redundancy. This makes it possible to improve the reliability of the semiconductor device 400. In FIG. 18(A), the terminal portion 403 and the terminal portion 404 are provided in two locations. , and one each may be provided.

[0190] FIG. 18B shows the circuit configuration of the pixel 410. The pixel 410 includes a first transistor The semiconductor device includes a capacitor 411, a second transistor 412, a capacitor 413, and an EL element 414. The gate electrode of the first transistor 411 is connected to the wiring 512_i. One of the source and drain electrodes (hereinafter referred to as the first electrode) of the transistor 411 is connected to the wiring 5. 16_j. A first electrode of the second transistor 412 is connected to a wiring 563. The other electrode of the source or drain of the second transistor 412 (hereinafter referred to as the second electrode) is connected to The first transistor (hereinafter referred to as the "transistor") is connected to one electrode of the EL element 414. The second electrode of the transistor 411 is connected to the gate electrode of the second transistor 412 and the The other electrode of the capacitor 413 is connected to the wiring 5 The other electrode of the EL element 414 is connected to a wiring 503. The potential of the wiring 503 may be set to a fixed potential such as 0 V, GND, or a common potential. The potential of the line 563 may be set appropriately depending on the amount of current flowing through the EL element.

[0191] The first transistor 411 is connected to the gate electrode of the second transistor 412 via a wiring 516_ j. When a signal that turns on the first transistor 411 is supplied to An image signal from the wiring 516_j is input to the gate electrode of the second transistor 412 and The potential is supplied to one electrode of the capacitor 413 .

[0192] The second transistor 412 receives an image signal held on the gate electrode of the second transistor 412. The second transistor 412 has a function of passing a current according to a signal to the EL element 414. The image signal held in the gate electrode is held between the electrodes of the capacitor element 413. The resistor 412 functions as a current source for supplying a current corresponding to an image signal to the EL element 414. do.

[0193] A semiconductor in which the channels of the first transistor 411 and the second transistor 412 are formed The layer can be made of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like. Examples of semiconductor materials include silicon, germanium, silicon germanium, Examples of the material include silicon carbide and gallium arsenide. The display device has a structure in which the semiconductor layer remains in the pixel region, so that the display device using the semiconductor When the device is used as a transmissive display device, the semiconductor layer should be made as thin as possible to allow visible light It is preferable to increase the transmittance of the

[0194] Also, the channels of the first transistor 411 and the second transistor 412 are formed. The semiconductor layer is preferably made of an oxide semiconductor. The gap is large at 3.0 eV or more, and the transmittance to visible light is high. In a transistor obtained by processing under appropriate conditions, the off-state current is At temperatures below 25°C (for example, 100 ΩA (1 × 10 -19 A) or less, or 10z A(1×10 -20 A) or less, and even 1zA (1×10 -21 A) The following can be done: Therefore, the gate electrode of the second transistor 412 can be This allows the potential applied to be maintained.

[0195] The first transistor 411 and the second transistor 412 are both n-channel transistors. Although the transistor will be described, it may be a p-channel transistor.

[0196] The capacitor 413 holds the image signal supplied to the gate electrode of the second transistor 412. Although the capacitor 413 is not necessarily provided, By providing the first transistor 411, when the first transistor 411 is in an off state, the first electrode and the second electrode The current flowing between the electrodes (off-state current) is applied to the gate electrode of the second transistor 412. Fluctuations in the obtained potential can be suppressed.

[0197] The EL element 414 is turned on in response to the amount of current flowing between the first electrode and the second electrode of the second transistor 412. The EL element 414 has one electrode serving as an anode and the other electrode serving as a cathode. The structure is such that an EL layer is sandwiched between the other electrode.

[0198] Next, an example of the configuration of the pixel 410 shown in FIG. 18 will be described with reference to FIGS. 13 and 14. FIG. 13 is a top view showing the planar configuration of the pixel 410, and FIG. 14 is a top view showing the stacked structure of the pixel 410. 13. It should be noted that A1-A2, B1-B2, C1-C2, and D in FIG. The dashed lines A1-A2 and B1-D2 indicate the cross sections A1-A2 and B1-D2 in FIGS. 14(A) to 14(D). B2, corresponds to section C1-C2, and section D1-D2.

[0199] The first transistor 411 and the second transistor 412 shown in this embodiment are arranged at equal intervals. The first electrode 506A and the second electrode 506B, and the first electrode 546A and the second electrode 546B, which face each other, The first electrode 506A and the second electrode 506B are shaped like the first electrode 506A and the second electrode 506B. The electrode 546A and the second electrode 546B may have other shapes. For example, , the second electrode 546B is connected to the first electrode 546A in a U-shape (C-shape, U-shape, or horseshoe shape). It is also possible to enclose the shape.

[0200] In addition, the semiconductor device described in this embodiment mode is formed with island-shaped semiconductor layers to simplify the process. Since no photolithography process or etching process is performed to form the entire pixel region 402, As a result, the semiconductor layer 505 remains (not shown in FIG. 13). functions as a gate electrode, and the wiring 516_j functions as one of a source electrode and a drain electrode. The first parasitic transistor functions as a source electrode or a drain electrode, and the wiring 563 functions as the other of the source electrode and the drain electrode. A transistor is created.

[0201] The gate electrode 542 of the second transistor 412 functions as a gate electrode. The electrode 506B functions as either a source electrode or a drain electrode, and the wiring 563 is connected to the source electrode. A second parasitic transistor is created which acts as the other of the pole or drain electrodes.

[0202] The gate electrode 542 functions as a gate electrode, and the wiring 563 functions as a source electrode or a drain electrode. The second electrode 546B functions as one of the source and drain electrodes. A third parasitic transistor acts as a

[0203] The parasitic transistor is formed by a first transistor 411 and a second transistor 412. A channel is formed in the remaining semiconductor layer outside the region where the transistor is to be formed. It is a star.

[0204] In addition, the gate electrode 542 of the second transistor 412 overlaps with the wiring 563, thereby The capacitor 413 is formed.

[0205] In the configuration of this embodiment, the photolithography process and etching process for forming the island-shaped semiconductor layer are performed. By omitting the etching process, damage to the semiconductor layer can be reduced, and deterioration of the semiconductor layer can be prevented. can be reduced.

[0206] The first parasitic transistor is connected to the wiring 512_i to turn on the first transistor 411. When a potential is supplied to the first parasitic transistor, the first parasitic transistor also turns on.

[0207] When the first parasitic transistor is turned on, the wiring 516_j and the wiring 563 are electrically connected. The first parasitic transistor electrically connects the wiring 516_j and the wiring 563. When the wiring 563 is properly connected, the current flowing from the wiring 563 to the wiring 516_j causes the image signal to be transmitted inaccurately. As a result, the potential supplied to the gate electrode 542 does not have the desired value.

[0208] The second parasitic transistor has a potential based on an image signal supplied to the gate electrode 542. As a result, a channel is formed in the semiconductor layer 505 overlapping the gate electrode 542, and a second parasitic The transistor is turned on.

[0209] When the second parasitic transistor is turned on, the second electrode 506B and the wiring 563 are electrically connected. The second electrode 506B and the wiring 563 are connected by the second parasitic transistor. When electrically connected, the image signal held in the gate electrode 542 is transferred by the second electrode 506B. becomes inaccurate, and the potential held at the gate electrode 542 is not the desired value.

[0210] The third parasitic transistor has a potential based on an image signal supplied to the gate electrode 542. As a result, a channel is formed in the semiconductor layer 505 overlapping the gate electrode 542, and a third parasitic The transistor is turned on.

[0211] When the third parasitic transistor is turned on, the wiring 563 and the second electrode 546B are electrically connected. The third parasitic transistor connects the wiring 563 and the second electrode 546B. When electrically connected, the amount of current flowing through the second transistor 412 is determined according to an image signal. The flow rate will be reduced, and the EL element 414 will not be able to emit light with the desired brightness.

[0212] Therefore, in this embodiment, a groove portion 530 is provided in the pixel 410 by removing the semiconductor layer 505. The groove 530 is formed to have a width equal to the width of the wiring 512_i, so that the parasitic transistor described above does not occur. By providing the wiring so as to cross over both ends of the direction, the generation of the first parasitic transistor can be prevented. This can be done.

[0213] The groove 530 is formed in a direction parallel to the direction in which the wiring 516_j or the wiring 563 extends. Therefore, by providing the gate electrode 542 so as to cross over both ends in the line width direction, the second The generation of the parasitic transistor and the third parasitic transistor can be prevented. The grooves 530 on the gate electrodes 542 and the grooves 530 on the gate electrodes 542 are each provided in plural. That's fine.

[0214] There is no particular limitation on the size of the groove 530 where the semiconductor layer 505 is removed. In order to reliably prevent the generation of a resistor, the direction perpendicular to the direction in which the wiring 516_j or the wiring 563 extends is The distance of the portion of the groove 530 where the semiconductor layer is removed in the direction of the groove 530 is set to 1 μm or more. It is preferable that the thickness is 2 μm or more, and it is more preferable that the thickness is 2 μm or more.

[0215] In addition, the first transistor 411 and the second transistor 412 of this embodiment are semiconductor A protective layer 651 is provided on the semiconductor layer 505 to reduce deterioration of the semiconductor layer 505. In particular, in this embodiment, an opening 60 is formed in a part of the protective layer 651 on the semiconductor layer 505. 1 and an opening 602 are provided, and the semiconductor layer 505, the first electrode 506A, and the second electrode 506B are In addition, an opening 6 is formed in a part of the protective layer 651 on the semiconductor layer 505. 6 and an opening 607 are provided, and the semiconductor layer 505, the first electrode 546A, and the second electrode 546B Therefore, a part of the semiconductor layer 505 is connected to the During the etching process, the first electrode 506A, the second electrode 506B, the first electrode 546A, and 2. Exposure to etching gas or etching solution during the etching process of electrode 546B This can reduce deterioration of the semiconductor layer 505.

[0216] In the layout of the pixel 410 shown in FIG. 13, the openings 601, 602, and 603 are 6 and the opening 607 are OPC (Optical Proximity Correlation) It is preferable to process the pattern using a photomask with optical proximity correction. The first electrode 506A and the second electrode 506B of the transistor 411 are connected to the semiconductor layer 505. 6, an opening 601 and an opening 602 for forming a first electrode 546A of the second transistor 412; and an opening 606 and an opening 60 for connecting the second electrode 546B and the semiconductor layer 505. By forming the 7 with a photomask using OPC, the change in the shape of the opening due to the diffraction of light can be prevented. This suppresses the shape of the transistor and reduces the variations in the channel width and length of each transistor. Cut.

[0217] The cross section A1-A2 shows a stacked structure of a first transistor 411 and a second transistor 412. The first transistor 411 and the second transistor 412 are bottom gate The cross section B1-B2 includes the EL element 414 and the groove 530. , the laminated structure from the wiring 516_j to the wiring 563 is shown. 5 shows the groove 530 and the laminated structure at the intersection of the wiring 563 and the wiring 512_i. The cross section D1-D2 shows the wiring 563 and the gate electrode 542 of the second transistor 412. 1 shows the laminated structure at the intersection of

[0218] In the cross section A1-A2 shown in FIG. 14(A), a base layer 501 is formed on a substrate 500, A gate electrode 502 and a gate electrode 542 are formed on the base layer 501. A gate insulating layer 504 and a semiconductor layer 505 are formed on the gate electrode 502 and the gate electrode 542. A protective layer 651 is formed on the semiconductor layer 505. 51, a first electrode 506A, a second electrode 506B, a first electrode 546A, and a second electrode 54 The semiconductor layer 505 is formed through the opening 601 and the protective layer 651. The opening 602 is connected to the first electrode 506A and the second electrode 506B. The layer 505 is formed by openings 606 and 607 in the protective layer 651, and the first electrode 54 is exposed therethrough. 6A and the second electrode 546B. on the electrode 506A, on the second electrode 506B, on the first electrode 546A, and on the second electrode 546B, An insulating layer 507 is formed. One electrode of the EL element 414 is formed on the insulating layer 507. The electrode 510 is formed on the insulating layer 507. The wiring 513 is formed on the insulating layer 507. The opening 603, a part of the gate insulating layer 504, a part of the semiconductor layer 505, and the protective layer 651 The second electrode 506B and the gate electrode 506C are exposed in an opening 604 where a part of the insulating layer 507 and a part of the insulating layer 507 are removed. Also, a part of the electrode 510, the wiring 513, the insulating layer 507 A partition wall layer 514 is formed on the electrode 51 to separate the EL layers into different colors. An EL layer 562 is formed on the EL layer 560 in an opening provided in the partition layer 514. The other electrode 54 of the EL element 414, which is part of the wiring 503, is provided on the partition wall layer 514. 4 is provided. The region where the electrode 510, the EL layer 562, and the electrode 544 are stacked is , becomes the EL element 414.

[0219] In the cross section B1-B2 shown in FIG. 14(B), a base layer 501 is formed on a substrate 500, A gate insulating layer 504 is formed on the base layer 501, and a semiconductor layer 50 is formed on the gate insulating layer 504. A protective layer 651 is formed on the semiconductor layer 505. 1, a wiring 516_j and a wiring 563 are formed, and a protective layer 651 and the wiring 516_j and An insulating layer 507 is formed on the wiring 563. An electrode 510 is formed on the insulating layer 507. In addition, EL layers are painted in different colors on a part of the electrode 510 and on the insulating layer 507. A barrier layer 514 is formed on the electrode 510. An EL layer 562 is formed in the opening. The electrode 510, the EL layer 562, and the electrode 544 are stacked. An EL element 414 is formed.

[0220] Between the wiring 563 and the electrode 510, a part of the gate insulating layer 504, a part of the semiconductor layer 505, and a protective layer A groove 530 is formed by removing a part of the protective layer 651 and a part of the insulating layer 507. The groove 530 is configured so that at least its bottom surface does not have a semiconductor layer.

[0221] In the cross section C1-C2 shown in FIG. 14(C), a base layer 501 is formed on a substrate 500, A wiring 512_i is formed on the base layer 501. A gate electrode 512_i is formed on the wiring 512_i. An insulating layer 504 and a semiconductor layer 505 are formed. A protective layer 6 is formed on the semiconductor layer 505. 51 is formed on the protective layer 651. Also, a wiring 563 is formed on the protective layer 651. An insulating layer 507 is formed. A partition layer 514 is formed on the insulating layer 507. An electrode 544 is provided on the partition layer 514. In addition, a part of the gate insulating layer 504 A groove portion 5 is formed by removing a part of the conductor layer 505, a part of the protective layer 651, and a part of the insulating layer 507. 30 is formed.

[0222] In the cross section D1-D2 shown in FIG. 14(D), a base layer 501 is formed on a substrate 500, A gate electrode 542 is formed on the base layer 501. A protective insulating layer 504 and a semiconductor layer 505 are formed on the semiconductor layer 505. An opening 605 is formed in the protective layer 651. A wiring 563 is formed on the semiconductor layer 505 of 05, and an insulating layer 507 is formed on the wiring 563. In addition, a partition layer 514 is formed on the insulating layer 507, and an electrode is formed on the partition layer 514. A pole 544 is provided.

[0223] The gate electrode 542 and the wiring 563 are overlapped with the gate insulating layer 504 and the semiconductor layer 505 sandwiched therebetween. The portion where the gate insulating layer 504 and the semiconductor layer 505 are formed functions as a capacitor element 413. The dielectric layer formed between the gate electrode 542 and the wiring 563 functions as a dielectric layer. By using a multi-layer structure, even if a pinhole occurs in one dielectric layer, the pinhole is not dissipated in the other dielectric layers. Since the oxide layer is coated on the capacitor element 413, the capacitor element 413 can function normally. Since the relative dielectric constant of a semiconductor is as high as 14 to 16, an oxide semiconductor is used for the semiconductor layer 505. Then, the capacitance value of the capacitor 413 can be increased.

[0224] Next, examples of pixel configurations different from the configuration shown in FIG. 13 will be explained using FIGS. 15 and 16. FIG. 15 is a top view showing the planar configuration of the pixel 420. The cross sections E1-E2, F1-F2, and G1-G2 shown in (C) are the same as the cross sections E1-E2, F1-F2, and G1-G2 shown in FIG. This corresponds to the cross section of the area indicated by the dashed lines -E2, F1-F2, and G1-G2. The pixel 420 differs from the pixel 410 shown in FIG. 13 in the configuration of the groove 530.

[0225] The pixel 420 has a groove 530 between the wiring 516_j and the electrode 510, and between the wiring 516_j and the electrode 510. The trench is provided between the gate electrode 502 of the first transistor 411. The portion 530 is also provided in the region between the gate electrode 502 and the electrode 510 of the first transistor 411. In this way, by arranging many grooves 530, the parasitic transistor This makes it possible to more reliably prevent the formation of bubbles.

[0226] Next, an example of a pixel configuration different from the configurations shown in FIGS. 13 to 16 will be described with reference to FIG. 17. 17 is a top view showing the planar configuration of pixel 430.

[0227] The pixel 430 shown in FIG. 17 has a plurality of grooves that cross over both ends of the wiring 512_i in the line width direction. By providing a number of wirings, the influence of the parasitic channel formed by overlapping with the wiring 512_i can be more reliably suppressed. 1 shows an example of a pixel configuration that suppresses

[0228] In the pixel 430, the grooves 551 and 552 where the semiconductor layer 505 has been removed are connected to the wiring 512 The wiring 512_i is provided so as to extend across both ends of the wiring 512_i in the line width direction. By providing a plurality of grooves that cross over both ends, the adjacent wiring 512_i is formed to overlap with the wiring 512_i. The influence of the live channel can be more reliably suppressed.

[0229] The pixel 430 also includes grooves 553, 554, and 555 where the semiconductor layer 505 has been removed. 5 is provided so as to cross over both ends of the gate electrode 542 in the line width direction. By providing a plurality of grooves that cross over both ends of the electrode 542 in the line width direction, the gate electrode 54 This makes it possible to more reliably suppress the influence of the parasitic channel formed by overlapping with 2.

[0230] Next, an example of the configuration of the terminal 405 and the terminal 406 will be described with reference to FIG. 19A1) and 19A2) respectively show a top view and a cross-sectional view of the terminal 405. The chain line J1-J2 in FIG. 19(A1) corresponds to the cross section J1-J2 in FIG. 19(A2). 19(B1) and 19(B2) are a top view and a cross-sectional view of the terminal 406, respectively. The chain line K1-K2 in FIG. 19(B1) is the same as the chain line K1-K2 in FIG. 19(B2). In addition, in the cross section J1-J2 and the cross section K1-K2, 2 and K2 correspond to the substrate edges.

[0231] In the cross section J1-J2, an underlayer 501 is formed on a substrate 500, and a semiconductor device is disposed on the underlayer 501. A wiring 512 is formed on the gate insulating layer 504 and the semiconductor layer 505. 5, a protective layer 651 and an insulating layer 507 are formed. An electrode 521 is formed on the insulating layer 507. The electrode 521 is formed by the gate insulating layer 504, the semiconductor layer 505, the protective layer 651, and the insulating layer 522. It is connected to the wiring 512 through an opening 519 formed in the layer 507 .

[0232] In the cross section K1-K2, a substrate 500 is provided with an underlayer 501, a gate insulating layer 504, a semiconductor A layer 505 and a protective layer 651 are formed on the insulating layer 505. A wiring 516 is formed on the protective layer 651. An insulating layer 507 is formed on the wiring 516. An electrode 522 is formed on the insulating layer 507. The electrode 522 is connected to the wiring 516 through an opening 520 formed in the insulating layer 507. are.

[0233] The configuration of the terminal 407 may be the same as that of the terminal 405 or the terminal 406. do.

[0234] The pixel region 402 and the terminal section 404 are connected by n wires 516. In the routing of the wiring 516 from 402 to the terminal 406 of the terminal portion 404 When the adjacent wirings 516 are close to each other, the potential difference between the adjacent wirings 516 A parasitic channel is formed in the semiconductor layer 505 between the adjacent wirings 516. There is a risk that 16 may be electrically connected to each other.

[0235] This phenomenon occurs throughout the entire region from the pixel region 402 to the terminal region 404 through the insulating layer. Alternatively, a conductive layer is provided between the adjacent wirings 516, and the potential of the conductive layer is applied to the semiconductor layer 505. This can be prevented by setting the potential at which no parasitic channel is formed.

[0236] For example, when an oxide semiconductor is used for the semiconductor layer 505, most oxide semiconductors have an n-channel Since the potential of the conductive layer is set to a potential lower than the potential supplied to the wiring 516, It should be left as that.

[0237] In the groove forming step described below, the semiconductor layer 505 between the adjacent wirings 516 is By removing the wirings 516, electrical connection between adjacent wirings 516 can also be prevented.

[0238] As shown in FIG. 20, a groove 540 is formed between adjacent wirings 516, and the semiconductor layer 505 is removed. 20A is a top view showing the planar configuration of the wiring 516 connected to the terminal 406. The cross section L1-L2 shown in FIG. 20(B) is taken along the chain line L1-L2 in FIG. 20(A). In FIG. 20A, the wiring 516_j corresponds to the cross section of the portion indicated by the arrow. , the wiring 516_j+1 is connected to the terminal 406_j+1, and the wiring 516_j+2 is connected to the terminal 406_j+2. The groove 540 is formed in the same manner as the groove 530. It is possible.

[0239] A groove portion where the semiconductor layer 505 is removed is formed between the adjacent wirings 516_j and 516_j+1. 540 is formed. In addition, between the adjacent wiring 516_j+1 and wiring 516_j+2 In this way, a groove 540 is formed by removing the semiconductor layer 505. By providing a groove 540 where the semiconductor layer 505 is removed between the lines 516, the adjacent wiring 51 This prevents electrical connections between the 6s.

[0240] There is no particular limitation on the size of the groove 540 where the semiconductor layer 505 is removed. In order to reliably prevent the generation of a loop, the direction in which the wire 516_j or the wire 516_j+1 extends is The distance of the portion where the semiconductor layer in the groove 540 is removed in the perpendicular direction is 1 μm or more. It is preferable that the thickness is 2 μm or more, and more preferable that the thickness is 2 μm or more.

[0241] Next, the method for manufacturing the pixel portion of the EL display device described with reference to FIG. 13 will be described with reference to FIGS. The following description will be made with reference to Fig. 22. Note that the cross sections A1-A2 and J1- J2 and the cross section K1-K2 correspond to A1-A2, J1-J2, and 21 and 22 are cross-sectional views of the portion indicated by the chain line K1-K2. In the description, a structure in which an oxide semiconductor is used for a semiconductor layer will be particularly described. The advantages of using the semiconductor layer are as described above.

[0242] First, an insulating layer to be the underlayer 501 is formed on the substrate 500 to a thickness of preferably 50 nm to 300 nm. The substrate 500 is formed to a thickness of 100 nm or more and 200 nm or less. In addition to the micro substrate, a plastic substrate with heat resistance that can withstand the processing temperature of this manufacturing process is also available. Examples of glass substrates include barium borosilicate glass and Uses alkali-free glass substrates such as aluminoborosilicate glass or aluminosilicate glass. In this embodiment, aluminoborosilicate glass is used for the substrate 500.

[0243] The underlayer 501 is made of aluminum nitride, aluminum oxynitride, silicon nitride, silicon oxide, or the like. a layer of one or more insulating layers selected from silicon, silicon oxide nitride, or silicon oxynitride; It can be formed by a layer structure, and has the function of preventing diffusion of impurity elements from the substrate 500. In this specification, silicon nitride oxide refers to a material containing more oxygen than silicon dioxide. High in nitrogen, preferably as measured by RBS and HFS The composition range is 5 atomic % to 30 atomic % of oxygen, and 20 atomic % to 55 atomic % of nitrogen. %, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen is 10 atomic % or more and 30 atomic % or less The underlayer 501 is formed by a method such as sputtering, CVD, or coating. , printing methods, etc. can be used as appropriate.

[0244] In this embodiment, the base layer 501 is a stack of silicon nitride and silicon oxide. Specifically, silicon nitride is formed on the substrate 500 to a thickness of 50 nm, and Silicon oxide is formed on the silicon substrate to a thickness of 150 nm.

[0245] Next, a 100% silicon dioxide film is formed on the underlayer 501 by sputtering, vacuum deposition, or plating. The conductive layer is formed to a thickness of 200 nm to 300 nm, preferably 200 nm to 300 nm. A resist mask is formed by a first photolithography process, and a conductive layer is selectively formed. The gate electrode 502, the gate electrode 542, and the wiring 512 are formed.

[0246] The conductive layer for forming the gate electrode 502, the gate electrode 542, and the wiring 512 is made of molybdenum. Mo, titanium (Ti), tungsten (W), tantalum (Ta), aluminum (A l), copper (Cu), chromium (Cr), neodymium (Nd), scandium (Sc), and other metals It can be formed as a single layer or a laminate using a material or an alloy material containing these as the main component. do.

[0247] In this embodiment, a Ti layer having a thickness of 5 nm is formed on the base layer 501 as a conductive layer. A 250 nm thick Cu layer is then formed on the substrate by a first photolithography process. The conductive layer is selectively etched away to form the gate electrode 502, the gate electrode 542, and the wiring 512. (See FIG. 21(A)). The formed gate electrode 502 and gate electrode 54 2. If the end of the wiring 512 is tapered, the covering properties of the insulating layer and the conductive layer to be laminated later are improved. This is preferable because it improves the

[0248] Unless otherwise specified, the photolithography process referred to in this specification includes a resist mask. a step of forming a resist mask, a step of etching a conductive layer or an insulating layer, and a step of removing the resist mask. It shall be included.

[0249] Next, a gate insulating layer 504 is formed on the gate electrode 502, the gate electrode 542, and the wiring 512. The thickness is 0 nm or more and 800 nm or less, preferably 100 nm or more and 600 nm or less. The gate insulating layer 504 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Silicon, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide Aluminum, tantalum oxide, gallium oxide, yttrium oxide, lanthanum oxide, hafnium oxide Hafnium, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen was introduced Hafnium silicate, hafnium aluminate with nitrogen introduced, etc. can be used. The gate insulating layer can be formed by a plasma CVD method, a sputtering method, or the like. 504 is not limited to a single layer and may be a laminate of different layers. For example, as the gate insulating layer A, Silicon nitride layer (SiN y (y>0)) is formed on the gate insulating layer A. A silicon oxide layer (SiO x (x>0)) to form a gate insulating layer It can also be 504.

[0250] The gate insulating layer 504 can be formed by a sputtering method, a plasma CVD method, or a microwave (e.g. Applying a film formation method such as high density plasma CVD using a frequency of 2.45 GHz It is possible.

[0251] In this embodiment, a stack of silicon nitride and silicon oxide is used as the gate insulating layer 504. Specifically, silicon nitride is deposited on the gate electrode 502 and the gate electrode 542 to a thickness of 50 nm. A silicon nitride film is formed to a thickness of 100 nm, and silicon oxide is formed on the silicon nitride film to a thickness of 100 nm.

[0252] The gate insulating layer 504 is made of an insulating material containing the same component as the oxide semiconductor to be formed later. When the gate insulating layer 504 is formed by stacking different layers, an oxide semiconductor The layer in contact with the oxide semiconductor may be made of an insulating material containing the same kind of component as the oxide semiconductor. The gate insulating layer 504 is compatible with an oxide semiconductor. This is because the state of the interface with the oxide semiconductor can be maintained in a good condition. The term "component" refers to one or more elements selected from the constituent elements of an oxide semiconductor.

[0253] Specifically, the same type of oxide semiconductor that can be used for the gate insulating layer 504 and will be formed later As an insulating material containing the above components, an oxide containing In, Ga, and Zn as an oxide semiconductor layer is When the oxide semiconductor is made of a material, Ga in In, Ga, and Zn, which are elements contained in the oxide semiconductor, is replaced with It is a material in which at least one element selected from elements that form tetravalent cations has been substituted. It is preferable that:

[0254] Examples of elements that become tetravalent cations include Ti, Zr, Hf, and Alternatively, Ge, which is a group 14 element, can be used. The group elements are used to construct oxide semiconductors by substituting Ga, which becomes a trivalent cation in IGZO. This increases the bonding strength with oxygen, resulting in a gate with higher insulating properties than IGZO. An insulating layer 504 can be obtained.

[0255] In addition, the lanthanide cerium (Ce) may also be used as a tetravalent cation. By substituting Ce for Ga, a gate insulating layer 504 having higher insulating properties than IGZO can be obtained. It is possible.

[0256] In addition, an insulating material containing the same component as an oxide semiconductor that can be used for the gate insulating layer 504 When an oxide material containing In, Ga, and Zn is used for the oxide semiconductor layer, The oxide semiconductor contains In, Ga, and Zn, and Ga is replaced with yttrium (Y). Yttrium is less electronegative than Ga, so it is an oxidizer. The electronegativity difference between the oxide and the oxygen can be increased, and the ionic bond with oxygen in the oxide semiconductor can be formed. The gate insulating layer 5 has better insulating properties than IGZO. You can get 04.

[0257] In addition, when the gate insulating layer 504 has a stacked structure, a layer containing the same kind of component as the oxide semiconductor may be formed. It may have a laminated structure of a film made of an insulating material and a film containing a material different from the component material of the film. .

[0258] In addition, when an oxide semiconductor layer is used as the semiconductor layer, hydrogen, hydroxide, etc. are contained in the oxide semiconductor layer. In order to minimize the inclusion of bases and moisture, a pretreatment for forming the oxide semiconductor layer was performed. The substrate 500 is preheated in a preheating chamber of the sputtering device, and the substrate 500 and the gate insulating film are It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the edge layer 504. The evacuation means provided in the preheating chamber is preferably a cryopump. This pre-heating can be omitted. The same process is carried out on the substrate 500 on which the electrode 502, the gate electrode 542, and the wiring 512 are formed. Good too.

[0259] The oxide semiconductor used for the semiconductor layer 505 is at least indium (In) or It is preferable that the alloy contains zinc (Zn). It is particularly preferable that the alloy contains In and Zn. As a stabilizer to reduce variations in the electrical characteristics of transistors that use conductive layers In addition to these, it is preferable to have gallium (Ga). It is preferable to have tin (Sn) as a stabilizer. ) as a stabilizer. It is preferable.

[0260] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0261] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide You can be there.

[0262] The oxide semiconductor layer is preferably an oxide semiconductor containing In, more preferably In, The oxide semiconductor layer is an oxide semiconductor containing Ga. Dehydration or dehydrogenation is effective.

[0263] Here, for example, the In-Ga-Zn oxide is a compound containing indium (In), gallium (Ga ), and zinc (Zn)-containing oxides, regardless of the ratio of In, Ga, and Zn. Furthermore, metal elements other than In, Ga, and Zn may be contained.

[0264] Oxide semiconductors can be in a single crystal, polycrystalline (also called polycrystalline), or amorphous state. Preferably, the oxide semiconductor is CAAC-OS (C Axis Aligned Oxide Semiconductor). Crystalline Oxide Semiconductor).

[0265] CAAC-OS is neither completely single crystalline nor completely amorphous. The oxide semiconductor has a crystalline-amorphous mixed phase structure in which a crystalline portion is present in the amorphous phase. The part is often small enough to fit inside a cube with a side of less than 100 nm. Transmission Electron Microscope (TEM) In the observation image by pe), the boundary between the amorphous and crystalline parts in CAAC-OS is clear. In addition, grain boundaries (also called grain boundaries) were observed in the CAAC-OS by TEM. Therefore, the decrease in electron mobility due to grain boundaries in CAAC-OS is not observed. be suppressed.

[0266] The crystalline part of the CAAC-OS has a c-axis that is perpendicular to the normal vector of the CAAC-OS surface. or parallel to the normal vector of the surface and triangular when viewed from the direction perpendicular to the ab plane. Or it has a hexagonal atomic arrangement, and the metal atoms are layered or metallic when viewed from the direction perpendicular to the c-axis. The a-axis and oxygen atoms are arranged in layers between different crystal parts. The direction of the b axis may be different. In this specification, when simply referring to vertical, it means 85°. Also, when simply describing it as parallel, it means that the angle is less than -5°. This also includes a range of up to 5°.

[0267] In the CAAC-OS, the distribution of the crystal parts does not have to be uniform. In the process of forming an OS, when crystal growth is performed from the surface side of the oxide semiconductor layer, The proportion of crystalline parts near the surface may be higher than that near the bottom. By adding impurities to the -OS, the crystalline portion in the impurity-doped region becomes amorphous. This may also occur.

[0268] The c-axis of the crystalline part of the CAAC-OS is the normal vector of the surface on which the CAAC-OS is formed. The shape of the CAAC-OS (cross section of the surface on which it is formed) is Depending on the surface shape or cross-sectional shape of the surface, the directions may be different from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS is formed or The direction is parallel to the normal vector of the surface. The film is formed by subjecting the film to a crystallization treatment such as heat treatment.

[0269] The electrical characteristics of transistors using CAAC-OS are stable when exposed to visible or ultraviolet light. small.

[0270] Next, sputtering, evaporation, PCVD, PLD, ALD, MBE, etc. The semiconductor layer 505 is formed using the above.

[0271] The semiconductor layer 505 is preferably formed by sputtering at a substrate temperature of 100° C. or higher and 600° C. or higher. ° C. or less, preferably 150° C. or more and 550° C. or less, and more preferably 200° C. or more and 500° C. The semiconductor layer 505 is formed in an oxygen gas atmosphere with a thickness of 1 nm to 40 nm. The higher the substrate temperature during film formation, the greater the thickness of the resulting film. The impurity concentration of the semiconductor layer 505 is reduced. In addition, the atomic arrangement in the semiconductor layer 505 is improved. The densification increases, and polycrystals or CAAC-OS tend to form. Since the film is formed by vapor deposition, it does not contain any extra atoms such as rare gases, so it is not polycrystalline or CAA. However, a mixed atmosphere of oxygen gas and rare gas may also be used. In this case, the proportion of oxygen gas is 30% by volume or more, preferably 50% by volume or more, and more preferably The thinner the semiconductor layer 505, the shorter the channel width of the transistor. However, if the thickness is too thin, the influence of interface scattering becomes strong and the field effect migration A decrease in intensity may occur.

[0272] When an In-Ga-Zn oxide material is formed as the semiconductor layer 505 by sputtering, Preferably, the atomic ratio of In:Ga:Zn is 1:1:1, 4:2:3, 3:1:2, 1 In-Ga-Zn oxide targets shown in :1:2, 2:1:3, or 3:1:4 An In-Ga-Zn oxide target having the above atomic ratio is used. By forming the organic layer 505, polycrystal or CAAC-OS is easily formed.

[0273] In this embodiment, an In-Ga-Zn-based oxide target is used for the oxide semiconductor layer. The oxide semiconductor layer is formed to a thickness of 30 nm by a sputtering method. Typically, under an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas and oxygen. The film can be formed by sputtering.

[0274] Examples of targets for forming an oxide semiconductor layer by sputtering include those having the following composition: As a metal oxide substrate, In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] Using the target, an In-Ga-Zn-O layer is deposited.

[0275] The sputtering gas used in forming the oxide semiconductor layer is hydrogen, water, a hydroxyl group, a hydride, or the like. It is preferable to use a high-purity gas from which impurities such as fluorine and fluorine are removed. When using argon, the purity must be 9N, the dew point must be -121°C, and the H2O content must be 0.1 ppb or less. The H2 content should be 0.5 ppb or less. If oxygen is used, the purity should be 8N and the dew point should be -112. °C, H2O content of 1 ppb or less, and H2 content of 1 ppb or less are preferred.

[0276] The oxide semiconductor layer was formed by holding a substrate in a deposition chamber kept under reduced pressure and raising the substrate temperature to 1000 K. The heating is carried out at a temperature of 00°C or higher and 600°C or lower, preferably 300°C or higher and 500°C or lower.

[0277] By forming the oxide semiconductor layer while heating the substrate, hydrogen and moisture contained in the formed oxide semiconductor layer can be reduced. The concentration of impurities such as hydrides and hydroxides can be reduced. Damage caused by the ring is reduced. Also, residual moisture in the film formation chamber is removed while hydrogen and moisture are removed. A sputtering gas from which the oxide semiconductor layer is removed is introduced, and an oxide semiconductor layer is formed using the target. .

[0278] To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, such as a cryopump, is used. It is preferable to use an ion pump or a titanium sublimation pump. The stage may be a turbomolecular pump with a cold trap added. The deposition chamber is evacuated using a pump, and contains hydrogen atoms, water (H2O), and other gases. Compounds containing carbon atoms (and more preferably compounds containing carbon atoms) are exhausted from the deposition chamber. The concentration of impurities contained in the formed oxide semiconductor layer can be reduced.

[0279] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. , DC power supply power 0.5kW, oxygen as sputtering gas (oxygen flow rate 100%) When a pulsed DC power supply is used, the powder generated during film formation is This is preferable because it reduces the amount of particles and dust and also makes the film thickness distribution uniform.

[0280] Next, first heat treatment is performed. By the first heat treatment, excess SiO 2 in the oxide semiconductor layer is removed. Hydrogen (including water and hydroxyl groups) is removed (dehydration or dehydrogenation) to remove impurities in the oxide semiconductor layer. The concentration of substances can be reduced.

[0281] The first heat treatment is performed under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, or an oxygen gas atmosphere. Ambient or ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy) method) The moisture content measured using a dew point meter is preferably 20 ppm or less (-55°C in dew point equivalent). In an atmosphere of 250°C or more and 750°C or less, preferably 1 ppm or less, and preferably 10 ppb or less, air, The heating is carried out at a temperature of 400°C or lower, or at a temperature of 400°C or higher but lower than the distortion point of the substrate.

[0282] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. is a rare gas such as argon or nitrogen, which does not react with the object to be treated by heat treatment. A suitable inert gas is used.

[0283] For example, in the first heat treatment, the substrate is moved into an inert gas heated to a high temperature, After heating for several minutes, the substrate is moved and taken out of the heated inert gas atmosphere for GRTA. It is also possible.

[0284] Heat treatment is carried out under an atmosphere of inert gas such as nitrogen or rare gas, oxygen, or ultra-dry air. In this case, it is preferable that the atmosphere does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gas introduced into the treatment equipment is preferably 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., 1 ppm or less, preferably It is preferable to keep the concentration below 0.1 ppm.

[0285] The first heat treatment is performed in a reduced pressure atmosphere or an inert atmosphere, and then the temperature is maintained. It is preferable to switch to an oxidizing atmosphere and then further heat treatment. When heat treatment is performed in an inert atmosphere, the impurity concentration in the oxide semiconductor layer can be reduced. However, oxygen vacancies are also generated at the same time. This can be reduced by heat treatment in a chemical atmosphere.

[0286] In this way, the hydrogen concentration is sufficiently reduced to achieve high purity, and oxygen deficiency is prevented by supplying sufficient oxygen. In oxide semiconductors where the defect levels in the energy gap due to carrier depletion are reduced, Concentration is 1×10 12 / cm 3 Less than 1×10 11 / cm 3 Less than, more desirable 1.45 x 10 10 / cm 3 For example, the off-state current ( Here, the value per unit channel width (1 μm) is 100 zA (1 zeptoampere A) is 1 x 10 -21 A) or less, preferably 10zA or less. Also, at 85°C, 100zA(1×10 -19 A) or less, preferably 10zA (1 x 10 -20 A) The following In this way, an i-type (intrinsic) or substantially i-type oxide semiconductor is used. As a result, the first transistor 411 and the second transistor 412 have excellent off-state current characteristics. You can get 412.

[0287] Furthermore, a transistor including a highly purified oxide semiconductor has low threshold voltage, on-state current, and other properties. There is almost no temperature dependency in any of the electrical characteristics. There is little gender variation.

[0288] In this way, the oxide is highly purified and made i-type (intrinsic) by reducing oxygen vacancies. Transistors using compound semiconductors have suppressed fluctuations in electrical characteristics and are electrically stable. Therefore, highly reliable EL display devices using oxide semiconductors with stable electrical characteristics are achieved. can be provided.

[0289] Next, a protective layer 651 is formed on the semiconductor layer 505. The protective layer 651 is a gate insulating layer. It can be formed from the same materials and methods as the edge layer 504 .

[0290] If the protective layer 651 in contact with the semiconductor layer 505 contains a large amount of oxygen, the semiconductor layer 505 It can function as a source of oxygen to supply 05.

[0291] In this embodiment, a silicon oxide layer having a thickness of 200 nm is used as the protective layer 651. Then, a resist mask is formed on the protective layer 651 by a second photolithography process. , a portion of the protective layer 651 on the semiconductor layer 505 is selectively removed to form openings 601 and 60 2. Openings 606 and 607 are formed (see FIG. 21(B)). A protective layer is formed on the remaining semiconductor layer 505 by forming the opening 602, the opening 606, and the opening 607. The shape of the layer is a trapezoid or a triangle in cross section, and the taper angle θ of the bottom end of the cross section is The angle is set to 60° or less, preferably 45° or less, and more preferably 30° or less. In this embodiment, a resist mask is formed on a silicon oxide layer by a photolithography process. Then, selective etching is performed to form the cross section of the protective layer 651 into a trapezoidal shape, and the protective layer 65 The taper angle θ of the lower end of the photolithography film 1 is set to about 30°. In the roughening process, the opening 605 is also the opening 601, the opening 602, the opening 606 and the opening It is formed in the same manner as the mouth portion 607 .

[0292] After the protective layer 651 is formed, heat treatment may be performed. Heat treatment is carried out at 0°C for 1 hour.

[0293] The protective layer 651 may be made of an insulating material containing the same kind of component as the semiconductor layer 505 . When the protective layer 651 is a laminate of different layers, the layer in contact with the oxide semiconductor is the oxide semiconductor. Such a material has good compatibility with oxide semiconductors. By using this as the protective layer 651, the state of the interface with the oxide semiconductor can be maintained in a good condition. Here, the term "component of the same kind as an oxide semiconductor" refers to a component of an oxide semiconductor. It means one or more elements selected from the elements.

[0294] Specifically, an insulating material containing the same component as an oxide semiconductor that can be used for the protective layer 651 When an oxide material containing In, Ga, and Zn is used for the oxide semiconductor layer, The elements contained in the compound semiconductor are In, Ga, and Zn, and Ga is converted into a tetravalent cation. It is preferable that the material be a material in which at least one element selected from the group consisting of substituted elements is used.

[0295] Examples of elements that become tetravalent cations include Ti, Zr, Hf, and Alternatively, Ge, which is a group 14 element, can be used. The group elements are used to construct oxide semiconductors by substituting Ga, which becomes a trivalent cation in IGZO. This increases the bonding strength with oxygen, resulting in a protective layer with higher insulating properties than IGZO. You can get 651.

[0296] In addition, the lanthanide cerium (Ce) may also be used as a tetravalent cation. By replacing Ga with Ce, a protective layer 651 with higher insulating properties than IGZO can be obtained. It is possible.

[0297] In addition, an insulating material containing the same kind of component as an oxide semiconductor that can be used for the protective layer 651 is In the case where an oxide material containing In, Ga, and Zn is used as the oxide semiconductor layer, The semiconductor contains elements In, Ga, and Zn, and Ga is replaced with yttrium (Y). Yttrium is less electronegative than Ga, so it reacts well with oxygen. The electronegativity difference can be increased, and the electronegativity can be increased by ionic bonding with oxygen in the oxide semiconductor. The bond can be made stronger, and a protective layer 651 with higher insulating properties than IGZO can be obtained. This can be done.

[0298] In addition, when the protective layer 651 has a laminated structure, an insulating material containing the same component as the oxide semiconductor is used. It may also be a laminated structure of a film made of a material and a film containing a material different from the component material of the film.

[0299] The openings 601, 602, 606, and 607 are formed by Impurities are likely to adhere to the surface of the semiconductor layer 505 exposed by etching. The etching gas or etching solution used in the etching may contain elements, or These include elements present in the etching chamber. Examples of the element include boron, chlorine, fluorine, carbon, and aluminum.

[0300] Next, a cleaning process is performed on the surfaces of the semiconductor layer 505 and the protective layer 651. The cleaning process is performed using TMA. This can be done using an alkaline solution such as H solution, water, or diluted hydrofluoric acid. Alternatively, the cleaning process may be carried out using oxygen, nitrous oxide, or a rare gas (typically argon). The cleaning process can be carried out by plasma treatment. The impurities attached to the surface of 51 can be removed.

[0301] Dilute hydrofluoric acid is 50% by weight hydrofluoric acid diluted 100 to 100,000 times with water. It is desirable to use diluted hydrofluoric acid for the cleaning process. Impurities adhering to the semiconductor layer 505 can be removed together with a portion of the semiconductor layer 505.

[0302] Next, the semiconductor layer 505 in the openings 601, 602, 606, and 607 On the top of the protective layer 651, a first electrode 506A, a second electrode 506B, and a first electrode 546A are disposed. , the second electrode 546B, and a conductive layer that will become the wiring 516. The conductive layers used for the electrode 506B, the first electrode 546A, the second electrode 546B, and the wiring 516 are The first electrode 502 can be formed using the same material and method as the gate electrode 502. 6A, the second electrode 506B, the first electrode 546A, the second electrode 546B, and the wiring 516. The conductive layer may be formed of a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide Indium tin oxide (In2O3-SnO2, abbreviated as ITO), indium zinc oxide ( In2O3-ZnO) or these metal oxide materials containing silicon oxide are used. You can be there.

[0303] In this embodiment, the semiconductors in the openings 601, 602, 606 and 607 are A 5 nm thick Ti layer was formed as a conductive layer on the conductive layer 505 and the protective layer 651. A 250 nm thick Cu layer is formed on the i-layer. Then, a third photolithography process is performed. A resist mask is formed, and the conductive layer is selectively etched away to form the first electrode 506A. , the second electrode 506B, the first electrode 546A, the second electrode 546B, and the wiring 516 are formed. (See Figure 21(C)).

[0304] Next, the first electrode 506A, the second electrode 506B, the first electrode 546A, the second electrode 546B, An insulating layer 507 is formed on the protective layer 651 and the wiring 516. The insulating layer 507 is a gate insulating layer. It can be formed using the same material and method as the edge layer 504 or the underlayer 501. Formation by sputtering is preferable in that it is less likely to be contaminated with oxygen or water. If hydrogen is contained in the edge layer 507, the hydrogen may penetrate into the oxide semiconductor layer or the hydrogen may cause oxidation. There is a risk that oxygen will be extracted from the oxide semiconductor layer, causing the oxide semiconductor layer to become low-resistance (n-type). Therefore, the insulating layer 507 is formed by a method that does not contain hydrogen or impurities containing hydrogen. It is important to form a film.

[0305] The insulating layer 507 is typically made of silicon oxide, silicon oxynitride, hafnium oxide, Inorganic insulating materials such as aluminum oxide and gallium oxide can be used. Since silicon is a material that is difficult to charge, the threshold voltage fluctuation due to charge-up in the insulating layer can be prevented. When an oxide semiconductor is used for the semiconductor layer 505, the insulating layer 507 or a metal oxide containing the same component as the oxide semiconductor, stacked with the insulating layer 507. A layer may be formed.

[0306] In this embodiment, silicon oxide having a thickness of 200 nm is deposited as the insulating layer 507 by sputtering. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide layer is formed by sputtering using a rare gas. (typically argon) atmosphere, oxygen atmosphere, or a mixture of rare gas and oxygen atmosphere The target can be silicon oxide or silicon. For example, silicon can be used as a target and sputtered in an atmosphere containing oxygen. By carrying out the above, silicon oxide can be formed.

[0307] In order to remove the residual moisture in the film-forming chamber during the formation of the insulating layer 507, an adsorption type vacuum pump is used. It is preferable to use a pump (such as a cryopump). The insulating layer 507 formed in the film formation chamber has a reduced concentration of impurities contained in the insulating layer 507. In addition, it can be used as an exhaust means for removing residual moisture in the film formation chamber of the insulating layer 507. may be a turbomolecular pump plus a cold trap.

[0308] The sputtering gas used in forming the insulating layer 507 is hydrogen, water, a hydroxyl group, a hydride, or the like. It is preferable to use a high-purity gas from which impurities have been removed.

[0309] Then, the mixture is heated under a reduced pressure, an inert gas atmosphere, an oxygen gas atmosphere, or an ultra-dry air atmosphere. A second heat treatment is carried out under atmospheric pressure (preferably at 200°C or higher and 600°C or lower, for example, at 250°C or higher and 55°C or lower). 0°C or less). However, the first photolithography process or the third photolithography process may be performed. When Al is used in the wiring layer formed by the lithography process, the heat treatment The temperature is set to 380°C or less, preferably 350°C or less, and Cu is used for the wiring layer. In this case, the temperature of the heat treatment is set to 450°C or less. For example, in a nitrogen atmosphere, the temperature is set to 450°C or less. The second heat treatment may be performed for 1 hour. The temperature is raised while a part of the insulating layer 507 (channel forming region) is in contact with the insulating layer 507, and the insulating layer 507 containing oxygen is Oxygen can be supplied from O7 to the semiconductor layer 505. It is preferable that the following are not included.

[0310] Next, a resist mask is formed by a fourth photolithography process, and the second electrode 50 A portion of the insulating layer 507 on the second electrode 6B is selectively removed to form an opening 603. A portion of the insulating layer 507 on the electrode 546B is selectively removed to form an opening 508. The insulating layer 507 on the gate electrode 542, the protective layer 651, the semiconductor layer 505, and the gate insulating layer A portion of 504 is selectively removed to form an opening 604. A portion of the insulating layer 507 on the wiring 516 in the insulating layer 507 is selectively removed to form an opening 520 . Also, on the wiring 512 in the cross section J1-J2, the insulating layer 507, the protective layer 651, the semiconductor A portion of the conductor layer 505 and the gate insulating layer 504 is selectively removed to form an opening 519. (See FIG. 22(A)). Although not shown, in this photolithography process, Therefore, the groove 530 is formed in the same manner as the opening 519. Therefore, the side surface of the groove 530 is insulated. Layer 507, protective layer 651, semiconductor layer 505, and gate insulating layer 504 are exposed.

[0311] The insulating layer 507, the protective layer 651, the semiconductor layer 505, and the gate insulating layer 504 are etched. Either dry etching or wet etching may be used, or both may be used. The etching gas used in etching is a gas containing chlorine (chlorine-based gas, for example, chlorine (C l2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4) etc.) can be used.

[0312] As dry etching, parallel plate type RIE (Reactive Ion Etching) ng) method and ICP (Inductively Coupled Plasma) In addition, the underlayer 501 is formed from the substrate 500. In order to prevent the diffusion of impurity elements from the underlayer 5 during the etching, It is preferable to adjust the etching conditions so that O1 is not etched as much as possible. stomach.

[0313] Generally, etching of the semiconductor layer and forming of the openings are performed using different photolithography and etching processes. However, according to the manufacturing process shown in this embodiment, the etching process can be performed in one step. The photolithography and etching processes can be performed simultaneously. This not only reduces the number of photomasks, but also the photolithography process itself. This allows for a reduction in the number of subsequent etching steps. The lithography process allows the EL display device to be manufactured at low cost and with good productivity.

[0314] Furthermore, according to the manufacturing process described in this embodiment, a photoresist is directly formed on the oxide semiconductor layer. In addition, the channel formation region of the oxide semiconductor layer is protected by the insulating layer 507. Therefore, the oxide semiconductor layer can be easily removed even in the subsequent photoresist stripping and cleaning process. Since moisture does not adhere to the channel forming region, the first transistor 411 and the second transistor The variation in the characteristics of the transistor 412 is reduced, improving reliability.

[0315] Next, the second electrode 506B in the opening 603, the gate electrode 542 in the opening 604, and the opening On the second electrode 546B of the portion 508 and on the insulating layer 507, the wiring 513, the electrode 510, and the electrode 5 Conductive layers to be the wiring 513, the electrode 510, the electrode 521, and the electrode 522 are formed. The conductive layer to be the electrode 522 is formed by sputtering, vacuum deposition, or the like. A conductive layer (also called a transparent conductive layer) having a thickness of 30 nm to 200 nm, preferably 50 nm The thickness of the insulating film is 100 nm or more and 100 nm or less (see FIG. 22(B)).

[0316] In this embodiment, an ITO layer having a thickness of 80 nm is formed as a light-transmitting conductive layer. A resist mask is formed by the photolithography process, and a light-transmitting conductive layer is selected. The wiring 513, the electrode 510, the electrode 521, and the electrode 522 are formed by selective etching. do.

[0317] The wiring 513 is connected to the second electrode 506B through the opening 603 and to the gate electrode 542 through the opening 604. The electrode 510 is connected to the second electrode 546B at the opening 508. The electrode 521 is connected to the wiring 512 through the opening 519. The electrode 522 is connected to the wiring 512 through the opening 520. 516.

[0318] In addition, in the openings 519 and 520 formed in the terminal portions 403 and 404, The wiring 512 and the wiring 516 are not left exposed, but are made of conductive oxide such as ITO. It is important to cover the wiring 512 and wiring 516 with a material. If the wiring 516 and the wiring 2 are left exposed, the exposed surfaces will be oxidized and the connection to the FPC etc. will be difficult. The contact resistance increases. The increase in contact resistance causes delays in the signals input from the outside and distortion of the waveform. This causes external signals to be transmitted imprecisely, resulting in a decrease in the reliability of the semiconductor device. 512 and the exposed surfaces of the wiring 516 are covered with an oxide conductive material such as ITO. An increase in contact resistance can be prevented, and the reliability of the semiconductor device can be improved.

[0319] The material of the electrode 510 constituting the EL element 414 is the same as the material of the EL layer 562 and the electrode 544. By appropriately selecting and configuring the above, the direction of light extracted from the EL element 414 can be set. In this embodiment, the structure in which light is extracted from the substrate 500 side is as follows. I will explain.

[0320] Examples of the light-transmitting conductive layer include indium oxide containing tungsten oxide, tungsten oxide, and Indium zinc oxide containing stainless steel, indium oxide containing titanium oxide, titanium oxide Indium tin oxide (hereinafter referred to as ITO), indium zinc Conductive materials with transparency, such as lead oxide and indium tin oxide with silicon oxide added, are used. It can be used.

[0321] Next, a material for forming a partition wall layer is provided on A1-A2, which corresponds to the cross section of the pixel portion. The partition layer 514 is formed using an organic insulating material or an inorganic insulating material. An opening 565 is formed by a photolithography process. The opening 565 is formed on the electrode 510. The material for the partition wall layer is a photosensitive resin material. The cross-sectional shape of the side wall of the opening 565 has a shape with a continuous curvature. Next, an EL layer 562 is formed in the region of the opening 565 that contacts the electrode 510. Next, a layer to be the other electrode of the EL element 414 is formed on the EL layer 562 and the partition layer 514. An electrode 544 is formed (see FIG. 22(C)).

[0322] The EL layer 562 includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, etc. The other electrode 544 of the EL element 414 may be a layer of an When the electrode 510 is used as an anode and a material with a large work function is used, a metal material with a small work function is used. Specifically, the electrode 544 is made of an alloy of aluminum and lithium. It is possible.

[0323] According to this embodiment, a semiconductor device can be fabricated using fewer photolithography steps than in the past. This makes it possible to manufacture the semiconductor layer at low cost and reduce the deterioration of the semiconductor layer. As a result, an EL display device with high productivity and excellent reliability can be produced.

[0324] This embodiment mode can be freely combined with other embodiment modes.

[0325] (Embodiment 3) FIG. 11 illustrates one mode of a display device using the transistor described in Embodiment 1 as an example.

[0326] FIG. 11A shows a transistor 4010 and a liquid crystal element 4013 mounted on a first substrate 4001. 4006 and a second substrate 4006 are sealed with a sealant 4005. 11(B) corresponds to a cross-sectional view taken along line MN in FIG. 11(A). A groove 4040 is provided on 4001 .

[0327] A sealing material 4005 is formed so as to surround a pixel portion 4002 provided on a first substrate 4001. A second substrate 4006 is provided on the pixel portion 4002. 002 is a liquid crystal display device formed by a first substrate 4001, a sealing material 4005, and a second substrate 4006. It is sealed together with the crystal layer 4008.

[0328] In addition, the area outside the area surrounded by the sealing material 4005 on the first substrate 4001 In the area, an input terminal 4020 is provided, and an FPC 4018a (Flexible Printed Circuit FPC4018a is connected to a separate circuit. The FPC 4018b is electrically connected to a signal line driver circuit 4003 formed on a substrate. The pixel electrodes are electrically connected to a scanning line driver circuit 4004 which is fabricated on a different substrate. Various signals and potentials given to the unit 4002 are transmitted through the FPC 4018a and the FPC 4018b. The signals are supplied from a signal line driver circuit 4003 and a scanning line driver circuit 4004 via the signal line driver circuit 4003 and the scanning line driver circuit 4004 .

[0329] The method of connecting the drive circuit fabricated on a separate substrate is not particularly limited. , COG (Chip On Glass) method, wire bonding method, TCP (Ta pe Carrier Package) method or TAB (Tape Automa A method such as ted bonding can be used.

[0330] Although not shown, the signal line driver circuit 4003 or the scanning line driver circuit 4004 is The transistors disclosed herein may be formed on the substrate 4001 .

[0331] A liquid crystal element (also called a liquid crystal display element) is used as a display element provided in the display device. In addition, display media such as electronic ink, which changes contrast through electrical effects, are also available. can be applied.

[0332] The display device shown in FIG. 11 has an electrode 4015 and a wiring 4016. The wiring 4016 is electrically connected to the terminals of the FPC 4018a via the anisotropic conductive layer 4019. are actively connected.

[0333] The electrode 4015 is formed from the same conductive layer as the first electrode 4030, and the wiring 4016 is formed from a conductive layer. The electrodes are formed from the same conductive layer as the source and drain electrodes of the transistor 4010 .

[0334] In this embodiment, the transistor described in Embodiment 1 is used as the transistor 4010. The transistor 4010 provided in the pixel portion 4002 is a display element. The display element is not particularly limited as long as it can display an image. Various display elements can be used.

[0335] FIG. 11 shows an example of a display device using a liquid crystal element as a display element. The liquid crystal element 4013, which is a display element, includes a first electrode 4030, a second electrode 4031, and The liquid crystal layer 4008 is sandwiched between insulating layers that function as alignment layers. An edge layer 4032 and an insulating layer 4033 are provided. The second electrode 4032 is also provided on the groove 4040. The second electrode 4031 is The first electrode 4030 and the second electrode 4031 are connected via the liquid crystal layer 4008. It has a stacked structure.

[0336] The spacers 4035 are columnar spacers formed on the second substrate 4006 by an insulating layer. The sensor is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. A spherical spacer may also be used.

[0337] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, etc. The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0338] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. The channel region is set to be able to hold charge for a predetermined period, taking into consideration factors such as the current. A transistor using a highly purified oxide semiconductor is used for a semiconductor layer where a As a result, the capacitance of the liquid crystal in each pixel is 1 / 3 or less, preferably 1 / 5 or less. It is sufficient to provide a storage capacitor having a certain size.

[0339] The transistor including the highly purified oxide semiconductor layer used in this embodiment has an off state. Therefore, the current value (off-state current value) at the time of the image signal or the like can be reduced. The data retention time can be extended, and the write interval can also be set longer when the power is on. This reduces the frequency of refresh operations, which has the effect of reducing power consumption. Furthermore, a transistor including a highly purified oxide semiconductor layer can be provided with a storage capacitor. Therefore, the potential applied to the liquid crystal element can be maintained without the need for a voltage.

[0340] In addition, by using an oxide semiconductor layer as a semiconductor layer of the transistor used in this embodiment, Higher field-effect mobility than transistors using amorphous silicon Therefore, when the above transistor is used in the pixel portion of a liquid crystal display device, By doing so, it is possible to provide a high-quality image. The driver circuit section and pixel section can be separately fabricated on the same substrate. The number of items can be reduced.

[0341] As described above, by applying the transistor exemplified in Embodiment 1, a transistor can be effectively used. The reliability of transistors can be improved without increasing the number of photomasks used in the manufacturing process of display devices. Therefore, a liquid crystal display device with improved performance can be manufactured at low cost and with high productivity. As a result, a highly reliable liquid crystal display device can be provided.

[0342] This embodiment mode can be freely combined with other embodiment modes.

[0343] (Fourth embodiment) FIG. 23 illustrates one mode of a display device using the transistor described in Embodiment 2 as an example.

[0344] FIG. 23A shows a transistor 5010 and an EL element 5013 mounted on a first substrate 5001. 5 is a plan view of a panel sealed between a first substrate 5001 and a second substrate 5006 by a sealant 5005. 23(B) corresponds to a cross-sectional view taken along line MN in FIG. 23(A). A groove 5040 is provided on 5001 .

[0345] A sealing material 5005 is formed so as to surround a pixel portion 5002 provided on a first substrate 5001. A second substrate 5006 is provided on the pixel portion 5002. 002 is sealed by a first substrate 5001, a sealing material 5005, and a second substrate 5006. It has been done.

[0346] In addition, the area outside the area surrounded by the sealing material 5005 on the first substrate 5001 In the area, an input terminal 5020 is provided, and an FPC 5018a (Flexible Printed FPC5018a is connected to a separate circuit. The FPC 5018b is electrically connected to a signal line driver circuit 5003 formed on a substrate. The pixel electrodes are electrically connected to a scanning line driver circuit 5004 which is fabricated on a different substrate. Various signals and potentials given to the unit 5002 are transmitted through the FPC 5018a and the FPC 5018b. The signals are supplied from a signal line driver circuit 5003 and a scanning line driver circuit 5004 via the signal line driver circuit 5003 and the scanning line driver circuit 5004 .

[0347] The method of connecting the drive circuit fabricated on a separate substrate is not particularly limited. , COG (Chip On Glass) method, wire bonding method, TCP (Ta pe Carrier Package) method or TAB (Tape Automa A method such as ted bonding can be used.

[0348] Although not shown, the signal line driver circuit 5003 or the scanning line driver circuit 5004 is The transistors disclosed herein may be formed on the substrate 5001 .

[0349] The display device shown in FIG. 23 has an electrode 5015 and a wiring 5016. The wiring 5016 is electrically connected to the terminal of the FPC 5018a via the anisotropic conductive layer 5019. are actively connected.

[0350] The electrode 5015 is formed from the same conductive layer as the first and second electrodes of the transistor 5010. The wiring 5016 has the same conductor as the first electrode 5030 which is one of the electrodes of the EL element 5013 . The insulating layer is formed of a conductive layer.

[0351] In this embodiment, the second transistor shown in Embodiment 2 is used as the transistor 5010. The transistor 5010 provided in the pixel portion 5002 is a display transistor. The elements are electrically connected to form a display panel.

[0352] The display device shown in Figure 23 is an example in which EL elements are used as display elements. In the figure, the EL element 5013 includes a first electrode 5030, a second electrode 5031, and an EL layer The partition layer 5009 on which the EL element 5013 is provided also includes the groove portion 5040. It is provided.

[0353] By filling the groove 5040 with the partition layer 5009, the semiconductor exposed when the groove 5040 is formed is prevented from being damaged. By using this structure, the ends of the body layer and the insulating layer can be covered. Since the portion can be protected, the reliability of the semiconductor device can be improved.

[0354] In addition, by using an oxide semiconductor layer as a semiconductor layer of the transistor used in this embodiment, Higher field-effect mobility than transistors using amorphous silicon Therefore, high-speed driving is possible. By doing so, it is possible to provide a high-quality image. It is possible to separately fabricate the driver circuit section or pixel section on the same substrate, so the EL display section The number of items can be reduced.

[0355] As described above, by applying the transistor exemplified in Embodiment 2, a transistor can be effectively used. The reliability of transistors can be improved without increasing the number of photomasks used in the manufacturing process of display devices. Therefore, an EL display device with improved properties can be manufactured at low cost and with high productivity. This makes it possible to provide an EL display device with excellent reliability.

[0356] This embodiment mode can be freely combined with other embodiment modes.

[0357] (Embodiment 5) In this embodiment, an example of an electronic device including the display device described in the above embodiment is We will explain about this.

[0358] FIG. 12A shows a notebook personal computer, which includes a main body 3001 and a housing 300 2, a display unit 3003, a keyboard 3004, etc. By applying the liquid crystal display device or the EL display device shown in This makes it possible to provide a high-performance and highly reliable notebook-type personal computer.

[0359] FIG. 12B shows a personal digital assistant (PDA), which has a main body 3021 including a display unit 3023 and a An external interface 3025 and operation buttons 3024 are provided. The liquid crystal display device or the like shown in the above embodiment has a stylus 3022 as an accessory. By applying EL display devices, it is possible to realize low-cost, highly productive, and highly reliable portable information devices. The terminal can be a PDA.

[0360] FIG. 12C shows an example of an electronic book. For example, the electronic book has a housing 2702 and The housing 2702 and the housing 2704 are made up of two housings. The opening and closing operation can be performed with the shaft portion 2712 as an axis. This configuration allows the device to function like a paper book.

[0361] The housing 2702 incorporates a display unit 2705, and the housing 2704 incorporates a display unit 2707. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 12C), and An image can be displayed on the display unit (display unit 2707 in FIG. 12C). By applying the liquid crystal display device or EL display device shown in the figure, it is possible to produce at low cost. This makes it possible to produce an e-book with high functionality and reliability.

[0362] FIG. 12C shows an example in which an operating unit and the like are provided in the housing 2702. For example, In the housing 2702, a power terminal 2721, operation keys 2723, a speaker 2725, etc. The operation key 2723 can be used to turn pages. A keyboard, pointing device, etc. may be provided on the same surface. External connection terminals (earphone terminal, USB terminal, etc.) and recording medium insertion port are located on the back and sides of the body. Furthermore, the electronic book may have a function as an electronic dictionary. This may also be configured as follows.

[0363] The electronic book may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to purchase and download desired book data from the server. be.

[0364] FIG. 12(D) shows a mobile phone, which is composed of two housings, a housing 2800 and a housing 2801. The housing 2801 contains a display panel 2802, a speaker 2803, a microphone, and 2804, pointing device 2806, camera lens 2807, external connection terminal The housing 2800 also includes a solar panel for charging the portable information terminal. It is equipped with a battery cell 2810, an external memory slot 2811, etc. The antenna is also attached to the case. It is built into the body 2801.

[0365] The display panel 2802 is equipped with a touch panel, and the image displayed in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also has a boost circuit to boost the voltage required for each circuit.

[0366] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the camera lens 2802, so video calls are possible. The speaker 2803 and microphone 2804 are not limited to voice calls, but also can be used for video calls, Recording and playback are possible. Furthermore, the housing 2800 and the housing 2801 can be slid apart. As shown in 12(D), it can be folded from the unfolded state to the overlapped state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0367] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 2811, it is possible to store and transfer a larger amount of data. do.

[0368] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. By applying the liquid crystal display device or the EL display device described in the above embodiment, This makes it possible to produce a mobile phone that is low cost, highly productive, and highly reliable.

[0369] FIG. 12(E) shows a digital video camera, which includes a main body 3051, a display unit (A) 3057, Eyepiece 3053, operation switch 3054, display unit (B) 3055, battery 3056, etc. The liquid crystal display device or the EL display device shown in the above embodiment is By applying this, a highly reliable digital video camera can be obtained.

[0370] 12(F) shows an example of a television device. The television device has a housing 96 The display unit 9603 is incorporated in the camera body 9601. The display unit 9603 can display images. In this example, the housing 9601 is supported by a stand 9605. By applying the liquid crystal display device or the EL display device described in the above embodiment, This makes it possible to provide a more reliable television device.

[0371] The television set can be operated using an operation switch on the housing 9601 or a separate remote control. In addition, the remote control device can be configured to output the A display unit for displaying information may be provided.

[0372] The television device is assumed to be equipped with a receiver, modem, etc. It can receive television broadcasts and can also communicate by wire or wireless via a modem. By connecting to a network, you can send and receive data in one direction (sender to receiver) or two directions (sender to receiver). It is also possible to communicate information between the recipient and the receiver, or between receivers themselves.

[0373] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Explanation of symbols]

[0374] 100 Semiconductor device 101 Substrate 102 pixel area 103 Terminal section 104 Terminal section 105 terminal 105_i terminal 106 terminals 106_j terminal 107 terminal 110 pixels 111 Transistor 112 Liquid crystal element 113 Capacitor element 114 Electrode 120 pixels 130 pixels 200 boards 201 Base layer 202 gate electrode 203 Wiring 204 Gate insulating layer 205 Semiconductor layer 206A Electrode 206B Electrode 207 Insulating layer 208 Opening 210 pixel electrode 212 Wiring 212_i wiring 216 Wiring 216_j Wiring 219 Opening 220 Opening 221 Electrode 222 Electrode 230 Groove 231 End 232 End 240 Groove 251 Groove 252 Groove 253 Groove 254 Groove 255 Groove 256 Groove 257 Groove 258 Groove 301 Opening 302 Opening 351 Protective layer 400 Semiconductor Devices 401 Substrate 402 pixel area 403 Terminal section 404 Terminal section 405 terminal 405_i terminal 406 terminal 406_j terminal 407 terminal 408 terminal 410 pixels 411 Transistor 412 transistors 413 Capacitor 414 EL element 420 pixels 430 pixels 500 boards 501 Base layer 502 gate electrode 503 Wiring 504 Gate insulating layer 505 Semiconductor layer 506A Electrode 506B Electrode 507 Insulation Layer 508 Opening 510 electrode 512 Wiring 512_i wiring 513 Wiring 514 Partition layer 516 Wiring 516_j Wiring 519 Opening 520 Opening 521 Electrode 522 Electrode 530 Groove 540 Groove 542 gate electrode 544 Electrode 546A Electrode 546B Electrode 551 Groove 552 Groove 553 Groove 554 Groove 555 Groove 562 EL layer 563 Wiring 565 Opening 601 Opening 602 Opening 603 Opening 604 Opening 605 Opening 606 Opening 607 Opening 651 Protective layer 2702 Case 2704 Housing 2705 ​​Display section 2707 Display section 2712 Shaft 2721 Power terminal 2723 Operation Key 2725 Speaker 2800 chassis 2801 Case 2802 Display panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 solar cell 2811 External Memory Slot 3001 main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main Unit 3022 stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4013 Liquid crystal element 4015 Electrode 4016 Wiring 4018a FPC 4018b FPC 4019 Anisotropic conductive layer 4020 Input terminal 4030 Electrode 4031 Electrode 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4040 Groove 5001 board 5002 Pixel unit 5003 Signal line driver circuit 5004 Scanning line driver circuit 5005 Sealing material 5006 Substrate 5008 EL layer 5009 Partition layer 5010 transistor 5013 EL element 5015 Electrode 5016 Wiring 5018a FPC 5018b FPC 5019 Anisotropic conductive layer 5020 Input terminal 5030 Electrode 5031 Electrode 5040 Groove 9601 Housing 9603 Display section 9605 Stand

Claims

1. A first to fourth wiring having regions extended in the row direction, A fifth wiring having a region extended in the direction of the row, The first to fourth transistors, The first EL element, It has a second EL element, The first transistor, the second transistor, and the first EL element are arranged in the first pixel. The third transistor, the fourth transistor, and the second EL element are arranged in the second pixel. In the row direction, the first pixel and the second pixel are adjacent to each other. The first image signal supplied from the first wiring is transmitted from the first wiring to the second transistor, at least through the channel formation region of the first transistor. The current corresponding to the first image signal transmitted to the second transistor flows from the second wiring to the first EL element, at least through the channel formation region of the second transistor. The second image signal supplied from the third wiring is transmitted from the third wiring to the fourth transistor, at least through the channel formation region of the third transistor. The current corresponding to the second image signal transmitted to the fourth transistor flows from the fourth wiring to the second EL element, at least through the channel formation region of the fourth transistor. The semiconductor layer having the channel formation region of the first transistor has the channel formation region of the second transistor, the channel formation region of the third transistor, the channel formation region of the fourth transistor, and an opening. The fifth wiring is electrically connected to the gate electrode of the first transistor and electrically connected to the gate electrode of the third transistor. The fifth wiring has a region that overlaps with the opening, The opening has a shape that extends in the column direction, and is a display device.

2. A first to fourth wiring having regions extended in the row direction, A fifth wiring having a region extended in the direction of the row, The first to fourth transistors, The first EL element, It has a second EL element, The first transistor, the second transistor, and the first EL element are arranged in the first pixel. The third transistor, the fourth transistor, and the second EL element are arranged in the second pixel. In the row direction, the first pixel and the second pixel are adjacent to each other. The first image signal supplied from the first wiring is transmitted from the first wiring to the second transistor, at least through the channel formation region of the first transistor. The current corresponding to the first image signal transmitted to the second transistor flows from the second wiring to the first EL element, at least through the channel formation region of the second transistor. The second image signal supplied from the third wiring is transmitted from the third wiring to the fourth transistor, at least through the channel formation region of the third transistor. The current corresponding to the second image signal transmitted to the fourth transistor flows from the fourth wiring to the second EL element, at least through the channel formation region of the fourth transistor. The semiconductor layer having the channel formation region of the first transistor has the channel formation region of the second transistor, the channel formation region of the third transistor, the channel formation region of the fourth transistor, and an opening. The fifth wiring is electrically connected to the gate electrode of the first transistor and electrically connected to the gate electrode of the third transistor. The fifth wiring has a region that overlaps with the opening, The opening has a shape that extends in the row direction, The display device wherein the region overlapping with the opening of the fifth wiring has one end and multiple ends in the wiring width direction of the fifth wiring.

3. In claim 1 or 2, The semiconductor layer is a display device having silicon.

Images