Charge detection device and charge detection method for semiconductor manufacturing

Abstract

To provide a charge detection device and a charge detection method capable of appropriately evaluating damage to a semiconductor device, including signs of electric charges that are generated during a semiconductor process.SOLUTION: A charge detection device 100 comprises an antenna structure 12, a diode and a MOSFET 10. The diode includes a first diode 14, the first diode 14 connecting between the antenna structure 12 and a gate of the MOSFET 10. For a positive charge detection device 100, the first diode 14 is connected in a forward direction with respect to a positive antenna charge generated in the antenna structure 12. For a negative charge detection device 100, the first diode 14 is connected in a forward direction with respect to a negative antenna charge generated in the antenna structure 12.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a charge detection device and a charge detection method used in the manufacture of semiconductor devices, and more particularly to a manufacturing evaluation device and a manufacturing evaluation method for evaluating plasma damage to semiconductor devices that occurs during a manufacturing process using plasma. [Background technology]

[0002] The manufacturing of semiconductor devices involves many processes that use plasma, such as plasma etching and plasma CVD. Plasma is a state in which positively charged ions and negatively charged electrons exist. It is known that charges in the plasma enter the conductors on the surface of semiconductor elements exposed to the plasma and flow into the semiconductor substrate via the gate electrode and gate insulating film. This can cause serious problems, such as damage and destruction of the gate insulating film, deterioration of LSI reliability, and a decrease in the yield rate.

[0003] Patent Document 1 discloses a semiconductor device manufacturing evaluation device having multiple first MOS devices on the same semiconductor substrate, each of which has an antenna exposed to plasma connected to its gate electrode, and the voltage applied between the gate electrode and the substrate is limited to different values ​​by protection diodes connected in parallel to the gate electrode. It also discloses that by changing the forward voltages (Vf = V1 / V2 / V3) of the protection diodes, the forward voltage Vf can be changed by the number of diodes connected in series. This allows the degree of damage to the MOSFET to be evaluated as the magnitude of Vf from the value of the forward voltage Vf.

[0004] Also disclosed is a field-effect MOS transistor having a p-type semiconductor substrate, n-type heavily doped source / drain regions formed on the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode made of first polycrystalline silicon formed on the gate insulating film, a protection diode made of second polycrystalline silicon formed on the semiconductor substrate, an intermediate insulating film formed on the gate electrode made of first polycrystalline silicon and the protection diode made of second polycrystalline silicon, a first metal electrode wiring connecting the gate electrode made of first polycrystalline silicon and the protection diode made of second polycrystalline silicon, and a second metal electrode wiring connecting the protection diode made of second polycrystalline silicon and the semiconductor substrate (Patent Document 2). The protection diode made of second polycrystalline silicon is insulated from the semiconductor substrate by the intermediate insulating film, preventing the formation of a parasitic pn junction. This allows the connection of a protection diode even in a depletion-mode NMOS transistor with a negative threshold. Furthermore, it is claimed that the connection of the protection diode is not affected by the body / well voltage, and the forward voltage of the protection diode can be adjusted by adjusting the number of polysilicon diodes connected in series.

[0005] Also disclosed is a plasma-induced damage testing structure that includes a MOS transistor under test, an antenna, a first pad, and a switch MOS transistor, where the antenna is connected to the gate electrode of the MOS transistor under test, and the first pad is connected to the gate electrode of the MOS transistor under test via the switch MOS transistor (Patent Document 3). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2000-332076 [Patent Document 2] Patent Publication No. 2006-24601 [Patent Document 3] Chinese Patent Application Publication No. 116417437 Summary of the Invention [Problem to be solved by the invention]

[0007] When plasma is used in the manufacturing process of semiconductor devices, the degree of damage caused to the device by electric charges varies depending on the process conditions and also on whether the electric charges are positive or negative. The technology described in Patent Document 1 can only evaluate positive charges induced by the process. If a p-type MOSFET is used to evaluate negative charges, the effects of positive and negative charges cannot be compared because the degree of damage detected differs between n-type and p-type MOSFETs depending on the amount of electric charge.

[0008] The technical objective of Patent Document 2 is to prevent forward current from flowing through a protection diode connected to the gate of a depletion-mode n-type MOSFET, which requires the application of a negative gate voltage for cutoff. If the protection diode is formed on the substrate and a PN junction is formed between the protection diode and the substrate, the forward voltage Vf can only be -0.7 V. Patent Document 2 connects two protection diodes in series to achieve a forward voltage Vf of -1.4 V. However, as with Patent Document 1, no consideration is given to distinguishing between positive and negative charges.

[0009] Patent Document 3 discloses only a configuration in which the gate of the MOS transistor and the antenna are directly connected, and does not disclose a configuration in which other components are connected between the gate of the MOS transistor and the antenna. [Means for solving the problem]

[0010] One aspect of the present invention is a charge detection device for evaluating damage caused by electric charges generated during a semiconductor process, the charge detection device comprising: an antenna structure formed on a semiconductor substrate; a diode; and a MOSFET, wherein the diode includes a first diode that is connected between the antenna structure and a gate of the MOSFET and is connected to have a forward direction with respect to a positive antenna charge generated in the antenna structure for positive charge detection; or the first diode that is connected between the antenna structure and a gate of the MOSFET and is connected to have a forward direction with respect to a negative antenna charge generated in the antenna structure for negative charge detection.

[0011] Preferably, the diode further includes a second diode, which is connected between the antenna structure and a well or a body of the MOSFET and is connected in a direction opposite to a positive antenna charge generated in the antenna structure for positive charge detection, or which is connected between the antenna structure and a body or a well of the MOSFET and is connected in a direction opposite to a negative antenna charge generated in the antenna structure for negative charge detection.

[0012] Preferably, a plurality of the first diodes are provided and the plurality of first diodes are connected in series.

[0013] Preferably, the diode is formed in a polysilicon layer insulated from the semiconductor substrate.

[0014] It is also preferable that the diode is formed on an SOI substrate, the diode is formed in an active region of the SOI substrate, and is insulated from the surroundings by an insulator and an element isolation region of the SOI substrate.

[0015] Another aspect of the present invention is a charge detection method using the charge detection device described above to evaluate damage caused by charges occurring during a process.

[0016] Here, it is preferable to determine the polarity of the charge that caused the damage based on the connection direction of the diode connected to the damaged MOSFET.

[0017] It is also preferable to evaluate the degree of damage based on the number of the first diodes connected in series with the damaged MOSFET.

[0018] Furthermore, the degree of damage is preferably evaluated by comparing the damage between n-type MOSFETs or between p-type MOSFETs.

[0019] Another aspect of the present invention is a charge detection device for evaluating damage due to charges generated during a semiconductor process, comprising: a first antenna structure formed on a semiconductor substrate; an n-type MOSFET; a diode connected between the first antenna structure and a gate of the n-type MOSFET, the diode being connected in a forward direction with respect to positive antenna charges generated in the first antenna structure to detect positive charges, or connected in a forward direction with respect to negative antenna charges generated in the first antenna structure to detect negative charges; a second antenna structure formed on the semiconductor substrate; a p-type MOSFET; and another diode connected between the second antenna structure and a gate of the p-type MOSFET, the diode being connected in a forward direction with respect to positive antenna charges generated in the second antenna structure to detect positive charges, or connected in a forward direction with respect to negative antenna charges generated in the second antenna structure to detect negative charges. [Effects of the Invention]

[0020] According to the present invention, it is possible to provide a charge detection apparatus and a charge detection method that can appropriately evaluate damage to a semiconductor device during processing, regardless of whether the charge is positive or negative. [Brief explanation of the drawings]

[0021] [Figure 1]FIG. 1 is a diagram illustrating a configuration of a charge detection device according to a first embodiment. [Figure 2] FIG. 1 is a diagram illustrating a configuration of a charge detection device according to a first embodiment. [Figure 3] FIG. 1 is a diagram illustrating a configuration of a charge detection device according to a first embodiment. [Figure 4] FIG. 1 is a diagram illustrating a configuration of a charge detection device according to a first embodiment. [Figure 5] 1 is a cross-sectional view schematically illustrating a structure of a charge detection device according to a first embodiment. [Figure 6] FIG. 10 is a diagram illustrating a configuration of a charge detection device according to a second embodiment. [Figure 7] FIG. 10 is a diagram illustrating a configuration of a charge detection device according to a second embodiment. [Figure 8] FIG. 10 is a diagram illustrating a configuration of a charge detection device according to a second embodiment. [Figure 9] FIG. 10 is a diagram illustrating a configuration of a charge detection device according to a second embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a structure of a charge detection device according to a second embodiment. [Figure 11] FIG. 4 is a cross-sectional view schematically illustrating another example of the structure of the charge detection device according to the first embodiment. [Figure 12] 5A to 5C are diagrams illustrating a method for manufacturing the charge detection device according to the embodiment of the present invention. [Figure 13] 4 is a flowchart showing a charge detection process using the charge detection device according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] [First embodiment] 1 to 4 show the configuration of a charge detection device 100 according to the first embodiment. The charge detection device 100 includes a MOSFET 10, an antenna structure 12, and a first diode .

[0023] The charge detection device 100 can be used to detect positive and / or negative charges that may damage a semiconductor device during the process of forming the device. That is, the charge detection device 100 is used as a TEG (Test Element Group) used to evaluate the influence of charges (antenna charges) generated from the antenna structure 12 during the process of manufacturing a semiconductor element.

[0024] 1 shows a configuration in which an n-type MOSFET is used as a MOSFET 10 to detect positive charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and an antenna structure 12. The first diode 14 is connected in the forward direction from the antenna structure 12 to the gate electrode of the MOSFET 10. The source electrode of the MOSFET 10 is connected to the body or well.

[0025] In this structure, when a positive charge is induced in the antenna structure 12, the first diode 14 is forward biased by the positive charge, and a positive charge voltage is applied to the gate of the MOSFET 10. In contrast, when a negative charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the negative charge, and the application of a negative charge voltage to the gate of the MOSFET 10 is prevented.

[0026] 2 shows a configuration in which an n-type MOSFET is used as the MOSFET 10 to detect negative charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in the reverse direction from the antenna structure 12 to the gate electrode of the MOSFET 10. The source electrode of the MOSFET 10 is connected to the body or well.

[0027] In this structure, when a negative charge is induced in the antenna structure 12, the first diode 14 is forward biased by the negative charge, and a negative charge voltage is applied to the gate of the MOSFET 10. On the other hand, when a positive charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the positive charge, and the application of a positive charge voltage to the gate of the MOSFET 10 is prevented.

[0028] 3 shows a configuration in which a p-type MOSFET is used as the MOSFET 10 to detect positive charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in the forward direction from the antenna structure 12 to the gate electrode of the MOSFET 10. The source electrode of the MOSFET 10 is connected to the body or well.

[0029] In this structure, when a positive charge is induced in the antenna structure 12, the first diode 14 is forward biased by the positive charge, and a positive charge voltage is applied to the gate of the MOSFET 10. In contrast, when a negative charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the negative charge, and the application of a negative charge voltage to the gate of the MOSFET 10 is prevented.

[0030] 4 shows a configuration in which a p-type MOSFET is used as the MOSFET 10 to detect negative charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in the reverse direction from the antenna structure 12 to the gate electrode of the MOSFET 10. The source electrode of the MOSFET 10 is connected to the body or well.

[0031] In this structure, when a negative charge is induced in the antenna structure 12, the first diode 14 is forward biased by the negative charge, and a negative charge voltage is applied to the gate of the MOSFET 10. On the other hand, when a positive charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the positive charge, and the application of a positive charge voltage to the gate of the MOSFET 10 is prevented.

[0032] 1 to 4, by changing the number of first diodes 14 connected in series, it is possible to adjust the forward voltage Vf of all the first diodes 14 connected from the antenna structure 12 to the MOSFET 10. By providing MOSFETs with different numbers of first diodes 14 connected in series, it is possible to investigate the degree of influence of plasma from the degree of damage to each MOSFET.

[0033] 1 to 4 may be formed as a TEG on the same semiconductor substrate. Alternatively, each of the charge detection devices 100 may be formed as a TEG on the same semiconductor substrate by changing the number of first diodes 14 connected in series.

[0034] The polarity of the charge can be detected in both the n-type MOSFET and the p-type MOSFET. The degree of damage caused varies depending on whether the MOSFET 10 is an n-type MOSFET or a p-type MOSFET. For example, the n-type MOSFET may not be damaged, but only the p-type MOSFET may be damaged. Conversely, the n-type MOSFET may be damaged, but not the p-type MOSFET. Therefore, it is important to measure both the n-type MOSFET and the p-type MOSFET to determine the degree of damage.

[0035] It is preferable that the first diode 14 is formed in a region insulated from the substrate, rather than inside the semiconductor substrate, thereby eliminating a parasitic junction in the first diode 14 and preventing the formation of a leakage current path other than the antenna for the charge during the process.

[0036] 5 shows a cross-sectional structure of the charge detection device 100 according to the first embodiment. The arrangement and size of each part in FIG. 5 have been changed to make the structure of the charge detection device 100 easier to understand.

[0037] The charge detection device 100 can be manufactured by a normal CMOS process. A p-type well 22p and an n-type well 22n are formed in a p-type substrate 20. The elements are insulated from each other by a buried insulating layer (STI: shallow trench isolation) 24. An n-type MOSFET 10n is formed in the p-type well 22p. A p-type MOSFET 10p is formed in the n-type well 22n. A gate insulating film is formed on the surface of the substrate 20. In FIG. 5, the gaps between the surface of the substrate 20 and the gate electrode, first diode 14, and second diode 16 represent insulating films.

[0038] 5, two first diodes 14a and 14b are connected in series between the antenna structure 12a and the gate electrode G of the n-type MOSFET 10n. The first diodes 14a and 14b are connected in the forward direction from the antenna structure 12a toward the gate electrode G of the n-type MOSFET 10n.

[0039] Furthermore, two first diodes 14c and 14d are connected in series between the antenna structure 12b and the gate electrode G of the p-type MOSFET 10p. The first diodes 14c and 14d are connected in opposite directions from the antenna structure 12b toward the gate electrode G of the p-type MOSFET 10p.

[0040] The first diodes 14a to 14d are made of polysilicon. For example, the polysilicon can be formed simultaneously with the polysilicon that forms the gate electrodes of the n-type MOSFET 10n and the p-type MOSFET 10p. The first diodes 14a to 14d can be formed by adding n-type dopants and p-type dopants only to necessary regions of the polysilicon using multiple masks. For example, a doping process for the n+ gate electrodes and a doping process for the p+ gate electrodes of the n-type MOSFET 10n and the p-type MOSFET 10p can be used.

[0041] However, other special polysilicon layers may be used, and other special doping processes may be applied. Furthermore, by changing the regions to which the n-type dopant and p-type dopant are added, it is also possible to form the first diode 14 connected in the opposite direction to that shown in FIG. 5.

[0042] By providing two polysilicon first diodes 14a and 14b in series, each with a forward voltage of Vf, the charging voltage across the n-type MOSFET 10n is reduced by 2Vf. By connecting one, two, ..., n first diodes 14 in series, the damage level in the plasma-based manufacturing process can be determined from the damage inflicted on the n-type MOSFET 10n. Similarly, by providing two polysilicon first diodes 14c and 14d in series, each with a forward voltage of Vf, the charging voltage across the p-type MOSFET 10p is reduced by 2Vf. By connecting one, two, ..., n first diodes 14 in series, the damage level in the plasma-based manufacturing process can be determined from the damage inflicted on the p-type MOSFET 10p.

[0043] [Second embodiment] 6 to 9 show the configuration of a charge detection device 200 according to the second embodiment. The charge detection device 200 includes a MOSFET 10, an antenna structure 12, a first diode 14, and a second diode 16.

[0044] The charge detection apparatus 200 can be used to detect positive and / or negative charges that may be damaging to semiconductor devices during the process of forming the devices.

[0045] 6 shows a configuration in which an n-type MOSFET is used as the MOSFET 10 to detect positive charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in a forward direction from the antenna structure 12 to the gate electrode of the MOSFET 10. Furthermore, a second diode 16 is connected between the connection point of the antenna structure 12 and the first diode 14 and the body or well. The second diode 16 is connected in a forward direction from the body or well to the antenna structure 12. The source electrode of the MOSFET 10 is connected to the body or well.

[0046] In this structure, when a positive charge is induced in the antenna structure 12, the first diode 14 is forward biased by the positive charge, and a positive charge voltage is applied to the gate of the MOSFET 10. At this time, the second diode 16 is reverse biased. On the other hand, when a negative charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the negative charge, and the application of a negative charge voltage to the gate of the MOSFET 10 is prevented. At this time, the second diode 16 is forward biased, and the negative charge induced in the antenna structure 12 is alleviated.

[0047] 7 shows a configuration in which an n-type MOSFET is used as the MOSFET 10 to detect negative charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in a reverse direction from the antenna structure 12 toward the gate electrode of the MOSFET 10. Furthermore, a second diode 16 is connected between the connection point of the antenna structure 12 and the first diode 14 and the body or well. The second diode 16 is connected in a reverse direction from the body or well toward the antenna structure 12. The source electrode of the MOSFET 10 is connected to the body or well.

[0048] In this structure, when negative charges are induced in the antenna structure 12, the first diode 14 is forward biased by the negative charges, and a negative charge voltage is applied to the gate of the MOSFET 10. At this time, the second diode 16 is reverse biased. On the other hand, when positive charges are induced in the antenna structure 12, the first diode 14 is reverse biased by the positive charges, and the application of a positive charge voltage to the gate of the MOSFET 10 is prevented. At this time, the second diode 16 is forward biased, and the positive charge induced in the antenna structure 12 is alleviated.

[0049] 8 shows a configuration in which a p-type MOSFET is used as the MOSFET 10 to detect positive charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in a forward direction from the antenna structure 12 to the gate electrode of the MOSFET 10. Furthermore, a second diode 16 is connected between the connection point of the antenna structure 12 and the first diode 14 and the body or well. The second diode 16 is connected in a forward direction from the body or well to the antenna structure 12. The source electrode of the MOSFET 10 is connected to the body or well.

[0050] In this structure, when a positive charge is induced in the antenna structure 12, the first diode 14 is forward biased by the positive charge, and a positive charge voltage is applied to the gate of the MOSFET 10. At this time, the second diode 16 is reverse biased. On the other hand, when a negative charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the negative charge, and the application of a negative charge voltage to the gate of the MOSFET 10 is prevented. At this time, the second diode 16 is forward biased, and the negative charge induced in the antenna structure 12 is alleviated.

[0051] 9 shows a configuration in which a p-type MOSFET is used as the MOSFET 10 to detect negative charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in a reverse direction from the antenna structure 12 toward the gate electrode of the MOSFET 10. Furthermore, a second diode 16 is connected between the connection point of the antenna structure 12 and the first diode 14 and the body or well. The second diode 16 is connected in a reverse direction from the body or well toward the antenna structure 12. The source electrode of the MOSFET 10 is connected to the body or well.

[0052] In this structure, when negative charges are induced in the antenna structure 12, the first diode 14 is forward biased by the negative charges, and a negative charge voltage is applied to the gate of the MOSFET 10. At this time, the second diode 16 is reverse biased. On the other hand, when positive charges are induced in the antenna structure 12, the first diode 14 is reverse biased by the positive charges, and the application of a positive charge voltage to the gate of the MOSFET 10 is prevented. At this time, the second diode 16 is forward biased, and the positive charge induced in the antenna structure 12 is alleviated.

[0053] According to the charge detection device 200 of the second embodiment, compared to the charge detection device 100 of the first embodiment, the effect of the second diode 16 can be suppressed by suppressing the influence of charges that are not of the desired polarity.

[0054] 6 to 9, by changing the number of first diodes 14 connected in series, it is possible to adjust the forward voltage Vf of all the first diodes 14 connected from the antenna structure 12 to the MOSFET 10. By providing MOSFETs with different numbers of first diodes 14 connected in series, it is possible to investigate the degree of influence of plasma from the degree of damage to each MOSFET.

[0055] However, since the second diode 16 serves as a bypass path for the reverse charge, it is more suitable to leave it as a single diode rather than connecting it in series.

[0056] 6 to 9 can be formed as a TEG on the same semiconductor substrate. Also, each charge detection device 200 can be formed as a TEG on the same semiconductor substrate by changing the number of first diodes 14 and second diodes 16 connected in series.

[0057] The polarity of the charge can be detected in both the n-type MOSFET and the p-type MOSFET. The degree of damage caused varies depending on whether the MOSFET 10 is an n-type MOSFET or a p-type MOSFET. For example, the n-type MOSFET may not be damaged, and only the p-type MOSFET may be damaged. Conversely, the n-type MOSFET may be damaged, and only the p-type MOSFET may not be damaged.

[0058] It is preferable that the first diode 14 and the second diode 16 are formed in an area insulated from the semiconductor substrate, thereby suppressing parasitic junctions in the first diode 14 and the second diode 16 and preventing the formation of a leakage current path for charges during the process.

[0059] 10 shows a cross-sectional structure of a charge detection device 200 according to the second embodiment. The arrangement and size of each part in FIG. 10 have been changed to make the structure of the charge detection device 200 easier to understand.

[0060] The charge detection device 200 can be manufactured by a normal CMOS process. A p-type well 22p and an n-type well 22n are formed in a p-type substrate 20. The elements are insulated from each other by a buried insulating layer (STI: shallow trench isolation) 24. An n-type MOSFET 10n is formed in the p-type well 22p. A p-type MOSFET 10p is formed in the n-type well 22n. A gate insulating film is formed on the surface of the substrate 20. In FIG. 10, the gaps between the surface of the substrate 20 and the gate electrode, first diode 14, and second diode 16 represent insulating films.

[0061] 10, a first diode 14a is connected between the antenna structure 12a and the gate electrode G of the n-type MOSFET 10n. The first diode 14a is connected in a forward direction from the antenna structure 12a toward the gate electrode G of the n-type MOSFET 10n. In addition, a second diode 16a is connected between the antenna structure 12a and the body or well electrode B. The second diode 16a is connected in a reverse direction from the antenna structure 12a toward the body or well electrode B.

[0062] Furthermore, one first diode 14b is connected between the antenna structure 12b and the gate electrode G of the p-type MOSFET 10p. The first diode 14b is connected in a reverse direction from the antenna structure 12b toward the gate electrode G of the p-type MOSFET 10p. Furthermore, one second diode 16b is connected between the antenna structure 12b and the body or well electrode B. The second diode 16b is connected in a forward direction from the antenna structure 12b toward the body or well electrode B.

[0063] The first diodes 14a and 14b and the second diodes 16a and 16b are made of polysilicon. For example, the polysilicon can be formed simultaneously with the polysilicon constituting the gate electrodes of the n-type MOSFET 10n and the p-type MOSFET 10p. The first diodes 14a and 14b and the second diodes 16a and 16b can be formed by adding n-type and p-type dopants to the polysilicon using multiple masks. For example, a doping process for the n+ gate electrodes and a doping process for the p+ gate electrodes of the n-type MOSFET 10n and the p-type MOSFET 10p can be used. However, other special polysilicon layers may be used. Other doping processes may also be applied. Furthermore, by changing the regions to which the n-type and p-type dopants are added, the first diode 14 and the second diode 16 can be formed in the opposite direction to that shown in FIG. 10 .

[0064] Note that multiple first diodes 14a may be connected in series. By connecting multiple first diodes 14a in series, the damage level in the n-type MOSFET 10n during the plasma-based manufacturing process can be determined from the damage. However, because the second diode 16a serves as a bypass path for reverse charge, it is more suitable to use a single diode rather than a series connection.

[0065] Alternatively, multiple first diodes 14b may be connected in series. By connecting multiple first diodes 14b in series, the damage level in the p-type MOSFET 10p during the plasma-based manufacturing process can be determined from the damage. However, because the second diode 16a serves as a bypass path for reverse charge, it is more suitable to use a single diode rather than a series connection.

[0066] [Configuration using SOI substrate] FIG. 11 shows a cross-sectional structure of a charge detection device 100 when the present invention is applied to an SOI-CMOS.

[0067] A buried oxide layer (BOX: Burried Oxide) 26 is provided on a p-type substrate 20. A p-type well 22p and an n-type well 22n are formed on the buried oxide layer 26. An n-type MOSFET 10n is formed in the p-type well 22p. A p-type MOSFET 10p is formed in the n-type well 22n. The elements are insulated from each other by a buried insulating layer (STI: Shallow Trench Isolation). A gate insulating film is formed on the surface of the substrate 20. In FIG. 11, the gap between the substrate 20 and the gate electrode represents the insulating film. Note that several layout ideas are known for connecting the body or well electrode in SOI-CMOS, but the details are not shown in FIG. 11.

[0068] 11, two first diodes 14a and 14b are connected between the antenna structure 12a and the gate electrode G of the n-type MOSFET 10n. The first diodes 14a and 14b are connected in the forward direction from the antenna structure 12a toward the gate electrode G of the n-type MOSFET 10n. The first diodes 14a and 14b are formed in a region of the n-type well 22n that is electrically isolated from other elements by the BOX and STI.

[0069] Two first diodes 14c and 14d are connected between the antenna structure 12b and the gate electrode G of the p-type MOSFET 10p. The first diodes 14c and 14d are connected in the forward direction from the antenna structure 12b toward the gate electrode G of the p-type MOSFET 10p. The first diodes 14c and 14d are formed in a region of a p-type well 22p that is electrically isolated from other elements in the SOI.

[0070] The charge detection device 200 can also be applied to SOI CMOS. That is, similar to the configuration shown in Fig. 11, a buried oxide layer 26 is provided in the substrate 20 to form an SOI structure, and the first diode 14 and the second diode 16 are formed in the SOI structure to form the charge detection device 200.

[0071] In this way, when SOI is used, the first diode 14 and the second diode 16 are formed in the bulk of the semiconductor substrate, thereby suppressing parasitic junctions in the first diode 14 and the second diode 16 and suppressing leakage current.

[0072] [Manufacturing method] 12 shows a method for manufacturing the charge detection device 100. Hereinafter, the method for manufacturing the charge detection device 100 will be described with reference to FIG.

[0073] First, as shown in FIG. 12(a), a buried insulating layer 24, which is an element isolation region, is formed in a p-type semiconductor substrate 20. The buried insulating layer 24 can be STI (Shallow Trench Isolation). The buried insulating layer 24 is formed to a depth of, for example, 300 nm. Next, after forming a mask by photolithography or the like, a p-type dopant is ion-implanted into the substrate 20 to form a p-type well 22p (PW). For example, boron (B) is implanted at 270 keV with a dose of 2.0×10 13 / cm2, 8.0 × 10 at 120 keV 12 / cm 2 and 2 × 10 at 40 keV 12 / cm2, and then a p-type well 22p is formed. Next, after forming a mask by photolithography or the like, an n-type dopant is ion-implanted into the substrate 20 to form an n-type well 22n (NW). For example, phosphorus (P) is ion-implanted at 2.0 × 10 13 / cm 2 , 8.0 × 10 at 240 keV 12 / cm 2 and 2 × 10 at 60 keV 12 / cm 2 The n-type well 22n is formed by multi-stage implantation using the above method. However, the dopant concentrations and dopant profiles of the p-type well 22p and the n-type well 22n are not limited to these, and may be any as long as they function as the p-type well 22p and the n-type well 22n.

[0074] Next, gate insulating films for the n-type MOSFET 10n and the p-type MOSFET 10p are formed on the surface of the substrate 20. The gate insulating film can be formed by, for example, an oxynitriding method. The thickness of the gate insulating film is preferably, for example, 3 nm. However, the method for forming the gate insulating film and its thickness are not limited to this, and may be set appropriately depending on the characteristics of the semiconductor elements formed on the substrate 20. The gate insulating film may be formed of a silicon oxide film (SiO2), a silicon nitride film (SiN), a silicon oxynitride film (SiO x N y 12, the gate insulating film is shown as a gap between the surface of the substrate 20 and the gate electrode, the first diode 14, and the second diode 16.

[0075] Next, as shown in FIG. 12(b), polysilicon that will become the gate electrodes G and first diodes 14 (14a to 14d) is formed. The polysilicon can be formed by chemical vapor deposition (CVD) or the like using a silicon-containing source gas such as silane (SiH4). The film thickness of the polysilicon can be, for example, 200 nm. The polysilicon is formed into the desired shapes of the gate electrodes G and first diodes 14 (14a to 14d) by applying photolithography and etching. However, the manufacturing method and film thickness of the polysilicon are not limited to this and can be set appropriately depending on the characteristics of the semiconductor device to be formed.

[0076] Thereafter, the source and drain regions of the n-type MOSFET 10n, the n-type polysilicon gate, and the n-type region of the first polysilicon diode 14 (14a to 14b) are formed. For example, photolithography is used to implant arsenic (As) into desired regions at 3×10 ion implantation energy of 23 keV. 15 / cm 2 Next, the source and drain regions of the p-type MOSFET 10p, the p-type polysilicon gate, and the p-type regions of the first polysilicon diodes 14 (14a to 14d) are formed. For example, boron fluoride (BF2) is implanted at a dose of 2×10 with an ion implantation energy of 13 keV. 15 / cm 2 However, the energy and dopant concentration of the ion implantation may be appropriately set depending on the required characteristics of the device.

[0077] At this time, in order to have different concentrations in the polysilicon regions of the first diode 14 (14a to 14d) during n-type and p-type ion implantation, an additional step may be provided to perform the ion implantation separately.

[0078] Generally, cobalt silicide is formed as the gate electrode and the source and drain regions, but it is necessary to prevent silicidation in the region of the first diode 14 (14a to 14d). Therefore, for example, a silicon nitride layer (SiN layer) is deposited as a silicide protection layer, and the regions corresponding to the gate electrode G and the source and drain regions are etched to form openings, and then a silicidation process is performed, thereby preventing silicidation of the polysilicon constituting the first diode 14 (14a to 14d).

[0079] The process of forming the first diode 14 can also be applied to the process of forming the second diode 16 in the charge detection device 200 in the same manner.

[0080] 12(c), the following steps are performed: depositing an interlayer insulating film, drilling contact holes, filling plugs, CMP, metal wiring including a desired antenna pattern for forming the antenna structure 12, forming contact electrodes, and wiring upper layers. Furthermore, the charge detection device 100 is manufactured through a back-end-of-line (BEOL) process. These steps can be performed in the same manner as in the manufacturing process of a general semiconductor device.

[0081] [Charge detection method] Hereinafter, a method for detecting electric charges from plasma in a semiconductor device manufacturing process using the electric charge detection device 100 will be described with reference to the flowchart of the electric charge detection method shown in FIG.

[0082] Charge detection processing is performed using a total of four types of charge detection devices 100, including two types of charge detection devices 100 using n-type MOSFETs 10 and two types of charge detection devices 100 using p-type MOSFETs 10, as shown in Figures 1 to 4.

[0083] In the first step S10, the shift amount of the threshold voltage Vth of each of the n-type MOSFET 10 and the p-type MOSFET 10, the decrease amount of the drain-source current, and the leakage current in the gate insulating film are measured.

[0084] In the second step S12, based on the measurement results, for example, when comparing the charge detection device 100 of the n-type MOSFET 10 shown in Fig. 1 with the charge detection device 100 of the n-type MOSFET 10 shown in Fig. 2, if the damage to the charge detection device 100 of the n-type MOSFET 10 shown in Fig. 1 is greater, it is determined that charging due to positive charges has occurred. Conversely, if the damage to the charge detection device 100 of the n-type MOSFET 10 shown in Fig. 2 is greater, it is determined that charging due to negative charges has occurred.

[0085] Similarly, in comparing the charge detection device 100 of the p-type MOSFET 10 shown in Fig. 3 with the charge detection device 100 of the p-type MOSFET 10 shown in Fig. 4, it is found that if the damage to the charge detection device 100 of the p-type MOSFET 10 shown in Fig. 3 is large, charging by positive charges has occurred. Conversely, if the damage to the charge detection device 100 of the p-type MOSFET 10 shown in Fig. 4 is large, it is found that charging by negative charges has occurred.

[0086] At this time, a phenomenon may occur in which none of the n-type MOSFETs 10 is damaged, but only one of the p-type MOSFETs 10 is damaged. Conversely, a phenomenon may occur in which none of the p-type MOSFETs 10 is damaged, but only one of the n-type MOSFETs 10 is damaged. Therefore, in preparation for such a phenomenon, it is preferable to check for damage in the four types of charge detection devices 100 shown in FIGS. 1 to 4.

[0087] In the third step S14, once the positive or negative charge has been determined, the level (degree) of charge is evaluated based on the number of first diodes 14 connected in series. For example, if damage is found in the n-type MOSFET 10 shown in FIG. 1, the level of positive charge is determined according to the number of first diodes 14 connected in series to that MOSFET 10. As a specific example, if damage has occurred in the n-type MOSFET 10 in which three first diodes 14 are connected in series, but no damage has occurred in the n-type MOSFET 10 in which four first diodes 14 are connected in series, the intensity of the positive charge is determined to be level 3. The level of charge can also be evaluated in the same way for the other types of charge detection devices 100 shown in FIGS. 2 to 4.

[0088] If damage is observed in both the charge detection device 100 including the n-type MOSFET 10 and the charge detection device 100 including the p-type MOSFET 10, it is preferable to evaluate the level of charge buildup in both. However, since the degree of damage differs between the n-type and the p-type, when comparing the degree of influence of charge in different processes, it is preferable to perform the evaluation based on the degree of damage between n-type charge detection devices 100 or the degree of damage between p-type charge detection devices 100.

[0089] Moreover, when the four types of charge detection devices 200 shown in FIGS. 6 to 9 are used, the charge detection process can be performed in the same manner as above.

[0090] [Configuration of the invention] [Configuration 1] A charge detection device for evaluating damage caused by electric charges generated during a semiconductor process, comprising: The antenna structure is formed on a semiconductor substrate, and the diode and the MOSFET are included. the diodes include a first diode; the first diode is connected between the antenna structure and the gate of the MOSFET and is connected to be in a forward direction with respect to a positive antenna charge generated in the antenna structure for positive charge detection; or the first diode is connected between the antenna structure and the gate of the MOSFET, and is connected in a forward direction with respect to negative antenna charge generated in the antenna structure for negative charge detection. [Configuration 2] The charge detection device according to configuration 1, the diode further includes a second diode; the second diode is connected between the antenna structure and a body or well of the MOSFET and is connected in a direction opposite to a positive antenna charge generated in the antenna structure for positive charge detection; or the second diode is connected between the antenna structure and a body or well of the MOSFET, and is connected in a direction opposite to a negative antenna charge generated in the antenna structure for detecting negative charges. [Configuration 3] The charge detection device according to any one of configurations 1 and 2, a plurality of the first diodes; A charge detection device, characterized in that a plurality of the first diodes are connected in series. [Configuration 4] 4. The charge detection device according to any one of configurations 1 to 3, wherein the diode is formed in a polysilicon layer insulated from the semiconductor substrate. [Configuration 5] The charge detection device according to any one of configurations 1 to 3, formed on an SOI substrate, The charge detection device is characterized in that the diode is formed in an active region of the SOI substrate and is insulated from the surroundings by an insulator and an element isolation region of the SOI substrate. [Configuration 6] 6. A charge detection method using the charge detection device according to any one of configurations 1 to 5 to evaluate damage caused by charges occurring during a process. [Configuration 7] The charge detection method according to configuration 6, A charge detection method comprising determining the polarity of the damaging charge based on the connection direction of the diode connected to the damaged MOSFET. [Configuration 8] The charge detection method according to any one of configurations 6 and 7, a charge detection method for evaluating the degree of damage based on the number of the first diodes connected in series with the damaged MOSFET; [Configuration 9] The charge detection method according to configuration 7, The charge detection method is characterized in that the degree of damage is evaluated by comparing damage between n-type MOSFETs or between p-type MOSFETs. [Configuration 10] A charge detection device for evaluating damage caused by electric charges generated during a semiconductor process, comprising: a first antenna structure formed on a semiconductor substrate; n-type MOSFET and a diode connected between the first antenna structure and the gate of the n-type MOSFET, the diode being connected in a forward direction with respect to a positive antenna charge generated in the first antenna structure for positive charge detection, or being connected in a forward direction with respect to a negative antenna charge generated in the first antenna structure for negative charge detection; a second antenna structure formed on the semiconductor substrate; p-type MOSFET and another diode connected between the second antenna structure and the gate of the p-type MOSFET, the diode being forward-connected with respect to a positive antenna charge generated in the second antenna structure for positive charge detection, or being forward-connected with respect to a negative antenna charge generated in the second antenna structure for negative charge detection; A charge detection device comprising: [Explanation of symbols]

[0091] 10 MOSFET, 12 (12a, 12b) antenna structure, 14 (14a to 14d) first diode, 16 (16a to 16d) second diode, 20 substrate, 22n n-type well, 22p p-type well, 24 buried insulating layer, 26 buried oxide layer, 100, 200 charge detection device.

Claims

1. A charge detection device for evaluating damage caused by electric charges generated during a semiconductor process, comprising: The antenna structure is formed on a semiconductor substrate, a diode, and a MOSFET; the diodes include a first diode; the first diode is connected between the antenna structure and the gate of the MOSFET and is connected in a forward direction with respect to a positive antenna charge generated in the antenna structure for detecting a positive charge; or a first diode connected between the antenna structure and the gate of the MOSFET, and connected in a forward direction with respect to negative antenna charge generated in the antenna structure for detecting negative charge;

2. 2. The charge detection device according to claim 1, the diode further includes a second diode; the second diode is connected between the antenna structure and a body or well of the MOSFET and is connected in a direction opposite to a positive antenna charge generated in the antenna structure for positive charge detection; or The charge detection device is characterized in that the second diode is connected between the antenna structure and the body or well of the MOSFET, and is connected in a direction opposite to the negative antenna charge generated in the antenna structure to detect negative charges.

3. 3. The charge detection device according to claim 1, a plurality of the first diodes; A charge detection device, characterized in that a plurality of the first diodes are connected in series.

4. 2. The charge detection device according to claim 1, wherein the diode is formed in a polysilicon layer insulated from the semiconductor substrate.

5. 2. The charge detection device according to claim 1, formed on an SOI substrate, The charge detection device is characterized in that the diode is formed in an active region of the SOI substrate and is insulated from the surroundings by an insulator and an element isolation region of the SOI substrate.

6. 10. A charge detection method, comprising: evaluating damage caused by electric charges occurring during a process, using the charge detection device according to claim 1.

7. 7. The charge detection method according to claim 6, A charge detection method characterized in that the polarity of the charge that caused damage is determined based on the connection direction of the diode connected to the damaged MOSFET.

8. 8. The charge detection method according to claim 6 or 7, A charge detection method comprising: evaluating the degree of damage based on the number of said first diodes connected in series with said damaged MOSFET.

9. 8. The charge detection method according to claim 7, The charge detection method is characterized in that the degree of damage is evaluated by comparing the damage between n-type MOSFETs or between p-type MOSFETs.

10. A charge detection device for evaluating damage caused by electric charges generated during a semiconductor process, comprising: a first antenna structure formed on a semiconductor substrate; an n-type MOSFET; a diode connected between the first antenna structure and the gate of the n-type MOSFET, the diode being connected in a forward direction with respect to a positive antenna charge generated in the first antenna structure for positive charge detection, or being connected in a forward direction with respect to a negative antenna charge generated in the first antenna structure for negative charge detection; a second antenna structure formed on the semiconductor substrate; a p-type MOSFET; another diode connected between the second antenna structure and the gate of the p-type MOSFET, the diode being connected in a forward direction with respect to a positive antenna charge generated in the second antenna structure for positive charge detection, or in a forward direction with respect to a negative antenna charge generated in the second antenna structure for negative charge detection; A charge detection device comprising:

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