Display device and method of manufacturing display device

Abstract

To reduce the number of times a second insulating film is processed.SOLUTION: A display device comprises a switching element, a first wiring, and a first terminal portion 37α. The switching element includes a first electrode formed of a first conductive film, a semiconductor portion disposed on the upper layer side via a first insulating film 31, and a second electrode and a third electrode each formed of a portion of a second conductive film disposed on the upper layer side of a semiconductor film. The first wiring is formed of a portion of a third conductive film disposed on the upper layer side of the second conductive film via a second insulating film 32. The first terminal portion 37α includes a first terminal component 37α1 formed of a portion of the second conductive film and a second terminal component 37α2 formed of a portion of the third conductive film. The second insulating film 32 includes a first contact hole disposed at a position overlapping both the first wiring and the second electrode, and a second contact hole CHT1 disposed at a position overlapping both the first terminal component 37α1 and the second terminal component 37α2.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a display device and a method for manufacturing a display device in which the number of times the second insulating film is processed is reduced. [Background technology]

[0002] One example of a conventional display device is known from Patent Document 1. The display device disclosed in Patent Document 1 has an active matrix substrate including a substrate, a first conductive layer, a second conductive layer, and an organic insulating film. In this active matrix substrate, the first conductive layer and the second conductive layer are partially laminated, the organic insulating film is disposed farther from the substrate than the first conductive layer and the second conductive layer, and the conductive layer of the first conductive layer or the second conductive layer that is disposed farther from the substrate is in contact with the organic insulating film via an inorganic insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-36012 Summary of the Invention [Problem to be solved by the invention]

[0004] The above-mentioned Patent Document 1 discloses a first source layer as a first conductive layer, a second source layer as a second conductive layer, and a second inorganic insulating film as an inorganic insulating film, and also discloses a first inorganic insulating film interposed between the first source layer and the second source layer. More specifically, in a region of an active matrix substrate where TFT elements and pixel electrodes are formed, a first inorganic insulating film is formed so as to have an opening above the first source layer which is a drain electrode, and the first source layer and the second source layer are electrically connected through this opening.

[0005] Incidentally, attachment components (drivers and flexible substrates) for supplying various signals are attached to the edge regions of the active matrix substrate, and terminal portions are provided at the attachment locations. These terminal portions connect the gate layer and the conductive member. To connect the gate layer and the conductive member, openings are provided in the gate insulating film, first inorganic insulating film, second inorganic insulating film, and organic insulating film interposed between them, so that they communicate with each other. Therefore, when manufacturing an active matrix substrate, it is necessary to perform at least the following steps: forming openings in the first inorganic insulating film in the region where the TFT elements and pixel electrodes are formed; and forming openings collectively in the gate insulating film, first inorganic insulating film, second inorganic insulating film, and organic insulating film in the edge regions. This has led to problems such as an increase in the number of times the first inorganic insulating film is processed and a long processing time. This problem tends to be particularly pronounced when the first inorganic insulating film is thick.

[0006] The technology described in this specification was developed based on the above circumstances, and aims to reduce the number of times the second insulating film is processed. [Means for solving the problem]

[0007] (1) A display device according to the technology described in this specification includes a display area where an image is displayed, a non-display area where the image is not displayed, a switching element disposed in the display area, a first wiring disposed in the display area and connected to the switching element, and a first terminal portion disposed in the non-display area, wherein the switching element includes a first electrode made of a first conductive film, a semiconductor portion formed of a semiconductor film disposed on an upper layer side of the first conductive film via a first insulating film and disposed so as to overlap the first electrode, a second conductive film disposed on an upper layer side of the semiconductor film and connected to the semiconductor portion, and a second electrode formed of a portion of the second conductive film different from the second electrode and connected to the semiconductor portion. the first wiring is made of a third conductive film disposed on an upper layer side of the second conductive film with a second insulating film interposed therebetween, and a portion of the first wiring is disposed so as to overlap with the second electrode; the first terminal portion has a first terminal component formed of a portion of the second conductive film different from the second electrode and the third electrode, and a second terminal component formed of a portion of the third conductive film different from the first wiring, and at least a portion of the first terminal component is disposed so as to overlap with the first terminal component; and the second insulating film is provided with a first contact hole disposed at a position overlapping with both the first wiring and the second electrode, and a second contact hole disposed at a position overlapping with both the first terminal component and the second terminal component.

[0008] (2) In addition to (1), the display device may further include a second wiring arranged in the display area, the second wiring consisting of a portion of the second conductive film that is different from the second electrode, the third electrode, and the first terminal component, and may be connected to the second electrode, extend along the first wiring, and be arranged to overlap the first wiring via the second insulating film.

[0009] (3) In addition to (1), the display device may further include a third wiring arranged in the display area, the third wiring being made of a part of the first conductive film that is different from the first electrode, connected to the first electrode, and intersecting with the first wiring via the first insulating film and the second insulating film.

[0010] (4) Furthermore, in addition to any one of (1) to (3), the display device may further include a fourth electrode arranged in the display area and connected to the third electrode, and a pixel electrode arranged in the display area and connected to the fourth electrode, wherein the fourth electrode is made of a part of the third conductive film that is different from the first wiring, and at least a portion of the fourth electrode is arranged overlapping with the third electrode, the pixel electrode is made of a fourth conductive film arranged on the upper side of the third conductive film via a third insulating film, and a portion of the pixel electrode is arranged overlapping with the fourth electrode, the second insulating film may be provided with a third contact hole arranged at a position overlapping with both the third electrode and the fourth electrode, and the third insulating film may be provided with a fourth contact hole arranged at a position overlapping with both the fourth electrode and the pixel electrode.

[0011] (5) Furthermore, in addition to any one of (1) to (3), the display device may further include a pixel electrode arranged in the display area and connected to the third electrode, the pixel electrode being made of a fourth conductive film arranged above the third conductive film via a third insulating film, a portion of which is arranged overlapping with the third electrode, and a fifth contact hole arranged in communication with the second insulating film and the third insulating film and positioned to overlap with both the third electrode and the pixel electrode.

[0012] (6) A display device according to the technology described in this specification includes a display area where an image is displayed, a non-display area where the image is not displayed, a switching element arranged in the display area, a first wiring arranged in the display area and connected to the switching element, a pixel electrode arranged in the display area and connected to the switching element, a common electrode arranged in the display area, and a second terminal section arranged in the non-display area, wherein the switching element has a first electrode made of a first conductive film, a semiconductor section made of a semiconductor film arranged on the upper side of the first conductive film with a first insulating film interposed therebetween and arranged to overlap with the first electrode, a second electrode made of a second conductive film arranged on the upper side of the semiconductor film and connected to the semiconductor section, and a third electrode made of a portion of the second conductive film different from the second electrode and connected to the semiconductor section, wherein the first wiring is made of a third conductive film arranged on the upper side of the second conductive film with a second insulating film interposed therebetween, and a portion of the common electrode overlapping the second electrode, the pixel electrode being made of a fourth conductive film arranged above the third conductive film with a third insulating film interposed therebetween, and a portion of the common electrode overlapping the third electrode and connected to the third electrode, the common electrode being made of a fifth conductive film arranged above the fourth conductive film with a fourth insulating film interposed therebetween, and being arranged to overlap the pixel electrode with the fourth insulating film interposed therebetween, the second terminal portion having a third terminal component consisting of a portion of the third conductive film different from the first wiring, and a fourth terminal component consisting of a portion of the fifth conductive film different from the common electrode, and at least a portion of which overlaps with the third terminal component, the second insulating film being provided with a first contact hole arranged at a position overlapping with both the first wiring and the second electrode, and the third insulating film and the fourth insulating film being provided with a sixth contact hole communicating with each other and arranged at a position overlapping with both the third terminal component and the fourth terminal component.

[0013] (7) A display device according to the technology described in this specification includes a display area where an image is displayed, a non-display area where the image is not displayed, a switching element arranged in the display area, a first wiring arranged in the display area and connected to the switching element, a pixel electrode arranged in the display area and connected to the switching element, a common electrode arranged in the display area, and a third terminal section arranged in the non-display area, wherein the switching element has: a first electrode made of a first conductive film; a semiconductor section made of a semiconductor film arranged on the upper layer side of the first conductive film via a first insulating film and arranged to overlap with the first electrode; a second electrode made of a second conductive film arranged on the upper layer side of the semiconductor film and connected to the semiconductor section; and a third electrode made of a part of the second conductive film different from the second electrode and connected to the semiconductor section, wherein the first wiring is arranged on the second conductive film via a second insulating film the pixel electrode is made of a fourth conductive film arranged on the upper side of the third conductive film with a third insulating film interposed therebetween, and a portion of the common electrode is arranged so as to overlap with the pixel electrode with the fourth insulating film interposed therebetween; the common electrode is made of a fifth conductive film arranged on the upper side of the fourth conductive film with a fourth insulating film interposed therebetween, and is arranged so as to overlap with the pixel electrode with the fourth insulating film interposed therebetween; the third terminal portion has a fifth terminal component consisting of a portion of the fourth conductive film different from the pixel electrode, and a sixth terminal component consisting of a portion of the fifth conductive film different from the common electrode with at least a portion of the fifth terminal component arranged so as to overlap with the fifth terminal component; the second insulating film is provided with a first contact hole arranged at a position overlapping with both the first wiring and the second electrode, and the fourth insulating film is provided with a seventh contact hole arranged at a position overlapping with both the fifth terminal component and the sixth terminal component.

[0014] (8) A method for manufacturing a display device according to the technology described in this specification includes forming a first conductive film, patterning the first conductive film to provide a first electrode in a display area where an image is displayed, forming a first insulating film on an upper layer side of the first conductive film, forming a semiconductor film on an upper layer side of the first insulating film, patterning the semiconductor film to provide a semiconductor portion superimposed on the first electrode, forming a second conductive film on an upper layer side of the semiconductor film, patterning the second conductive film to provide a second electrode connected to the semiconductor portion and a third electrode connected to the semiconductor portion, and providing a first terminal component in a non-display area where the image is not displayed, and forming a first insulating film on an upper layer side of the second conductive film. a second insulating film is formed on the upper layer side of the second insulating film, and the second insulating film is patterned to provide a first contact hole arranged at a position overlapping the second electrode and a second contact hole arranged at a position overlapping the first terminal component; a third conductive film is formed on the upper layer side of the second insulating film, and the third conductive film is patterned to provide a first wiring arranged in the display area, a portion of which overlaps with the second electrode and the first contact hole; and a second terminal component arranged in the non-display area, at least a portion of which overlaps with the first terminal component and the second contact hole, and which constitutes a first terminal component together with the first terminal component. [Effects of the Invention]

[0015] According to the technique described in this specification, the number of times the second insulating film is processed can be reduced. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a plan view of a liquid crystal panel and the like that constitute a liquid crystal display device according to Embodiment 1. [Figure 2] 1 is a schematic cross-sectional view of a liquid crystal panel according to a first embodiment. [Figure 3] 1 is a plan view of a display area of ​​an array substrate that constitutes a liquid crystal panel according to Embodiment 1. [Figure 4] 1 is a cross-sectional view of the pixel electrode and its vicinity on an array substrate according to Embodiment 1. [Figure 5]FIG. 1 is a plan view showing a pixel arrangement on an array substrate according to a first embodiment; [Figure 6] 6 is a cross-sectional view of the array substrate according to the first embodiment taken along line vi-vi in ​​FIG. 5 . [Figure 7] FIG. 1 is a plan view showing a configuration in the vicinity of a driver arrangement region of an array substrate according to a first embodiment; [Figure 8] 1 is a bottom view of a driver according to a first embodiment; [Figure 9] 1 is a cross-sectional view showing a connection state between a terminal portion of an array substrate and a bump of a driver according to the first embodiment; [Figure 10] 1 is a cross-sectional view of the first terminal portion and its vicinity in the array substrate according to the first embodiment; [Figure 11] 1 is a cross-sectional view of a terminal portion as a reference example of the array substrate according to the first embodiment; [Figure 12A] 7 is a cross-sectional view similar to FIG. 6 showing a state in which a first metal film is patterned in a first step included in the manufacturing method of the array substrate according to the first embodiment; FIG. [Figure 12B] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the semiconductor film is patterned in a second step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 12C] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the second metal film is patterned in a fourth step included in the method for manufacturing the array substrate according to the first embodiment; FIG. [Figure 13A] 11 is a cross-sectional view similar to FIG. 10 illustrating a state in which the first metal film is patterned in a first step included in the method for manufacturing the array substrate according to the first embodiment; [Figure 13B] 11 is a cross-sectional view similar to FIG. 10 showing a state in which the semiconductor film is patterned in a second step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 13C] 11 is a cross-sectional view similar to FIG. 10 illustrating a state in which the second metal film is patterned in a fourth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 14A] 12 is a cross-sectional view similar to FIG. 11 illustrating a state in which the first metal film is patterned in a first step included in the manufacturing method of the array substrate according to the first embodiment; FIG. [Figure 14B]12 is a cross-sectional view similar to FIG. 11 showing a state in which the semiconductor film is patterned in a second step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 14C] 12 is a cross-sectional view similar to FIG. 11 showing a state in which the gate insulating film is patterned in a third step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 14D] 12 is a cross-sectional view similar to FIG. 11 illustrating a state in which the second metal film is patterned in a fourth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 15A] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the first interlayer insulating film is patterned in a fifth step included in the method for manufacturing the array substrate according to the first embodiment; FIG. [Figure 15B] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the third metal film is patterned in a sixth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 15C] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the planarization film is patterned in a seventh step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 16A] 11 is a cross-sectional view similar to FIG. 10 illustrating a state in which the first interlayer insulating film is patterned in a fifth step included in the method for manufacturing the array substrate according to the first embodiment; [Figure 16B] 11 is a cross-sectional view similar to FIG. 10 illustrating a state in which the third metal film is patterned in a sixth step included in the method for manufacturing the array substrate according to the first embodiment; [Figure 16C] 11 is a cross-sectional view similar to FIG. 10 illustrating a state in which the planarization film is patterned in a seventh step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 17A] 12 is a cross-sectional view similar to FIG. 11 illustrating a state in which the first interlayer insulating film is patterned in a fifth step included in the method for manufacturing the array substrate according to the first embodiment; FIG. [Figure 17B] 12 is a cross-sectional view similar to FIG. 11 illustrating a state in which the third metal film is patterned in a sixth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 17C]12 is a cross-sectional view similar to FIG. 11 illustrating a state in which the planarization film is patterned in a seventh step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 18A] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the second interlayer insulating film is patterned in an eighth step included in the method for manufacturing the array substrate according to the first embodiment; FIG. [Figure 18B] 7 is a cross-sectional view similar to FIG. 6 illustrating a state in which the first transparent electrode film and the fourth metal film are patterned in a ninth step included in the manufacturing method of the array substrate according to the first embodiment. [Figure 18C] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the fourth metal film is patterned in a tenth step included in the method for manufacturing the array substrate according to the first embodiment; FIG. [Figure 19A] 11 is a cross-sectional view similar to FIG. 10 illustrating a state in which the second interlayer insulating film is patterned in an eighth step included in the method for manufacturing the array substrate according to the first embodiment; [Figure 19B] 11 is a cross-sectional view similar to FIG. 10 illustrating a state in which the first transparent electrode film and the fourth metal film are patterned in a ninth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 19C] 11 is a cross-sectional view similar to FIG. 10 illustrating a state in which the fourth metal film is patterned in a tenth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 20A] 12 is a cross-sectional view similar to FIG. 11 illustrating a state in which the second interlayer insulating film is patterned in an eighth step included in the method for manufacturing the array substrate according to the first embodiment; FIG. [Figure 20B] 12 is a cross-sectional view similar to FIG. 11 illustrating a state in which the first transparent electrode film and the fourth metal film are patterned in a ninth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 20C] 12 is a cross-sectional view similar to FIG. 11 illustrating a state in which the fourth metal film is patterned in a tenth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 21A] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the third interlayer insulating film is patterned in an eleventh step included in the method for manufacturing the array substrate according to the first embodiment; FIG. [Figure 21B]7 is a cross-sectional view similar to FIG. 6 showing a state in which the second transparent electrode film is patterned in a twelfth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 22A] 11 is a cross-sectional view similar to FIG. 10 illustrating a state in which the third interlayer insulating film is patterned in an eleventh step included in the method for manufacturing the array substrate according to the first embodiment; [Figure 22B] 11 is a cross-sectional view similar to FIG. 10 illustrating a state in which the second transparent electrode film is patterned in a twelfth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 23A] 12 is a cross-sectional view similar to FIG. 11 illustrating a state in which the third interlayer insulating film is patterned in an eleventh step included in the method for manufacturing the array substrate according to the first embodiment; FIG. [Figure 23B] 12 is a cross-sectional view similar to FIG. 11 illustrating a state in which the second transparent electrode film is patterned in a twelfth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 24] FIG. 10 is a plan view showing a pixel arrangement on an array substrate according to a second embodiment. [Figure 25] 25 is a cross-sectional view of the array substrate according to the second embodiment taken along line xxv-xxv in FIG. 24. [Figure 26] 26 is a cross-sectional view of the array substrate according to the second embodiment taken along line xxvi-xxvi in ​​FIG. 24. [Figure 27] 6A and 6B are cross-sectional views of an array substrate according to a third embodiment of the present invention; [Figure 28A] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the first interlayer insulating film is patterned in a fifth step included in the method for manufacturing an array substrate according to the third embodiment; FIG. [Figure 28B] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the third metal film is patterned in a sixth step included in the method for manufacturing the array substrate according to the third embodiment. [Figure 28C] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the planarization film is patterned in a seventh step included in the method for manufacturing an array substrate according to the third embodiment. [Figure 29A] 8 is a cross-sectional view similar to FIG. 6 showing a state in which the first interlayer insulating film and the second interlayer insulating film are patterned in an eighth step included in the method for manufacturing an array substrate according to the third embodiment. [Figure 29B] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the first transparent electrode film and the fourth metal film are patterned in a ninth step included in the method for manufacturing an array substrate according to the third embodiment. [Figure 29C] 10 is a cross-sectional view similar to FIG. 6 illustrating a state in which the fourth metal film is patterned in a tenth step included in the method for manufacturing an array substrate according to the third embodiment. [Figure 30] 10 is a cross-sectional view of the first terminal portion and its vicinity in the array substrate according to the fourth embodiment. [Figure 31] 10 is a cross-sectional view showing a case where a lead wire made of a second metal film according to a fourth embodiment is connected to a first terminal portion; [Figure 32] 10 is a cross-sectional view showing a case where a lead wire made of a first metal film according to a fourth embodiment is connected to a first terminal portion; [Figure 33] 10 is a cross-sectional view of the first terminal portion and its vicinity in the array substrate according to the fifth embodiment. [Figure 34] 10 is a cross-sectional view showing a case where a lead wire made of a third metal film according to a fifth embodiment is connected to a first terminal portion; [Figure 35] 10 is a cross-sectional view showing a case where a lead wire made of a second metal film according to a fifth embodiment is connected to a first terminal portion; [Figure 36] 10 is a cross-sectional view showing a case where a lead wire made of a first metal film according to a fifth embodiment is connected to a first terminal portion; [Figure 37] 13 is a cross-sectional view of the array substrate according to the sixth embodiment, showing the vicinity of a second terminal portion. [Figure 38] 37 in the array substrate according to the sixth embodiment. [Figure 39] 13 is a cross-sectional view of the array substrate according to the seventh embodiment, showing the vicinity of a third terminal portion. [Figure 40] 39 in the array substrate according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] <Embodiment 1> Embodiment 1 will be described with reference to Fig. 1 to Fig. 23B. In this embodiment, a liquid crystal display device 10 having a display function and a touch panel function (position input function) will be illustrated. Note that X-axis, Y-axis, and Z-axis are shown in some of the drawings, and each axis direction is drawn to correspond to the direction shown in each drawing.

[0018] As shown in Fig. 1, a liquid crystal display device 10 includes at least a horizontally elongated rectangular liquid crystal panel (display device, display panel) 11 capable of displaying images, and a backlight device (illumination device) that is an external light source that irradiates the liquid crystal panel 11 with light to be used for display. The backlight device is disposed on the rear side (back surface) of the liquid crystal panel 11 and includes a light source (e.g., an LED) that emits white light and optical components that convert the light from the light source into planar light by applying an optical effect to the light. The central portion of the screen of the liquid crystal panel 11 is a display area AA where an image is displayed. In contrast, the frame-shaped outer peripheral portion surrounding the display area AA on the screen of the liquid crystal panel 11 is a non-display area NAA where no image is displayed.

[0019] As shown in Fig. 1, a circuit section (peripheral circuit section, gate circuit section) 14 is provided in the non-display area NAA of the liquid crystal panel 11. A pair of circuit sections 14 are arranged so as to sandwich the display area AA from both sides in the X-axis direction. The circuit section 14 is provided in a strip-shaped range extending along the Y-axis direction. The circuit section 14 is for supplying scanning signals to gate wiring 26 (described later), and is provided monolithically on an array substrate 21 (described later). The circuit section 14 is a GDM (Gate Driver Monolithic) circuit. The circuit section 14 includes a shift register circuit that outputs scanning signals at predetermined timing, a buffer circuit that amplifies the scanning signals, and the like.

[0020] The liquid crystal panel 11 will be described in detail with reference to FIG. 1 and FIG. 2. As shown in FIGS. 1 and 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21 together. The front side (front surface) of the pair of substrates 20 and 21 is a counter substrate (CF substrate, second substrate) 20, and the back side (rear surface) is an array substrate (active matrix substrate, first substrate) 21. The counter substrate 20 and the array substrate 21 are each formed by laminating various films on the inner surface of glass substrates (substrates) 20GS and 21GS. A liquid crystal layer (medium layer) 22 containing liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied, is disposed between the pair of substrates 20 and 21. A seal portion 23 that seals the liquid crystal layer 22 is disposed between the outer peripheral edges of the pair of substrates 20 and 21. The seal portion 23 is formed in a rectangular frame shape (endless ring) so as to surround the liquid crystal layer 22. A polarizing plate 15 is attached to the outer surface of each of the substrates 20 and 21.

[0021] 1 and 2, the short side dimension of the counter substrate 20 is shorter than the short side dimension of the array substrate 21. The counter substrate 20 is attached to the array substrate 21 so that one end in the short side direction (Y-axis direction) is aligned with the array substrate 21. Therefore, the other end in the short side direction of the array substrate 21 is an exposed portion 21A that protrudes laterally from the counter substrate 20 and is exposed. The entire exposed portion 21A is a non-display area NAA, and is equipped with a driver (signal supply unit) 12 and a flexible substrate 13 for supplying various signals related to the display function and touch panel function described below.

[0022] The driver 12 shown in FIGS. 1 and 2 is an LSI chip with an internal drive circuit. The driver 12 is mounted on the exposed portion 21A of the array substrate 21 using COG (Chip On Glass) technology. The driver 12 processes various signals transmitted by the flexible substrate 13. The driver 12 supplies various signals (e.g., image signals, touch signals, etc.) to wiring in the display area AA (specifically, source wiring 27 and touch wiring 30, which will be described later). The flexible substrate 13 is configured by forming multiple wiring patterns on a base material made of an insulating and flexible synthetic resin material (e.g., polyimide resin). As shown in FIGS. 1 and 2, one end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit board (e.g., a control board). The flexible substrate 13 is connected to the end of the exposed portion 21A on the opposite side of the display area AA from the driver 12 in the Y-axis direction.

[0023] The liquid crystal panel 11 according to this embodiment has both a display function for displaying images and a touch panel function for detecting a position (input position) at which a user inputs information based on the displayed image. A touch panel pattern for achieving the touch panel function is integrated (in-cell) into the liquid crystal panel 11. This touch panel pattern is a so-called projected capacitive type, and its detection method is a self-capacitive type. As shown in FIG. 1 , the touch panel pattern is composed of a plurality of touch electrodes (position detection electrodes) 29 arranged in a matrix on the main surface of the liquid crystal panel 11. The touch electrodes 29 are arranged in a display area AA of the liquid crystal panel 11. Therefore, the display area AA of the liquid crystal panel 11 substantially coincides with a touch area (position input area) where an input position can be detected, and the non-display area NAA substantially coincides with a non-touch area (non-position input area) where an input position cannot be detected. When a user approaches a conductive finger (position input object) to the surface (display surface) of the liquid crystal panel 11 to input a position based on the image in the display area AA of the liquid crystal panel 11 that the user is viewing, a capacitance is formed between the finger and the touch electrodes 29. As a result, the capacitance detected at the touch electrodes 29 near the finger changes as the finger approaches, and becomes different from that of the touch electrodes 29 farther away from the finger, making it possible to detect the input position based on this. Note that the specific number of touch electrodes 29 installed can be changed as appropriate, in addition to the number shown in FIG. 1. The touch electrodes 29 are substantially rectangular in plan view, with each side measuring approximately several millimeters. Therefore, the size of the touch electrodes 29 in plan view is much larger than a pixel (described later) and is arranged in an area spanning multiple pixels in the X-axis and Y-axis directions.

[0024] 1, a plurality of touch wirings (position detection wirings) 30 provided on the liquid crystal panel 11 are selectively connected to the plurality of touch electrodes 29. The touch wirings 30 extend roughly along the Y-axis direction, with one end connected to the driver 12 in the non-display area NAA and the other end connected to a specific touch electrode 29 among the plurality of touch electrodes 29 arranged along the Y-axis direction in the display area AA. The touch wirings 30 are further connected to a detection circuit. The detection circuit may be provided in the driver 12, or may be provided outside the liquid crystal panel 11 via the flexible substrate 13. The detailed configuration of the touch wirings 30 will be described again later.

[0025] Next, the configuration of the display area AA of the array substrate 21 will be described with reference to FIG. 3. As shown in FIG. 3, at least TFTs (switching elements) 24 and pixel electrodes 25 are provided on the inner surface of the display area AA of the array substrate 21. The TFTs 24 and pixel electrodes 25 are arranged in a matrix (row and column) with multiple TFTs 24 and multiple pixel electrodes 25 spaced apart along the X-axis and Y-axis directions. Gate wiring (third wiring, scanning wiring) 26 and source wiring (image wiring, signal wiring) 27 are arranged around these TFTs 24 and pixel electrodes 25, intersecting each other at right angles (intersecting). The gate wiring 26 extends along the X-axis direction, and multiple gate wirings 26 are arranged at intervals along the Y-axis direction. The source wirings 27 extend along the Y-axis direction (first direction), and multiple source wirings 27 are arranged at intervals along the X-axis direction (second direction intersecting the first direction). The TFT 24 has a gate electrode (first electrode) 24A connected to the gate line 26, a source electrode (second electrode) 24B connected to the source line 27, a drain electrode (third electrode) 24C connected to the pixel electrode 25, and a semiconductor portion 24D connected to the source electrode 24B and the drain electrode 24C. The TFT 24 is driven based on a scanning signal supplied to the gate electrode 24A by the gate line 26. This scanning signal includes a potential higher than the threshold voltage of the TFT 24. Then, a potential related to an image signal (signal) supplied from the driver 12 to the source electrode 24B by the source line 27 is supplied to the drain electrode 24C via the semiconductor portion 24D. As a result, the pixel electrode 25 is charged to the potential related to the image signal. The pixel electrode 25 is disposed in a region surrounded by the gate line 26 and the source line 27, and has a planar shape of, for example, a substantially rectangular shape.

[0026] In addition, a plurality of color filters are provided in the display area AA of the counter substrate 20 at positions facing each pixel electrode 25 on the array substrate 21 side. The color filters are composed of three colors, R (red), G (green), and B (blue), repeatedly arranged in a predetermined order, and together with the pixel electrodes 25, form pixels of each color (red pixels, green pixels, and blue pixels). The three pixels, red, green, and blue pixels, form display pixels capable of displaying a predetermined color gradation. In addition, a light-shielding portion (black matrix) is formed between each color filter to prevent color mixing. Note that, of both substrates 20 and 21, an alignment film for aligning the liquid crystal molecules contained in the liquid crystal layer 22 is formed on the innermost surface (top layer) that contacts the liquid crystal layer 22.

[0027] Next, a cross-sectional configuration of the array substrate 21 near the center of the pixel electrode 25 will be described with reference to FIG. 4. As shown in FIG. 4, a common electrode 28 is formed on the inner surface of the display area AA of the array substrate 21 so as to overlap all of the pixel electrodes 25. The common electrode 28 extends across almost the entire display area AA. A slit 28S is formed in each of the portions of the common electrode 28 that overlap with each pixel electrode 25. The common electrode 28 is disposed above the pixel electrodes 25 (toward the liquid crystal layer 22) via a third interlayer insulating film 35, which will be described later. A common potential signal serving as a common potential (reference potential) is supplied to the common electrode 28. When the pixel electrodes 25 are charged to a potential based on an image signal transmitted to the source line 27 as the TFTs 24 are driven, a potential difference is generated between the pixel electrodes 25 and the common electrode 28. As a result, a fringe electric field (oblique electric field) including a component normal to the main surface of the array substrate 21, as well as a component along the main surface of the array substrate 21, is generated between the opening edge of the slit 28S in the common electrode 28 and the pixel electrode 25. Therefore, by utilizing this fringe electric field, the orientation state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled, and a predetermined display is performed based on the orientation state of the liquid crystal molecules. In other words, the liquid crystal panel 11 according to this embodiment operates in FFS (Fringe Field Switching) mode.

[0028] As shown in FIG. 1 , the common electrode 28 constitutes the touch electrode 29 described above. The common electrode 28 has partition openings (partition slits) 28A that separate adjacent touch electrodes 29. The partition openings 28A include a first partition opening 28A1 that crosses the entire length of the common electrode 28 substantially along the X-axis direction and a second partition opening 28A2 that crosses the entire length of the common electrode 28 substantially along the Y-axis direction, forming a substantially lattice-like shape in a plan view. The common electrode 28 is divided by the partition openings 28A into a substantially grid-like pattern in a plan view, and is composed of a plurality of electrically independent touch electrodes 29. The touch electrodes 29 aligned along the Y-axis direction are separated by the first partition openings 28A1, whereas the touch electrodes 29 aligned along the X-axis direction are separated by the second partition openings 28A2. A common potential signal related to the image display function and a touch signal (position detection signal) related to the touch panel function are supplied in a time-division manner from the driver 12 to the touch wiring 30 connected to such touch electrode 29. The timing when the common potential signal is supplied from the driver 12 to the touch wiring 30 is the display period, and the timing when the touch signal is supplied from the driver 12 to the touch wiring 30 is the sensing period (position detection period). This common potential signal is transmitted to all touch wirings 30 at the same timing (display period), so that all touch electrodes 29 have a common potential (reference potential) based on the common potential signal and function as the common electrode 28.

[0029] 4 and 5, the touch wiring 30 is arranged to overlap the source wiring 27 in a plan view. As shown in FIG. 1, the touch wiring 30 is arranged across a first partition opening 28A1 that separates the touch electrodes 29 adjacent to each other in the Y-axis direction.

[0030] Here, various films laminated on the inner surface side of the array substrate 21 will be described with reference to Fig. 6. Fig. 6 shows a cross-sectional configuration of the array substrate 21 near the TFT 24. As shown in Fig. 6, on the glass substrate (substrate) 21GS of the array substrate 21, from the lower layer side (glass substrate 21GS side), a first metal film (first conductive film) M1, a gate insulating film (first insulating film) 31, a semiconductor film S1, a second metal film (second conductive film) M2, a first interlayer insulating film (second insulating film) 32, a third metal film (third conductive film) M3, a second interlayer insulating film (third insulating film) 33, a planarizing film (third insulating film) 34, a first transparent electrode film (fourth conductive film) T1, a fourth metal film (fourth conductive film) M4, a third interlayer insulating film (fourth insulating film) 35, a second transparent electrode film (fifth conductive film) T2, and an alignment film are laminated. Of these, the first metal film M1 is shown in Figures 13A and 14A, the semiconductor film S1 is shown in Figures 12B, 13B and 14B, the second metal film M2 is shown in Figures 12C, 13C and 14D, the third metal film M3 is shown in Figures 15B, 16B and 17B, the first transparent electrode film T1 and the fourth metal film M4 are shown in Figures 18B, 19B and 20B, and the second transparent electrode film T2 is shown in Figures 21B, 22B and 23B.

[0031] The first metal film M1, the second metal film M2, the third metal film M3, and the fourth metal film M4 are each a single layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials, and are therefore conductive and light-blocking. The first metal film M1 constitutes the gate line 26, the gate electrode 24A of the TFT 24, etc. The second metal film M2 constitutes a part of the source line 27, the source electrode 24B and the drain electrode 24C of the TFT 24, etc. The third metal film M3 constitutes a part of the source line 27, etc. The fourth metal film M4 constitutes a part of the touch line 30, a part of the pixel electrode 25, etc. The first transparent electrode film T1 and the second transparent electrode film T2 are made of a transparent electrode material (e.g., ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), etc.). The first transparent electrode film T1 constitutes a part of the touch line 30, a part of the pixel electrode 25, etc. The second transparent electrode film T2 constitutes the common electrode 28 (touch electrode 29), etc. The alignment film is as described above.

[0032] The semiconductor film S1 is made of an oxide semiconductor material and constitutes the semiconductor portion 24D of the TFT 24. The semiconductor film S1 may contain at least one metal element selected from the group consisting of In, Ga, and Zn, and may be, for example, an In-Ga-Zn-O-based semiconductor (e.g., indium gallium zinc oxide). The In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc). The ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and examples include In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, and In:Ga:Zn=1:1:2. The In-Ga-Zn-O-based semiconductor used in the semiconductor film S1 may be amorphous or crystalline. The semiconductor film S1 may contain other oxide semiconductors instead of the In-Ga-Zn-O-based semiconductor. For example, an In—Sn—Zn—O based semiconductor (e.g., In2O3—SnO2—ZnO; InSnZnO) may be included. The In—Sn—Zn—O based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may include an In-W-Zn-O-based semiconductor containing W (tungsten), an In-W-Sn-Zn-O-based semiconductor, an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O-based semiconductor, a Cd-Ge-O-based semiconductor, a Cd-Pb-O-based semiconductor, CdO (cadmium oxide), an Mg-Zn-O-based semiconductor, an In-Ga-Sn-O-based semiconductor, an In-Ga-O-based semiconductor, a Zr-In-Zn-O-based semiconductor, an Hf-In-Zn-O-based semiconductor, an Al-Ga-Zn-O-based semiconductor, a Ga-Zn-O-based semiconductor, an In-Ga-Zn-Sn-O-based semiconductor, etc. The oxide semiconductor material of the semiconductor film S1 has a characteristic of having a higher resistance value when no voltage is applied (off state) compared to a polysilicon semiconductor material. Moreover, the oxide semiconductor material of the semiconductor film S1 has a higher electron mobility than the amorphous silicon semiconductor material.

[0033] The gate insulating film 31, the first interlayer insulating film 32, the second interlayer insulating film 33, and the third interlayer insulating film 35 are each made of silicon nitride (SiN xThe first interlayer insulating film 32 is an inorganic insulating film made of an inorganic material such as silicon dioxide (SiO2). The thicknesses of the gate insulating film 31, the first interlayer insulating film 32, the second interlayer insulating film 33, and the third interlayer insulating film 35 are greater than the thicknesses of the first transparent electrode film T1 and the second transparent electrode film T2. Of these, the first interlayer insulating film 32, which is stacked on the upper side of the semiconductor film S1, not only contains silicon dioxide as an inorganic material but also has a greater thickness than the other inorganic insulating films, the gate insulating film 31, the second interlayer insulating film 33, and the third interlayer insulating film 35. The first interlayer insulating film 32 is configured in this manner, making it difficult for impurities (e.g., moisture) to diffuse from layers above the first interlayer insulating film 32 (e.g., the planarizing film 34) to the semiconductor film S1. This improves the operational reliability of the TFTs 24 including the semiconductor portions 24D made of the semiconductor film S1 and also improves the yield of the array substrate 21. The planarizing film 34 is an organic insulating film made of an organic material such as PMMA (acrylic resin). The thickness of the planarization film 34 is much greater than the thicknesses of the gate insulating film 31, the first interlayer insulating film 32, the second interlayer insulating film 33, and the third interlayer insulating film 35. The planarization film 34 flattens the inner surface of the array substrate 21 (the surface on the liquid crystal layer 22 side).

[0034] The structure of the TFT 24 will be described in detail. As shown in FIGS. 5 and 6, the TFT 24 has a gate electrode 24A made of a portion of the first metal film M1, which is located below a semiconductor portion 24D made of a portion of the semiconductor film S1, with a gate insulating film 31 interposed between them. In other words, the TFT 24 can be considered a bottom-gate transistor. The gate electrode 24A is formed by a portion of the gate wiring 26 extending along the X-axis direction (a portion overlapping with the semiconductor portion 24D). The source electrode 24B and the drain electrode 24C, each made of a portion of the second metal film M2, are spaced apart in the X-axis direction, and each portion is connected directly to the upper side of the semiconductor portion 24D. The source electrode 24B is formed by a partially widened portion of the source wiring 27. More specifically, the line width of the source wiring 27 at a portion intersecting with the gate wiring 26 is wider than the remaining portion, and this wider portion constitutes the source electrode 24B. An intermediate electrode (fourth electrode) 36 made of a third metal film M3 is disposed so as to overlap the end of the drain electrode 24C opposite the semiconductor portion 24D side. A first pixel contact hole (third contact hole) CHP1 is opened in the first interlayer insulating film 32 interposed between the drain electrode 24C and the intermediate electrode 36. The drain electrode 24C and the intermediate electrode 36 are connected through the first pixel contact hole CHP1. The intermediate electrode 36 is disposed so as to overlap a portion of the pixel electrode 25. A second pixel contact hole (fourth contact hole) CHP2 is formed in the second interlayer insulating film 33 and the planarization film 34 interposed between the intermediate electrode 36 and a portion of the pixel electrode 25, communicating with the second pixel contact hole CHP2. The intermediate electrode 36 and the pixel electrode 25 are connected through the second pixel contact hole CHP2.

[0035] As shown in FIGS. 4 and 6 , the pixel electrode 25 has a laminated structure of a first transparent electrode film T1 and a third metal film M3 at a portion overlapping the intermediate electrode 36, while the portion not overlapping the intermediate electrode 36 has a single-layer structure of the first transparent electrode film T1 without the third metal film M3. The portion of the pixel electrode 25 overlapping the intermediate electrode 36 includes the third metal film M3, and therefore functions as a light-shielding portion 25A that blocks light. The light-shielding portion 25A is positioned to overlap the pixel contact holes CHP1 and CHP2, so that even if the pixel contact holes CHP1 and CHP2 cause misalignment of liquid crystal molecules around the contact holes and light leakage, the light leakage can be blocked. Meanwhile, the touch wiring 30 has a laminated structure of a first transparent electrode film T1 and a third metal film M3 along its entire length. In addition, the portion of the pixel electrode 25 other than the light-shielding portion 25A has a single-layer structure of the first transparent electrode film T1 that does not include the third metal film M3, so that light from the backlight device can be transmitted efficiently.

[0036] The configuration of the source wiring 27 will be described in detail. As shown in FIGS. 4 to 6, the source wiring 27 includes a lower wiring (second wiring) 27A formed from a portion of the second metal film M2 and an upper wiring (first wiring) 27B formed from a portion of the third metal film M3. The lower wiring 27A and the upper wiring 27B extend along the Y-axis direction, and are arranged such that most of the wiring overlaps with each other via the first interlayer insulating film 32. The lower wiring 27A and the upper wiring 27B are arranged concentrically in the line width direction (X-axis direction). The lower wiring 27A formed from a portion of the second metal film M2 has a wider line width at a portion where it intersects with the gate wiring 26 than at other portions, and this wider portion forms the source electrode 24B. The upper wiring 27B formed from a portion of the third metal film M3 has a substantially constant line width over its entire length, which is slightly smaller than the line width of the lower wiring 27A excluding the source electrode 24B. The upper-layer wiring 27B is arranged to overlap the lower-layer wiring 27A over almost its entire length. Therefore, it can be said that a portion of the upper-layer wiring 27B is arranged to overlap the source electrode 24B, which is part of the lower-layer wiring 27A. In the first interlayer insulating film 32 interposed between the second metal film M2 and the third metal film M3, a source contact hole (first contact hole) CHS is opened at a position where the source electrode 24B of the lower-layer wiring 27A and the upper-layer wiring 27B overlap. The source electrode 24B and the upper-layer wiring 27B are connected through the source contact hole CHS in the first interlayer insulating film 32. It can be said that the lower-layer wiring 27A is connected to the upper-layer wiring 27B via the source electrode 24B. The number of source contact holes CHS arranged to overlap the upper-layer wiring 27B matches the number of TFTs 24 arranged in the Y-axis direction (the number of gate wirings 26). In this way, the source wiring 27 is configured by the lower layer wiring 27A and the upper layer wiring 27B that are connected to each other, so it is possible to reduce the wiring resistance of the source wiring 27 compared to when the source wiring is configured by only one of the lower layer wiring 27A and the upper layer wiring 27B. Furthermore, even if one of the lower layer wiring 27A and the upper layer wiring 27B is broken, signal transmission can be maintained by the other, thereby achieving redundancy.Furthermore, since the lower layer wiring 27A and the upper layer wiring 27B are arranged so that most of them overlap each other via the first interlayer insulating film 32, the space required for arranging the lower layer wiring 27A and the upper layer wiring 27B in the display area AA can be kept small, which is advantageous for improving the aperture ratio of the pixels.

[0037] The connection structure between the touch electrode 29 (common electrode 28) and the touch wiring 30 will be described. As shown in FIG. 6, a third interlayer insulating film 35 is interposed between a portion of the touch wiring 30 made of a part of the third metal film M3 and the touch electrode 29 made of a part of the second transparent electrode film T2. A touch contact hole CHTP for connecting the touch wiring 30 and the touch electrode 29 is opened and formed in the third interlayer insulating film 35. The touch contact hole CHTP is arranged at a position overlapping both the touch wiring 30 and the touch electrode 29 to which the touch wiring 30 is to be connected.

[0038] As shown in Fig. 7, a plurality of terminal portions 37 are provided on the inner surface of the exposed portion 21A, which is the non-display area NAA of the array substrate 21. The plurality of terminal portions 37 are arranged in a placement area (mounting area) of the driver 12 in the exposed portion 21A that overlaps at least the driver 12 in a plan view. Fig. 7 illustrates the plurality of terminal portions 37 arranged in the placement area of ​​the driver 12 (the area surrounded by a two-dot chain line). The plurality of terminal portions 37 are also arranged in a placement area (mounting area) of the flexible substrate 13 in the exposed portion 21A that overlaps the flexible substrate 13 in a plan view (see Figs. 1 and 2). The plurality of terminal portions 37 arranged in the placement area of ​​the driver 12 are connected to wiring drawn from the source wiring 27 arranged in the display area AA, wiring drawn from the circuit unit 14, and wiring drawn from the placement area of ​​the flexible substrate 13. Furthermore, the plurality of terminal sections 37 arranged in the placement area of ​​the flexible substrate 13 are connected to wiring drawn out from the circuit section 14 and wiring drawn out from the placement area of ​​the driver 12. The plurality of terminal sections 37 arranged in the placement area of ​​the driver 12 include terminal sections (output terminal sections) that output signals etc. to the driver 12 and terminal sections (input terminal sections) that receive signals output from the driver 12. The detailed configuration of the terminal sections 37 will be described again later.

[0039] 8, a plurality of bumps 38 connected to a plurality of terminal portions 37 are provided on the main surface (bottom surface, back surface) of the driver 12 facing the array substrate 21. The bumps 38 are provided to protrude along the Z-axis direction from the main surface of the driver 12 toward the array substrate 21. The bumps 38 are connected to a circuit provided inside the driver 12. A plurality of bumps 38 are arranged side by side on the main surface of the driver 12 at positions overlapping with the respective terminal portions 37 on the array substrate 21 side. The plurality of bumps 38 include bumps to which signals from the array substrate 21 are input (input bumps) and bumps to which signals are output to the array substrate 21 (output bumps).

[0040] As shown in FIG. 9 , a plurality of terminal portions 37 arranged in the arrangement region of the driver 12 on the array substrate 21 and a plurality of bumps 38 provided on the driver 12 are connected via an anisotropic conductive film (ACF) 39. The anisotropic conductive film 39 will now be described. The anisotropic conductive film 39 is formed by dispersing a large number of conductive particles 39B in a binder 39A made of a thermosetting resin material. When mounting the driver 12, the anisotropic conductive film 39 and the driver 12 are set in the arrangement region of the driver 12 on the array substrate 21, and in this state, the driver 12 is thermocompressed by applying a load toward the array substrate 21. This electrically connects the terminal portions 37 on the array substrate 21 side and the bumps 38 on the driver 12 side via the conductive particles 39B. Furthermore, the binder 39A is thermally cured, thereby mechanically fixing the driver 12 to the array substrate 21. In addition, a plurality of terminal portions 37 arranged in the placement area of ​​the flexible substrate 13 of the array substrate 21 are connected to a plurality of terminal portions (not shown) provided on the flexible substrate 13 using an anisotropic conductive film 39 similar to that described above.

[0041] The multiple terminal portions 37 include a first terminal portion 37α shown in FIG. 10. The first terminal portion 37α has at least a second metal film portion (first terminal portion) 37α1 made of a part of the second metal film M2 and a third metal film portion (second terminal portion) 37α2 made of a part of the third metal film M3. The planarization film 34 is removed from at least the exposed portion 21A (including the arrangement region of the driver 12 and the arrangement region of the flexible substrate 13) of the array substrate 21. The second metal film portion 37α1 is stacked on the upper layer side of the gate insulating film 31. The third metal film portion 37α2 is superimposed on the second metal film portion 37α1 with the first interlayer insulating film 32 interposed therebetween. The first interlayer insulating film 32, which is interposed between the second metal film portion 37α1 and the third metal film portion 37α2, has a first terminal contact hole (second contact hole) CHT1 arranged at a position overlapping both the second metal film portion 37α1 and the third metal film portion 37α2. The second metal film portion 37α1 and the third metal film portion 37α2 are connected to each other through the first terminal contact hole CHT1 in the first interlayer insulating film 32.

[0042] As shown in FIG. 10 , the first terminal portion 37α includes a second metal film portion 37α1, a third metal film portion 37α2, and a transparent electrode portion 37α3 formed from a portion of the second transparent electrode film T2. The transparent electrode portion 37α3 is arranged to overlap the third metal film portion 37α2 via the second interlayer insulating film 33 and the third interlayer insulating film 35. A second terminal contact hole CHT2 is provided in the second interlayer insulating film 33 and the third interlayer insulating film 35, which are interposed between the third metal film portion 37α2 and the transparent electrode portion 37α3, and is positioned so as to overlap both the third metal film portion 37α2 and the transparent electrode portion 37α3. The third metal film portion 37α2 and the transparent electrode portion 37α3 are connected through the second terminal contact hole CHT2 in the second interlayer insulating film 33 and the third interlayer insulating film 35. In this way, the second metal film portion 37α1 and the third metal film portion 37α2, both made of a metal material, are protected by being covered with the transparent electrode portion 37α3 made of a transparent electrode material, making them less susceptible to corrosion and the like.

[0043] However, if the multiple terminal portions 37 include a terminal portion 1 configured as shown in FIG. 11 , the following problem may occur. The configuration of the terminal portion 1 and the problems resulting from this configuration will be described below. The terminal portion 1 is configured by interconnecting a first metal film portion 2 consisting of a part of the first metal film M1, a second metal film portion 3 consisting of a part of the second metal film M2, and a transparent electrode portion 4 consisting of a part of the second transparent electrode film T2. A contact hole 5 for connecting the two metal film portions 2 and 3 is provided in a gate insulating film 31 interposed between the two metal film portions 2 and 3. A contact hole 6 for connecting the second metal film portion 3 and the transparent electrode portion 4 is provided in a first interlayer insulating film 32, a second interlayer insulating film 33, and a third interlayer insulating film 35 interposed between the second metal film portion 3 and the transparent electrode portion 4. To provide the terminal portion 1 having such a configuration, it is necessary to form the third interlayer insulating film 35 during the manufacturing process and then form the contact holes 6 communicating with the first interlayer insulating film 32, the second interlayer insulating film 33, and the third interlayer insulating film 35. Meanwhile, in the display area AA, the source contact hole CHS and the first pixel contact hole CHP1 are formed in the first interlayer insulating film 32 after the first interlayer insulating film 32 is formed. Therefore, if the terminal portion 1 described above is included in the terminal portion 37, there are problems such as the number of times the first interlayer insulating film 32 needs to be processed and the time required for processing increases. In particular, in this embodiment, the thickness of the first interlayer insulating film 32 is greater than the thicknesses of the other inorganic insulating films (the gate insulating film 31, the second interlayer insulating film 33, and the third interlayer insulating film 35), which tends to exacerbate the above-mentioned problems. Furthermore, if the terminal portion 37 includes three or more layers of metal film, there is a problem in that the indentations that occur on the surface of the terminal portion 37 when the driver 12 is mounted will be difficult to identify during inspection, so the metal film that makes up the terminal portion 37 must be two or less layers.

[0044] In this embodiment, in the non-display area NAA, the first terminal portion 37α included in the plurality of terminal portions 37 is composed of a second metal film portion 37α1 made of a part of the second metal film M2 and a third metal film portion 37α2 made of a part of the third metal film M3, as shown in FIG. 10 , and both terminal components 37α1, 37α2 are connected through a first terminal contact hole CHT1 in the first interlayer insulating film 32. In contrast, in the display area AA, as shown in FIG. 6 , the source electrode 24B made of a part of the second metal film M2 and the upper wiring 27B made of a part of the third metal film M3 are connected through a source contact hole CHS in the first interlayer insulating film 32. Therefore, during manufacturing, after the first interlayer insulating film 32 is formed, the source contact hole CHS and the first terminal contact hole CHT1 can be opened in the first interlayer insulating film 32 in the same process. This makes it possible to reduce the number of times the first interlayer insulating film 32 is processed, compared to when the plurality of terminals 37 include the terminal 1 described above.

[0045] The first terminal portion 37α configured as described above is connected to wiring (hereinafter referred to as "drawing wiring") drawn from the source wiring 27, the circuit portion 14, etc., as follows: For example, if the drawing wiring is made of a part of the second metal film M2, the drawing wiring is directly connected to the second metal film portion 37α1. For example, if the drawing wiring is made of a part of the third metal film M3, the drawing wiring is directly connected to the third metal film portion 37α2. For example, if the drawing wiring is made of a part of the first metal film M1, the drawing wiring is connected to the second metal film portion 37α1 through a contact hole provided in the gate insulating film 31. For example, if the drawing wiring is made of a part of each of the first transparent electrode film T1 and the fourth metal film M4, the drawing wiring is connected to the third metal film portion 37α2 through a contact hole provided in the second interlayer insulating film 33.

[0046] Furthermore, in this embodiment, in the display region AA, as shown in FIG. 6, the drain electrode 24C, which is made of a part of the second metal film M2, and the intermediate electrode 36, which is made of a part of the third metal film M3, are connected through the first pixel contact hole CHP1 in the first interlayer insulating film 32. Therefore, during manufacturing, after the first interlayer insulating film 32 is formed, the source contact hole CHS, the first terminal contact hole CHT1, and the first pixel contact hole CHP1 can be opened in the first interlayer insulating film 32 in the same process. If the intermediate electrode 36 were not provided and the pixel electrode 25 were directly connected to the drain electrode 24C, a process for opening contact holes connecting the first interlayer insulating film 32, the second interlayer insulating film 33, and the planarization film 34 would be required. In contrast, because the first pixel contact hole CHP1 can be opened in the same process as the opening of the source contact hole CHS and the first terminal contact hole CHT1 in the first interlayer insulating film 32, the number of times the first interlayer insulating film 32 is processed can be reduced.

[0047] The liquid crystal panel 11 according to this embodiment has the above-described structure, and its manufacturing method will now be described. The manufacturing method for the liquid crystal panel 11 includes a counter substrate manufacturing process (second substrate manufacturing process) for manufacturing the counter substrate 20, an array substrate manufacturing process (first substrate manufacturing process) for manufacturing the array substrate 21, and a bonding process for bonding the manufactured counter substrate 20 and array substrate 21 together. The array substrate manufacturing process will be described below with reference to Figures 12A to 23B.

[0048] 12A to 23B, FIGS. 12A to 12C, 15A to 15C, 18A to 18C, 21A, and 21B show manufacturing procedures for the TFT 24, pixel electrode 25, common electrode 28, and touch wiring 30 shown in FIG. 6. 12A to 23B, FIGS. 13A to 13C, 16A to 16C, 19A to 19C, 22A, and 22B show manufacturing procedures for the first terminal unit 37α shown in FIG. 10. 12A to 23B, FIGS. 14A to 14C, 17A to 17C, 20A to 20C, 23A, and 23B show, for reference, manufacturing procedures for the terminal unit 1 shown in FIG. 11. That is, in this embodiment, the plurality of terminals 37 include the first terminal 37α, but do not include the terminal 1, and therefore the manufacturing procedure for the terminal 1 described below is a reference technique.

[0049] The array substrate manufacturing process includes a first step of forming and patterning a first metal film M1, a second step of forming a gate insulating film 31 and a semiconductor film S1 and patterning the semiconductor film S1, a third step of patterning the gate insulating film 31, a fourth step of forming and patterning a second metal film M2, a fifth step of forming and patterning a first interlayer insulating film 32, a sixth step of forming and patterning a third metal film M3, and a sixth step of forming and patterning a second interlayer insulating film 34. The process includes at least a seventh step of depositing the first transparent electrode film T1 and the fourth metal film M4 and patterning the planarization film 34, an eighth step of patterning the second interlayer insulating film 33, a ninth step of depositing the first transparent electrode film T1 and the fourth metal film M4 and patterning them, a tenth step of patterning the fourth metal film M4, an eleventh step of depositing the third interlayer insulating film 35 and patterning it, and a twelfth step of depositing the second transparent electrode film T2 and patterning it.

[0050] The term "patterning" used above refers to film processing based on a general photolithography method. Specifically, a photoresist film is formed on the film to be processed, the photoresist film is exposed to light by an exposure device through a photomask having a predetermined opening pattern, the photoresist film is developed, and etching is performed through the developed photoresist film, thereby processing the film to be processed, i.e., patterning the film.

[0051] In the first step, a first metal film M1 is formed on the glass substrate 21GS of the array substrate 21, as shown by the two-dot chain lines in FIGS. 12A, 13A, and 14A. The formed first metal film M1 is patterned by the general photolithography method described above. After the first metal film M1 is patterned, the gate electrode 24A and gate wiring 26 are provided in the display area AA, as shown in FIG. 12A. Meanwhile, in the arrangement area of ​​the driver 12 and flexible substrate 13 in the non-display area NAA, the first metal film is removed, as shown in FIG. 13A. If the multiple terminal portions 37 include a terminal portion 1, a first metal film portion 2 of the terminal portion 1 is provided, as shown in FIG. 14A.

[0052] In the second step, a gate insulating film 31 is formed on the first metal film M1 (see FIGS. 12B, 13B, and 14B). Subsequently, a semiconductor film S1 is formed on the gate insulating film 31, as shown by the two-dot chain lines in FIGS. 12B, 13B, and 14B. The formed semiconductor film S1 is patterned by a typical photolithography method. After the semiconductor film S1 is patterned, a semiconductor portion 24D is provided in the display area AA, as shown in FIG. 12B. Meanwhile, in the arrangement area of ​​the driver 12 and the flexible substrate 13 in the non-display area NAA, the semiconductor film S1 is removed, as shown in FIGS. 13B and 14B.

[0053] In the third step, the gate insulating film 31 is patterned by a general photolithography method. If the plurality of terminal portions 37 includes a terminal portion 1, a contact hole 5 is opened and provided in the gate insulating film 31 at a position overlapping the first metal film portion 2, as shown in Fig. 14C. Note that the gate insulating film 31 is not processed in the display area AA, and is also not processed in the arrangement area of ​​the driver 12 and flexible substrate 13 in the non-display area NAA.

[0054] In the fourth step, a second metal film M2 is formed on the semiconductor film S1, as shown by the two-dot chain lines in FIGS. 12C, 13C, and 14D. The formed second metal film M2 is patterned using the general photolithography method described above. After the second metal film M2 is patterned, the source electrode 24B, the drain electrode 24C, and the lower wiring 27A are provided in the display area AA, as shown in FIG. 12C. Meanwhile, in the non-display area NAA, where the driver 12 and the flexible substrate 13 are disposed, a second metal film portion 37α1 of the first terminal portion 37α is provided, as shown in FIG. 13C. If the multiple terminal portions 37 include a terminal portion 1, a second metal film portion 3 of the terminal portion 1 is provided, as shown in FIG. 14D. The second metal film portion 3 is connected to the first metal film portion 2 through a contact hole 5.

[0055] In the fifth step, the first interlayer insulating film 32 is patterned by a typical photolithography method. Since the first interlayer insulating film 32 contains silicon oxide, dry etching is used to pattern the first interlayer insulating film 32. After the first interlayer insulating film 32 is patterned, in the display area AA, as shown in FIG. 15A, a source contact hole CHS is formed in the first interlayer insulating film 32 at a position overlapping the source electrode 24B, and a first pixel contact hole CHP1 is formed in the first interlayer insulating film 32 at a position overlapping the drain electrode 24C. Meanwhile, in the non-display area NAA, as shown in FIG. 16A, a first terminal contact hole CHT1 is formed in the first interlayer insulating film 32 at a position overlapping the second metal film portion 37α1. If the multiple terminal portions 37 include a terminal portion 1, the first interlayer insulating film 32 is not processed near the terminal portion 1, as shown in FIG. 17A.

[0056] In the sixth step, as shown by the two-dot chain lines in FIGS. 15B, 16B, and 17B, a third metal film M3 is formed on the first interlayer insulating film 32. The formed third metal film M3 is patterned by the general photolithography method described above. After the third metal film M3 is patterned, an upper-layer wiring 27B and an intermediate electrode 36 are provided in the display area AA, as shown in FIG. 15B. The upper-layer wiring 27B is connected to the source electrode 27B through a source contact hole CHS in the first interlayer insulating film 32. Meanwhile, in the non-display area NAA, where the driver 12 and flexible substrate 13 are disposed, a third metal film portion 37α2 of the first terminal portion 37α is provided, as shown in FIG. 16B. The third metal film portion 37α2 is connected to the second metal film portion 37α1 through a first terminal contact hole CHT1 in the first interlayer insulating film 32. If the terminal portion 1 is included in the plurality of terminal portions 37, the third metal film M3 is removed near the terminal portion 1 as shown in FIG. 17B.

[0057] In the seventh step, a second interlayer insulating film 33 is formed on the third metal film M3, and then a planarization film 34 is formed on the second interlayer insulating film 33 (see FIGS. 15C, 16C, and 17C). Of the formed second interlayer insulating film 33 and planarization film 34, the planarization film 34 is selectively patterned by the general photolithography method described above. When the planarization film 34 is patterned, in the display area AA, as shown in FIG. 15C, a part of the second pixel contact hole CHP2 is opened at a position of the planarization film 34 that overlaps with the intermediate electrode 36. Meanwhile, in the arrangement area of ​​the driver 12 and the flexible substrate 13 in the non-display area NAA, the planarization film 34 is removed as shown in FIGS. 16C and 17C.

[0058] In the eighth step, the second interlayer insulating film 33 is patterned by a typical photolithography method. When the second interlayer insulating film 33 is patterned, in the display area AA, as shown in Fig. 18A, the remaining portion of the second pixel contact hole CHP2 is opened at a position of the second interlayer insulating film 33 that overlaps the intermediate electrode 36, so as to communicate with a part of the second pixel contact hole CHP2 in the planarization film 34. On the other hand, in the arrangement region of the driver 12 and the flexible substrate 13 in the non-display area NAA, as shown in Figs. 19A and 20A, the second interlayer insulating film 33 is not processed.

[0059] In the ninth step, a first transparent electrode film T1 is formed on the planarization film 34, and then a fourth metal film M4 is formed on the first transparent electrode film T1 (see FIGS. 18B, 19B, and 20B). The formed first transparent electrode film T1 and fourth metal film M4 are both patterned by the general photolithography method described above. After the first transparent electrode film T1 and fourth metal film M4 are patterned, the touch wiring 30 and pixel electrode 25 are provided in the display area AA, as shown in FIG. 18B. The pixel electrode 25 is connected to the intermediate electrode 36 through the second pixel contact hole CHP2. At this stage, the pixel electrode 25 includes a portion made of the fourth metal film M4 throughout its entire area. The touch wiring 30 is kept insulated from the source wiring 27 (upper-layer wiring 27B) that overlaps it by the second interlayer insulating film 33 and the planarization film 34. On the other hand, in the arrangement area of ​​the driver 12 and the flexible substrate 13 in the non-display area NAA, both the first transparent electrode film T1 and the fourth metal film M4 are removed as shown in FIGS. 19B and 20B.

[0060] In the tenth step, the fourth metal film M4, which is one of the first transparent electrode film T1 and the fourth metal film M4 formed in the ninth step, is selectively patterned by the general photolithography method described above. After the fourth metal film M4 is patterned, a light-shielding portion 25A of the pixel electrode 25 is formed, as shown in FIG. 18C. At this time, the portion of the pixel electrode 25 made of the fourth metal film M4 that does not overlap with the intermediate electrode 36 is selectively removed, while the portion that overlaps with the intermediate electrode 36 is selectively left. This results in the formation of a pixel electrode 25 including the light-shielding portion 25A. Meanwhile, in the arrangement region of the driver 12 and flexible substrate 13 in the non-display area NAA, the first transparent electrode film T1 and the fourth metal film M4 were both removed in the previous ninth step, as shown in FIGS. 19C and 20C, so no change occurs in the tenth step.

[0061] In an eleventh step, the third interlayer insulating film 35 is patterned by a general photolithography method. When the third interlayer insulating film 35 is patterned, in the display area AA, as shown in FIG. 21A , a touch contact hole CHTP is opened and provided in the third interlayer insulating film 35 at a position overlapping a part of the touch wiring 30. Meanwhile, in the arrangement area of ​​the driver 12 and the flexible substrate 13 in the non-display area NAA, as shown in FIG. 22A , the second interlayer insulating film 33 is etched in addition to the third interlayer insulating film 35, and a second terminal contact hole CHT2 is provided in communication with the second interlayer insulating film 33 and the third interlayer insulating film 35 at a position overlapping the third metal film portion 37α2. In addition, if the multiple terminal portions 37 include a terminal portion 1, as shown in Figure 23A, in addition to the third interlayer insulating film 35, the first interlayer insulating film 32 and the second interlayer insulating film 33 are etched, and contact holes 6 are provided in communication with the first interlayer insulating film 32, the second interlayer insulating film 33, and the third interlayer insulating film 35 at positions that overlap the second metal film portion 3.

[0062] In a twelfth step, a second transparent electrode film T2 is formed on the third interlayer insulating film 35 (see FIGS. 21B, 22B, and 23B). The formed second transparent electrode film T2 is then patterned by the general photolithography method described above. After the second transparent electrode film T2 is patterned, a common electrode 28 is provided in the display area AA, as shown in FIG. 21B. The common electrode 28 is partitioned by partition openings 28A to form multiple touch electrodes 29 (see FIG. 1). The touch electrodes 29 are connected to the touch wiring 30 to be connected through touch contact holes CHTP. Meanwhile, in the arrangement area of ​​the driver 12 and the flexible substrate 13 in the non-display area NAA, a transparent electrode portion 37α3 is provided at a position overlapping with the third metal film portion 37α2, as shown in FIG. 22B. The transparent electrode portion 37α3 is connected to the third metal film portion 37α2 through a second terminal contact hole CHT2 in the second interlayer insulating film 33 and the third interlayer insulating film 35. If the multiple terminal portions 37 include a terminal portion 1, the transparent electrode portion 4 is provided at a position overlapping the second metal film portion 3, as shown in FIG. 23B . The transparent electrode portion 4 is connected to the second metal film portion 3 through a contact hole 6 in the first interlayer insulating film 32, the second interlayer insulating film 33, and the third interlayer insulating film 35.

[0063] As described above, in the manufacturing method of the liquid crystal panel 11 according to this embodiment, by patterning the first interlayer insulating film 32 in step 5, the source contact hole CHS and the first pixel contact hole CHP1 are provided in the display area AA, and the first terminal contact hole CHT1 is provided in the non-display area NAA. That is, the source contact hole CHS, the first pixel contact hole CHP1, and the first terminal contact hole CHT1 are collectively provided in the first interlayer insulating film 32 in the same step (single etching). In contrast, if multiple terminal portions 37 include terminal portions 1, it is necessary to provide a part of the contact hole 6 in the first interlayer insulating film 32 in step 11, which forces the first interlayer insulating film 32 to be etched twice, in steps 5 and 11 (see FIGS. 15A and 22A). In contrast, in this embodiment, the number of times the first interlayer insulating film 32 is etched can be reduced by one.

[0064] As described above, the liquid crystal panel (display device) 11 of this embodiment includes a display area AA where an image is displayed, a non-display area NAA where an image is not displayed, a TFT (switching element) 24 arranged in the display area AA, upper layer wiring (first wiring) 27B arranged in the display area AA and connected to the TFT 24, and a first terminal portion 37α arranged in the non-display area NAA. The TFT 24 includes a gate electrode (first electrode) 24A made of a first metal film (first conductive film) M1, a semiconductor film S1 arranged on the upper layer side of the first metal film M1 with a gate insulating film (first insulating film) 31 interposed therebetween, the semiconductor portion 24D arranged to overlap the gate electrode 24A, a second metal film (second conductive film) M2 arranged on the upper layer side of the semiconductor film S1, a source electrode (second electrode) 24B connected to the semiconductor portion 24D, and a drain electrode (third electrode) 24B made of a portion of the second metal film M2 different from the source electrode 24B and connected to the semiconductor portion 24D. 24C, the upper layer wiring 27B is made of a third metal film (third conductive film) M3 arranged on the upper layer side of the second metal film M2 via a first interlayer insulating film (second insulating film) 32, and a part of it is arranged to overlap with the source electrode 24B, the first terminal portion 37α is made of a second metal film portion (first terminal constituent portion) 37α1 consisting of a part of the second metal film M2 that is different from the source electrode 24B and the drain electrode 24C, and a part of the third metal film M3 that is different from the upper layer wiring 27B, The first interlayer insulating film 32 has a third metal film portion (second terminal component) 37α2, at least a portion of which is arranged overlapping with the second metal film portion 37α1, and the first interlayer insulating film 32 is provided with a source contact hole (first contact hole) CHS arranged at a position overlapping with both the upper layer wiring 27B and the source electrode 24B, and a first terminal contact hole (second contact hole) CHT1 arranged at a position overlapping with both the second metal film portion 37α1 and the third metal film portion 37α2.

[0065] The TFT 24 arranged in the display area AA is driven when a potential equal to or greater than the threshold voltage is supplied to the gate electrode 24A. Then, a signal supplied from the upper-layer wiring 27B to the source electrode 24B is supplied to the drain electrode 24C via the semiconductor portion 24D. In the display area AA, the upper-layer wiring 27B, which is a part of the third metal film M3, is connected to the source electrode 24B, which is a part of the second metal film M2, through a source contact hole CHS in the first interlayer insulating film 32. In the non-display area NAA, the third metal film portion 37α2, which is a part of the third metal film M3, is connected to the second metal film portion 37α1, which is a part of the second metal film M2, through a first terminal contact hole CHT1 in the first interlayer insulating film 32, and together with the second metal film portion 37α1, forms the first terminal portion 37α. Therefore, during manufacturing, after the first interlayer insulating film 32 is formed, the source contact hole CHS and the first terminal contact hole CHT1 can be opened in the first interlayer insulating film 32 in the same process. This allows the number of times the first interlayer insulating film 32 is processed to be reduced compared to the conventional method.

[0066] The display region AA also includes lower-layer wiring (second wiring) 27A. The lower-layer wiring 27A is made up of a portion of the second metal film M2 that is different from the source electrode 24B, the drain electrode 24C, and the second metal film portion 37α1. The lower-layer wiring 27A is connected to the source electrode 24B, extends along the upper-layer wiring 27B, and is disposed so as to overlap the upper-layer wiring 27B via the first interlayer insulating film 32. Since the lower-layer wiring 27A is connected to the source electrode 24B, it is at the same potential as the upper-layer wiring 27B. This reduces the wiring resistance of the upper-layer wiring 27B and the lower-layer wiring 27A. Even if one of the upper-layer wiring 27B and the lower-layer wiring 27A is broken, signal transmission can be maintained by the other, thereby achieving redundancy. Furthermore, the lower wiring 27A, which is made up of a part of the second metal film M2, extends along the upper wiring 27B, which is made up of a part of the third metal film M3, and is arranged overlapping the upper wiring 27B via the first interlayer insulating film 32, so that the space required for arranging the upper wiring 27B and the lower wiring 27A in the display area AA is small, which is advantageous for improving the aperture ratio.

[0067] The pixel electrode 25 is also provided with an intermediate electrode (fourth electrode) 36 that is arranged in the display area AA and connected to the drain electrode 24C, and a pixel electrode 25 that is arranged in the display area AA and connected to the intermediate electrode 36, the intermediate electrode 36 being made of a part of the third metal film M3 that is different from the upper layer wiring 27B, and at least a part of the intermediate electrode 36 is arranged to overlap with the drain electrode 24C, and the pixel electrode 25 is made of a first conductive film that is a fourth conductive film that is arranged on the upper layer side of the third metal film M3 via a second interlayer insulating film 33 and a planarizing film 34 that are third insulating films. The TFT 24 is made of a transparent electrode film T1 and a fourth metal film M4, and is disposed so as to partially overlap the intermediate electrode 36. A first pixel contact hole (third contact hole) CHP1 is provided in the first interlayer insulating film 32 at a position overlapping both the drain electrode 24C and the intermediate electrode 36. A second pixel contact hole (fourth contact hole) CHP2 is provided in the second interlayer insulating film 33 and the planarizing film 34, which are the third insulating film, at a position overlapping both the intermediate electrode 36 and the pixel electrode 25. When the TFT 24 is driven, a signal supplied to the drain electrode 24C is supplied to the pixel electrode 25 via the intermediate electrode 36. The pixel electrode 25 is charged to the potential of the signal. The intermediate electrode 36, which is formed as a part of the third metal film M3, is connected to the drain electrode 24C, which is formed as a part of the second metal film M2, through the first pixel contact hole CHP1 in the first interlayer insulating film 32. The pixel electrode 25, which is made up of the first transparent electrode film T1 (the fourth conductive film) and a part of the fourth metal film M4, is connected to the intermediate electrode 36, which is made up of a part of the third metal film M3, through the second interlayer insulating film 33 (the third insulating film) and the second pixel contact hole CHP2 in the planarization film 34. During manufacturing, after the first interlayer insulating film 32 is formed, the source contact hole CHS, the first terminal contact hole CHT1, and the first pixel contact hole CHP1 can be opened in the first interlayer insulating film 32 in the same process. If the intermediate electrode 36 were not provided and the pixel electrode 25 were directly connected to the drain electrode 24C, a process would be required to open contact holes that communicate the first interlayer insulating film 32, the second interlayer insulating film 33 (the third insulating film), and the planarization film 34.In comparison, the first pixel contact hole CHP1 can be formed in the same process as forming the source contact hole CHS and the first terminal contact hole CHT1 in the first interlayer insulating film 32, so the number of times the first interlayer insulating film 32 is processed can be reduced.

[0068] Furthermore, the manufacturing method of the liquid crystal panel 11 according to this embodiment includes forming a first metal film M1, patterning the first metal film M1 to provide a gate electrode 24A in a display area AA where an image is displayed, forming a gate insulating film 31 on an upper side of the first metal film M1, forming a semiconductor film S1 on an upper side of the gate insulating film 31, patterning the semiconductor film S1 to provide a semiconductor portion 24D arranged to overlap the gate electrode 24A, forming a second metal film M2 on an upper side of the semiconductor film S1, and patterning the second metal film M2 to provide a source electrode 24B connected to the semiconductor portion 24D and a drain electrode 24C connected to the semiconductor portion 24D, and providing a second metal film portion 37α1 in a non-display area NAA where an image is not displayed, and forming a first metal film M2 on an upper side of the second metal film M2. An interlayer insulating film 32 is formed, and the first interlayer insulating film 32 is patterned to provide a source contact hole CHS arranged at a position overlapping with the source electrode 24B and a first terminal contact hole CHT1 arranged at a position overlapping with the second metal film portion 37α1.A third metal film M3 is formed on the upper side of the first interlayer insulating film 32, and the third metal film M3 is patterned to provide an upper wiring 27B arranged in the display area AA and partially overlapping with the source electrode 24B and the source contact hole CHS, and a third metal film portion 37α2 arranged in the non-display area NAA and at least partially overlapping with the second metal film portion 37α1 and the first terminal contact hole CHT1, and constituting the first terminal portion 37α together with the second metal film portion 37α1.

[0069] A semiconductor film S1 is formed and patterned to provide a semiconductor portion 24D. The semiconductor portion 24D is arranged to overlap a gate electrode 24A made of a first metal film M1 via a gate insulating film 31. A second metal film M2 is formed and patterned to provide a source electrode 24B and a drain electrode 24C in the display area AA, and a second metal film portion 37α1 in the non-display area NAA. The source electrode 24B and the drain electrode 24C are each connected to the semiconductor portion 24D. A first interlayer insulating film 32 is formed and patterned to provide a source contact hole CHS in the display area AA, and a first terminal contact hole CHT1 in the non-display area NAA. After the third metal film M3 is formed and patterned, an upper-layer wiring 27B is provided in the display area AA, and a third metal film portion 37α2 is provided in the non-display area NAA. The upper-layer wiring 27B is connected to the source electrode 24B through the overlapping source contact hole CHS. The third metal film portion 37α2 is connected to the second metal film portion 37α1 through the overlapping first terminal contact hole CHT1, and together with the second metal film portion 37α1, forms the first terminal portion 37α. In this way, in the process of patterning the first interlayer insulating film 32, the source contact hole CHS and the first terminal contact hole CHT1 are opened in the first interlayer insulating film 32. This reduces the number of times the first interlayer insulating film 32 is processed compared to conventional methods.

[0070] <Embodiment 2> 24 to 26. In this embodiment 2, a case where the configuration of the source line 127 is changed is shown. Note that a duplicated description of the structure, action, and effect similar to those of the above-mentioned embodiment 1 will be omitted.

[0071] As shown in FIGS. 24 and 25, the source wiring (first wiring) 127 according to this embodiment has a single-layer structure made of a portion of the third metal film M3. In other words, the source wiring 127 according to this embodiment can be said to be composed only of the upper-layer wiring 27B (see FIG. 4) described in the first embodiment. As shown in FIGS. 24 and 26, the source wiring 127 made of a portion of the third metal film M3 is connected to a source electrode 124B made of a portion of the second metal film M2 through a source contact hole CHS in the first interlayer insulating film 132 interposed therebetween. As shown in FIG. 25, the source wiring 127 having such a configuration intersects with the gate wiring (third wiring) 126 made of a portion of the first metal film via the gate insulating film 131 and the first interlayer insulating film 132. In the first embodiment described above, the lower-layer wiring 27A constituting the source wiring 27 is made of a portion of the second metal film, and this lower-layer wiring 27A intersects with the gate wiring 26 via the gate insulating film 31 (see FIG. 6). Therefore, in this embodiment, compared to Embodiment 1, the distance between the intersections of the gate wiring 126 and the source wiring 127 is larger by approximately the thickness of the first interlayer insulating film 132. This makes it possible to reduce the parasitic capacitance that may occur between the gate wiring 126 and the source wiring 127.

[0072] As described above, according to this embodiment, the display region AA is provided with a gate line (third line) 126. The gate line 126 is made of a portion of the first metal film M1 that is different from the gate electrode 124A. The gate line 126 is continuous with the gate electrode 124A and intersects with a source line (first line) 127 via a gate insulating film 131 and a first interlayer insulating film 132. The gate line 126 can supply a potential equal to or greater than the threshold voltage of the TFT 124 to the gate electrode 124A. The gate line 126, which is made of a portion of the first metal film M1, and the source line 127, which is made of a portion of the third metal film M3, intersect with each other with the gate insulating film 131 and the first interlayer insulating film 132 interposed therebetween. Therefore, compared to a case in which the source line 127 is made of a portion of the second metal film M2, the distance between the intersections of the gate line 126 and the source line 127 is greater. This reduces parasitic capacitance that may occur between the gate line 126 and the source line 127.

[0073] <Embodiment 3> 27 to 29C, a third embodiment will be described. In this third embodiment, the intermediate electrode 36 is omitted from the first embodiment. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0074] 27, in the TFT 224 according to this embodiment, the drain electrode 224C is directly connected to the pixel electrode 225 without the intermediate electrode 36 (see FIG. 6) described in the first embodiment. More specifically, a part of the pixel electrode 225 is superimposed on the end of the drain electrode 224C opposite to the semiconductor portion 224D side. A third pixel contact hole (fifth contact hole) CHP3 is provided in communication with the first interlayer insulating film 232, the second interlayer insulating film 233, and the planarizing film 234 interposed between the drain electrode 224C and the pixel electrode 225. The drain electrode 224C and the pixel electrode 225 are connected through the third pixel contact hole CHP3.

[0075] In the first embodiment described above, the intermediate electrode 36, which is made of a part of the third metal film M3, is connected to both the drain electrode 224C and the pixel electrode 225 (see FIG. 6 ). This raises concerns that a short circuit may occur between the intermediate electrode 36 and the upper-layer wiring 27B, which is made of a part of the third metal film M3, resulting in a decrease in yield. In contrast, in the present embodiment, the intermediate electrode 36, which is made of the third metal film M3, is not present at a position overlapping the drain electrode 224C, making it less likely that a short circuit will occur in the upper-layer wiring 227B. This improves yield compared to the first embodiment.

[0076] Next, the array substrate manufacturing process included in the manufacturing method of the liquid crystal panel 11 will be described with reference to Figures 28A to 29C. Figures 28A to 29C show the manufacturing procedures for the TFT 224, pixel electrode 225, touch wiring 230, etc. shown in Figure 27, and these manufacturing procedures will be described below. Of the first to twelfth steps included in the array substrate manufacturing process, the fifth to ninth steps, which are different from those in the first embodiment, will be mainly described. Note that, below, descriptions that overlap with those in the first embodiment, such as the manufacturing procedure for the first terminal portion 37α (see Figures 13A to 13C, 16A to 16C, 19A to 19C, 22A and 22B), will be omitted.

[0077] After the second metal film M2 is patterned through the fourth process, the fifth process is performed. In the fifth process, the first interlayer insulating film 232 is patterned by a typical photolithography method. After the first interlayer insulating film 232 is patterned, source contact holes CHS are opened in the first interlayer insulating film 232 at positions overlapping the source electrodes 24B in the display region AA, as shown in FIG. 28A. At this time, no opening is formed in the first interlayer insulating film 232 at positions overlapping the drain electrodes 224C.

[0078] In the sixth step, as shown by the two-dot chain line in FIG. 28B, a third metal film M3 is formed on the first interlayer insulating film 232. The formed third metal film M3 is patterned by the general photolithography method described above. After the third metal film M3 is patterned, an upper-layer wiring 227B is provided in the display area AA, as shown in FIG. 28B. The upper-layer wiring 227B is connected to the source electrode 224B through the source contact hole CHS in the first interlayer insulating film 232.

[0079] In a seventh step, a second interlayer insulating film 233 is formed on the third metal film M3, and then a planarizing film 234 is formed on the second interlayer insulating film 233 (see FIG. 28C). Of the formed second interlayer insulating film 233 and planarizing film 234, the planarizing film 234 is selectively patterned by the general photolithography method described above. When the planarizing film 234 is patterned, in the display region AA, as shown in FIG. 28C, a part of the third pixel contact hole CHP3 is opened at a position of the planarizing film 234 that overlaps with the drain electrode 224C.

[0080] In the eighth step, the first interlayer insulating film 231 and the second interlayer insulating film 233 are patterned by a typical photolithography method. When the first interlayer insulating film 231 and the second interlayer insulating film 233 are patterned, in the display region AA, as shown in FIG. 29A , the remaining part of the third pixel contact hole CHP3 is opened at a position of the first interlayer insulating film 231 and the second interlayer insulating film 233 that overlaps with the drain electrode 224C, so as to communicate with a part of the second pixel contact hole CHP2 in the planarization film 234.

[0081] In the ninth step, a first transparent electrode film T1 is formed on the planarization film 234, and then a fourth metal film M4 is formed on the first transparent electrode film T1 (see FIG. 29B). The formed first transparent electrode film T1 and fourth metal film M4 are both patterned by the general photolithography method described above. After the first transparent electrode film T1 and fourth metal film M4 are patterned, the touch wiring 230 and pixel electrode 225 are provided in the display area AA, as shown in FIG. 29B. The pixel electrode 225 is directly connected to the drain electrode 224C through the third pixel contact hole CHP3. At this stage, the pixel electrode 225 includes a portion made of the fourth metal film M4 throughout its entire area. The touch wiring 230 is kept insulated from the overlapping upper wiring 227B by the second interlayer insulating film 233 and the planarization film 234. Thereafter, when a tenth process is performed, the fourth metal film M4 is selectively patterned, and the light-shielding portion 225A of the pixel electrode 225 is provided, as shown in FIG. 29C.

[0082] As described above, according to this embodiment, the pixel electrode 225 is disposed in the display area AA and is connected to the drain electrode 224C. The pixel electrode 225 is composed of a first transparent electrode film T1 and a fourth metal film M4, which are fourth conductive films disposed above the third metal film M3 via the second interlayer insulating film 233 and the planarizing film 234, which are third insulating films. The pixel electrode 225 is disposed so as to partially overlap the drain electrode 224C. A third pixel contact hole (fifth contact hole) CHP3 is provided in communication with the first interlayer insulating film 232 and the second interlayer insulating film 233 and the planarizing film 234, which are third insulating films. The third pixel contact hole CHP3 is disposed at a position overlapping both the drain electrode 224C and the pixel electrode 225. When the TFT 224 is driven, a signal supplied to the drain electrode 224C is supplied to the pixel electrode 225. The pixel electrode 225 is charged to the potential of the signal. The pixel electrode 225, which is made up of the first transparent electrode film T1 (the fourth conductive film) and a part of the fourth metal film M4, is connected to the drain electrode 224C, which is made up of a part of the second metal film M2, through a third pixel contact hole CHP3 that communicates with the first interlayer insulating film 232 and the third insulating film (the second interlayer insulating film 233 and the planarization film 234). If an electrode made up of a part of the third metal film M3 were provided at a position overlapping the drain electrode 224C and connected to both the drain electrode 224C and the pixel electrode 225, there is a concern that the electrode and the upper wiring 227B would short-circuit, deteriorating the yield. In this regard, since there is no electrode made up of the third metal film M3 at a position overlapping the drain electrode 224C, the yield can be improved.

[0083] <Embodiment 4> A fourth embodiment will be described with reference to Figures 30 to 32. In this fourth embodiment, the configuration of the first terminal portion 337α is changed from that of the first embodiment. Note that redundant descriptions of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0084] As shown in FIG. 30 , the first terminal 337α according to this embodiment includes at least a third metal film portion 337α2 formed from a portion of the third metal film and a transparent electrode portion 337α3 formed from a portion of the second transparent electrode film. The third metal film portion 337α2 and the transparent electrode portion 337α3 are connected to each other through a second terminal contact hole CHT2 extending through the second interlayer insulating film 333 and the third interlayer insulating film 335. The configuration of the first terminal 337α varies depending on the configuration of the lead-out wiring 40 to be connected. The lead-out wiring 40 is a wiring extending from the source wiring 27 in the display area AA or the circuit unit 14 in the non-display area NAA (see FIGS. 1 and 5 ). For example, when the lead-out wiring 40 is formed from a portion of the third metal film, the third metal film portion 337α2 of the first terminal 337α is directly connected to the lead-out wiring 40. Therefore, in this case, the first terminal portion 337α is composed of the third metal film portion 337α2 and the transparent electrode portion 337α3.

[0085] On the other hand, for example, when the lead-out wiring 40 is made of a part of the second metal film M2, as shown in FIG. 31 , the first terminal portion 337α has a second metal film portion 337α1 made of a part of the second metal film M2. The lead-out wiring 40 is directly connected to the second metal film portion 337α1 of the first terminal portion 337α. The second metal film portion 337α1 is connected to the third metal film portion 337α2 through a first terminal contact hole CHT1 provided in the first interlayer insulating film 332. In this case, the first terminal contact hole CHT1 is arranged so as not to overlap the second terminal contact hole CHT2.

[0086] Furthermore, for example, when the lead-out wiring 40 is made of a portion of the first metal film M1, as shown in FIG. 32, the first terminal portion 337α has a second metal film portion 337α1 made of a portion of the second metal film M2 and a first metal film portion 337α4 made of a portion of the first metal film M1. The lead-out wiring 40 is directly connected to the first metal film portion 337α4 of the first terminal portion 337α. The second metal film portion 337α1 is connected to the first metal film portion 337α4 through a third terminal contact hole CHT3 provided in the gate insulating film 331. The third metal film portion 337α2 is connected to the second metal film portion 337α1 through a first terminal contact hole CHT1 provided in the first interlayer insulating film 332. In this case, the first terminal contact hole CHT1, the second terminal contact hole CHT2, and the third terminal contact hole CHT3 are arranged so as not to overlap one another.

[0087] In both cases where the lead-out wiring 40 is made of a portion of the second metal film M2 and where the lead-out wiring 40 is made of a portion of the first metal film M1, a first terminal contact hole CHT1 is provided in the first interlayer insulating film 332, as shown in FIGS. 31 and 32 . Therefore, during manufacturing, both the source contact hole CHS and the first terminal contact hole CHT1 can be provided in the first interlayer insulating film 332 in the fifth step described in the first embodiment. This, as in the first embodiment, reduces the number of times the first interlayer insulating film 332 is processed. Note that, when the lead-out wiring 40 is made of a portion of each of the first transparent electrode film T1 and the fourth metal film M4, the lead-out wiring 40 is connected to the third metal film portion 337α2 through a contact hole provided in the second interlayer insulating film 333, eliminating the need to provide a new contact hole in the first interlayer insulating film 332.

[0088] <Embodiment 5> Embodiment 5 will be described with reference to Figures 33 to 36. In this embodiment 5, the configuration of the first terminal portion 437α is changed from that of the above-described embodiment 1. Note that redundant explanations of the structure, action, and effects similar to those of the above-described embodiment 1 will be omitted.

[0089] As shown in FIG. 33 , the first terminal 437α according to this embodiment includes at least a laminated film portion 437α5 formed of a portion of the first transparent electrode film T1 and a portion of the fourth metal film M4, and a transparent electrode portion 437α3 formed of a portion of the second transparent electrode film. The laminated film portion 437α5 and the transparent electrode portion 437α3 are connected through a fourth terminal contact hole CHT4 provided in the third interlayer insulating film 435 interposed therebetween. The configuration of the first terminal 437α varies depending on the configuration of the lead-out wiring 440 to be connected. This lead-out wiring 440 is a wiring led out from the source wiring 27 in the display area AA or the circuit unit 14 in the non-display area NAA (see FIGS. 1 and 5 ). For example, when the lead-out wiring 440 is formed of a portion of the first transparent electrode film T1 and a portion of the fourth metal film M4, the laminated film portion 437α5 of the first terminal 437α is directly connected to the lead-out wiring 440. Therefore, in this case, the first terminal portion 437α is composed of the laminated film portion 437α5 and the transparent electrode portion 437α3.

[0090] On the other hand, for example, when the lead-out wiring 440 is made of a part of the third metal film M3, as shown in FIG. 34, the first terminal 437α has a third metal film portion 437α2 made of a part of the third metal film M3. The lead-out wiring 440 is directly connected to the third metal film portion 437α2 of the first terminal 437α. The third metal film portion 437α2 is connected to the stacked film portion 437α5 through a fifth terminal contact hole CHT5 provided in the second interlayer insulating film 433. In this case, the fifth terminal contact hole CHT4 is arranged so as not to overlap with the fourth terminal contact hole CHT4.

[0091] 35, when the lead-out wiring 440 is made of a part of the second metal film M2, the first terminal 437α has a second metal film portion 437α1 made of a part of the second metal film M2. The lead-out wiring 440 is directly connected to the second metal film portion 437α1 of the first terminal 437α. The third metal film portion 437α2 is connected to the second metal film portion 437α1 through a first terminal contact hole CHT1 provided in the first interlayer insulating film 432. In this case, the first terminal contact hole CHT1 is arranged so as not to overlap the fourth terminal contact hole CHT4 and the fifth terminal contact hole CHT4.

[0092] 36, when the lead-out wiring 440 is made of a part of the first metal film M1, the first terminal 437α has a second metal film portion 437α1 made of a part of the second metal film M2 and a first metal film portion 437α4 made of a part of the first metal film M1. The lead-out wiring 440 is directly connected to the first metal film portion 437α4 of the first terminal 437α. The second metal film portion 437α1 is connected to the first metal film portion 437α4 through a third terminal contact hole CHT3 provided in the gate insulating film 431. The third metal film portion 437α2 is connected to the second metal film portion 437α1 through a first terminal contact hole CHT1 provided in the first interlayer insulating film 432. In this case, the first terminal contact hole CHT1, the third terminal contact hole CHT3, the fourth terminal contact hole CHT4, and the fifth terminal contact hole CHT5 are arranged so as not to overlap one another.

[0093] In any of the cases where the lead-out wiring 440 is made of a part of the third metal film M3, where the lead-out wiring 440 is made of a part of the second metal film M2, and where the lead-out wiring 440 is made of a part of the first metal film M1, the first interlayer insulating film 432 is provided with a first terminal contact hole CHT1, as shown in FIGS. 34 to 36. Therefore, during manufacturing, both the source contact hole CHS and the first terminal contact hole CHT1 can be provided in the first interlayer insulating film 432 in the fifth step described in the first embodiment. This provides the effect of reducing the number of times the first interlayer insulating film 432 is processed, as in the first embodiment.

[0094] <Embodiment 6> A sixth embodiment will be described with reference to Fig. 37 or 38. In this sixth embodiment, a second terminal portion 537β is added to the terminal portion 37 of the first embodiment. Note that a redundant description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0095] The multiple terminals 37 (see FIG. 7) according to this embodiment include a second terminal 537β shown in FIGS. 37 and 38. The second terminal 537β has a third metal film portion (third terminal portion) 537β1 made of a part of the third metal film M3, and a transparent electrode portion (fourth terminal portion) 537β2 made of a part of the second transparent electrode film. The third metal film portion 537β1 is stacked on the upper layer side of the first interlayer insulating film 532. The transparent electrode portion 537β2 is superimposed on the third metal film portion 537β1 with the second interlayer insulating film (third insulating film) 533 and the third interlayer insulating film 535 interposed therebetween. A sixth terminal contact hole (sixth contact hole) CHT6, which is arranged at a position overlapping both the third metal film portion 537β1 and the transparent electrode portion 537β2, is provided in the second interlayer insulating film 533 and the third interlayer insulating film 535, which are interposed between the third metal film portion 537β1 and the transparent electrode portion 537β2, and communicates with the second interlayer insulating film 533 and the third interlayer insulating film 535. The third metal film portion 537β1 and the transparent electrode portion 537β2 are connected through the sixth terminal contact hole CHT6 in the second interlayer insulating film 533 and the third interlayer insulating film 535.

[0096] As described above, in this embodiment, the sixth terminal contact hole CHT6 for connecting the third metal film portion 537β1 and the transparent electrode portion 537β2 that constitute the second terminal portion 537β is provided in the second interlayer insulating film 533 and the third interlayer insulating film 535, but is not formed in the first interlayer insulating film 532. Therefore, during manufacturing, it is not necessary to process the first interlayer insulating film 532 to provide the second terminal portion 537β in the non-display area NAA. This makes it possible to reduce the number of times the first interlayer insulating film 532 is processed compared to conventional methods.

[0097] As described above, the liquid crystal panel 11 according to this embodiment includes a display area AA (see FIG. 1) where an image is displayed, a non-display area NAA (see FIG. 1) where an image is not displayed, a TFT 24 (see FIG. 6) arranged in the display area AA, upper layer wiring 27B (see FIG. 4) arranged in the display area AA and connected to the TFT 24, a pixel electrode 25 (see FIG. 6) arranged in the display area AA and connected to the TFT 24, a common electrode 28 (see FIG. 4) arranged in the display area AA, and a second terminal portion 537β arranged in the non-display area NAA. The TFT 24 includes a first metal film M1 a semiconductor portion 24D arranged to overlap the gate electrode 24A, a source electrode 24B made of a second metal film M2 arranged on the upper side of the semiconductor film S1 and connected to the semiconductor portion 24D, and a drain electrode 24C made of a portion of the second metal film M2 different from the source electrode 24B and connected to the semiconductor portion 24D. The upper wiring 27B is made of a third metal film M3 arranged on the upper side of the second metal film M2 with a first interlayer insulating film 532 interposed therebetween. The pixel electrode 25 is made of a first transparent electrode film T1 and a fourth metal film M4, which are fourth conductive films arranged on the upper layer side with respect to the third metal film M3 via a second interlayer insulating film 533, which is a third insulating film, and a planarizing film 34, and is made of a second transparent electrode film T1 and a fourth metal film M4, which are fourth conductive films arranged on the upper layer side with respect to the third metal film M3 via a third interlayer insulating film (fourth insulating film) 535, and is connected to the drain electrode 24C. The common electrode 28 is made of a second transparent electrode film (fifth conductive film) T2, which is arranged on the upper layer side with respect to the first transparent electrode film T1 and the fourth metal film M4, which are fourth conductive films, via a third interlayer insulating film (fourth insulating film) 535, and is made of a third layer The second terminal portion 537β is arranged to overlap the pixel electrode 25 via the interlayer insulating film 535, and has a third metal film portion (third terminal component) 537β1 consisting of a portion of the third metal film M3 that is different from the upper layer wiring 27B, and a transparent electrode portion (fourth terminal component) 537β2 consisting of a portion of the second transparent electrode film T2 that is different from the common electrode 28, and at least a portion of which is arranged to overlap the third metal film portion 537β1, and the first interlayer insulating film 532 is provided with a source contact hole CHS (see Figure 6) that is arranged at a position that overlaps both the upper layer wiring 27B and the source electrode 24B,A sixth terminal contact hole (sixth contact hole) CHT6 is provided in communication with the second interlayer insulating film (third insulating film) 533 and the third interlayer insulating film 535, and is arranged at a position overlapping both the third metal film portion 537β1 and the transparent electrode portion 537β2.

[0098] The TFT 24 arranged in the display area AA is driven when a potential equal to or greater than the threshold voltage is supplied to the gate electrode 24A. Then, a signal is supplied from the upper-layer wiring 27B to the source electrode 24B, and then to the drain electrode 24C via the semiconductor portion 24D. The pixel electrode 25 connected to the drain electrode 24C is charged to the potential of the signal. An electric field corresponding to the potential difference is generated between the pixel electrode 25 and the common electrode 28 overlapping the pixel electrode 25 via the third interlayer insulating film 35, and this electric field is utilized to perform display. In the display area AA, the upper-layer wiring 27B, which is a part of the third metal film M3, is connected to the source electrode 24B, which is a part of the second metal film M2, through a source contact hole CHS in the first interlayer insulating film 32. In the non-display area NAA, a transparent electrode portion 537β2 consisting of a part of the second transparent electrode film T2 is connected to a third metal film portion 537β1 consisting of a part of the third metal film M3 through a sixth terminal contact hole CHT6 that communicates with the second interlayer insulating film 33 and the third interlayer insulating film 35. Therefore, during manufacturing, there is no need to process the first interlayer insulating film 32 to provide the second terminal portion 537β in the non-display area NAA. This makes it possible to reduce the number of times the first interlayer insulating film 32 is processed compared to conventional methods.

[0099] <Embodiment 7> Embodiment 7 will be described with reference to Fig. 39 or 40. In this embodiment 7, a third terminal portion 637γ is added to the terminal portion 637 of the above-described embodiment 1. Note that a redundant description of the structure, action, and effect similar to those of the above-described embodiment 1 will be omitted.

[0100] The multiple terminals 37 (see FIG. 7) according to this embodiment include a third terminal 637γ shown in FIGS. 39 and 40. The third terminal 637γ has a stacked film portion (fifth terminal portion) 637γ1 made up of a portion of the first transparent electrode film T1 and a portion of the fourth metal film M4, and a transparent electrode portion (sixth terminal portion) 637γ2 made up of a portion of the second transparent electrode film. The stacked film portion 637γ1 is disposed on the upper side of the second interlayer insulating film 633. The transparent electrode portion 637γ2 is disposed overlapping the stacked film portion 637γ1 via the third interlayer insulating film 635. The third interlayer insulating film 635, interposed between the stacked film portion 637γ1 and the transparent electrode portion 637γ2, is provided with a seventh terminal contact hole (seventh contact hole) CHT7, which is disposed at a position overlapping both the stacked film portion 637γ1 and the transparent electrode portion 637γ2. The laminated film portion 637γ1 and the transparent electrode portion 637γ2 are connected to each other through a seventh terminal contact hole CHT7 in the third interlayer insulating film 635.

[0101] As described above, in this embodiment, the seventh terminal contact hole CHT7 for connecting the stacked film portion 637γ1 and the transparent electrode portion 637γ2 that constitute the third terminal portion 637γ is provided in the third interlayer insulating film 635, but is not formed in the first interlayer insulating film 632. Therefore, during manufacturing, there is no need to process the first interlayer insulating film 632 to provide the third terminal portion 637γ in the non-display area NAA. This allows the number of times the first interlayer insulating film 632 is processed to be reduced compared to conventional methods.

[0102] As described above, the liquid crystal panel 11 according to this embodiment includes a display area AA (see FIG. 1) where an image is displayed, a non-display area NAA (see FIG. 1) where no image is displayed, a TFT 24 (see FIG. 6) arranged in the display area AA, upper layer wiring 27B (see FIG. 4) arranged in the display area AA and connected to the TFT 24, a pixel electrode 25 (see FIG. 6) arranged in the display area AA and connected to the TFT 24, a common electrode 28 (see FIG. 4) arranged in the display area AA, and a third terminal portion 637γ arranged in the non-display area NAA. The TFT 24 includes: The upper wiring 27B includes a gate electrode 24A made of a first metal film M1, a semiconductor portion 24D made of a semiconductor film S1 arranged on the upper layer side of the first metal film M1 via a gate insulating film 631 and arranged to overlap the gate electrode 24A, a source electrode 24B made of a second metal film M2 arranged on the upper layer side of the semiconductor film S1 and connected to the semiconductor portion 24D, and a drain electrode 24C made of a portion of the second metal film M2 different from the source electrode 24B and connected to the semiconductor portion 24D. The upper wiring 27B is an upper layer wiring 27B that is connected to the second metal film M2 via a first interlayer insulating film 32. The pixel electrode 25 is made of a third metal film M3 disposed on the side of the third metal film M3, and a part of the third metal film M3 overlaps with the source electrode 24B, the pixel electrode 25 is made of a first transparent electrode film T1 and a fourth metal film M4 which are fourth conductive films disposed on the upper side with the second interlayer insulating film 633 which is a third insulating film and the planarizing film 34 interposed therebetween, the common electrode 28 is made of a second transparent electrode film T2 which is disposed on the upper side with the first transparent electrode film T1 and the fourth metal film M4 which are fourth conductive films interposed therebetween, the third interlayer insulating film 635 interposed therebetween, and ... third terminal portion 637 γ has a stacked film portion (fifth terminal component) 637γ1 consisting of a portion of the fourth conductive film, the first transparent electrode film T1, and the fourth metal film M4, which is different from the pixel electrode 25, and a transparent electrode portion (sixth terminal component) 637γ2 consisting of a portion of the second transparent electrode film T2, which is different from the common electrode 28, and at least a portion of which is arranged to overlap with the stacked film portion 637γ1, and the first interlayer insulating film 632 is provided with a source contact hole CHS (see FIG. 6) arranged at a position overlapping with both the upper layer wiring 27B and the source electrode 24B, and the third interlayer insulating film 635 hasA seventh terminal contact hole (seventh contact hole) CHT7 is provided at a position where it overlaps with both the stacked film portion 637γ1 and the transparent electrode portion 637γ2.

[0103] The TFT 24 arranged in the display area AA is driven when a potential equal to or greater than the threshold voltage is supplied to the gate electrode 24A. Then, a signal is supplied from the upper-layer wiring 27B to the source electrode 24B, and then to the drain electrode 24C via the semiconductor portion 24D. The pixel electrode 25 connected to the drain electrode 24C is charged to the potential of the signal. An electric field corresponding to the potential difference is generated between the pixel electrode 25 and the common electrode 28 overlapping the pixel electrode 25 via the third interlayer insulating film 635, and this electric field is utilized for display. In the display area AA, the upper-layer wiring 27B, which is a part of the third metal film M3, is connected to the source electrode 24B, which is a part of the second metal film M2, through a source contact hole CHS in the first interlayer insulating film 632. In the non-display area NAA, a transparent electrode portion 637γ2 consisting of a part of the second transparent electrode film T2 is connected to a stacked film portion 637γ1 consisting of the first transparent electrode film T1, which is the fourth conductive film, and a part of the fourth metal film M4, through a seventh terminal contact hole CHT7 in the third interlayer insulating film 635. Therefore, during manufacturing, there is no need to process the first interlayer insulating film 632 to provide the third terminal portion 637γ in the non-display area NAA. This makes it possible to reduce the number of times the first interlayer insulating film 632 is processed compared to conventional methods.

[0104] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0105] (1) The first terminal portion 37α, 337α, 437α, the second terminal portion 537β and the third terminal portion 637γ may be included in a plurality of terminal portions 37 arranged in the arrangement area of ​​the flexible substrate 13 in the non-display area NAA of the array substrate 21.

[0106] (2) The relationship in line width between the lower layer wiring 27A and the upper layer wiring 27B constituting the source wiring 27, 127 can be changed as appropriate other than as shown in the drawings. In addition, the relationship in line width between the touch wiring 30, the lower layer wiring 27A, and the upper layer wiring 27B can also be changed as appropriate other than as shown in the drawings.

[0107] (3) The gate wiring 26, 126 may be configured to have a partially widened width, and the widened portions may form the gate electrodes 24A, 124A of the TFTs 24, 124, 224.

[0108] (4) The specific planar shapes of the gate electrodes 24A, 124A, source electrodes 24B, 124B, 224B, drain electrodes 24C, 224C, and semiconductor portions 24D, 224D of the TFTs 24, 124, 224 can be appropriately changed from those shown in the drawings.

[0109] (5) The specific planar shapes of the pixel electrodes 25 and 225 can be appropriately changed to those not shown in the drawings.

[0110] (6) In the array substrate 21, the fourth metal film M4 may be disposed on the lower side of the first transparent electrode film T1. In this case, an insulating film may be provided between the lower fourth metal film M4 and the upper first transparent electrode film T1. When an insulating film is provided between the fourth metal film M4 and the first transparent electrode film T1, the touch wiring 30 may have a single-layer structure made of only the fourth metal film M4, and the pixel electrodes 25, 225 may have a single-layer structure made of only the first transparent electrode film T1.

[0111] (7) The liquid crystal panel 11 may not have a touch panel pattern (touch panel function). In this case, the common electrode 28 has an undivided structure, and the touch electrode 29 is not formed. In this case, instead of the touch wiring 30, a common wiring connected to the common electrode 28 and supplying a common potential signal may be provided using the first transparent electrode film T1 and the third metal film M3.

[0112] (8) In the above (7), the array substrate 21 may not have the fourth metal film M4. In that case, the touch wiring 30 and the common wiring may not be formed.

[0113] (9) The number and arrangement of the drivers 12 and flexible substrates 13 can be changed as appropriate to other than those shown in the drawings.

[0114] (10) The material of the semiconductor film provided on the array substrate 21 may be an amorphous silicon material, a polycrystalline polysilicon material, or the like, in addition to an oxide semiconductor material.

[0115] (11) The pixel electrode 25 may be made of the second transparent electrode film T2, and the common electrode 28 may be made of the first transparent electrode film T1. In this case, it is preferable to form a slit in the pixel electrode 25 for alignment control.

[0116] (12) The TFTs 24, 124, and 224 may be of either a top gate type or a double gate type.

[0117] (13) Instead of the circuit unit 14, a gate driver may be mounted on the array substrate 21.

[0118] (14) The driver 12 may be mounted on the flexible substrate 13 by COF (Chip On Film) which is mounted on the array substrate 21 by FOG (Film On Glass).

[0119] (15) The planar shape of the liquid crystal panel 11 may be a vertically long rectangle, a square, a circle, a semicircle, a vertically long oval, an ellipse, a trapezoid, or the like.

[0120] (16) The display mode of the liquid crystal panel 11 may be, other than the FFS mode, a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, or the like.

[0121] (17) The liquid crystal panel 11 may be a reflective or semi-transmissive type in addition to a transmissive type.

[0122] (18) The display device may be other than the liquid crystal panel 11 (such as an organic EL (Electro Luminescence) display panel) or an EPD (microcapsule electrophoretic display panel). [Explanation of symbols]

[0123] 11... liquid crystal panel (display device), 24, 124, 224... TFT (switching element), 24A, 124A... gate electrode (first electrode), 24B, 124B, 224B... source electrode (second electrode), 24C, 224C... drain electrode (third electrode), 24D, 224D... semiconductor portion, 25, 225... pixel electrode, 26, 126... gate wiring (third wiring), 27A... lower layer wiring (second wiring), 27B... upper layer wiring (first wiring), 28... common electrode, 31, 131, 231, 331, 431, 531, 631... gate insulating film (first insulating film), 32,132,232,332,432,532,632...first interlayer insulating film (second insulating film), 33,233,333,433,533,633...second interlayer insulating film (third insulating film), 34,234...planarization film (third insulating film), 35,335,435,535,635...third interlayer insulating film (fourth insulating film), 36...intermediate electrode (fourth electrode), 37α,337α,437α...first terminal portion, 37α1,337α1,437α1...second metal film portion (first terminal component), 37α2,337α2,437α2...third metal film portion (second terminal sub-component), 127...source wiring (first wiring), 537β...second terminal portion, 537β1...third metal film portion (third terminal portion), 537β2...transparent electrode portion (fourth terminal portion), 637γ...third terminal portion, 637γ1...laminated film portion (fifth terminal portion), 637γ2...transparent electrode portion (sixth terminal portion), AA...display area, CHP1...first pixel contact hole (third contact hole), CHP2...second pixel contact hole (fourth contact hole), CHP3...third pixel contact hole (fifth contact hole), CHS... Source contact hole (first contact hole), CHT1...first terminal contact hole (second contact hole), CHT6...sixth terminal contact hole (sixth contact hole), CHT7...seventh terminal contact hole (seventh contact hole), M1...first metal film (first conductive film), M2...second metal film (second conductive film), M3...third metal film (third conductive film), M4...fourth metal film (fourth conductive film), NAA...non-display area, S1...semiconductor film, T1...first transparent electrode film (fourth conductive film), T2...second transparent electrode film (fifth conductive film)

Claims

1. a display area in which an image is displayed; a non-display area in which the image is not displayed; a switching element disposed in the display area; a first wiring arranged in the display area and connected to the switching element; a first terminal portion disposed in the non-display area, the switching element has: a first electrode made of a first conductive film; a semiconductor portion made of a semiconductor film arranged on an upper layer side of the first conductive film with a first insulating film interposed therebetween and arranged so as to overlap the first electrode; a second electrode made of a second conductive film arranged on an upper layer side of the semiconductor film and connected to the semiconductor portion; and a third electrode made of a portion of the second conductive film different from the second electrode and connected to the semiconductor portion, the first wiring is made of a third conductive film disposed on an upper layer side of the second conductive film via a second insulating film, and a part of the third conductive film is disposed so as to overlap the second electrode; the first terminal portion has a first terminal component made of a portion of the second conductive film different from the second electrode and the third electrode, and a second terminal component made of a portion of the third conductive film different from the first wiring, at least a portion of which is arranged to overlap the first terminal component, A display device in which the second insulating film is provided with a first contact hole arranged at a position overlapping both the first wiring and the second electrode, and a second contact hole arranged at a position overlapping both the first terminal component and the second terminal component.

2. a second wiring disposed in the display area; 2. The display device according to claim 1, wherein the second wiring is made of a part of the second conductive film that is different from the second electrode, the third electrode, and the first terminal component, is connected to the second electrode, extends along the first wiring, and is arranged overlapping the first wiring via the second insulating film.

3. a third wiring disposed in the display area; 2. The display device according to claim 1, wherein the third wiring is made of a part of the first conductive film that is different from the first electrode, is connected to the first electrode, and intersects with the first wiring via the first insulating film and the second insulating film.

4. a fourth electrode disposed in the display area and connected to the third electrode; a pixel electrode disposed in the display region and connected to the fourth electrode; the fourth electrode is made of a portion of the third conductive film that is different from the first wiring, and is disposed so that at least a portion of the fourth electrode overlaps with the third electrode; the pixel electrode is made of a fourth conductive film disposed on an upper layer side of the third conductive film via a third insulating film, and a part of the fourth conductive film is disposed so as to overlap with the fourth electrode; a third contact hole is provided in the second insulating film so as to overlap both the third electrode and the fourth electrode; 4. The display device according to claim 1, wherein the third insulating film is provided with a fourth contact hole arranged at a position overlapping both the fourth electrode and the pixel electrode.

5. a pixel electrode disposed in the display area and connected to the third electrode; the pixel electrode is made of a fourth conductive film disposed on an upper layer side of the third conductive film via a third insulating film, and a part of the fourth conductive film is disposed so as to overlap the third electrode; 4. The display device according to claim 1, wherein a fifth contact hole is provided in the second insulating film and the third insulating film so as to communicate with the second insulating film and the third insulating film, the fifth contact hole being arranged at a position overlapping both the third electrode and the pixel electrode.

6. a display area in which an image is displayed; a non-display area in which the image is not displayed; a switching element disposed in the display area; a first wiring arranged in the display area and connected to the switching element; a pixel electrode disposed in the display area and connected to the switching element; a common electrode disposed in the display area; a second terminal portion disposed in the non-display area, the switching element has: a first electrode made of a first conductive film; a semiconductor portion made of a semiconductor film arranged on an upper layer side of the first conductive film with a first insulating film interposed therebetween and arranged so as to overlap the first electrode; a second electrode made of a second conductive film arranged on an upper layer side of the semiconductor film and connected to the semiconductor portion; and a third electrode made of a portion of the second conductive film different from the second electrode and connected to the semiconductor portion, the first wiring is made of a third conductive film disposed on an upper layer side of the second conductive film via a second insulating film, and a part of the third conductive film is disposed so as to overlap the second electrode; the pixel electrode is made of a fourth conductive film disposed on an upper layer side of the third conductive film via a third insulating film, and a part of the pixel electrode is disposed to overlap with the third electrode and is connected to the third electrode; the common electrode is made of a fifth conductive film disposed on an upper layer side of the fourth conductive film with a fourth insulating film interposed therebetween, and is disposed so as to overlap the pixel electrode with the fourth insulating film interposed therebetween; the second terminal portion has a third terminal component made of a portion of the third conductive film different from the first wiring, and a fourth terminal component made of a portion of the fifth conductive film different from the common electrode, at least a portion of which is arranged to overlap the third terminal component, a first contact hole is provided in the second insulating film so as to overlap both the first wiring and the second electrode; The display device further comprises a sixth contact hole provided in the third insulating film and the fourth insulating film so as to communicate with the sixth contact hole and to be arranged at a position overlapping both the third terminal component and the fourth terminal component.

7. a display area in which an image is displayed; a non-display area in which the image is not displayed; a switching element disposed in the display area; a first wiring arranged in the display area and connected to the switching element; a pixel electrode disposed in the display area and connected to the switching element; a common electrode disposed in the display area; a third terminal portion disposed in the non-display area, the switching element has: a first electrode made of a first conductive film; a semiconductor portion made of a semiconductor film arranged on an upper layer side of the first conductive film with a first insulating film interposed therebetween and arranged so as to overlap the first electrode; a second electrode made of a second conductive film arranged on an upper layer side of the semiconductor film and connected to the semiconductor portion; and a third electrode made of a portion of the second conductive film different from the second electrode and connected to the semiconductor portion, the first wiring is made of a third conductive film disposed on an upper layer side of the second conductive film via a second insulating film, and a part of the third conductive film is disposed so as to overlap the second electrode; the pixel electrode is made of a fourth conductive film disposed above the third conductive film with a third insulating film interposed therebetween, the common electrode is made of a fifth conductive film disposed on an upper layer side of the fourth conductive film with a fourth insulating film interposed therebetween, and is disposed so as to overlap the pixel electrode with the fourth insulating film interposed therebetween; the third terminal portion has a fifth terminal component made of a portion of the fourth conductive film different from the pixel electrode, and a sixth terminal component made of a portion of the fifth conductive film different from the common electrode, at least a portion of which is arranged to overlap the fifth terminal component, a first contact hole is provided in the second insulating film so as to overlap both the first wiring and the second electrode; The display device further comprises a seventh contact hole provided in the fourth insulating film, the seventh contact hole being arranged at a position overlapping both the fifth terminal component and the sixth terminal component.

8. forming a first conductive film, and patterning the first conductive film to provide a first electrode in a display area where an image is displayed; forming a first insulating film on the upper layer side of the first conductive film; forming a semiconductor film on an upper layer side of the first insulating film, and patterning the semiconductor film to provide a semiconductor portion disposed so as to overlap the first electrode; forming a second conductive film on an upper layer side of the semiconductor film, and patterning the second conductive film to provide a second electrode connected to the semiconductor portion and a third electrode connected to the semiconductor portion, and providing a first terminal component in a non-display area where the image is not displayed; forming a second insulating film on an upper layer side of the second conductive film, and patterning the second insulating film to provide a first contact hole arranged at a position overlapping the second electrode and a second contact hole arranged at a position overlapping the first terminal component; a third conductive film formed on an upper layer side of the second insulating film; and patterning the third conductive film to provide a first wiring that is arranged in the display area and a portion of which overlaps with the second electrode and the first contact hole; and a second terminal component that is arranged in the non-display area and at least a portion of which overlaps with the first terminal component and the second contact hole, and that constitutes a first terminal together with the first terminal component.

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