Display device

Abstract

To provide a liquid crystal display device capable of reducing power consumption.SOLUTION: A liquid crystal display device includes: a display panel including a driver circuit portion and a pixel portion; a signal generation circuit for generating a control signal for driving the driver circuit portion and an image signal which is supplied to the pixel portion; a memory circuit for storing the image signal by frame periods; a comparison circuit for detecting a difference between image signals for a series of frame periods among the image signals stored by frame periods in the memory circuit; a selection circuit which selects and outputs the image signals for the series of frame periods, when the difference is detected in the comparison circuit; and a display control circuit which supplies the control signal and the image signals output from the selection circuit to the driver circuit portion, when the difference is detected in the comparison circuit, and stops supplying the control signal to the driver circuit portion, when the difference is not detected in the comparison circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a liquid crystal display device, or to an electronic device equipped with the liquid crystal display device. do. [Background technology]

[0002] As typified by liquid crystal display devices, thin film transistors formed on flat plates such as glass substrates are They are made of amorphous silicon, polycrystalline silicon, etc. Thin-film transistors using silicon have low field-effect mobility, but they are suitable for large-area applications on glass substrates. On the other hand, thin film transistors using crystalline silicon can handle field effect mobility Although the cost is high, a crystallization process such as laser annealing is required, and it is difficult to increase the area of ​​glass substrates. It has the characteristic that it is not always suitable.

[0003] In response to this, thin film transistors are being fabricated using oxide semiconductors, and they are being used in electronic devices and optical devices. For example, zinc oxide or I Thin film transistors were fabricated using n-Ga-Zn-O oxide semiconductors, and used in liquid crystal displays. Patent Document 1 discloses a technique used for switching elements and the like. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 Summary of the Invention [Problem to be solved by the invention]

[0005] Thin film transistors that use oxide semiconductors for the channel region are made of amorphous silicon. It has been pointed out that a higher field-effect mobility can be obtained than in thin-film transistors using a silicon nitride film in the panel region. A pixel including a thin film transistor formed using such an oxide semiconductor is It is expected to be applied to display devices such as liquid crystal displays.

[0006] Each pixel of the liquid crystal display device has a holding circuit that holds a voltage for controlling the orientation of the liquid crystal element. The size of the storage capacitor is determined by the off-state of the thin film transistor. By reducing the off-current, the voltage can be maintained by the storage capacitor. This allows for a longer battery life and reduces power consumption when displaying still images, etc. becomes important.

[0007] In addition to achieving low power consumption when displaying still images, the display also displays moving images. It is important to make the device into a display device in order to increase the added value of the display device. By determining the image and switching between still and moving images, It is important to enhance the effect of reducing power consumption by reducing the power consumption of the

[0008] The off-state current described in this specification refers to the current that flows when a thin film transistor is in an off state (also called a non-conducting state). This refers to the current that flows between the source and drain when the n-channel thin-film transistor In a transistor (for example, with a threshold voltage of about 0 to 2 V), a voltage applied between the gate and source This refers to the current that flows between the source and drain when the applied voltage is negative.

[0009] In addition, LCD displays with added value, such as 3D displays and 4k2k displays, are also available. In the device, the area per pixel is expected to become smaller, while the aperture ratio is expected to improve. In order to improve the aperture ratio, it is important to reduce the storage capacitor area. It is desirable to reduce the off-state current of film transistors.

[0010] In view of this, one embodiment of the present invention is to provide a pixel including a thin film transistor using an oxide semiconductor. The present invention provides a liquid crystal display device capable of reducing the off-current of a thin film transistor and reducing power consumption. One of the challenges is to [Means for solving the problem]

[0011] One embodiment of the present invention is a transistor including a driver circuit portion and a semiconductor layer formed of an oxide semiconductor. a display panel having a pixel section in which a pixel is provided with a pixel driver, a control signal for driving a driving circuit section, and a signal generating circuit for generating an image signal to be supplied to the pixel unit; and a signal generating circuit for generating an image signal to be supplied to the pixel unit during a frame period. a memory circuit for storing the image signals for each frame period, and a memory circuit for storing the image signals for each frame period. A comparison circuit detects the difference between the image signals during the frame period, and when the comparison circuit detects the difference, A selection circuit selects and outputs the image signals of consecutive frame periods, and a comparison circuit detects the difference. When the signal is output, the control signal and the image signal output from the selection circuit are supplied to the drive circuit. When the comparison circuit does not detect a difference, a display control circuit stops supplying a control signal to the drive circuit. and a liquid crystal display device having a line.

[0012] In one aspect of the present invention, the control signal may be a high power supply potential, a low power supply potential, a clock signal, a star signal, or a combination of the above. The liquid crystal display device may also include a start pulse signal and a reset signal.

[0013] In one embodiment of the present invention, the oxide semiconductor has a hydrogen concentration detected by secondary ion mass spectrometry. is 1×10 16 / cm 3 The following liquid crystal display device may also be used.

[0014] In one embodiment of the present invention, the oxide semiconductor has a carrier density of 1×10 14 / cm 3 Less than A liquid crystal display device may also be used. [Effects of the Invention]

[0015] In a pixel including a thin film transistor using an oxide semiconductor, an off-state current is reduced. Therefore, the period during which the voltage can be held by the storage capacitor can be extended, and still images can be displayed. It is possible to provide a liquid crystal display device that can reduce power consumption when displaying the above. By improving the aperture ratio, it is possible to provide a liquid crystal display device having a high-definition display portion. can.

[0016] Furthermore, by configuring the display device to display moving images in addition to still images, It is possible to increase added value. By switching between these two modes to display a still image, it is possible to reduce power consumption. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a block diagram illustrating an example of a liquid crystal display device. [Figure 2] FIG. 2 is a diagram showing an example of a driver circuit. [Figure 3] FIG. 2 is a timing chart of a driver circuit. [Figure 4] FIG. 2 is a diagram showing an example of a driver circuit. [Figure 5] 1A to 1C illustrate a thin film transistor. [Figure 6]1A to 1C illustrate a method for manufacturing a thin film transistor. [Figure 7] 1A to 1C illustrate a thin film transistor. [Figure 8] 1A to 1C illustrate a method for manufacturing a thin film transistor. [Figure 9] 1A to 1C illustrate a thin film transistor. [Figure 10] 1A to 1C illustrate a method for manufacturing a thin film transistor. [Figure 11] 1A to 1C illustrate a method for manufacturing a thin film transistor. [Figure 12] 1A to 1C illustrate a method for manufacturing a thin film transistor. [Figure 13] 1A to 1C illustrate a method for manufacturing a thin film transistor. [Figure 14] 1A to 1C illustrate a thin film transistor. [Figure 15] FIG. 2 is a diagram illustrating a liquid crystal panel. [Figure 16] 1A and 1B are diagrams illustrating electronic devices. [Figure 17] 1A and 1B are diagrams illustrating electronic devices. [Figure 18] 1A and 1B illustrate a display panel and a thin film transistor. [Figure 19] FIG. 22 is a diagram for explaining embodiment 13. [Figure 20] FIG. 22 is a diagram for explaining embodiment 13. [Figure 21] FIG. 22 is a diagram for explaining embodiment 13. [Figure 22] FIG. 22 is a diagram for explaining embodiment 13. [Figure 23] FIG. 20 is a diagram for explaining embodiment 14. [Figure 24] FIG. 20 is a diagram for explaining embodiment 14. [Figure 25] FIG. 20 is a diagram for explaining embodiment 14. [Figure 26] FIG. 1 is a diagram for explaining the first embodiment. [Figure 27] FIG. 1 is a diagram for explaining a first embodiment. [Figure 28] FIG. 1 is a diagram for explaining a first embodiment. [Figure 29] FIG. 10 is a diagram for explaining a second embodiment. [Figure 30] FIG. 10 is a diagram for explaining a second embodiment. [Figure 31] FIG. 10 is a diagram for explaining a third embodiment. [Figure 32] FIG. 10 is a diagram for explaining a third embodiment. [Figure 33] FIG. 10 is a diagram for explaining a fourth embodiment. [Figure 34] FIG. 10 is a diagram for explaining a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments and examples of the present invention will be described with reference to the drawings. The invention can be embodied in many different ways, and it is understood that these may not depart from the spirit and scope of the invention. It will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the present embodiment and examples. In the configuration of the present invention described below, the same reference numerals are used in different drawings. This is common to all.

[0019] The size, thickness of layers, and regions of each component shown in the drawings of each embodiment are not clearly indicated. The figures may be exaggerated for clarity. It will not be done.

[0020] The terms "first," "second," "third," and "Nth" (N is a natural number) used in this specification refer to the configurations. It is added to avoid confusion of elements and is not intended to limit the number. do.

[0021] (Embodiment 1) In this embodiment, a block diagram of a display device, a procedure for stopping the operation in a driver circuit, and The start procedure will be described below. First, referring to FIG. 1, a block diagram of the display device will be described.

[0022] The liquid crystal display device 1000 shown in this embodiment includes a display panel 1001, a signal generating circuit 10, and a 02, memory circuit 1003, comparison circuit 1004, selection circuit 1005, display control circuit 1006 It has.

[0023] The display panel 1001 includes, for example, a driver circuit portion 1007 and a pixel portion 1008 . The gate line driving circuit 1009A and the signal line driving circuit 1009B are included. 1009A and a signal line driver circuit 1009B drive a pixel portion 1008 having a plurality of pixels. The gate line driver circuit 1009A and the signal line driver circuit 1009B are driver circuits for The pixel portion 1008 and the pixel portion 1009 are configured by transistors formed on the same substrate. So that's fine.

[0024] The gate line driver circuit 1009A, the signal line driver circuit 1009B, and the pixel portion 1008 are The transistor used is an n-channel transistor with an oxide semiconductor semiconductor layer. In addition, the gate line driver circuit 1009A or the signal line driver circuit 1009B in the driver circuit section 1007 is 1009B may be formed on the same substrate or on a separate substrate. You may do so.

[0025] The display method in the pixel unit 1008 may be a progressive method, an interlace method, etc. In addition, RG can be used as a color element controlled by pixels when displaying colors. It is not limited to the three colors of RGBW (W is white) and B (R is red, G is green, B is blue). (representing the color), or RGB plus one or more colors such as yellow, cyan, or magenta The size of the display area may be different for each dot of the color element. The present invention is not limited to color display devices, but may also be applied to monochrome display devices. It is also possible to do so.

[0026] Next, the gate line driver circuit 1009A, the signal line driver circuit 1009B, and the pixel portion 1008 An oxide semiconductor layer used as a semiconductor layer of a transistor forming the semiconductor device will be described.

[0027] The oxide semiconductor used in this embodiment has a hydrogen concentration of 1×10 16 / c m 3 The hydrogen or OH bond contained in the oxide semiconductor is removed. Carrier density is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 The following acids The thin film transistor has a channel region formed of a nitride semiconductor film. In the specification, the carrier density is 1×10 12 / cm 3 An oxide semiconductor with an average conductivity of less than 1000 Ω is called an intrinsic (I-type) oxide semiconductor. and above that, the carrier density is 1×10 14 / cm 3 The following oxide semiconductors are essentially The hydrogen concentration in the oxide semiconductor layer is measured by secondary ion mass spectrometry. (SIMS: Secondary Ion Mass Spectroscopy) This was done.

[0028] The band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, and more preferably If the voltage is set to 3 eV or more, the carriers generated by thermal excitation can be ignored. Impurities such as hydrogen that can become carriers are reduced as much as possible, and the carrier density is reduced to 1×10 14 / cm 3 less than , preferably 1 x 10 12 / cm 3 That is, the capacitance of the oxide semiconductor layer is set as follows. The rear density should be as close to zero as possible.

[0029] In this way, highly purified oxide was obtained by thoroughly removing hydrogen contained in the oxide semiconductor. By using a nitride semiconductor in the channel formation region of a thin-film transistor, the channel width can be increased to 10 m. Even in the case of m, the drain voltage ranges from 1V to 10V and the gate voltage ranges from -5V to -2 In the 0V range, the drain current is 1×10 -13 It will be A or below.

[0030] A display device or the like is manufactured using a thin film transistor with an extremely small off-state current. In this case, the off-state current is small and there is almost no leakage, so the display data can be retained for a long time. It can be made easier.

[0031] Specifically, the transistor including the oxide semiconductor layer has a channel width of 10 μm. In this case, the off-state current per 1 μm of channel width is 10 aA / μm (1 × 10 -17 A / μm) or less, and further, 1 aA / μm (1×10 -18 A / μm or less It is possible to create a transistor with an extremely small current value in the off state (off-state current value). A gate line driver circuit 1009A, a signal line driver circuit 1009B, and a pixel portion 1008 are formed. By using it as a transistor, it is possible to extend the retention time of electrical signals such as video signals. Since the retention time can be extended, for example, after writing a video signal, The retention period is 10 seconds or more, preferably 30 seconds or more, and more preferably 1 minute or more but less than 10 minutes. By extending the retention period, the interval between writes can be extended, reducing power consumption. This can increase the effectiveness of the product.

[0032] The difficulty in flowing an off-state current through a transistor can be expressed as an off-state resistivity. Resistivity is the resistivity of the channel formation region when the transistor is off, and the off resistivity is It can be calculated from the off-state current.

[0033] Specifically, if the values ​​of the off-state current and drain voltage are known, the transistor can be calculated from Ohm's law. The resistance value when the transistor is off (off resistance R) can be calculated. The cross-sectional area A and the length of the channel formation region (corresponding to the distance between the source and drain electrodes) L are Then, the off-resistivity ρ can be calculated from the formula ρ=RA / L (R is the off-resistance).

[0034] Here, the cross-sectional area A is defined as follows: A = dW. The length L of the channel forming region is the channel length L. As described above, the off-state resistivity can be calculated from the off-state current.

[0035] The off-state resistivity of the transistor including the oxide semiconductor layer of this embodiment is 1×10 9 Ω m More than 1×10 is preferable, and even more preferable is 1×10 10 Ω·m or more is more preferable.

[0036] On the other hand, for example, in a transistor using low-temperature polysilicon, the off-current is 1×10 -12 The design is based on the estimation that it is equivalent to A / μm. In a transistor having When the capacitance is the same (about 0.1 pF), the voltage retention period is 10 5 Stretch it out to about twice its size. In addition, in the case of a transistor having amorphous silicon, the channel width is 1 The off-state current per μm is 1×10 -13 A / μm or more. Therefore, the retention capacity is When the capacitance is the same (about 0.1 pF), the transistor using a high-purity oxide semiconductor has a higher capacitance. Compared to transistors using amorphous silicon, the voltage retention period is 10 4 More than double It can be stretched out.

[0037] For example, a pixel having a transistor using low-temperature polysilicon typically displays a 60 This is done at frames per second (16 msec per frame). Similarly, if the rate is reduced (the interval between writes is extended), the pixel voltage decreases and the display On the other hand, when a transistor including the above-described oxide semiconductor layer is used, In this case, the off-state current is small, so the retention period for one signal write is 10 5 double 160 It can be set to about 0 seconds.

[0038] Furthermore, even with a small number of image signal writes, still images can be displayed on the display unit. Since the retention period can be made longer, the frequency of writing signals can be reduced, especially when displaying still images. For example, the number of times that a pixel is written during the display period of one still image can be reduced. , 1 time or n times, where n is 2 or more and 10 3 This is the number of times or less. This makes it possible to reduce the power consumption of the display device.

[0039] Generally, each pixel is constructed by sandwiching an insulating layer as a dielectric between a pair of electrodes. A storage capacitor is provided. The size of the storage capacitor is determined by the number of transistors provided in each pixel. The value may be set in consideration of the off-state current and the like. In this embodiment mode, By using a transistor having a high-purity oxide semiconductor layer as a transistor, The capacitance is 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in the element. It is sufficient to provide a storage capacitor.

[0040] The above-described transistor including a high-purity oxide semiconductor layer can have a long retention period. Therefore, the frequency of signal writing can be significantly reduced, especially when displaying still images. Therefore, when displaying still images with few changes in display, the writing of signals to pixels is Since the number of write operations can be reduced, power consumption can be reduced.

[0041] In addition, when displaying a still image, the retention rate of the voltage applied to the liquid crystal element during the retention period is taken into consideration. For example, a signal may be written to the pixel electrode of the liquid crystal element. The timing when the voltage drops to a predetermined level compared to the voltage value (initial value) immediately after The voltage to be set as the predetermined level is set to the value that is the same as the initial value but without flickering. It is preferable to set it to a level that is not noticeable. Specifically, it should be set to 10% lower than the initial value. Preferably, a refresh operation (rewrite) is performed every time the voltage drops by 3%. preferable.

[0042] In addition, during the retention period of a still image display, the opposing electrode (also called the common electrode) ) can be in a floating state. Specifically, a common potential is applied to the opposing electrode. A switch is provided between the power supply and the counter electrode, and the switch is turned on during the writing period. After applying a common potential from the power source to the counter electrode, the switch is turned off for the remaining hold period. The switch can also be made of the high purity oxide semiconductor described above. It is preferable to use a transistor having a conductive layer.

[0043] The signal generating circuit 1002 includes a gate line driving circuit 1009A and a signal line driving circuit 1006B. The signal generating circuit 1002 is a circuit that generates a signal to drive the wiring 09B. A circuit for outputting a signal for driving the driving circuit unit 1007 via a wiring, and a memory An image signal (also called a video voltage, a video signal, or video data) is output to the circuit 1003. In other words, it is a circuit for transmitting control signals for driving the driving circuit portion 1007 and 008.

[0044] Specifically, the signal generating circuit 1002 outputs control signals to a gate line driving circuit 1009A, The signal line driver circuit 1009B is supplied with a high power supply potential VDD and a low power supply potential VSS. A start pulse SP, a clock signal CK, and / Or, generate a start pulse SP and a clock signal CK for the signal line driver circuit 1009B. The signal generating circuit 1002 also generates and outputs an image signal for displaying a moving image or a still image. The signal Data is output to the memory circuit 1003 .

[0045] The moving image is a representation of a human being, which is created by switching between multiple time-divided frames at high speed. Specifically, it refers to an image that is recognized as a moving image by the human eye at 60 times per second (60 frames). By switching between images more than 100 frames per second, the human eye perceives the image as a moving image with less flicker. On the other hand, still images are different from moving images in that they are generated over multiple frame periods. Although multiple time-division images are switched at high speed, the For example, an image signal that does not change between the nth frame and the (n+1)th frame is called say.

[0046] The signal generating circuit 1002 is also a circuit that generates other signals such as image signals and latch signals. The signal generating circuit 1002 may also include a gate line driving circuit 1009A and / or a signal The signal line driver circuit 1009B is provided with a reset signal to stop the output of the pulse signal of each driver circuit. Each signal may be a first clock signal, a second clock signal, or a The signal may be a signal composed of multiple signals such as a clock signal.

[0047] The high power supply potential VDD is a potential higher than the reference potential, and the low power supply potential VSS is The high power supply potential and the low power supply potential are both potentials below the reference potential. It is desirable that the potential be such that the device can operate.

[0048] Voltage refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage difference, respectively. It is possible to do this.

[0049] The image signal output from the signal generating circuit 1002 to the memory circuit 1003 is an analog signal. In this case, the signal is converted into a digital signal via an A / D converter or the like and stored in the memory circuit 1003. It is sufficient to configure it to output.

[0050] The memory circuit 1003 stores a plurality of frames for storing image signals relating to the plurality of frames. The frame memory includes a memory 1010. The frame memory may be, for example, a DRAM (Dynamic Random Access Memory). andom Access Memory), SRAM (Static Random The memory may be configured using a memory element such as a memory access memory (RAM).

[0051] The frame memory 1010 may be configured to store an image signal for each frame period. The number of frame memories is not particularly limited. The image signal of 0 is selectively read out by the comparison circuit 1004 and the selection circuit 1005. That is why.

[0052] The comparison circuit 1004 compares the image signals of successive frame periods stored in the memory circuit 1003. This is a circuit for selectively reading out the image signals, comparing them, and detecting the difference. When a difference is detected by the comparison of the image signals in the comparison circuit 1004, the difference is detected. On the other hand, the image in the comparator circuit 1004 is judged to be a moving image. When a difference is not detected by comparing the signals, the difference is not detected in the consecutive frames. In other words, the comparison circuit 1004 detects the difference between the still and the still images. whether the image signals for successive frame periods are image signals for displaying moving images, or It is judged whether the signal is an image signal for displaying a still image. When the difference obtained by the comparison exceeds a certain level, it is determined that a difference has been detected. It may be set as follows.

[0053] The selection circuit 1005 includes a plurality of switches, for example, switches formed of thin film transistors. When an image signal for displaying a moving image is determined by detecting a difference in the comparison circuit, The image signal is selected from the frame memory 1010 in which the image signal is stored, and the display control circuit The comparison circuit 1004 outputs the difference between the frames to the line 1006. If no difference in the image signal is detected, the image displayed in successive frame periods is a still image. In this case, the display control circuit controls the image signal of the latter half of the consecutive frame period. It is only necessary to configure it so that it is not output to the path 1006.

[0054] The display control circuit 1006 receives an image signal, a high power supply potential VDD, a low power supply potential VSS, a start potential Regarding the control signals of the pulse SP, clock signal CK, and reset signal Res, 1007. 4, if it is determined to be a moving image, that is, if the difference between the image signals of consecutive frame periods is extracted, The image signal is supplied from the selection circuit 1005 and is transmitted to the drive circuit 1006 via the display control circuit 1006. The control signal is supplied to the drive circuit unit 1007 via the display control circuit 1006. On the other hand, the comparator circuit 1004 judges that the image is a still image, i.e., a continuous frame. When the difference between the image signals in the frame period is not extracted, the image signal is supplied from the selection circuit 1005. Therefore, the image signal is not supplied from the display control circuit 1006 to the driver circuit 1007. The display control circuit 1006 stops supplying the control signal to the drive circuit unit 1007 .

[0055] In addition, when it is determined that the image is a still image, if the period during which the image is determined to be a still image is short, the control Of the signals, the high power supply potential VDD and the low power supply potential VSS may not be stopped. The power consumption caused by frequently stopping and restarting the high power supply potential VDD and the low power supply potential VSS This is preferable because it can reduce the increase.

[0056] The image signal and the control signal are stopped when each pixel of the pixel unit 1008 can hold an image signal. It is desirable to supply the image signal again after the retention period of each pixel. The display control circuit 1006 then supplies the image signal and control signal that it previously supplied again. It is sufficient to have a configuration like this.

[0057] The supply of a signal means supplying a predetermined potential to a wiring. and a wiring to which a predetermined fixed potential is supplied, for example, a low power supply potential VS S is connected to the wiring to which the signal is supplied. This refers to cutting off the electrical connection to the wiring connected to the board and leaving it in a floating state.

[0058] As described above, the thin film transistor including the oxide semiconductor layer has an off-state current of 1×10 -12 A / μm or less, the retention period can be extended. In this embodiment, a synergistic effect is seen in reducing power consumption when displaying a still image. It will be included.

[0059] As mentioned above, the video signal is compared to determine whether it is a moving image or a still image, and the clock signal and start pulse are By selectively restarting or stopping the supply of control signals such as pulses to the drive circuit, low power consumption is achieved. Electrification can be achieved.

[0060] Next, the gate line driver circuit 1009A and the signal line driver circuit 1009B of the driver circuit section 1007 are An example of the configuration of the shift register that constitutes this is shown in FIG.

[0061] The shift register shown in FIG. 2A includes first to Nth pulse output circuits 10_1 to 10_N. The shift register shown in FIG. 2A has an output circuit 10_N (N≧3). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are connected to the first wiring 11. A first clock signal CK1 is transmitted through the first wiring 12, a second clock signal CK2 is transmitted through the second wiring 13, and a third clock signal CK3 is transmitted through the third wiring 14. A third clock signal CK3 is transmitted from a line 13, and a fourth clock signal CK4 is transmitted from a fourth line 14. In the first pulse output circuit 10_1, a start pulse is supplied from the fifth wiring 15. The pulse SP1 (first start pulse) is input. The nth pulse output from the second stage onwards In the circuit 10_n (n is a natural number of 2≦n≦N), the pulse output circuit 10_n- The signal from 1 (called the previous stage signal OUT(n-1)) is input. The circuit 10_1 receives a signal from a third pulse output circuit 10_3 located two stages later. Similarly, in the n-th pulse output circuit 10_n in the second stage or later, the (n+2)-th pulse output circuit in the second stage or later The signal from the pulse output circuit 10_(n+2) (called the next stage signal OUT(n+2)) is input. Therefore, the pulse output circuit of each stage outputs the pulses of the next stage and / or the two stages before it. A first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the circuit Then, second output signals (OUT(1)) to OUT(N)) are outputted and inputted to another circuit or the like. As shown in FIG. 2(A), the last two stages of the shift register are connected to the next stage signal. Since OUT(n+2) is not input, for example, a second switch is separately connected to the seventh wiring 17. A third start pulse SP2 is input from the eighth wiring 18, and a third start pulse SP3 is input from the eighth wiring 19. Alternatively, it may be a signal generated internally. The (n+1)th pulse output circuit 10 does not contribute to the pulse output of (n+1) ,th (n+2) Pulse output circuit 10 (n+2) (also called a dummy stage), and the second Generate signals corresponding to the start pulse (SP2) and the third start pulse (SP3). It may also be configured as follows.

[0062] The first clock signal (CK1) to the fourth clock signal (CK4) are generated at regular intervals. It is a signal that alternates between H and L signals. The clock signal (CK4) is delayed by 1 / 4 period in order. The pulse output circuit is driven using the clock signal (CK1) to the fourth clock signal (CK4). The clock signal CK is output as GCK or It is sometimes called SCK, but here we will explain it as CK.

[0063] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are connected functionally, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) Therefore, the predetermined connection relationship For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be applied to the connections shown in the drawings or text. This also includes things other than relationships.

[0064] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The output terminal 25 has a first output terminal 26 and a second output terminal 27 (see FIG. 2(B)).

[0065] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 2(A) and 2(B), for example, In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11. the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal The terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10 2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is The third input terminal 23 is electrically connected to the third wiring 13, and the third input terminal 24 is electrically connected to the fourth wiring 14. It continues.

[0066] 2A and 2B, the first pulse output circuit 10_1 has a fourth input terminal 2 The first start pulse SP1 is input to the input terminal 4, and the subsequent signal OUT(3 ) is input, and the first output signal OUT(1)(SR) is output from the first output terminal 26. , the second output terminal 27 outputs the second output signal OUT(1).

[0067] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0068] In FIG. 2C, the first terminal of the first transistor 31 is electrically connected to the power supply line 51. the second terminal of the ninth transistor 39 is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode of the The second transistor 32 has a first terminal electrically connected to the fourth input terminal 24. The second terminal is electrically connected to the power supply line 52, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. and a gate electrode electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first input terminal 21. The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 One terminal is electrically connected to the power supply line 52, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the power supply line 52. The two terminals are the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 has a first terminal electrically connected to the power supply line 51 and a second terminal electrically connected to the second transistor 36. The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The seventh transistor 3 has a gate electrode electrically connected to the fifth input terminal 25. The first terminal of the transistor 7 is electrically connected to the power supply line 51, and the second terminal of the transistor 38 is electrically connected to the power supply line 51. The gate electrode is electrically connected to the second terminal and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a second terminal connected to the gate electrode of the second transistor 32. 4, and the gate electrode is electrically connected to the second input terminal 2 The ninth transistor 39 has a first terminal electrically connected to the first transistor 2. the second terminal of the second transistor 31 and the second terminal of the second transistor 32; The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are supplied with a voltage. The gate electrode is electrically connected to the power supply line 51. The first terminal of the sigma 40 is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the second output terminal 22. the gate electrode of the ninth transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has a first terminal electrically connected to the power supply line 52. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. do.

[0069] In FIG. 2C, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is defined as a node NA. Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, The second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point between the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is called a node Let's call it NB.

[0070] When the pulse output circuit in FIG. 2C is the first pulse output circuit 10_1, the first input A first clock signal CK1 is input to the input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the third input terminal 24. A start pulse SP is input to the fourth input terminal 24, and a The subsequent signal OUT(3) is input, and the first output signal OUT(1) is output from the first output terminal 26. )(SR) is output, and the second output terminal 27 outputs the second output signal OUT(1). This will be the case.

[0071] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. 2(C) is The chart is shown in FIG. 3. When the shift register is a scanning line driving circuit, The period 61 corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period.

[0072] The driving circuit shown in Figures 2 and 3 is made up of multiple n-channel transistors. In the dynamic circuit, when displaying still images and dynamic images, supply or stop of the potential of each wiring The procedure will be explained below.

[0073] First, when the operation of the drive circuit unit 1007 is stopped, the display control circuit 1006 Then, after the start pulse SP stops, the pulse output shifts. After the register reaches the final stage, each clock signal CK is stopped. The high power supply potential VDD and the low power supply potential VSS are stopped (see FIG. 26(A)). When the operation of the path section 1007 is to be resumed, the display control circuit 1006 first A power supply potential VDD and a low power supply potential VSS are supplied to the driving circuit unit 1007. Then, the supply of the start pulse SP is resumed (see FIG. 26(B)). .

[0074] 2 and 3, the configuration of the drive circuit that does not supply the reset signal Res is shown. However, the configuration for supplying the reset signal Res will be described with reference to FIG.

[0075] The shift register shown in FIG. 4A includes first to Nth pulse output circuits 10_1 to 10_N. The shift register shown in FIG. 4A has an output circuit 10_N (N≧3). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are connected to the first wiring 11. A first clock signal CK1 is transmitted through the first wiring 12, a second clock signal CK2 is transmitted through the second wiring 13, and a third clock signal CK3 is transmitted through the third wiring 14. A third clock signal CK3 is transmitted from a line 13, and a fourth clock signal CK4 is transmitted from a fourth line 14. In the first pulse output circuit 10_1, a start pulse is supplied from the fifth wiring 15. The pulse SP1 (first start pulse) is input. The nth pulse output from the second stage onwards In the circuit 10_n (n is a natural number of 2≦n≦N), the pulse output circuit 10_n- The signal from 1 (called the previous stage signal OUT(n-1)) is input. The circuit 10_1 receives a signal from a third pulse output circuit 10_3 located two stages later. Similarly, in the n-th pulse output circuit 10_n in the second stage or later, the (n+2)-th pulse output circuit in the second stage or later The signal from the pulse output circuit 10_(n+2) (called the next stage signal OUT(n+2)) is input. Therefore, the pulse output circuit of each stage outputs the pulses of the next stage and / or the two stages before it. A first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the circuit , a second output signal (OUT(1) to OUT(N)) is outputted, which is inputted to another circuit or the like. A reset signal Res is supplied to the pulse output circuit of each stage through a sixth wiring 16. .

[0076] The pulse output circuit shown in Figure 4 differs from the pulse output circuit shown in Figure 2 in that the reset signal The point is that there is a sixth wiring 16 that supplies the signal Res, and the points regarding other parts are the same as those in FIG. Same as the description.

[0077] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, a second output terminal 27, and a sixth input terminal 28 ( See Figure 4(B)).

[0078] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 4(A) and 4(B), for example, In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11. the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal The terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10 2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is The third input terminal 23 is electrically connected to the third wiring 13, and the third input terminal 24 is electrically connected to the fourth wiring 14. It continues.

[0079] 4A and 4B, the first pulse output circuit 10_1 has a fourth input terminal 2 The first start pulse SP1 is input to the input terminal 4, and the subsequent signal OUT(3 ) is input, and the first output signal OUT(1)(SR) is output from the first output terminal 26. , the second output terminal 27 outputs the second output signal OUT(1), and the sixth input terminal 28 This means that the reset signal Res is input.

[0080] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0081] In FIG. 4C, the first terminal of the first transistor 31 is electrically connected to the power supply line 51. the second terminal of the ninth transistor 39 is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode of the The second transistor 32 has a first terminal electrically connected to the fourth input terminal 24. The second terminal is electrically connected to the power supply line 52, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. and a gate electrode electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first input terminal 21. The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 One terminal is electrically connected to the power supply line 52, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the power supply line 52. The two terminals are the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 has a first terminal electrically connected to the power supply line 51 and a second terminal electrically connected to the second transistor 36. The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The seventh transistor 3 has a gate electrode electrically connected to the fifth input terminal 25. The first terminal of the transistor 7 is electrically connected to the power supply line 51, and the second terminal of the transistor 38 is electrically connected to the power supply line 51. The gate electrode is electrically connected to the second terminal and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a second terminal connected to the gate electrode of the second transistor 32. 4, and the gate electrode is electrically connected to the second input terminal 2 The ninth transistor 39 has a first terminal electrically connected to the first transistor 2. the second terminal of the second transistor 31 and the second terminal of the second transistor 32; The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are supplied with a voltage. The gate electrode is electrically connected to the power supply line 51. The first terminal of the sigma 40 is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the second output terminal 22. the gate electrode of the ninth transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has a first terminal electrically connected to the power supply line 52. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, The second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 are connected to a reset signal R The reset signal Res is electrically connected to a wiring 53 for supplying the reset signal Res. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the gate electrode of the fifth transistor the second terminal of the sixth transistor 35, the second terminal of the eighth transistor 36, The potential of the first terminal of the 11th transistor 41 is set to a high power supply potential level. By supplying a signal, the output from the pulse output circuit is forced to a signal of low power supply potential level. This is a signal to drop to the next level.

[0082] In FIG. 4C, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is defined as a node NA. Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, The second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point between the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is called a node Let's call it NB.

[0083] When the pulse output circuit in FIG. 4C is the first pulse output circuit 10_1, the first input A first clock signal CK1 is input to the input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the third input terminal 24. A start pulse SP is input to the fourth input terminal 24, and a The subsequent signal OUT(3) is input, and the first output signal OUT(1) is output from the first output terminal 26. )(SR) is output, and the second output terminal 27 outputs the second output signal OUT(1). A reset signal Res is input from the sixth input terminal 28 .

[0084] In addition, the timing circuit of the shift register having a plurality of pulse output circuits shown in FIG. The timing chart is the same as that of FIG. 2(C) shown in FIG.

[0085] Figure 4 shows an example of a driver circuit made using multiple n-channel transistors. In this case, the procedure for supplying or stopping the potential of each wiring when displaying a moving image from a still image is This article explains:

[0086] First, when the operation of the drive circuit unit 1007 is stopped, the display control circuit 1006 Then, after the start pulse SP stops, the pulse output shifts. After the register reaches the final stage, each clock signal CK is stopped. Next, the high power supply potential VDD and the low power supply potential VSS of the power supply voltage are stopped. (See FIG. 26(C)). When the operation of the driving circuit unit 1007 is to be restarted, first The display control circuit 1006 controls the high power supply potential VDD and the low power supply potential VSS of the power supply voltage. Then, a reset signal Res is supplied to the path unit 1007. Then, a clock signal Then, the supply of the start pulse SP is resumed (see FIG. 26(D)).

[0087] As explained in Figure 4, in addition to the configurations in Figures 2 and 3, a configuration that supplies a reset signal is used. This reduces malfunctions caused by signal delays when switching between still and moving images. This is preferable because it can be

[0088] In addition, when displaying a still image, a thin film transistor that constitutes the driving circuit section is provided on the The common potential electrode may be separated from the common potential line and placed in a floating state. When the drive circuit is to be operated again after the still image mode, the common potential electrode is connected to the common potential line. In this way, it is possible to prevent malfunction of the thin film transistors in the drive circuit section. .

[0089] FIG. 18(A) shows an example of such a display panel 1800, and FIG. 18(B) shows its cross-sectional structure. The display panel 1800 includes driver circuits 1802 and 1804 and a pixel unit. A common potential electrode 1806 is provided in the area where the driver circuit 1802 is provided. Between the common potential electrode 1808 and the common potential terminal 1812, A switch element 1810 is provided to control connection / disconnection of the parties.

[0090] As shown in FIG. 18(B), a common potential electrode 1808 is disposed on a TFT 1803 of a driving circuit. A common potential electrode 1808 is provided on the TFT 1803. The 1803 is electrostatically shielded to prevent threshold voltage shifts and the formation of parasitic channels. .

[0091] The switching element 1810 can have the same configuration as the TFT 1803 . These elements have extremely low leakage current when off, which stabilizes the operation of the display panel. That is, when a still image is displayed, the switch element 180 Even if 3 is turned off and the common potential electrode is left floating, the potential remains constant. It's effective.

[0092] In this way, a TFT made of an oxide semiconductor with a wide band gap is used. , by providing a common potential electrode to shield the external electric field, In addition, the potential of the common potential electrode can be adjusted to match the operation of the drive circuit. By appropriately controlling the voltage and current in combination, the operation of the display panel can be stabilized.

[0093] As described above, the off-state current of a thin film transistor using an oxide semiconductor is small. If this feature is used in a liquid crystal display device, the period during which the voltage can be held by the storage capacitor can be extended. This allows for lower power consumption when displaying still images, etc. By stopping the control signal at the time of the still image, further reduction in power consumption can be achieved. This allows switching between a live image and a moving image without any malfunction.

[0094] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0095] (Embodiment 2) One mode of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment is shown in FIGS. This will be explained using Figure 6.

[0096] In this embodiment, an example of a thin film transistor that can be applied to the liquid crystal display device disclosed in this specification is shown. The thin film transistor 410 shown in this embodiment is the same as that of the pixel portion 1008 in Embodiment 1. It can be used for the thin film transistor used in each pixel.

[0097] 5(A) and 5(B) show an example of the planar and cross-sectional structure of a thin film transistor. The thin film transistor 410 shown in FIG. 1 is a thin film transistor with a top gate structure. .

[0098] FIG. 5A is a plan view of a thin film transistor 410 having a top gate structure, and FIG. 5B is a plan view of a thin film transistor 410 having a top gate structure. FIG. 6 is a cross-sectional view taken along line C1-C2 in FIG. 5(A).

[0099] The thin film transistor 410 is formed on a substrate 400 having an insulating surface, an insulating layer 407, an oxide semiconductor The conductor layer 412, the source or drain electrode layer 415a, and the source or drain electrode layer the source electrode layer 415b, the gate insulating layer 402, and the gate electrode layer 411; The drain electrode layer 415a and the source or drain electrode layer 415b are connected to the wiring layer 4 14a and a wiring layer 414b are provided in contact with each other and are electrically connected.

[0100] The thin film transistor 410 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0101] 6A to 6E, a thin film transistor 410 is fabricated on a substrate 400. The process will be explained.

[0102] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least In either case, it is necessary for the material to have heat resistance sufficient to withstand the subsequent heat treatment.

[0103] Furthermore, for example, when a glass substrate is used as the substrate 400, the temperature of the subsequent heat treatment is high. In this case, it is advisable to use a glass substrate with a strain point of 730°C or higher. Luminosilicate glass, aluminoborosilicate glass, barium borosilicate glass, etc. Glass material is used. Compared to boric acid, it contains more barium oxide (BaO). By including more BaO than B2O3, a more practical heat-resistant glass can be obtained. It is preferable to use a glass substrate containing a large amount of

[0104] The substrate 400 may be a ceramic substrate, a quartz substrate, a surface substrate, or the like, in addition to the glass substrate. A substrate made of an insulating material such as a fiber substrate may also be used. Alternatively, a crystallized glass substrate may be used. In addition, a plastic substrate or the like can also be used as appropriate.

[0105] First, an insulating layer 407 is formed as a base film over a substrate 400 having an insulating surface. The insulating layer 407 in contact with the conductor layer is a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or the like. It is preferable to use an oxide insulating layer such as an aluminum layer or an aluminum oxynitride layer. The method for forming the film 07 can be a plasma CVD method, a sputtering method, or the like. However, in order to prevent a large amount of hydrogen from being contained in the insulating layer 407, the sputtering method is used. It is preferable to deposit the insulating layer 407 by using a silicon dioxide film.

[0106] In this embodiment, a silicon oxide layer is formed as the insulating layer 407 by a sputtering method. The substrate 400 is transferred to a processing chamber and subjected to a spatula containing high-purity oxygen from which hydrogen and moisture have been removed. A target is introduced to deposit silicon oxide on the substrate 400 as an insulating layer 407. The substrate 400 may be at room temperature or may be heated.

[0107] For example, quartz (preferably synthetic quartz) is used as the target, the substrate temperature is 108° C., and the substrate The distance between the plate and the target (TS distance) was 60 mm, the pressure was 0.4 Pa, and the high frequency power 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1 1) A silicon oxide film is formed by RF sputtering in a 100 MPa atmosphere. nm. Note that the silicon target is replaced with silicon oxide instead of quartz (preferably synthetic quartz). It can be used as a target for forming a silicon film. This is carried out using oxygen or a mixed gas of oxygen and argon.

[0108] In this case, it is preferable to form the insulating layer 407 while removing the remaining moisture in the processing chamber. This is to prevent the insulating layer 407 from containing hydrogen, a hydroxyl group, or moisture.

[0109] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen molecules and water (H2 Since compounds containing hydrogen atoms such as O are exhausted, the insulating layer 407 is formed in the film formation chamber. The concentration of impurities contained can be reduced.

[0110] The insulating layer 407 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. Use high-purity gas in which impurities have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable that

[0111] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and DC sputtering. DC sputtering using a power supply, pulsed DC sputtering using a pulsed bias The RF sputtering method is mainly used to form insulating films, while the DC sputtering method The tarnishing method is mainly used when forming a metal film.

[0112] Alternatively, a multi-target sputtering device capable of installing multiple targets of different materials may be used. The sputtering equipment can deposit layers of different materials in the same chamber, or It is also possible to simultaneously discharge multiple types of materials to form films.

[0113] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. A sputtering device using a sputtering method may also be used.

[0114] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. Alternatively, a bias sputtering method in which a voltage is also applied to the substrate during film formation may be used.

[0115] The insulating layer 407 may have a laminated structure, for example, a silicon nitride layer, a nitride layer, and so on from the substrate 400 side. nitride insulation such as silicon oxide, aluminum nitride, or aluminum oxide nitride layers; The insulating layer may have a stacked structure of the insulating layer and the oxide insulating layer.

[0116] For example, a high-purity nitrogen gas containing hydrogen and moisture removed is used between the silicon oxide layer and the substrate 400. A sputtering gas containing silicon nitride is introduced and a silicon target is used to form a silicon nitride layer. In this case, similar to the silicon oxide layer, the silicon nitride layer is formed while removing the remaining moisture in the processing chamber. It is preferable to deposit a layer.

[0117] When forming a silicon nitride layer, the substrate may also be heated during film formation.

[0118] When a silicon nitride layer and a silicon oxide layer are stacked as the insulating layer 407, the silicon nitride layer The silicon oxide layer and the silicon nitride layer are formed in the same processing chamber using a common silicon target. First, a sputtering gas containing nitrogen is introduced to the silicon substrate installed in the processing chamber. A silicon nitride layer is formed using a target, and then the sputtering gas is changed to a sputtering gas containing oxygen. The silicon nitride layer is then deposited using the same silicon target. The silicon nitride layer and the silicon oxide layer can be formed successively without exposure to the atmosphere. It is possible to prevent impurities such as hydrogen and moisture from being adsorbed onto the surface of the cement layer.

[0119] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the insulating layer 407. .

[0120] In addition, in order to minimize the amount of hydrogen, hydroxyl groups, and moisture contained in the oxide semiconductor film, As a pretreatment, the substrate 40 on which the insulating layer 407 is formed is heated in a preheating chamber of the sputtering device. 0 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 400 are desorbed and exhausted. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. The preheating process can be omitted.

[0121] Before the oxide semiconductor film was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and dust adhering to the surface of the insulating layer 407 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using a high frequency power supply under atmospheric pressure to form plasma near the substrate and This is a method of modifying the surface. Note that nitrogen, helium, oxygen, etc. can be used instead of the argon atmosphere. Good too.

[0122] The oxide semiconductor film is formed by sputtering. nO series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O series , Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn- O-based, Al-Zn-O-based, In-O-based, Sn-O-based, and Zn-O-based oxide semiconductor films are used. In this embodiment, the oxide semiconductor film is formed using an In—Ga—Zn—O-based oxide semiconductor target. Specifically, the composition ratio is In2O3: Ga2O3:ZnO=1:1:1 [mol%] (i.e., In:Ga:Zn=1:1: 0.5 [atom%]). In addition, In:Ga:Zn=1:1:1 [atom% ], or a target having a composition ratio of In:Ga:Zn=1:1:2 [atom %] is used. The filling rate of the oxide semiconductor target is 90% or more and 100% or less. Preferably, the filling rate is 95% or more and 99.9% or less. By using the sputtering atmosphere, the oxide semiconductor film formed becomes a dense film. The atmosphere may be a rare gas (typically argon), oxygen, or a mixture of rare gas and oxygen. The target may contain 2% to 10% by weight of SiO2.

[0123] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. High purity gas in which impurities have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable to use

[0124] The oxide semiconductor film is formed by holding the substrate in a treatment chamber maintained in a reduced pressure state and removing residual moisture in the treatment chamber. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the target is used. A film is formed on the substrate 400. To remove residual moisture in the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, or a titanium sublimator may be used. It is preferable to use a pump for exhausting the gas. The deposition chamber evacuated using a cryopump may be, for example, For example, hydrogen molecules, water (H2O) and other compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) Since impurities (including compounds containing impurities) are exhausted, the impurities contained in the oxide semiconductor film formed in the film formation chamber The concentration of the substance can be reduced. Further, the substrate may be heated during the formation of the oxide semiconductor film.

[0125] An example of the film formation conditions is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, Pressure 0.4 Pa, DC power 0.5 kW, oxygen and argon (oxygen flow rate 15 scc The conditions are as follows: argon flow rate 30 sccm; pulsed direct current (DC ) power supply, powdery substances (also called particles or dust) generated during film formation can be reduced. The thickness of the oxide semiconductor film is preferably 2 nm or more and 200 nm or less. The thickness of the oxide semiconductor material is set to 5 nm or less, preferably 5 nm or more and 30 nm or less. The appropriate thickness varies depending on the material, and the thickness can be selected appropriately depending on the material.

[0126] Next, the oxide semiconductor film is subjected to a first photolithography process to form an island-shaped oxide semiconductor layer 4 In order to form the island-shaped oxide semiconductor layer 412, The resist mask for this purpose may be formed by an ink-jet method. When the film is formed by the PET method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0127] The etching of the oxide semiconductor film here can be performed by either dry etching or wet etching. Either one or both may be used.

[0128] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0129] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0130] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0131] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0132] In addition, after wet etching, the etching solution is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The waste liquid after etching may be reused. By recovering and reusing materials, resources can be used more effectively and costs can be reduced.

[0133] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0134] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 412 by etching.

[0135] In this embodiment, the oxide semiconductor layer 412 is subjected to first heat treatment. The temperature is set to 400° C. or higher and 750° C. or lower. If the strain point of the substrate 400 is 750° C. or lower, The temperature is 400°C or higher and lower than the distortion point of the substrate. The oxide semiconductor layer was subjected to heat treatment at 450°C for 1 hour in a nitrogen atmosphere. After this, the temperature was lowered to room temperature without exposure to the air, and the absorption of water and hydrogen into the oxide semiconductor layer was confirmed. The oxide semiconductor layer 412 is obtained by the first heat treatment. The above-mentioned dehydration and / or dehydrogenation can be carried out.

[0136] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. A rare gas such as argon and / or nitrogen that does not react with the object to be treated by heat treatment. A suitable inert gas is used.

[0137] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. become.

[0138] In the first heat treatment, nitrogen and / or helium, neon, argon, etc. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen and / or rare gases such as helium, neon, and argon is 6N (99.99%). 99%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1pp m or less, preferably 0.1 ppm or less).

[0139] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may crystallize to form a microcrystalline or polycrystalline film. % or more, or 80% or more of the oxide semiconductor film may be microcrystalline. Depending on the conditions of the heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may undergo a crystalline formation. In some cases, the oxide semiconductor film may be an amorphous oxide semiconductor film containing no oxide. The microcrystalline part (grain size 1 nm to 20 nm (typically 2 nm to 4 nm)) is mixed in. In some cases, the oxide semiconductor film is an oxide semiconductor film.

[0140] The first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into the island-shaped oxide semiconductor layer 412. In that case, the oxide semiconductor film is heated by the heating apparatus after the first heat treatment. The substrate is removed and subjected to a photolithography process.

[0141] In the above, the oxide semiconductor layer is dehydrated and / or dehydrogenated. In the example shown, the heat treatment is performed immediately after the formation of the oxide semiconductor layer 412. If the film is formed after the source electrode and the drain electrode are laminated on the oxide semiconductor layer, the source electrode and the drain electrode are laminated on the oxide semiconductor layer. This may be performed either after forming a gate insulating layer on the source electrode and the drain electrode.

[0142] Next, a conductive film is formed over the insulating layer 407 and the oxide semiconductor layer 412. The conductive film can be formed by galvanizing or vacuum deposition. , Ta, Ti, Mo, W, or an alloy containing the above elements. , and alloy films combining the above elements. A material selected from one or more of zirconium, beryllium, and yttrium The conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, or a titanium film laminated on an aluminum film, Two-layer structure: Ti film, aluminum film on top of the Ti film, and T In addition, titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium) , Sc (Scandium), or a film or alloy film made of a single or multiple combinations of elements selected from the group consisting of In this embodiment, a 150 nm thick film is formed by sputtering. A titanium film of thickness m is deposited.

[0143] Then, a resist mask is formed over the conductive film by a second photolithography process. The resist mask may be formed by an inkjet method. Since no photomask is used when forming the film, the manufacturing cost can be reduced. The source or drain electrode layer 415a is etched to form a After the dopant electrode layer 415b is formed, the resist mask is removed (see FIG. 6(B)). In addition, when the end portions of the formed source electrode layer and drain electrode layer are tapered, the end portions of the upper layer This is preferable because it improves the coverage of the gate insulating layer.

[0144] Note that when the conductive film is etched, the oxide semiconductor layer 412 is removed, and the insulating layer The materials and etching conditions are adjusted appropriately so that 407 is not exposed.

[0145] In this embodiment, a Ti film is used as the conductive film, and an In—Ga Since a Zn-O-based oxide semiconductor was used, ammonia hydrogen peroxide (31 wt.%) was used as an etchant. % hydrogen peroxide solution: 28% ammonia water: water = 5:2:2) is used.

[0146] Note that in the second photolithography step, only a part of the oxide semiconductor layer 412 is etched. In some cases, the oxide semiconductor layer is etched to have a groove (depression).

[0147] The exposure to light when forming the resist mask in the second photolithography process is done using ultraviolet light or KrF laser. The source electrodes adjacent to each other on the oxide semiconductor layer 412 may be irradiated with laser light or ArF laser light. The width of the gap between the bottom end of the drain electrode layer and the bottom end of the thin film transistor to be formed later The channel length L of the photoresist is determined. Note that when exposure is performed with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nanometers to a few tens of nanometers. olet) is used to perform exposure when forming a resist mask in the second photolithography process. Extreme ultraviolet light exposure provides high resolution and a large depth of focus. It is also possible to set the channel length L of the film transistor to 10 nm or more and 1000 nm or less. This allows for faster circuit operation and, due to the extremely small off-state current, also reduces power consumption. This can be achieved.

[0148] Next, the insulating layer 407, the oxide semiconductor layer 412, the source or drain electrode layer 415 a) A gate insulating layer 402 is formed over the source or drain electrode layer 415b (FIG. 6 See (C). ).

[0149] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer 402 can be formed as a single layer or a stacked layer. In order to minimize the inclusion of fluorine atoms, the gate insulating layer 402 is formed by sputtering. When forming a silicon oxide film by sputtering, it is preferable to use a target A silicon target or a quartz target is used as the sputtering gas. In this embodiment, the pressure is 0.4 Pa and the high frequency voltage is 100 V. 1.5 kW power source, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = A silicon oxide layer with a thickness of 100 nm was formed by RF sputtering in a 1:1 atmosphere. do.

[0150] The gate insulating layer 402 has a multilayer structure in which a silicon oxide layer and a silicon nitride layer are stacked from the bottom. For example, a first gate insulating layer can be formed to a thickness of 5 nm by sputtering. A silicon oxide layer (SiO x (x>0)) and form the first gate insulator A second gate insulating layer is deposited on the edge layer by sputtering to a thickness of 50 nm to 200 nm. The following silicon nitride layer (SiN y (y>0)) is laminated to a thickness of 70nm to 400nm Below that, for example, the gate insulating layer may be 100 nm.

[0151] Next, a resist mask is formed by a third photolithography process and selectively etched. The source electrode layer or the drain electrode layer 402 is removed by etching. 15a, openings 421a and 421b reaching the source electrode layer or the drain electrode layer 415b are formed. (See Figure 6(D)).

[0152] Next, a conductive film is formed on the gate insulating layer 402 and the openings 421a and 421b. In this embodiment, a titanium film having a thickness of 150 nm is formed by sputtering. A gate electrode layer 411 and wiring layers 414a and 414b are formed by the photolithography process of 4. The resist mask may be formed by an ink-jet method. When formed using the inkjet method, no photomask is used, reducing manufacturing costs. .

[0153] The gate electrode layer 411 and the wiring layers 414a and 414b are made of molybdenum, titanium, and chromium. Metallic materials such as tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. The layer can be formed as a single layer or a multilayer using an alloy material containing these as the main component.

[0154] For example, a two-layer laminate structure of a gate electrode layer 411 and wiring layers 414a and 414b may be Two-layer laminate structure with a molybdenum layer on an aluminum layer, or molybdenum on a copper layer Two-layer structure with a copper layer and a titanium nitride layer or tantalum nitride layer on top of the copper layer Preferably, the titanium nitride layer and the molybdenum layer are laminated together to form a two-layer structure. The laminated structure is composed of a tungsten layer or tungsten nitride layer, and a layer of aluminum and silicon. A titanium nitride layer or titanium layer is laminated with an aluminum alloy or an aluminum-titanium alloy. It is preferable to form the gate electrode layer using a light-transmitting conductive film. Examples of the conductive film having light-transmitting properties include a light-transmitting conductive oxide. It is possible.

[0155] Next, a second heat treatment (preferably 2 In this embodiment, the temperature is 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the thin film transistor 410 .

[0156] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to 10 Repeat heating from 0℃ to 200℃ and cooling from the heating temperature to room temperature multiple times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. Heating under reduced pressure can shorten the heating time.

[0157] Through the above steps, the oxide semiconductor layer 41 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. 2 can be formed (see FIG. 6(E)). The transistor 410 is applied to the thin film transistor 105 in Embodiment 1. can be done.

[0158] In addition, a protective insulating layer and a planarizing insulating layer for planarization are provided over the thin film transistor 410. For example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like may be used as the protective insulating layer. A silicon nitride oxide layer, a silicon nitride oxide layer, or an aluminum oxide layer may be formed as a single layer or a stacked layer. can.

[0159] The planarization insulating layer may be made of polyimide, acrylic, benzocyclobutene, or polyamide. In addition to the above organic materials, organic materials having heat resistance such as epoxy can be used. Low-k materials, siloxane resins, PSG (phosphor glass), BP SG (phosphorus boron glass) can be used. A planarizing insulating layer may be formed by stacking a plurality of insulating films.

[0160] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0161] The method for forming the planarizing insulating layer is not particularly limited, and may be a sputtering method, an SOG method, or the like depending on the material. Spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coater or the like can be used.

[0162] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0163] The thin film transistors thus fabricated are used to form a plurality of display sections of a liquid crystal display device. By using this in the pixel, it is possible to reduce the leakage current from the pixel. This allows the storage capacitor to hold the voltage for a longer period, resulting in lower power consumption when displaying still images, etc. It is possible to provide a liquid crystal display device that can reduce power consumption. By stopping the control signal at the time of the still image, further reduction in power consumption can be achieved. Switching to a moving image can be performed without malfunction.

[0164] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0165] (Embodiment 3) The present embodiment is directed to another thin film transistor that can be applied to the liquid crystal display device disclosed in this specification. Note that the same parts as those in the second embodiment or parts and steps having similar functions are used in the second embodiment. It is sufficient to use the same method as in the second embodiment, and the repeated explanation will be omitted. The thin film transistor 460 described in this embodiment is the same as that described in Embodiment 1. It can be used for the thin film transistors used in each pixel of 1008.

[0166] One mode of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment is shown in FIGS. This will be explained using FIG.

[0167] 7(A) and 7(B) show an example of the planar and cross-sectional structure of a thin film transistor. The thin film transistor 460 shown in FIG. 1 is a top-gate thin film transistor. .

[0168] FIG. 7A is a plan view of a thin film transistor 460 having a top gate structure, and FIG. FIG. 8 is a cross-sectional view taken along line D1-D2 in FIG. 7(A).

[0169] The thin film transistor 460 is formed by forming an insulating layer 457, a source electrode 458, a gate electrode 459, a gate electrode 459a, a gate electrode 459b, a gate electrode 459c, a gate electrode 459d, a gate electrode 459e, a gate electrode 459f, a gate electrode 459g ... a drain or electrode layer 465a (465a1, 465a2), an oxide semiconductor layer 462, the source or drain electrode layer 465b, the wiring layer 468, the gate insulating layer 452, and the gate The electrode layer 461 (461a, 461b) includes a source electrode layer or a drain electrode layer 465a. (465a1, 465a2) are electrically connected to the wiring layer 464 via the wiring layer 468. Although not shown, the source or drain electrode layer 465b is also formed as a gate insulating layer. An opening provided in 452 electrically connects to the wiring layer.

[0170] 8A to 8E, a thin film transistor 460 is fabricated on a substrate 450. The process will be explained.

[0171] First, an insulating layer 457 serving as a base film is formed over a substrate 450 having an insulating surface.

[0172] In this embodiment, a silicon oxide layer is formed as the insulating layer 457 by a sputtering method. The substrate 450 is transferred to a processing chamber and subjected to a spatula containing high-purity oxygen from which hydrogen and moisture have been removed. A target gas is introduced, and a silicon target or quartz (preferably synthetic quartz) is used to form a substrate 45 A silicon oxide layer is formed on the insulating layer 457. is carried out using a mixed gas of oxygen and argon.

[0173] For example, in this embodiment, the purity is 6N, and quartz (preferably synthetic quartz) is used as the target. The substrate temperature was 108°C, and the distance between the substrate and the target (TS distance) was 60 mm, pressure 0.4 Pa, high frequency power supply 1.5 kW, oxygen and argon (oxygen flow rate 25 scc The oxide film was deposited by RF sputtering under an atmosphere of argon (flow rate 25 sccm, 1:1). A silicon film is formed. The film thickness is 100 nm. Instead of quartz (preferably synthetic quartz), In addition, a silicon target is used as a target for forming a silicon oxide film. can be done.

[0174] In this case, it is preferable to form the insulating layer 457 while removing the remaining moisture in the processing chamber. This is to prevent the insulating layer 457 from containing hydrogen, hydroxyl groups, and / or moisture. The deposition chamber evacuated using a cryopump contains, for example, hydrogen molecules and water (H2O). Since compounds containing atomic atoms are exhausted, the impurities contained in the insulating layer 457 formed in the deposition chamber are The concentration of pure substances can be reduced.

[0175] The insulating layer 457 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. Use high-purity gas in which impurities have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable that

[0176] The insulating layer 457 may have a laminated structure, for example, a silicon nitride layer, a nitride layer, and so on from the substrate 450 side. and nitride insulating layers such as silicon oxide layers, aluminum nitride layers, and aluminum oxide nitride layers. The insulating film may have a stacked structure with the oxide insulating layer.

[0177] For example, a spat containing high-purity nitrogen from which hydrogen and moisture have been removed is used between the silicon oxide layer and the substrate. A silicon nitride layer is formed by introducing a target gas and using a silicon target. Even if the silicon nitride layer is formed, the remaining moisture in the processing chamber is removed, just like the silicon oxide layer. It is preferable to coat the surface.

[0178] Next, a conductive film is formed on the insulating layer 457. The conductive film may be made of Al, Cr, or C. An element selected from U, Ta, Ti, Mo, and W, or an alloy containing the above elements or an alloy film made of a combination of the above elements. , zirconium, beryllium, and yttrium. The conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a titanium film laminated on an aluminum film, A two-layer structure is formed by laminating a Ti film and an aluminum film on top of the Ti film. Examples include a three-layer structure in which a Ti film is formed. In addition, titanium (Ti) and tantalum are added to Al. (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium) ), Sc (Scandium), a film or alloy film made of a single or multiple combinations of elements, Alternatively, a nitride film may be used. In this embodiment, the conductive film is formed by sputtering. A titanium film with a thickness of 150 nm is formed. Then, a first photolithography process is performed. A resist mask is formed on the conductive film, and selective etching is performed to form a source electrode layer or a drain electrode layer. After forming the conductive electrode layers 465a1 and 465a2, the resist mask is removed (FIG. 8(A)). The source and drain electrode layers 465a1 and 465a2 are separated in the cross-sectional view. Although it is shown as a circular film, as shown in FIG. 7(A), it is a continuous film with a circular ring shape in part. The formed source and drain electrode layers 465a1 and 465a2 have tapered edges. This is preferable because it improves the coverage of the gate insulating layer to be laminated thereon.

[0179] Next, an oxide semiconductor having a thickness of 2 nm to 200 nm, for example, 5 nm to 30 nm, is deposited. The appropriate thickness varies depending on the oxide semiconductor material used. In this embodiment, an In-Ga- The film is formed by sputtering using a Zn-O based oxide semiconductor target.

[0180] The oxide semiconductor film is formed by holding the substrate in a treatment chamber maintained in a reduced pressure state and removing residual moisture in the treatment chamber. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the substrate is sputtered using a target. To remove residual moisture in the processing chamber, an adsorption type vacuum pump is used. For example, cryopumps, ion pumps, titanium sublimation pumps, etc. It is preferable to use a pump. As an exhaust means, a turbo pump with a cold transistor is used. The deposition chamber evacuated using a cryopump may be, for example, Hydrogen molecules, water (H2O), and other compounds containing hydrogen atoms (preferably compounds containing carbon atoms) Since gases such as impurities are exhausted, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber increases. The substrate may be heated during the formation of the oxide semiconductor film.

[0181] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. High purity gas in which impurities have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable to use

[0182] An example of the film formation conditions is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, Pressure 0.4 Pa, DC power 0.5 kW, oxygen and argon (oxygen flow rate 15 scc m: argon flow rate 30 sccm) atmosphere conditions are applied.

[0183] Next, the oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 46 2 (see FIG. 8(B)). In this embodiment, phosphoric acid and acetic acid are used as the etching solution. The oxide semiconductor film was then etched into island-shaped oxide films by wet etching using a solution containing nitric acid and acetic acid. The resulting semiconductor layer 462 is then processed.

[0184] In this embodiment, first heat treatment is performed on the oxide semiconductor layer 462. The temperature is set to 400° C. or higher and 750° C. or lower. If the strain point of the substrate 450 is 750° C. or lower, The temperature is 400°C or higher and lower than the distortion point of the substrate. The oxide semiconductor layer was subjected to heat treatment at 450°C for 1 hour in a nitrogen atmosphere. After this, the temperature was lowered to room temperature without exposure to the air, and the absorption of water and hydrogen into the oxide semiconductor layer was confirmed. The oxide semiconductor layer 462 is obtained by the first heat treatment. The above-mentioned dehydration and / or dehydrogenation can be carried out.

[0185] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. For example, the first heat treatment may be performed at a temperature of 650°C to 70°C. The substrate is placed in an inert gas atmosphere heated to 0°C, and after heating for several minutes, the substrate is GRTA can also be performed by moving the sample and removing it from the inert gas heated to a high temperature. This allows high-temperature heat treatment in a short time.

[0186] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0187] The oxide semiconductor layer 462 may be formed into a thin film depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer 462. In some cases, the film crystallizes to form a microcrystalline or polycrystalline film.

[0188] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0189] In the above, the oxide semiconductor layer is dehydrated and / or dehydrogenated. In the example shown, the heat treatment is performed immediately after the formation of the oxide semiconductor layer 462. After the formation, the source electrode layer or the drain electrode layer 465b may be further formed over the oxide semiconductor layer. After the stacking, the gate insulating layer 452 is formed over the source or drain electrode layer 465b. After that, you can do either of the following.

[0190] Next, a conductive film was formed over the insulating layer 457 and the oxide semiconductor layer 462. A resist mask is formed on the conductive film by a lithography process, and selective etching is performed. After forming the source or drain electrode layer 465b and the wiring layer 468, a resist mask The source or drain electrode layer 465b and the wiring layer 465c are removed (see FIG. 8C). The source electrode layer 68 is formed by the same material and process as the source electrode layer 465a1 and the drain electrode layer 465a2. It is sufficient to form it.

[0191] In this embodiment, the source or drain electrode layer 465b and the wiring layer 468 are formed by sputtering. A titanium film having a thickness of 150 nm is formed by a deposition method. and the source or drain electrode layers 465a1 and 465a2. In this example, the same titanium film is used for the source electrode layer 465a1 and the drain electrode layer 46b. The source or drain electrode layer 465b and the source or drain electrode layer 465a2 have a selectivity in etching. Therefore, the source electrode layer 465a1 and the drain electrode layer 465a2 are not connected to the source electrode The oxide semiconductor layer 465b is not etched during etching of the drain electrode layer 465a. The wiring layer 468 is formed on the source electrode layer or the drain electrode layer 465a2 that is not covered with the dielectric layer 462. The source and drain electrode layers 465a1 and 465a2 are provided. The drain electrode layer 465b is made of a different material having a high selectivity in an etching process. When used, the source or drain electrode layer 465a2 is protected during etching. The wiring layer 468 does not necessarily have to be provided.

[0192] Note that when the conductive film is etched, the oxide semiconductor layer 462 is partly etched. The respective materials and etching conditions are adjusted so that the oxide semiconductor layer 462 is not removed more than necessary. Adjust the mixing conditions accordingly.

[0193] In this embodiment, a Ti film is used as the conductive film, and an In—Ga -Zn-O based oxide semiconductor is used, so ammonia hydrogen peroxide (31 A mixture of 28% by weight hydrogen peroxide water, 28% by weight ammonia water, and water (5:2:2) is used.

[0194] Note that in the second photolithography step, only a part of the oxide semiconductor layer 462 is etched. In some cases, the oxide semiconductor layer has a groove (a recess). A resist mask for forming the drain electrode layer 465b and the wiring layer 468 is formed by inkjet printing. If the resist mask is formed by the ink-jet method, the photomask Since no additional materials are used, the manufacturing cost can be reduced.

[0195] Next, the insulating layer 457, the oxide semiconductor layer 462, the source or drain electrode layer 465 a1, 465a2, and a gate insulating layer 452 on the source or drain electrode layer 465b. Form.

[0196] The gate insulating layer 452 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer 452 can be formed as a single layer or a stacked layer. In order to minimize the inclusion of SiO 2 , the gate insulating layer 452 is formed by sputtering. When forming a silicon oxide film by sputtering, it is preferable to use a target A silicon target or a quartz target is used as the sputtering gas. It is carried out using a mixed gas of oxygen and argon.

[0197] The gate insulating layer 452 is provided between the source and drain electrode layers 465a1 and 465a2, A silicon oxide layer and a silicon nitride layer were stacked on the source electrode layer or drain electrode layer 465b side. In this embodiment, the pressure is 0.4 Pa, the high frequency power supply is 1.5 kW, Oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) atmosphere A silicon oxide layer with a thickness of 100 nm is formed on the substrate by RF sputtering.

[0198] Next, a resist mask is formed by a fourth photolithography process and selectively etched. A part of the gate insulating layer 452 is removed by etching to form an opening 423 reaching the wiring layer 438. Although not shown, when the opening 423 is formed, the source electrode layer or the drain electrode layer is formed. An opening may be formed that reaches the drain electrode layer 465b. Alternatively, the opening to the drain electrode layer 465b is formed after an interlayer insulating layer is further laminated. In this example, a wiring layer connected to the wiring layer is formed in the opening.

[0199] Next, a conductive film is formed over the gate insulating layer 452 and the opening 423, and then a fifth photolithography is performed. A gate electrode layer 461 (461a, 461b) and a wiring layer 464 are formed by a photolithography process. The resist mask may be formed by an ink-jet method. When formed by the jet method, no photomask is used, which reduces manufacturing costs.

[0200] The gate electrode layer 461 (461a, 461b) and the wiring layer 464 are made of molybdenum. , titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium It is formed by using a metal material such as aluminum or an alloy material containing these as the main component, in a single layer or in a laminated form. It is possible.

[0201] In this embodiment, gate electrode layer 461 (461a, 461b) and wiring layer 464 are formed of silicon dioxide. A titanium film with a thickness of 150 nm is formed by a quartz crystal deposition method. Layers 461 (461a, 461b) are shown separated, but are not shown in FIG. In this way, the source electrode layer or drain electrode layer 465a1 and 465a2 are The electrode layer 465b is formed so as to overlap with the circular gap portion formed between the electrode layers 465b.

[0202] Next, a second heat treatment (preferably 2 In this embodiment, the temperature is 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the thin film transistor 460 .

[0203] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to 10 Repeat heating from 0℃ to 200℃ and cooling from the heating temperature to room temperature multiple times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. Heating under reduced pressure can shorten the heating time.

[0204] Through the above steps, the oxide semiconductor layer 46 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. A thin film transistor 460 having the above structure can be fabricated (see FIG. 8E). The transistor 460 is a thin-film transistor used in each pixel of the pixel portion 1008 in Embodiment 1. It can be used for

[0205] In addition, a protective insulating layer and a planarization insulating layer for planarization are provided over the thin film transistor 460. Although not shown, the source insulating layer 452, the protective insulating layer, and the planarizing insulating layer may be formed. An opening reaching the source or drain electrode layer 465b is formed in the opening. A wiring layer electrically connected to the drain electrode layer 465b is formed.

[0206] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0207] As described above, the display portion of a liquid crystal display device having a thin film transistor using an oxide semiconductor layer Therefore, the off-state current can be reduced in the plurality of pixels constituting the storage capacitor. This allows the voltage to be maintained for a longer period, which reduces power consumption when displaying still images, etc. In addition, when a still image is displayed, the control signal is transmitted to the liquid crystal display device. By stopping the switching between still images and moving images, power consumption can be reduced. In this embodiment, the channel is circular, and the source The channel length is shortened by forming the electrode layer and the drain electrode layer using different layers. In this way, the channel width can be increased even in a relatively small area. This allows the formation of thin film transistors with large capacitance, enabling large current switching. Although the channel width is large, the off-state current is extremely low because a highly purified oxide semiconductor is used. It has the characteristic of being extremely small.

[0208] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0209] (Fourth embodiment) The thin film transistor of this embodiment will be described with reference to FIG. Other examples of thin film transistors that can be applied to the liquid crystal display device disclosed in the embodiment will be described below. The same parts as those in Embodiment 2 or parts having similar functions, and the steps are the same as those in Embodiment 2. Therefore, the repeated explanation will be omitted. Also, detailed explanation of the same parts will be omitted. The thin film transistors 425 and 426 shown in the figure correspond to the respective pixels of the pixel portion 1008 in Embodiment 1. It can be used in thin film transistors used in the above.

[0210] 9(A) and 9(B) show an example of a cross-sectional structure of a thin film transistor. The thin film transistors 425 and 426 each have an oxide semiconductor layer sandwiched between a conductive layer and a gate electrode layer. It is one of the thin film transistors with this structure.

[0211] 9(A) and 9(B), a silicon substrate is used as the substrate, and the silicon substrate 42 Thin film transistors 425 and 426 are provided on an insulating layer 422 provided on the substrate 400. are.

[0212] In FIG. 9A, an insulating layer 422 and an insulating layer 407 are provided on a silicon substrate 420. A conductive layer 427 is provided between the oxide semiconductor layer 412 and the conductive layer 427 so as to overlap with at least the entire oxide semiconductor layer 412. do.

[0213] 9B, the conductive layer between the insulating layer 422 and the insulating layer 407 is a conductive layer such as the conductive layer 424. The oxide semiconductor layer 412 is processed by etching as shown in FIG. This is an example of partial overlap.

[0214] The conductive layers 427 and 424 may be made of any metal material that can withstand the heat treatment temperature in the subsequent process. Titanium (Ti), Tantalum (Ta), Tungsten (W), Molybdenum (Mo), An element selected from Cr, Nd, and Sc, or any of the above an alloy containing the above elements as a component, an alloy film containing a combination of the above elements, or an alloy film containing the above elements as a component The nitride may have a single layer structure or a laminated structure. For example, a single tungsten layer or a laminated structure of a tungsten nitride layer and a tungsten layer. can be used.

[0215] The conductive layers 427 and 424 are connected to the gate electrode layers of the thin film transistors 425 and 426. It may be the same as or different from 411 and may function as a second gate electrode layer. Alternatively, the potentials of the conductive layers 427 and 424 may be fixed potentials such as GND and 0V. Good too.

[0216] The conductive layers 427 and 424 control the electrical characteristics of the thin film transistors 425 and 426. It is possible.

[0217] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0218] (Embodiment 5) In this embodiment, an example of a thin film transistor that can be applied to the liquid crystal display device disclosed in this specification is shown. show.

[0219] One mode of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment will be described with reference to FIGS. This will be used to explain.

[0220] 10A to 10E show examples of cross-sectional structures of thin film transistors. The thin film transistor 390 shown in (E) is one of the bottom gate structures and is an inverted staggered thin film transistor. Also called a transistor.

[0221] The thin film transistor 390 will be described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel formation regions may be used. It is also possible to create a

[0222] 10(A) to 10(E), a thin film transistor 390 is fabricated on a substrate 394. The process will be explained.

[0223] First, a conductive film is formed on a substrate 394 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 391 is formed by this process. The end of the gate electrode layer is tapered. This is preferable because it improves the coverage of the gate insulating layer to be laminated thereon. The mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0224] There is no significant limitation on the substrate that can be used for the substrate 394 having an insulating surface, but at least In either case, it is necessary for the material to have heat resistance sufficient to withstand the subsequent heat treatment.

[0225] For example, when a glass substrate is used as the substrate 394, if the temperature of the subsequent heat treatment is high, For the glass substrate, it is advisable to use a glass having a strain point of 730°C or higher. Luminosilicate glass, aluminoborosilicate glass, barium borosilicate glass, etc. Glass material is used. Compared to boric acid, it contains more barium oxide (BaO). By including more BaO than B2O3, a more practical heat-resistant glass can be obtained. It is preferable to use a glass substrate containing a large amount of

[0226] The substrate 394 may be a ceramic substrate, a quartz substrate, a surface substrate, or the like, in addition to the glass substrate. A substrate made of an insulating material such as a fiber substrate may also be used. Alternatively, a crystallized glass substrate may be used. In addition, a plastic substrate or the like can also be used as appropriate.

[0227] An insulating film serving as a base film may be provided between the substrate 394 and the gate electrode layer 391. , which has the function of preventing the diffusion of impurity elements from the substrate 394, and the silicon nitride film, silicon oxide film, The insulating film is made of one or more films selected from a silicon film, a silicon nitride oxide film, and a silicon oxynitride film. The insulating film can be formed by a laminated structure.

[0228] The material of the gate electrode layer 391 is molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0229] For example, the gate electrode layer 391 may have a two-layer laminate structure, such as a molybdenum layer on an aluminum layer. Two-layer structure with a molybdenum layer on a copper layer, two-layer structure with a nitride layer on a copper layer a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated; a titanium nitride layer and a molybdenum layer A two-layer structure in which a tungsten nitride layer and a tungsten layer are laminated, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are laminated, As the three-layer laminated structure, a tungsten layer or a tungsten nitride layer and , aluminum and silicon alloy or aluminum and titanium alloy and titanium nitride or It is preferable that a layer including a titanium layer and a light-transmitting conductive film is used. The gate electrode layer can also be formed by using a light-transmitting conductive film. Examples of such materials include oxides.

[0230] Next, a gate insulating layer 397 is formed over the gate electrode layer 391 .

[0231] The gate insulating layer 397 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer 397 can be formed as a single layer or a stacked layer. In order to minimize the inclusion of SiO 2 , the gate insulating layer 397 is formed by sputtering. When forming a silicon oxide film by sputtering, it is preferable to use a target A silicon target or a quartz target is used as the sputtering gas. It is carried out using a mixed gas of oxygen and argon.

[0232] The gate insulating layer 397 is formed by stacking a silicon nitride layer and a silicon oxide layer from the gate electrode layer 391 side. For example, a layered structure can be formed by sputtering as the first gate insulating layer. A silicon nitride layer (SiN) with a thickness of 50 nm or more and 200 nm or less is formed. y (y>0) On the first gate insulating layer, an oxide film having a thickness of 5 nm to 300 nm is formed as a second gate insulating layer. Silicon oxide layer (SiO x (x>0)) is stacked to form a gate insulating film with a thickness of, for example, 100 nm. The layer is called a layer.

[0233] In addition, the gate insulating layer 397 and the oxide semiconductor film 393 contain hydrogen, a hydroxyl group, and moisture as much as possible. In order to prevent this, a gate electrode is placed in the preheating chamber of the sputtering equipment as a pretreatment for film formation. A substrate 394 on which a gate electrode layer 391 is formed, or a substrate on which up to a gate insulating layer 397 is formed The plate 394 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 394 are desorbed and exhausted. The preheating temperature is preferably 100°C or higher and 400°C or lower. The temperature is between 150 and 300°C. The exhaust means installed in the preheating chamber is a cryopump. It is preferable that the preheating step is omitted. Before the oxide insulating layer 396 is formed, the source electrode layer 395a and the drain electrode layer 395b shown in FIG. The same process may be carried out on the substrate 394 on which the layers up to the drain electrode layer 395b have been formed.

[0234] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm or more, is formed on the gate insulating layer 397. An oxide semiconductor film 393 having a thickness of 30 nm or less is formed by sputtering (FIG. 10(A)). )reference.).

[0235] Note that before the oxide semiconductor film 393 is formed by a sputtering method, argon gas is introduced. The reverse sputtering is performed by introducing the silicon dioxide into the gate insulating layer 397 to generate plasma. It is preferable to remove the dust particles that are sputtered. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. It is also possible to use nitrogen, helium, oxygen, etc. instead of argon atmosphere. Either may be used.

[0236] The oxide semiconductor film 393 may be an In-Ga-Zn-O based, In-Sn-Zn-O based, or In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- An O-based or Zn—O-based oxide semiconductor film is used. In this embodiment, the oxide semiconductor film 393 The film is formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. Specifically, the composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [mo l%] (i.e., In:Ga:Zn=1:1:0.5 [atom%]) is used. In:Ga:Zn=1:1:1 [atom%] or In:Ga:Zn=1:1:2 A target having a composition ratio of [atom %] can also be used. The target filling rate is 90% to 100%, preferably 95% to 99.9%. By using an oxide semiconductor target with a high filling rate, the oxide semiconductor film formed The oxide semiconductor film 393 is formed in a rare gas (typically, argon) atmosphere. In air, oxygen, or a rare gas (typically argon) and oxygen atmosphere, It can be formed by sputtering. The target contains 2 wt. % or more and 10% or less by weight.

[0237] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate is heated to room temperature or a temperature below 400°C. Then, the remaining moisture in the processing chamber is removed, and the sputtering gas from which hydrogen and moisture have been removed is heated. A gas is introduced, and an oxide semiconductor film 393 is formed over a substrate 394 using the target. To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump contains, for example, hydrogen molecules, water (H2O ) and other compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) are exhausted. Therefore, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced. The sputtering film formation is performed while removing the moisture remaining in the processing chamber using a cryopump. The substrate temperature when the oxide semiconductor film 393 is formed can be from room temperature to lower than 400° C. can.

[0238] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed direct current (DC) power supply is used, the powdery substances (particles) generated during film formation are This is preferable because it can reduce the amount of dust (also called crumbs or dirt) and make the film thickness distribution uniform.

[0239] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and direct sputtering. DC sputtering using a current source, and pulsed DC sputtering using a pulsed bias. RF sputtering is mainly used to form insulating films. The DC sputtering method is mainly used when forming metal films.

[0240] Alternatively, a multi-target sputtering device capable of installing multiple targets of different materials may be used. The sputtering equipment can deposit layers of different materials in the same chamber, or It is also possible to simultaneously discharge multiple types of materials to form films.

[0241] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. A sputtering device using a sputtering method may also be used.

[0242] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. Alternatively, a bias sputtering method in which a voltage is also applied to the substrate during film formation may be used.

[0243] Next, the oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 3 10B). In addition, an island-shaped oxide semiconductor layer 399 is formed. A resist mask for this purpose may be formed by an ink-jet method. When the film is formed by the jet method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0244] In addition, when a contact hole is formed in the gate insulating layer 397, the process is performed using an oxide semiconductor This can be done when layer 399 is formed.

[0245] Note that the etching of the oxide semiconductor film 393 here can be performed by dry etching or wet etching. Alternatively, etching or both may be used.

[0246] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0247] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0248] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0249] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0250] In addition, after wet etching, the etching solution is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The waste liquid after etching may be reused. By recovering and reusing materials, resources can be used more effectively and costs can be reduced.

[0251] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0252] Note that reverse sputtering is performed before forming a conductive film in the next step, and the oxide semiconductor layer 399 and the gate electrode 396 are formed. It is preferable to remove resist residues and the like adhering to the surface of the insulating layer 397.

[0253] Next, a conductive film is formed over the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive film can be formed by sputtering or vacuum deposition. Elements selected from r, Cu, Ta, Ti, Mo, and W, or materials containing the above elements as components Examples of the alloy include an alloy film of the above elements, and an alloy film of a combination of the above elements. selected from one or more of sodium, zirconium, beryllium, and yttrium The metal conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a titanium film on an aluminum film, A two-layer structure in which a Ti film is laminated and an aluminum film is laminated on top of the Ti film. A three-layer structure is also possible, where a titanium (Ti) film is formed on top of Al. , Tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Nd (Neodymium), Sc (Scandium) , an alloy film, or a nitride film may also be used.

[0254] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 395a and the drain electrode layer 395b by etching, a resist The mask is removed (see FIG. 10(C)).

[0255] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrode layer is formed on the oxide semiconductor layer 399. The width of the gap between the end of the drain electrode layer and the lower end of the drain electrode layer determines the channel width of the thin film transistor to be formed later. The channel length L is determined. When performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from 10 nm to several tens of nm. t) is used to perform exposure when forming a resist mask in the third photolithography process. UV exposure has high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. The operating speed can be increased, and the off-current value is extremely small, so power consumption can also be reduced. This can be done.

[0256] Note that the conductive film was etched so that the oxide semiconductor layer 399 was not removed. The material and etching conditions are adjusted appropriately.

[0257] In this embodiment, a Ti film is used as the conductive film, and an In—Ga Since a Zn-O-based oxide semiconductor was used, ammonia hydrogen peroxide (ammonia hydrogen peroxide) was used as an etchant. A mixture of water, hydrogen peroxide, and water is used.

[0258] Note that in the third photolithography step, only a part of the oxide semiconductor layer 399 is etched. In some cases, the source electrode layer 3 is formed as an oxide semiconductor layer having a groove (a recess). 95a, a resist mask for forming the drain electrode layer 395b is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0259] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0260] After removing the resist mask, a process using gases such as N2O, N2, or Ar is performed. The plasma treatment removes adsorbed water and the like adhering to the exposed surface of the oxide semiconductor layer 399. Alternatively, a plasma treatment may be performed using a mixed gas of oxygen and argon.

[0261] Next, an oxide insulating layer is formed as an oxide insulating layer that will be a protective insulating film in contact with a part of the oxide semiconductor layer. 396 is formed (see FIG. 10(D)). When the plasma treatment is performed, After the treatment, the oxide semiconductor layer 399 is not exposed to the air, and the oxide insulating layer 396 is formed in succession. Note that in this embodiment, the oxide semiconductor layer 399 may be formed as the source electrode layer 395. a) In a region that does not overlap with the drain electrode layer 395b, the oxide semiconductor layer 399 and the oxide The insulating layer 396 is formed so as to be in contact with the insulating layer 396 .

[0262] In this embodiment, the island-shaped oxide semiconductor layer 399, the source electrode layer 395a, the drain electrode The substrate 394 formed up to the layer 395b is heated to room temperature or a temperature less than 100° C., and hydrogen and A sputtering gas containing high-purity oxygen with moisture removed is introduced to the silicon semiconductor target. A silicon oxide layer including defects is formed as an oxide insulating layer 396 using the silicon oxide film.

[0263] For example, a silicon target with a purity of 6N and doped with boron (resistivity 0.01 Ωcm), the distance between the substrate and the target (TS distance) was 89 mm, and the pressure was 0. 4 Pa, direct current (DC) power supply 6 kW, pulse DC in oxygen (oxygen flow rate 100%) atmosphere The film is formed by sputtering. The film thickness is 300 nm. The silicon target Instead, quartz (preferably synthetic quartz) is used as a target for forming a silicon oxide film. It should be noted that oxygen or a mixture of oxygen and argon can be used as the sputtering gas. This is done using a

[0264] In this case, the oxide insulating layer 396 is formed while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor layer 399 and the oxide insulating layer 396 contain hydrogen, a hydroxyl group, and / or This is to prevent moisture from being absorbed.

[0265] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen molecules and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The impurity concentration in the oxide insulating layer 396 can be reduced.

[0266] Note that as the oxide insulating layer 396, a silicon oxynitride layer or an oxide An aluminum layer, an aluminum oxynitride layer, or the like can also be used.

[0267] After the oxide insulating layer 396 is formed, the oxide insulating layer 396 and the oxide semiconductor layer 399 are Heat treatment may be performed at 100° C. to 400° C. in this state. Since the oxide insulating layer 396 contains many defects, the oxide semiconductor layer 399 is Impurities such as hydrogen, moisture, a hydroxyl group, or hydride contained in the oxide insulating layer 396 are diffused into the oxide insulating layer 396. Therefore, the impurities contained in the oxide semiconductor layer 399 can be further reduced.

[0268] Through the above steps, an oxide semiconductor having reduced concentrations of hydrogen, moisture, hydroxyl groups, and / or hydrides is obtained. A thin film transistor 390 having a dielectric layer 392 can be formed (see FIG. 10(E)). .).

[0269] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0270] A protective insulating layer may be provided over the oxide insulating layer. In this embodiment, the protective insulating layer 398 is formed by an oxide insulating film. The protective insulating layer 398 is formed on the oxide insulating layer 396. The protective insulating layer 398 may be a silicon nitride film, a nitride oxide film, or the like. A silicon film, an aluminum nitride film, an aluminum nitride oxide film, or the like is used.

[0271] The substrate 394 on which the oxide insulating layer 396 has been formed is heated at 100°C to 4 The temperature was raised to 00°C, and a sputtering gas containing high-purity nitrogen from which hydrogen and moisture had been removed was introduced. In this case, a silicon nitride film is formed using a silicon semiconductor target. Similarly to the oxide insulating layer 396, a protective insulating layer 398 is formed while removing residual moisture in the treatment chamber. It is preferable to coat the surface.

[0272] When forming the protective insulating layer 398, the temperature is set to 100° C. to 400° C. during the formation of the protective insulating layer 398. By heating the plate 394, hydrogen and / or moisture contained in the oxide semiconductor layer are oxidized. In this case, after the oxide insulating layer 396 is formed, a heat treatment is performed. There is no need to carry out the theory.

[0273] A silicon oxide layer is formed as the oxide insulating layer 396, and a silicon nitride layer is formed as the protective insulating layer 398. When stacking silicon layers, the silicon oxide layer and silicon nitride layer are processed in the same processing chamber using a common silicon nitride layer. The film can be formed using a silicon target. First, an etching gas containing oxygen is introduced. Then, a silicon oxide layer is formed using a silicon target installed in the processing chamber, and then The etching gas was changed to a nitrogen-containing etching gas and the same silicon target was used. The silicon oxide layer and the silicon nitride layer are formed in succession without being exposed to the atmosphere. Since the silicon oxide layer can be formed continuously, impurities such as hydrogen and moisture are not adsorbed on the surface of the silicon oxide layer. In this case, a silicon oxide layer is used as the oxide insulating layer 396. After that, a silicon nitride layer was stacked as a protective insulating layer 398. Heat treatment (temperature 100°C or higher) to diffuse the hydrogen or moisture contained in the oxide insulating layer into the oxide insulating layer. It is recommended to perform heating at 400℃.

[0274] After the protective insulation layer is formed, it is further heated in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature. In addition, the temperature rises from room temperature to a heating temperature of 100°C or more and 200°C, and the temperature rises from the heating temperature to room temperature. The temperature may be lowered several times. Alternatively, the heating may be carried out under reduced pressure. When the heating treatment is carried out under reduced pressure, the heating time can be shortened. This heat treatment causes the threshold voltage to drop in the case of a normally-off (n-channel) transistor. Therefore, a thin film transistor in which the voltage is positive can be obtained. This can improve the reliability of the display device.

[0275] In addition, when an oxide semiconductor layer serving as a channel formation region is formed over a gate insulating layer, a reaction By removing residual moisture in the atmosphere, the concentrations of hydrogen and hydride in the oxide semiconductor layer are reduced. can be reduced.

[0276] The above process can be applied to LCD panels, electroluminescent display panels, and electronic ink displays. Used in the manufacture of backplanes (substrates on which thin film transistors are formed) for display devices The above process is carried out at a temperature of 400°C or less, so the thickness is 1 mm or less. It can also be applied to manufacturing processes using glass substrates with sides exceeding 1 m. All processes can be carried out at temperatures below 00°C, making it ideal for manufacturing display panels. This means that you don't have to consume a lot of energy.

[0277] In the thin film transistor using the oxide semiconductor layer manufactured as described above, Therefore, such a thin film transistor is used in a liquid crystal display device. By using it for multiple pixels that make up the display, the period during which the voltage can be held by the storage capacitor can be extended. LCD display that can be taken for a long time and can reduce power consumption when displaying still images, etc. In addition, by stopping the control signal when displaying a still image, it is possible to reduce power consumption. It is possible to reduce power consumption. It is also possible to switch between still images and moving images without malfunction. can.

[0278] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0279] (Sixth embodiment) One embodiment of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment will be described with reference to FIG. and explain.

[0280] The present embodiment is directed to another thin film transistor that can be applied to the liquid crystal display device disclosed in this specification. The thin film transistor 310 shown in this embodiment is the same as the thin film transistor 310 in the pixel portion 100 of Embodiment 1. The thin film transistors used in each of the eight pixels can be used.

[0281] 11A to 11E show examples of cross-sectional structures of thin film transistors. The thin film transistor 310 shown in (E) is a type of bottom gate structure, and is an inverted staggered thin film transistor. Also called a transistor.

[0282] The thin film transistor 310 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0283] 11(A) to 11(E), a thin film transistor 310 is fabricated on a substrate 300. The process will be explained.

[0284] First, a conductive film is formed on a substrate 300 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 311 is formed by a process. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0285] There is no significant limitation on the substrate that can be used for the substrate 300 having an insulating surface, but at least In either case, it is necessary for the material to have heat resistance sufficient to withstand the subsequent heat treatment.

[0286] For example, when a glass substrate is used as the substrate 300, if the temperature of the subsequent heat treatment is high, For the glass substrate, it is advisable to use a material with a strain point of 730°C or higher. Glasses such as silicate glass, aluminoborosilicate glass, and barium borosilicate glass The material used is barium oxide (BaO), which contains more barium oxide than boric acid. Therefore, more BaO than B2O3 is used. It is preferable to use a glass substrate containing

[0287] The substrate 300 may be a ceramic substrate, a quartz substrate, a surface substrate, or the like, in addition to the glass substrate. A substrate made of an insulating material such as a fiber substrate may also be used. Alternatively, a crystallized glass substrate may be used. You can be there.

[0288] An insulating film serving as a base film may be provided between the substrate 300 and the gate electrode layer 311. , which has the function of preventing the diffusion of impurity elements from the substrate 300, and is a silicon nitride film, a silicon oxide film, A laminated structure of one or more films selected from a silicon nitride oxide film or a silicon oxynitride film It can be formed.

[0289] The material of the gate electrode layer 311 is selected from the group consisting of molybdenum, titanium, chromium, tantalum, and tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0290] For example, the gate electrode layer 311 may have a two-layer laminate structure, such as a molybdenum layer on an aluminum layer. Two-layer laminated structure with a molybdenum layer on a copper layer, two-layer laminated structure with a molybdenum layer on a copper layer, copper layer A two-layer laminate structure with a titanium nitride layer or tantalum nitride layer on top, a titanium nitride layer and a molybdenum nitride layer Two-layer laminated structure consisting of a tungsten nitride layer and a tungsten layer, or two-layer laminated structure consisting of a tungsten nitride layer and a tungsten layer It is preferable to have a three-layer laminate structure. Tungsten nitride, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a nitride It is preferable to use a laminated layer formed by laminating a titanium oxide or titanium layer.

[0291] Next, the gate insulating layer 302 is formed on the gate electrode layer 311 .

[0292] The gate insulating layer 302 is a silicon oxide layer formed by using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer in a single layer or For example, SiH4, oxygen, and nitrogen are used as the deposition gas. A silicon oxynitride layer may be formed by plasma CVD. The thickness is 100 nm to 500 nm. In the case of a laminate, for example, the thickness is 50 nm to 2 a first gate insulating layer having a thickness of 500 nm or less and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less on the first gate insulating layer; The second gate insulating layer is laminated to a thickness of 1 m or less.

[0293] In this embodiment, the gate insulating layer 302 is formed by plasma CVD to a thickness of 100 nm or more. A bottom silicon oxynitride layer is formed.

[0294] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm or more, is formed on the gate insulating layer 302. The oxide semiconductor film 330 having a thickness of 30 nm or less is formed by sputtering. The appropriate thickness varies depending on the compound semiconductor material, and the thickness can be selected appropriately depending on the material. The cross section at this stage corresponds to FIG. 11(A).

[0295] Before the oxide semiconductor film 330 was formed by sputtering, argon gas was introduced. Reverse sputtering is performed to generate plasma, and dust adhering to the surface of the gate insulating layer 302 is removed. It is preferable to remove nitrogen, helium, oxygen, etc. instead of argon atmosphere. It may be used.

[0296] The oxide semiconductor film 330 may be an In-Ga-Zn-O based, In-Sn-Zn-O based, or In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- An O-based or Zn—O-based oxide semiconductor film is used. In this embodiment, the oxide semiconductor film 330 The film was formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. Specifically, the composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [mol %] (i.e., In:Ga:Zn=1:1:0.5[atom%]). , In:Ga:Zn=1:1:1[atom%], or In:Ga:Zn=1:1:2[ It is also possible to use a target having a composition ratio of [atomic %]. The target filling rate is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using an oxide semiconductor target with a high filling rate, the deposited oxide semiconductor film In addition, the target contains 2% to 10% by weight of SiO2. It may be possible. The sputtering atmosphere is a rare gas (typically argon), oxygen, or a rare gas and oxygen. The mixed atmosphere may be

[0297] The oxide semiconductor film 330 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or hydrogen. High purity, with impurities such as chlorides removed to 1 ppm or less, preferably 10 ppb or less It is preferable to use a gas.

[0298] Sputtering is performed by holding the substrate in a processing chamber maintained under reduced pressure and raising the substrate temperature to 100°C. The temperature is preferably 200°C to 400°C. By forming the oxide semiconductor film, the impurity concentration in the formed oxide semiconductor film can be reduced. Also, damage caused by sputtering is reduced. And residual moisture in the processing chamber is removed. The sputtering gas from which hydrogen and moisture have been removed is introduced while removing the target. An oxide semiconductor film 330 is formed on the substrate 300. In order to remove residual moisture in the treatment chamber, It is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, It is preferable to use a titanium sublimation pump. A cryopump with a cold trap may be used. The deposition chamber is filled with, for example, hydrogen molecules, compounds containing hydrogen atoms such as water (H2O), etc. (preferably Since the oxide semiconductor film formed in the film formation chamber is exhausted, The concentration of impurities contained in the film can be reduced.

[0299] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed direct current (DC) power supply is used, the powdery substances (particles) generated during film formation are This is preferable because it can reduce the amount of dust (also called crumbs or dirt) and make the film thickness distribution uniform.

[0300] Next, the oxide semiconductor film 330 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. The oxide semiconductor layer 331 is then processed into an oxide semiconductor layer 331. A resist mask for forming an island-shaped oxide semiconductor layer is then formed. The resist mask may be formed by an ink-jet method. Since no photomask is used, manufacturing costs can be reduced.

[0301] Next, first heat treatment is performed on the oxide semiconductor layer 331. The first heat treatment can dehydrate and / or dehydrogenate the oxide semiconductor layer 331. The temperature is 400°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is After heat treatment at 450°C for 1 hour in a nitrogen atmosphere, The temperature is lowered to 100°C, and the oxide semiconductor layer 331 is prevented from being mixed with water or hydrogen. (See FIG. 11(B)).

[0302] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0303] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. become.

[0304] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0305] As a result of the first heat treatment, hydrogen and the like contained in the oxide semiconductor layer 331 are removed. At the same time, oxygen deficiency occurs, resulting in an n-type semiconductor (a semiconductor with low resistance). The compound semiconductor layer 331 may be crystallized and formed into a fine structure depending on the conditions of the first heat treatment or the material. It may be a crystalline or polycrystalline film. For example, the crystallinity may be 90% or more, or 80% or more. In some cases, the oxide semiconductor layer 331 is a microcrystalline oxide semiconductor film. Depending on the conditions of the heat treatment or the material, it may become an amorphous oxide semiconductor that does not contain crystalline components. In addition, there are cases where microcrystalline parts (grain size 1 nm or more) are present in the amorphous oxide semiconductor. In the case where an oxide semiconductor film having a thickness of 0 nm or less (typically, 2 nm or more and 4 nm or less) is formed, There are also.

[0306] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 330 can also be subjected to the first heat treatment. In that case, after the first heat treatment, The substrate is removed and subjected to a photolithography process.

[0307] The heat treatment that has the effect of dehydrating and / or dehydrogenating the oxide semiconductor layer is carried out by an oxidation treatment. After forming the oxide semiconductor layer, a source electrode and a drain electrode are laminated on the oxide semiconductor layer. This may be performed either after forming a protective insulating film on the source electrode and the drain electrode.

[0308] In addition, when a contact hole is formed in the gate insulating layer 302, the process is performed using an oxide semiconductor. Even before the film 330 or the oxide semiconductor layer 331 is subjected to dehydration and / or dehydrogenation treatment, You can go after you go.

[0309] Note that the etching of the oxide semiconductor film here is not limited to wet etching, but may be dry etching. Etching may also be used.

[0310] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0311] Next, a conductive film is formed over the gate insulating layer 302 and the oxide semiconductor layer 331. The film can be formed by sputtering or vacuum deposition. Materials for the conductive film include Al, Cr, C An element selected from U, Ta, Ti, Mo, and W, or an alloy containing the above elements or an alloy film made of a combination of the above elements. , zirconium, beryllium, and yttrium. The conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a titanium film laminated on an aluminum film, A two-layer structure is formed by laminating a Ti film and an aluminum film on top of the Ti film. Examples include a three-layer structure in which a Ti film is formed. In addition, titanium (Ti) and tantalum are added to Al. (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium) ), Sc (Scandium), a film or alloy film made of a single or multiple combinations of elements, Alternatively, a nitride film may be used.

[0312] When a heat treatment is performed after the conductive film is formed, the conductive film must have heat resistance to withstand this heat treatment. It is preferable that

[0313] Next, a resist mask is formed over the conductive film by a third photolithography process. After etching the source electrode layer 315a and the drain electrode layer 315b, Remove the plaque mask (see Figure 11(C)).

[0314] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrodes adjacent to each other on the oxide semiconductor layer 331 are preferably irradiated with laser light or ArF laser light. The width of the gap between the bottom end of the drain electrode layer and the bottom end of the thin film transistor to be formed later The channel length L of the photoresist is determined. Note that when exposure is performed with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nanometers to a few tens of nanometers. olet) is used to perform exposure when forming a resist mask in the third photolithography process. Extreme ultraviolet light exposure provides high resolution and a large depth of focus. It is also possible to set the channel length L of the film transistor to 10 nm or more and 1000 nm or less. This allows for faster circuit operation and, due to the extremely small off-state current, also reduces power consumption. This can be achieved.

[0315] Note that the conductive film was etched so that the oxide semiconductor layer 331 was not removed. The material and etching conditions are adjusted appropriately.

[0316] In this embodiment, a Ti film is used as the conductive film, and an In—Ga Since a Zn-O-based oxide semiconductor was used, ammonia hydrogen peroxide (ammonia hydrogen peroxide) was used as an etchant. A mixture of water, hydrogen peroxide, and water is used.

[0317] Note that in the third photolithography step, only a part of the oxide semiconductor layer 331 is etched. In some cases, the source electrode layer 3 is formed as an oxide semiconductor layer having a groove (a recess). 15a, a resist mask for forming the drain electrode layer 315b is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0318] Further, an oxide conductive layer is formed between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. The oxide conductive layer and the metal layer for forming the source and drain electrode layers may be The oxide conductive layer can function as a source region and a drain region.

[0319] The oxide conductive layer is formed as a source region and a drain region by forming an oxide semiconductor layer and a source electrode layer. By providing the source and drain electrode layers between the source and drain regions, the resistance of the source and drain regions can be reduced. This allows the transistor to operate at high speed.

[0320] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0321] Next, plasma treatment is performed using gases such as N2O, N2, or Ar. The treatment removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0322] After the plasma treatment, the protective insulating film in contact with a part of the oxide semiconductor layer was removed without being exposed to the air. An oxide insulating layer 316 is formed as an insulating film.

[0323] The oxide insulating layer 316 has a thickness of at least 1 nm and is formed by an oxide insulating method such as sputtering. The layer 316 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the layer 316 . When hydrogen is contained in the oxide insulating layer 316, the hydrogen penetrates into the oxide semiconductor layer or The oxygen in the oxide semiconductor layer is extracted by the This may result in the formation of a parasitic channel. The insulating layer 316 is formed without using hydrogen so that the film contains as little hydrogen as possible. It is important to

[0324] In this embodiment, a silicon oxide film having a thickness of 200 nm is deposited by sputtering as the oxide insulating layer 316. The substrate temperature during film formation may be set to between room temperature and 300° C. The temperature is set at 100°C in this case. The silicon oxide film is formed by sputtering using a rare gas (typically, The test should be carried out under an atmosphere of rare gases, oxygen, or a mixture of rare gases and oxygen. In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used in a sputtering process under an oxygen and nitrogen atmosphere. The oxide film formed in contact with the oxide semiconductor layer having a low resistance can be formed by the above-mentioned method. The oxide insulating layer 316 is resistant to moisture, hydrogen ions, and OH - It does not contain impurities such as An inorganic insulating film is used to block the penetration of oxygen from the inside of the material. A silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0325] In this case, the oxide insulating layer 316 is formed while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor layer 331 and the oxide insulating layer 316 contain hydrogen, a hydroxyl group, and / or This is to prevent moisture from being absorbed.

[0326] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen molecules and water (H2 O), etc., which contain hydrogen atoms, The concentration of impurities contained in 316 can be reduced.

[0327] The oxide insulating layer 316 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or a hydrogenated High purity gas in which impurities such as ions have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable to use a

[0328] Next, a second heat treatment (preferably 2 For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. A portion of the oxide layer (channel formation region) is heated in contact with the oxide insulating layer 316 .

[0329] Through the above steps, the oxide semiconductor film after deposition is dehydrated and / or dehydrated. The heat treatment for hydrogenation was performed, and the resistance of the oxide semiconductor film was reduced. As a result, the channel forming region 313 overlapping the gate electrode layer 311 is in an excessive state. The source electrode layer 315a is overlapped with the source electrode layer 315b, and the high resistance source electrode layer 315b is made of a low resistance oxide semiconductor. The region 314a and the drain electrode layer 315b overlap each other. The anti-drain region 314b is formed in a self-aligned manner. 10 is formed (see FIG. 11(D)).

[0330] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By this heat treatment, the oxide semiconductor layer can be converted into an oxide film. Hydrogen is taken into the insulating layer, and a normally-off thin film transistor can be obtained. Therefore, the reliability of the liquid crystal display device can be improved. When a silicon oxide layer is used, the hydrogen and moisture contained in the oxide semiconductor layer are removed by this heat treatment. impurities such as hydroxyl groups or hydrides are diffused into the oxide insulating layer, and the impurities contained in the oxide semiconductor layer are This has the effect of further reducing the impurities that are present in the product.

[0331] Note that the oxide semiconductor layer overlapping with the drain electrode layer 315b (and the source electrode layer 315a) forming a high-resistance drain region 314b (or a high-resistance source region 314a) in This improves the reliability of the thin film transistor. By forming the drain electrode layer 315b, the high-resistance drain region 314b is 14b, a structure in which the conductivity can be changed stepwise from the first region to the channel forming region 313. Therefore, a line that supplies a high power supply potential VDD to the drain electrode layer 315b can be provided. When the device is connected to a line, a high-voltage power supply is provided between the gate electrode layer 311 and the drain electrode layer 315b. Even when an electric field is applied, the high-resistance drain region acts as a buffer, preventing the application of a local high electric field. The withstand voltage of the transistor can be improved.

[0332] The high-resistance source region or the high-resistance drain region in the oxide semiconductor layer is preferably formed of an oxide semiconductor. When the oxide layer is thin, 15 nm or less, it is formed throughout the entire thickness direction. When the thickness of the conductor layer is thicker, between 30 nm and 50 nm, a part of the oxide semiconductor layer, The resistance of the region in contact with the source electrode layer or the drain electrode layer and its vicinity is reduced, forming a high-resistance source region. Alternatively, a high-resistance drain region is formed, and the region of the oxide semiconductor layer close to the gate insulating film is It can also be type I.

[0333] A protective insulating layer may be further formed on the oxide insulating layer 316. For example, a protective insulating layer may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is used to form a protective insulating layer. This is a preferred method. The protective insulating layer is resistant to moisture, hydrogen ions, and OH - Contains impurities such as First, inorganic insulating films are used to block these substances from entering from the outside, and silicon nitride films, An aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, or the like is used. In this embodiment, the protective insulating layer 303 is formed using a silicon nitride film. (See Figure 11(E)).

[0334] In this embodiment, the protective insulating layer 303 is formed on the substrate 3 up to the oxide insulating layer 316. 00 is heated to a temperature of 100℃ to 400℃, and high-purity nitrogen from which hydrogen and moisture have been removed is obtained. A sputtering gas is introduced and a silicon nitride film is formed using a silicon semiconductor target. In this case, similarly to the oxide insulating layer 316, the remaining moisture in the treatment chamber is removed and the treatment chamber is maintained. A protective insulating layer 303 is preferably deposited.

[0335] A planarization insulating layer for planarization may be provided over the protective insulating layer 303.

[0336] As described above, the display portion of a liquid crystal display device having a thin film transistor using an oxide semiconductor layer Therefore, the off-state current can be reduced in the plurality of pixels constituting the storage capacitor. This allows the voltage to be maintained for a longer period, which reduces power consumption when displaying still images, etc. In addition, when a still image is displayed, the control signal is transmitted to the liquid crystal display device. By stopping the switching between still images and moving images, power consumption can be reduced. This can be done without any malfunctions.

[0337] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0338] (Embodiment 7) One mode of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment will be described with reference to FIGS. This will be used to explain.

[0339] The present embodiment is directed to another thin film transistor that can be applied to the liquid crystal display device disclosed in this specification. The thin film transistor 360 shown in this embodiment is the same as the thin film transistor 360 in the pixel portion 100 of Embodiment 1. The thin film transistors used in each of the eight pixels can be used.

[0340] 12(A) to 12(D) show an example of a cross-sectional structure of a thin film transistor. The thin film transistor 360 shown in (D) is a channel protection type (also called a channel stop type). It is one of the bottom gate structures known as inverted staggered thin film transistors.

[0341] The thin film transistor 360 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0342] 12(A) to 12(D), a thin film transistor 360 is fabricated on a substrate 320. The process will be explained.

[0343] First, a conductive film is formed on a substrate 320 having an insulating surface, and then a first photolithography is performed. A resist mask is formed by a process, and the conductive film is selectively etched using the resist mask. A gate electrode layer 361 is formed. Then, the resist mask is removed. The resist mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0344] The material of the gate electrode layer 361 is molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0345] Next, the gate insulating layer 322 is formed on the gate electrode layer 361 .

[0346] In this embodiment, the gate insulating layer 322 is formed by plasma CVD to a thickness of 100 nm or more. A bottom silicon oxynitride layer is formed.

[0347] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 322. The oxide semiconductor layer is then processed into an island-shaped oxide semiconductor layer by a second photolithography process. In this example, an In-Ga-Zn-O oxide semiconductor target is used as the oxide semiconductor film. The film is formed by sputtering.

[0348] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0349] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen molecules and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The concentration of impurities contained in the oxide semiconductor film can be reduced.

[0350] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. High purity gas in which impurities have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable to use

[0351] Next, the oxide semiconductor layer is dehydrated and / or dehydrogenated. The temperature of the first heat treatment for nitrification is 400°C or higher and 750°C or lower, preferably 400°C or higher. The substrate is placed in an electric furnace, which is a type of heat treatment device. After heat treatment was performed on the oxide semiconductor layer at 450° C. for 1 hour in a nitrogen atmosphere, The oxide semiconductor layer 33 is formed without contact with the atmosphere, preventing water and hydrogen from entering the oxide semiconductor layer. 2 is obtained (see Figure 12(A)).

[0352] Next, plasma treatment is performed using gases such as N2O, N2, or Ar. The treatment removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0353] Next, an oxide insulating layer was formed over the gate insulating layer 322 and the oxide semiconductor layer 332. After that, a resist mask is formed by a third photolithography process, and selective etching is performed. After forming the oxide insulating layer 366, the resist mask is removed.

[0354] In this embodiment, a silicon oxide film having a thickness of 200 nm is deposited by sputtering as the oxide insulating layer 366. The substrate temperature during film formation may be set to between room temperature and 300° C. The temperature is set at 100°C in this case. The silicon oxide film is formed by sputtering using a rare gas (typically, The test should be carried out under an atmosphere of rare gases, oxygen, or a mixture of rare gases and oxygen. In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used in a sputtering process under an oxygen and nitrogen atmosphere. The oxide insulating layer 3 formed in contact with the oxide semiconductor layer can be formed by the above-mentioned method. 66 is water, hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film that blocks the light is used, typically a silicon oxide film or a silicon oxynitride film. A film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0355] In this case, the oxide insulating layer 366 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 332 and the oxide insulating layer 366 contain hydrogen, a hydroxyl group, and / or This is to prevent moisture from being absorbed.

[0356] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen molecules and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The impurity concentration in the oxide insulating layer 366 can be reduced.

[0357] The oxide insulating layer 366 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or a hydrogenated High purity gas in which impurities such as ions have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable to use a

[0358] Next, a second heat treatment (preferably 2 For example, the heating may be performed at a temperature of 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. A second heat treatment is carried out at 250°C for 1 hour in a nitrogen atmosphere. A part of the oxide semiconductor layer (channel formation region) is heated in a state where the part is in contact with the oxide insulating layer 366. do.

[0359] In this embodiment, an oxide insulating layer 366 is further provided and a part of the oxide semiconductor is exposed. The oxide insulating layer 332 is subjected to heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. The exposed regions of the oxide semiconductor layer 332 that are not covered by 66 are filled with nitrogen, an inert gas, Heat treatment under a nitrogen atmosphere or reduced pressure can lower the resistance. Heat treatment is carried out in an atmosphere at 250°C for 1 hour.

[0360] Heat treatment in a nitrogen atmosphere on the oxide semiconductor layer 332 provided with the oxide insulating layer 366 As a result, the exposed region of the oxide semiconductor layer 332 has a low resistance, and the region with a different resistance (FIG. 12( In Fig. 1B, the oxide semiconductor layer 362 has a region indicated by hatched areas and white areas.

[0361] Next, a conductive film is formed on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. After forming the conductive film, a resist mask is formed by a fourth photolithography process. After selectively etching the silicon dioxide film to form the source electrode layer 365a and the drain electrode layer 365b, The resist mask is removed (see FIG. 12(C)).

[0362] The source electrode layer 365a and the drain electrode layer 365b may be made of Al, Cr, Cu, or T. An element selected from the group consisting of a, Ti, Mo, and W, or an alloy containing the above elements, or Examples include alloy films that combine the elements mentioned above. Conductive films can be either single-layer or double-layered. The above laminated structure may also be used.

[0363] By performing the above steps, a part of the oxide semiconductor film is selectively made into an oxygen-excess state. As a result, the channel forming region 363 overlapping the gate electrode layer 361 becomes I-shaped, and A high-resistance source region 364a overlaps the source electrode layer 365a, and a high-resistance source region 364b overlaps the drain electrode layer 365b. The high resistance drain region 364b is formed in a self-aligned manner. A star 360 is formed.

[0364] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By this heat treatment, the oxide semiconductor layer can be converted into an oxide film. Hydrogen is taken into the insulating layer, and a normally-off thin film transistor can be obtained. This improves the reliability of the liquid crystal display device.

[0365] Note that the oxide semiconductor layer overlapping with the drain electrode layer 365b (and the source electrode layer 365a) In this case, the high-resistance drain region 364b (or the high-resistance By forming the source region 364a), the reliability of the thin film transistor can be improved. Specifically, by forming the high-resistance drain region 364b, the drain electrode The conductivity is gradually increased from the layer to the high-resistance drain region 364b and the channel forming region 363. Therefore, the drain electrode layer 365b can be provided with a high When the gate electrode layer 361 and the drain electrode 362 are connected to a wiring that supplies a power supply potential VDD, the gate electrode layer 361 and the drain electrode 362 are connected to a wiring that supplies a power supply potential VDD. Even if a high voltage is applied between the drain electrode layer 365b and the high-resistance drain region, the high-resistance drain region acts as a buffer. Local electric field concentration is unlikely to occur, and the breakdown voltage of the transistor can be improved. .

[0366] A protective insulating layer 3 is formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film. (See Figure 12(D)).

[0367] Note that a thin film is further formed over the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. An oxide insulating layer may be formed and a protective insulating layer 323 may be stacked over the oxide insulating layer.

[0368] As described above, the display portion of a liquid crystal display device having a thin film transistor using an oxide semiconductor layer Therefore, the off-state current can be reduced in the plurality of pixels constituting the storage capacitor. This allows the voltage to be maintained for a longer period, which reduces power consumption when displaying still images, etc. In addition, when a still image is displayed, the control signal is transmitted to the liquid crystal display device. By stopping the switching between still images and moving images, power consumption can be reduced. This can be done without any malfunctions.

[0369] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0370] (Embodiment 8) The present embodiment is directed to another thin film transistor that can be applied to the liquid crystal display device disclosed in this specification. The thin film transistor 350 shown in this embodiment is the same as the thin film transistor 350 in the pixel portion 100 of Embodiment 1. The thin film transistors used in each of the eight pixels can be used.

[0371] One mode of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment will be described with reference to FIGS. This will be used to explain.

[0372] The thin film transistor 350 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0373] 13A to 13D, a thin film transistor 350 is fabricated on a substrate 340. The process will be explained.

[0374] First, a conductive film is formed on a substrate 340 having an insulating surface, and then a first photolithography is performed. In this embodiment, the gate electrode layer 351 is formed by a process. Then, a tungsten film having a thickness of 150 nm is formed by sputtering.

[0375] Next, a gate insulating layer 342 is formed over the gate electrode layer 351. A silicon oxynitride layer having a thickness of 100 nm or less is formed as the insulating layer 342 by the plasma CVD method. Form.

[0376] Next, a conductive film is formed on the gate insulating layer 342, and a second photolithography process is performed. A resist mask is formed over the conductive film, and selective etching is performed to form a source electrode layer 355a After the drain electrode layer 355b is formed, the resist mask is removed (see FIG. 13A). .).

[0377] Next, an oxide semiconductor film 345 is formed (see FIG. 13B). The semiconductor film 345 is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target. The oxide semiconductor film 345 is formed into an island shape by a third photolithography process. The oxide semiconductor layer is processed into an oxide semiconductor layer.

[0378] In this case, the oxide semiconductor film 345 is formed while removing residual moisture in the treatment chamber. In order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film 345, This is the case.

[0379] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen molecules and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The concentration of impurities in the oxide semiconductor film 345 can be reduced.

[0380] The oxide semiconductor film 345 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or hydrogen. High purity, with impurities such as chlorides removed to 1 ppm or less, preferably 10 ppb or less It is preferable to use a gas.

[0381] Next, the oxide semiconductor layer is dehydrated and / or dehydrogenated. The temperature of the first heat treatment for nitrification is 400°C or higher and 750°C or lower, preferably 400°C or higher. The substrate is placed in an electric furnace, which is a type of heat treatment device. After heat treatment was performed on the oxide semiconductor layer at 450° C. for 1 hour in a nitrogen atmosphere, The oxide semiconductor layer 34 is formed without contact with the atmosphere, preventing water and hydrogen from entering the oxide semiconductor layer. 6 is obtained (see Figure 13(C)).

[0382] In the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is removed from the inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. do.

[0383] An oxide insulating layer 356 serving as a protective insulating film in contact with the oxide semiconductor layer 346 is formed.

[0384] The oxide insulating layer 356 has a thickness of at least 1 nm and is formed by an oxide insulating method such as sputtering. The layer 356 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the layer 356. When hydrogen is contained in the oxide insulating layer 356, the hydrogen penetrates into the oxide semiconductor layer or The oxygen in the oxide semiconductor layer is extracted by the This may result in the formation of a parasitic channel. The insulating layer 356 is formed without using hydrogen so that the film contains as little hydrogen as possible. It is important to

[0385] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed as the oxide insulating layer 356 by sputtering. The substrate temperature during film formation may be set to between room temperature and 300° C. The temperature is set at 100°C in this case. The silicon oxide film is formed by sputtering using a rare gas (typically, The test should be carried out under an atmosphere of rare gases, oxygen, or a mixture of rare gases and oxygen. In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used in a sputtering process under an oxygen and nitrogen atmosphere. The oxide insulating layer 3 formed in contact with the oxide semiconductor layer can be formed by the above-mentioned method. 56 is water, hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film that blocks the light is used, typically a silicon oxide film or a silicon oxynitride film. A film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0386] In this case, the oxide insulating layer 356 is formed while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor layer 346 and the oxide insulating layer 356 contain hydrogen, a hydroxyl group, and / or This is to prevent moisture from being absorbed.

[0387] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen molecules and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The impurity concentration in the oxide insulating layer 356 can be reduced.

[0388] The oxide insulating layer 356 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or a hydrogenated High purity gas in which impurities such as ions have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable to use a

[0389] Next, a second heat treatment (preferably 2 For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. A portion of the oxide layer (channel formation region) is heated in contact with the oxide insulating layer 356 .

[0390] By going through the above steps, the oxide semiconductor film is made to have an oxygen excess state. The thin film transistor 350 is fabricated by the above steps. can be.

[0391] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By this heat treatment, the oxide semiconductor layer can be converted into an oxide film. Hydrogen is taken into the insulating layer, and a normally-off thin film transistor can be obtained. This improves the reliability of the liquid crystal display device.

[0392] A protective insulating layer may be further formed on the oxide insulating layer 356. For example, a protective insulating layer may be formed by RF sputtering. In this embodiment, the protective insulating layer 343 is formed as a protective insulating layer. The insulating film is formed using a silicon nitride film (see FIG. 13(D)).

[0393] A planarization insulating layer for planarization may be provided over the protective insulating layer 343.

[0394] The thin film transistor using the oxide semiconductor layer obtained in the above manner has a reduced off-state current. Therefore, these thin film transistors are used to form the display section of a liquid crystal display device. By using it for multiple pixels, the period during which the voltage can be held by the storage capacitor can be extended. and a liquid crystal display device capable of reducing power consumption when displaying still images, etc. In addition, by stopping the control signal when displaying a still image, power consumption can be further reduced. Furthermore, it is possible to switch between still images and moving images without any malfunction. .

[0395] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0396] (Embodiment 9) In this embodiment mode, an example in which a part of the manufacturing process of a thin film transistor is different from that in Embodiment Mode 6 is shown in FIG. 4. Figure 14 is the same as Figure 11 except for some differences in the process, so the same parts are The same reference numerals are used and detailed explanations of the same parts are omitted.

[0397] The present embodiment is directed to another thin film transistor that can be applied to the liquid crystal display device disclosed in this specification. The thin film transistor 380 shown in this embodiment is the same as the thin film transistor 380 in the pixel portion 100 of Embodiment 1. The thin film transistors used in each of the eight pixels can be used.

[0398] According to the sixth embodiment, a gate electrode layer 381 is formed on the substrate 370, and a first gate insulating layer 382 is formed on the substrate 370. In this embodiment, a gate insulating layer 372a and a second gate insulating layer 372b are stacked. The first gate insulating layer 372a is a nitride insulating layer, and the second gate insulating layer 3 An oxide insulating layer is used for 72b.

[0399] The oxide insulating layer may be a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. As the nitride insulating layer, an aluminum oxynitride layer, or the like can be used. a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer A layer or the like can be used.

[0400] In this embodiment, a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer 381 side. The first gate insulating layer 372a is formed by sputtering to a thickness of 50 nm. A silicon nitride layer (SiN y (y> 0)) is formed on the first gate insulating layer 372a as a second gate insulating layer 372b. A silicon oxide layer (SiO ) having a thickness of 5 nm to 300 nm (100 nm in this embodiment) x (x>0) is laminated to form a gate insulating layer having a thickness of, for example, 150 nm.

[0401] Next, an oxide semiconductor film is formed, and the oxide semiconductor film is formed into island shapes by a photolithography process. In this embodiment, the oxide semiconductor film is formed of In-Ga-Z The film is formed by sputtering using an nO-based oxide semiconductor target.

[0402] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0403] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen molecules and water (H2 O), etc., which contain hydrogen atoms, are exhausted. The concentration of impurities contained in the film can be reduced.

[0404] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. High purity gas in which impurities have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable to use

[0405] Next, the oxide semiconductor layer is dehydrated and / or dehydrogenated. The temperature of the first heat treatment for denitrification is 400° C. or higher and 750° C. or lower, preferably 42° C. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. If the temperature is below 5°C, the heating time is longer than 1 hour. The substrate is placed in an electric furnace, which is one of the treatment apparatuses, and the oxide semiconductor layer is heated in a nitrogen atmosphere. After the heat treatment, the oxide semiconductor layer is kept free from exposure to the air to prevent water and hydrogen from entering the oxide semiconductor layer. After that, high-purity oxygen gas and high-purity N2O gas are added to the same furnace. Alternatively, ultra-dry air (dew point of -40°C or less, preferably -60°C or less) is introduced for cooling. It is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. The purity of oxygen gas or N2O gas introduced into the heat treatment device is 6N (99.9999%). or more, preferably 7N (99.99999%) or more (i.e., oxygen gas or N2O gas) It is preferable to set the impurity concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0406] The heat treatment device is not limited to an electric furnace, and may be, for example, a GRTA (Gas Rapid Th thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Use an RTA (Rapid Thermal Anneal) device such as an LRTA devices can be used with halogen lamps, metal halide lamps, and xenon lamps. Arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp. Heat is generated by heat conduction or heat radiation from heating elements such as TA devices, lamps, and resistance heating elements. The GRTA is a device that uses high-temperature gas to heat the object to be treated. The gas used is a rare gas such as argon, and / or a rare gas such as nitrogen. An inert gas that does not react with the object to be treated is used in the heat treatment. Heat treatment may be performed at 00°C to 750°C for several minutes.

[0407] In addition, after the first heat treatment for dehydration and / or dehydrogenation, the temperature is set to 200°C or higher and 400°C or lower. Preferably, the temperature is 200°C or higher and 300°C or lower in an oxygen gas or N2O gas atmosphere. Heat treatment may be carried out.

[0408] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0409] By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, and thus a high resistance Thus, the oxide semiconductor layer 382 is entirely i-type.

[0410] Next, a resist mask is formed over the oxide semiconductor layer 382 by a photolithography process. Then, selective etching is performed to form a source electrode layer 385a and a drain electrode layer 385b. Then, an oxide insulating layer 386 is formed by sputtering.

[0411] In this case, the oxide insulating layer 386 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 382 and the oxide insulating layer 386 contain hydrogen, a hydroxyl group, and / or This is to prevent moisture from being absorbed.

[0412] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen molecules and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The impurity concentration in the oxide insulating layer 386 can be reduced.

[0413] The oxide insulating layer 386 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or a hydrogenated High purity gas in which impurities such as ions have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable to use a

[0414] Through the above steps, the thin film transistor 380 can be manufactured.

[0415] Next, in order to reduce the variation in the electrical characteristics of the thin film transistors, Alternatively, heat treatment (preferably at 150°C or higher and lower than 350°C) is carried out in a nitrogen gas atmosphere. For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0416] In addition, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By this heat treatment, the oxide semiconductor layer can be converted into an oxide film. Hydrogen is taken into the insulating layer, and a normally-off thin film transistor can be obtained. This improves the reliability of the liquid crystal display device.

[0417] The protective insulating layer 373 is formed over the oxide insulating layer 386. In this embodiment, the protective insulating layer 3 As the film 73, a silicon nitride film having a thickness of 100 nm is formed by sputtering.

[0418] The protective insulating layer 373 and the first gate insulating layer 372a made of a nitride insulating layer are resistant to moisture and water. It does not contain impurities such as hydrogen, hydrides, or hydroxides, and blocks these from entering from the outside. It has the effect of checking.

[0419] Therefore, in the manufacturing process after the protective insulating layer 373 is formed, impurities such as moisture from the outside In addition, it is possible to prevent the intrusion of dust particles into the liquid crystal display device for a long period of time after the device is completed. In addition, it can prevent the intrusion of impurities such as moisture from the outside, improving the long-term reliability of the device. It is possible.

[0420] In addition, between the protective insulating layer 373 made of a nitride insulating layer and the first gate insulating layer 372a The insulating layer is removed, and the protective insulating layer 373 and the first gate insulating layer 372a are in contact with each other. The structure may be such that:

[0421] Therefore, impurities such as moisture, hydrogen, hydrides, and hydroxides in the oxide semiconductor layer can be reduced. In addition, the inclusion of the impurities can be prevented, and the impurity concentration in the oxide semiconductor layer can be kept low. Cut.

[0422] A planarization insulating layer for planarization may be provided over the protective insulating layer 373.

[0423] As described above, the display portion of a liquid crystal display device having a thin film transistor using an oxide semiconductor layer Therefore, the off-state current can be reduced in the plurality of pixels constituting the storage capacitor. This allows the voltage to be maintained for a longer period, which reduces power consumption when displaying still images, etc. In addition, when a still image is displayed, the control signal is transmitted to the liquid crystal display device. By stopping the switching between still images and moving images, power consumption can be reduced. This can be done without any malfunctions.

[0424] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0425] (Embodiment 10) The present embodiment is directed to another thin film transistor that can be applied to the liquid crystal display device disclosed in this specification. The thin film transistor shown in this embodiment is the same as the thin film transistor 1 of Embodiment 1. 05 can be applied to the thin film transistors of Embodiments 2 to 8. can.

[0426] In this embodiment mode, a light-transmitting conductive film is formed in the gate electrode layer, the source electrode layer, and the drain electrode layer. Therefore, the other steps can be carried out in the same manner as in the above embodiment. The description of the same parts as those in the embodiment, or parts having similar functions, and repeated steps will be omitted. Also, detailed explanations of the same parts will be omitted.

[0427] For example, the gate electrode layer, the source electrode layer, and the drain electrode layer may be made of a material that is transparent to visible light. Photoconductive materials, such as In-Sn-O, In-Sn-Zn-O, and In-Al -Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn- O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O Zn-O and Zn-O metal oxides can be used, with a film thickness of 50 nm to 300 nm. The metal oxide used in the gate electrode layer, the source electrode layer, and the drain electrode layer is appropriately selected within the range. The deposition method of the oxide is sputtering, vacuum deposition (electron beam deposition, etc.), arc deposition, etc. Discharge ion plating method, spray method, and sputtering method are used. In this case, the film is formed using a target containing 2% by weight or more and 10% by weight or less of SiO2, and the film is transparent. The conductive film contains SiOx (X>0) which inhibits crystallization, and the heating process It is preferable to suppress crystallization during the treatment.

[0428] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and is measured by an electron probe microanalyzer. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be evaluated by analysis.

[0429] In addition, the pixel where the thin film transistor is arranged has a pixel electrode layer or other electrode layer (capacitor The transparent electrode layer and other wiring layers (such as the capacitor wiring layer) are transparent to visible light. By using a conductive film, a display device having a high aperture ratio can be realized. The gate insulating layer, oxide insulating layer, protective insulating layer, and planarizing insulating layer present therein are also transparent to visible light. It is preferable to use a membrane having the following properties:

[0430] In this specification, a film that is transparent to visible light is a film that has a visible light transmittance of 75 to 100 %, and if the film is conductive, it is also called a transparent conductive film. Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes As a metal oxide applied to the wiring layer, a conductive film that is semi-transparent to visible light is used. Translucent to visible light means that the transmittance of visible light is 50 to 75%. .

[0431] By making the thin film transistor transparent, the aperture ratio can be improved. In small LCD panels of 100mm or less, the number of gate wirings can be increased to improve the image quality. In order to achieve high definition, a high aperture ratio can be achieved even if the pixel size is made smaller. In addition, a wide viewing angle is achieved by using a transparent film as a component of the thin-film transistor. Therefore, a high aperture ratio can be achieved even when one pixel is divided into multiple sub-pixels. In other words, even if a group of high-density thin-film transistors is arranged, a large aperture ratio can be obtained, and the display For example, two to four sub-pixels can be placed in one pixel. When a cell is provided, the aperture ratio can be improved because the thin film transistor has light-transmitting properties. In addition, the storage capacitor can be formed using the same material in the same process as the constituent members of the thin film transistor. In this case, the storage capacitor can also be made translucent, which can further improve the aperture ratio. do.

[0432] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0433] (Embodiment 11) The appearance and cross section of a liquid crystal display panel, which is one form of liquid crystal display device, will be explained using FIG. 15. FIG. 15 shows a thin film transistor 4010 formed on a first substrate 4001. The liquid crystal element 4011 and the liquid crystal element 4013 are sandwiched between the second substrate 4006 and the liquid crystal display panel 4008 by a sealant 4005. 15(B) is a plan view of the panel sealed by the sealing method shown in FIG. 15(A) or FIG. 15(C). ) corresponds to a cross section at MN.

[0434] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0435] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, a wire The ear bonding method, TAB method, etc. can be used. FIG. 15(C) shows an example of mounting a signal line driver circuit 4003 by the G method, and FIG. 15(D) shows an example of mounting a signal line driver circuit 4003 by the TAB method. This is an example in which a signal line driver circuit 4003 is mounted.

[0436] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 15B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The insulating layers 4041 and 4042 are formed on the thin film transistors 4010 and 4011. 2, 4020, and 4021 are provided.

[0437] The thin film transistors 4010 and 4011 are the thin film transistors according to any one of the second to ninth embodiments. A thin film transistor can be used as appropriate and can be formed using similar processes and materials. The oxide semiconductor layers of the transistors 4010 and 4011 have reduced hydrogen and water. The thin film transistors 4010 and 4011 are highly reliable thin film transistors. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors. do.

[0438] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is formed on the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the layer at a position overlapping the channel forming region of the nitride semiconductor layer, In this case, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0439] The pixel electrode layer 4030 of the liquid crystal element 4013 is The liquid crystal element 4013 is electrically connected to the source electrode layer or the drain electrode layer. The counter electrode layer 4031 is formed on the second substrate 4006. The portion where the electrode layer 4031 and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. The pixel electrode layer 4030 and the counter electrode layer 4031 are insulating layers that function as alignment films. The liquid crystal layer 4008 is connected to the insulating layer 4032 and the insulating layer 4033. It is being held.

[0440] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film Films can be used.

[0441] 4035 is a columnar spacer obtained by selectively etching the insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrode layer 40 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0442] Liquid crystal materials include thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, These liquid crystal materials can be cholesteric or antiferroelectric depending on the conditions. These phases include smectic phase, cubic phase, chiral nematic phase, and isotropic phase.

[0443] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. It is optically isotropic, so alignment treatment is not required, and viewing angle dependency is small. Since there is no need to provide an alignment film, rubbing treatment is also unnecessary. This prevents electrostatic breakdown caused by the liquid crystal display device during the manufacturing process. Therefore, it is possible to improve the productivity of the liquid crystal display device. In particular, thin film transistors using oxide semiconductor layers are susceptible to static electricity. Therefore, the electrical characteristics of the capacitor may fluctuate significantly and deviate from the design range. It is possible to use a blue phase liquid crystal material in a liquid crystal display device having a thin film transistor using a layer. It is more effective.

[0444] The specific resistance of the liquid crystal material is 1×10 12 Ω·cm or more, preferably 1×10 1 3 Ω cm, and more preferably 1×10 14Exceeds Ω·cm It is preferable that the resistance of a liquid crystal cell be Impurities from the alignment film and sealing material may be mixed in. 11 Ω cm More preferably, 1×10 12 A preferable requirement is that the resistance exceeds Ω·cm. In addition, the resistivity values ​​in this specification are values ​​measured at 20°C.

[0445] The higher the resistivity of the liquid crystal material, the less charge can leak through the liquid crystal material. This can mitigate the phenomenon that the voltage required to maintain the device in an operating state decreases over time. Since the interval can be made longer, the frequency of writing signals can be reduced, leading to lower power consumption of the display device. This can be achieved.

[0446] In addition to the transmissive liquid crystal display device, the present invention can also be applied to semi-transmissive liquid crystal display devices or reflective liquid crystal display devices. The display device of the present embodiment is not limited to a liquid crystal display device, and may be any other display device. EL display devices that use light-emitting elements such as electroluminescent elements (EL elements) It may also be placed.

[0447] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer and a display element are provided on the inner side. In this example, the polarizing plate is provided on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment, and the materials of the polarizing plate and the colored layer and The conditions may be appropriately set depending on the manufacturing process conditions. A light-shielding film that functions as a light-shielding film may be provided.

[0448] An insulating layer 4041 is provided over the thin film transistors 4011 and 4010 in contact with the oxide semiconductor layer. The insulating layer 4041 is formed using a material similar to that of the oxide insulating layer 416 described in Embodiment 2. Here, the insulating layer 4041 is formed by the same material and method as in Embodiment 2. A silicon oxide layer is formed by sputtering. The protective insulating layer 4042 is formed by the same method as in Embodiment 2. It may be formed in the same manner as the edge layer 403, and for example, a silicon nitride film may be used. A planarizing insulating film is formed on the protective insulating layer 4042 to reduce surface irregularities caused by the thin film transistor. The insulating layer 4021 functions as a protective layer.

[0449] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking a plurality of insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0450] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a S OG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, lean printing, offset printing, etc.), doctor knife, roll coater, curtain coater A knife coater or the like can be used. By using the same as the substrate, it becomes possible to manufacture a liquid crystal display device efficiently.

[0451] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium tin oxide (ITO) and indium oxide. IZO (indium zinc oxide) is a mixture of indium and zinc oxide (ZnO). , conductive materials made by mixing indium oxide with silicon oxide (SiO2), organic indium, organic silicon Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, etc. Any light-transmitting conductive material can be used. If the device does not need to be translucent or needs to be reflective, W, Molybdenum (Mo), Zirconium (Zr), Hafnium (Hf), Vanadium (V), Niobium (Nb), Tantalum (Ta), Chromium (Cr), Cobalt (C o), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper ( One or more of metals such as Cu, silver (Ag), or their alloys or metal nitrides It can be formed using several types.

[0452] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0453] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0454] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0455] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0456] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0457] In FIG. 15, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0458] In addition, optical components such as black matrices (light-shielding layers), polarizing components, phase difference components, and anti-reflection components For example, a polarizing substrate and a retardation substrate are used to generate circularly polarized light. In addition, a backlight, a sidelight, or the like may be used as the light source.

[0459] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is displayed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0460] Furthermore, thin film transistors are easily damaged by static electricity, so the pixel section or drive It is preferable that a protection circuit be provided over the same substrate as the operation circuit. For example, the protection circuit is configured by using a nonlinear element. In this embodiment, a plurality of protection circuits are provided between the line input terminal and the signal line input terminal. A surge voltage is applied to the scanning lines, signal lines, and capacitance bus lines due to static electricity or the like. It is designed to prevent damage to pixel transistors, etc. When a voltage is applied to the transistor, the charge is released to the common wiring. is a nonlinear element arranged in parallel between a scanning line, a signal line, or a capacitance bus line and a common wiring. The nonlinear element is a two-terminal element such as a diode and / or a transistor. It is made up of a three-terminal element like a transistor. For example, it is made in the same process as the thin-film transistor in the pixel section. For example, the gate terminal and the drain terminal can be connected to form a It can have the same properties as an aerod.

[0461] The LCD module is available in TN (Twisted Nematic) mode, IP S (In-Plane-Switching) mode, FFS (Fringe Field d Switching) mode, ASM (Axially Symmetric al Ignition Micro-cell mode, OCB (Optically Comp Insulated Birefringence mode, FLC (Ferrerolector ic Liquid Crystal) mode, AFLC (AntiFerroelec tric Liquid Crystal) can be used.

[0462] As described above, the liquid crystal display device disclosed in the present specification is not particularly limited, and may be any of TN liquid crystal, OCB LCD, STN LCD, VA LCD, ECB type LCD, GH LCD, polymer dispersed LCD, Among them, normally black type liquid crystal panel is used. Preferably, the display device is a transmissive liquid crystal display device employing a vertical alignment (VA) mode. There are several types of vertical alignment modes, such as MVA (Multi-D Main Vertical Alignment mode, PVA (Pattern Use the ED Vertical Alignment mode, ASV mode, etc. can be done.

[0463] The present invention can also be applied to VA type liquid crystal display devices. VA type LCDs are a type of LCD panel that controls the alignment of liquid crystal molecules. This is a method in which the liquid crystal molecules are oriented perpendicular to the panel surface when no voltage is applied. In addition, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. It is called multi-domain or multi-domain design, which is designed to defeat molecules. The method can be used.

[0464] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0465] (Embodiment 12) In this embodiment, an electronic device including the liquid crystal display device described in the above embodiment will be described. An example will be described.

[0466] FIG. 16(A) shows a portable gaming machine, which includes a housing 9630, a display unit 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, recording medium reading unit 9672, etc. The portable gaming machine shown in FIG. 16(A) can be used to play a program or data recorded on a recording medium. It also has the function of reading out data and displaying it on the display, and of sharing information with other portable gaming machines via wireless communication. The portable gaming machine shown in FIG. 16(A) has the following functions. The functions are not limited to these, and various functions can be provided.

[0467] FIG. 16B shows a digital camera, which includes a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, connection terminal 9636, shutter button 9676, image receiving unit 9677 , etc. The digital camera with a television receiving function shown in FIG. 16(B) can have: Functions for taking still images, shooting videos, and automatically or manually correcting captured images Function, function to acquire various information from the antenna, image taken or acquired from the antenna It has the function of saving the captured information, displaying the captured image or the information obtained from the antenna on the display. It should be noted that the digital camera with television reception function shown in FIG. The functions of the mobile camera are not limited to these, and the mobile camera may have a variety of functions.

[0468] FIG. 16C shows a television receiver, which includes a housing 9630, a display portion 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, etc. A television receiver has the functions of processing television radio waves and converting them into image signals, It has functions such as converting signals suitable for display and converting the frame frequency of image signals. It should be noted that the functions of the television receiver shown in FIG. 16(C) are not limited to these. It can have a variety of functions.

[0469] FIG. 17A shows a computer, which includes a housing 9630, a display portion 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, pointing devices 9681, external connection points The computer shown in FIG. 17(A) can store various information. (still images, videos, text images, etc.) on the display, Functions for controlling processing by means of a program, communication functions such as wireless or wired communication, the ability to connect to various computer networks using the communication function, It can have a function to transmit or receive data, etc. The functions possessed by the computer are not limited to these, and the computer may have a variety of functions.

[0470] Next, FIG. 17B shows a mobile phone, which includes a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, microphone 9638, etc. The mobile phone shown in has the function of displaying various information (still images, videos, text images, etc.), Functions for displaying the calendar, date, time, etc. on the display, and for operating or It has the function of editing, the function of controlling the processing by various software (programs), etc. The functions of the mobile phone shown in FIG. 17(B) are not limited to these. It can have a variety of functions.

[0471] Next, FIG. 17C shows an electronic paper (also called an E-book), which has a housing 9630, a display The electronic pen 9630 shown in FIG. 17(C) may have a display unit 9631, operation keys 9635, etc. The user can display various information (still images, videos, text images, etc.), a calendar, , the function to display the date or time on the display unit, and the function to operate or edit the information displayed on the display unit Functions, functions to control processing by various software (programs), etc. The functions of the electronic paper shown in FIG. 17(C) are not limited to these. It can have a variety of functions.

[0472] In the electronic device described in this embodiment, in a plurality of pixels constituting a display portion, Therefore, the period during which the voltage can be maintained by the storage capacitor can be extended. The liquid crystal display device is capable of displaying still images and the like with low power consumption. In addition, by stopping the control signal when displaying a still image, the electronic device This allows for lower power consumption. It is possible.

[0473] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0474] (Embodiment 13) In this embodiment, the operation principle of a bottom-gate transistor using an oxide semiconductor will be described. and explain.

[0475] FIG. 19 is a cross-sectional view of an inverted staggered insulated gate transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is formed on a gate electrode (G1) via a gate insulating film (GI1). A source electrode (S) and a drain electrode (D) are provided thereon. A second gate insulating film (GI2) is formed on the source electrode (S) and the drain electrode (D), and The second gate electrode (G2) is provided on the gate electrode. G2 is kept at ground potential. .

[0476] The following explanation will be given using an energy band diagram. Please note that this has been simplified as much as possible to make it easier to understand, and is not rigorous. FIG. 20 is an energy band diagram (schematic diagram) in the cross section taken along the line AA' shown in FIG. In FIG. 20(A), the voltages between the gate, source, and drain are set to be equipotential (VD=0V). Figure 20(B) shows the case where a positive potential (VD>0) is applied to the gate and drain relative to the source. This shows the case where

[0477] FIG. 21 is an energy band diagram (schematic diagram) in the cross section taken along line B-B' in FIG. Figure 21(A) shows the state where a positive potential (+VG) is applied to the gate (G1), and the source The figure shows the ON state where carriers (electrons) flow between the gate and drain. , a negative potential (-VG) is applied to the gate (G1), and the transistor is in the off state (minority carry). A indicates that the signal does not flow.

[0478] Figure 22 shows the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). Shows.

[0479] Since metals are degenerate, the conduction band and the Fermi level coincide. The body is generally n-type, in which case the Fermi level (Ef) is located in the center of the band gap. It is located away from the intrinsic Fermi level (Ei) and closer to the conduction band. It is known that hydrogen is a donor in semiconductors and is one of the factors that cause them to become n-type.

[0480] In contrast, the oxide semiconductor according to the present invention removes hydrogen, which is an n-type impurity, from the oxide semiconductor. By removing impurities other than the main components of the oxide semiconductor and purifying it to the utmost, It is made intrinsic (type I) or substantially intrinsic, i.e., it is made without adding impurities. Instead of converting it to I-type, impurities such as hydrogen and water are removed as much as possible to achieve high purity. It is characterized by being an I-type (intrinsic semiconductor) or close to it. The Fermi level (Ef) can be made to be the same as the intrinsic Fermi level (Ei).

[0481] When the band gap (Eg) of an oxide semiconductor is 3.15 eV, the electron affinity (χ) is The titanium (Ti) that makes up the source and drain electrodes is said to be 4.3 eV. The electron affinity function is approximately equal to the electron affinity (χ) of the oxide semiconductor. At the interface between the layers, no Schottky barrier is formed for electrons.

[0482] That is, when the work function (φM) of the metal and the electron affinity (χ) of the oxide semiconductor are equal, When a person comes into contact with the surface, an energy band diagram (schematic diagram) such as that shown in FIG. 20(A) is displayed.

[0483] In FIG. 20(B), black circles (●) represent electrons, and a positive potential is applied to the gate and drain. When the electrons are injected into the oxide semiconductor, they cross the barrier (h) and flow toward the drain. In this case, the barrier height (h) changes depending on the gate voltage and drain voltage. When a positive drain voltage is applied, the barrier height in FIG. 20(A) is In other words, the barrier height (h) is smaller than half the band gap (Eg).

[0484] At this time, the electrons injected into the oxide semiconductor pass through the oxide semiconductor as shown in FIG. In addition, in FIG. 21(B), when a negative potential (reverse bias) is applied to the gate electrode (G1), When a voltage is applied, the number of holes, which are minority carriers, is essentially zero, so the current flows close to zero. The value is close to B.

[0485] For example, if the channel width W of the insulated gate transistor is 1×10 4 μm Even with a device with a channel length of 3 μm, the off-state current is 10 -13 A or less, and A power swing value (S value) of 0.1V / dec. (gate insulating film thickness 100nm) can be obtained. .

[0486] The intrinsic carrier density of silicon semiconductor is 1.45 × 10 10 / cm 3 (300K) This means that thermally excited carriers exist even at room temperature. In practice, impurities such as phosphorus or boron are added. In addition, even if it is called an intrinsic silicon wafer, it is not intended to be In reality, the amount of impurities that cannot be controlled is 1×10 14 / cm 3 More than a career exists in silicon semiconductors, which contributes to conduction between the source and drain. The band gap of silicon semiconductor is 1.12 eV, so The off-state current of a transistor varies greatly depending on the temperature.

[0487] Therefore, rather than simply applying a wide bandgap oxide semiconductor to a transistor, By purifying the oxide semiconductor to the extent possible so that it contains as few impurities as possible other than the main component, Carrier density is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 It will be as follows This eliminates thermally excited carriers at practical operating temperatures and allows The transistor can be operated only by the carriers injected from the , off-current 1×10 -13 [A] or less, and the off-current Therefore, a transistor can be obtained that operates extremely stably with almost no change in the capacitance.

[0488] The technical idea of ​​the present invention is to provide a method for producing an oxide semiconductor that is unintentionally present without further addition. By removing impurities such as water and hydrogen, the oxide semiconductor itself can be highly purified. That is, by removing water or hydrogen that constitutes the donor level, oxygen vacancies are further reduced. By supplying a sufficient amount of oxygen to remove the oxide semiconductor, the oxide semiconductor itself can be highly purified. It is characterized by the following.

[0489] Oxide semiconductors are 10 20 / cm3 The hydrogen level is measured by SIMS (secondary ion This can be observed by mass spectrometry. The water or hydrogen that creates this impurity called the donor level can be intentionally removed. The oxygen (a component of oxide semiconductors) that is simultaneously reduced with the removal of water or hydrogen is also removed. By adding one of these to the oxide semiconductor, the oxide semiconductor is highly purified and electrically becomes I-type ( One of the technical concepts is to make it an intrinsic semiconductor.

[0490] As a result, the less hydrogen there is, the better, and the fewer carriers there are in the oxide semiconductor. The less the better. When oxide semiconductors are used in insulated gate transistors, Rather than intentionally having carriers as oxide semiconductors, the carriers in oxide semiconductors are eliminated. As a semiconductor, it was given the meaning of a path through which carriers could pass. It is a purified type I (intrinsic) semiconductor.

[0491] As a result, by eliminating or reducing carriers in the oxide semiconductor, The technique according to one embodiment of the present invention is to reduce the off-state current of an edge-gate transistor. That is, hydrogen is 1×10 16 / cm 3 Below, career The density is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 The following is required: In terms of the technical concept of the present invention, it is ideal that the value is zero or close to zero.

[0492] As a result, the oxide semiconductor functions as a path, and the oxide semiconductor itself is a carrier. It is a highly purified type I (true) that has no or very little carbon, and the carrier is The degree of supply depends on the electron affinity χ of the oxide semiconductor, the ferroelectric constant χ, and the Fermi level, ideally the Fermi level coincides with the intrinsic Fermi level, and the source, drain The barrier height is determined by the work function of the electrode.

[0493] Therefore, the lower the off-state current, the better. Insulated gate transistor characteristics when voltage is applied: current per unit channel width is 100 aA / μm (i.e., the measured current is the channel width of the thin film transistor (unit (value obtained by dividing by μm) or less, preferably 10 aA / μm or less, and more preferably 1 aA / μm or less. One of its features is that it is less than / μm.

[0494] (Embodiment 14) In this embodiment, the following will be described about the measured values ​​of the off-state current using an evaluation element (also referred to as a TEG). Explained below.

[0495] In Figure 23, 200 thin film transistors with L / W = 3 μm / 50 μm are connected in parallel. The initial characteristics of the thin film transistor with a thickness of 3 μm / 10,000 μm are shown in Fig. 24. The dotted line in FIG. 24(B) shows the top view of the enlarged part of the figure. The enclosed area is a single-stage thin-film transistor with L / W=3μm / 50μm and Lov=1.5μm. In order to measure the initial characteristics of the thin film transistor, the substrate temperature was set to room temperature, and the source- The drain-to-drain voltage (hereinafter referred to as drain voltage or Vd) is set to 10 V, and the source-gate When the gate voltage (hereafter referred to as Vg) is changed from -20V to +20V The change characteristics of the source-drain current (hereinafter referred to as drain current or Id) of The Vg-Id characteristics were measured. In FIG. 23, Vg is shown in the range of -20 V to +5 V. is doing.

[0496] As shown in FIG. 23, a thin film transistor with a channel width W of 10000 μm has a Vd of 1 V and At 10V and 10V, the off-state current is 1×10 -13 [A] or less, and the measuring instrument (semiconductor The resolution of the parameter analyzer (Agilent 4156C; Agilent) 100fA) or less.

[0497] A method for manufacturing the thin film transistors used for the measurements will be described.

[0498] First, a silicon nitride layer is formed on a glass substrate as a base layer by a CVD method. A silicon oxynitride layer was formed on the silicon oxynitride layer by a sputtering method as a gate electrode layer. A tungsten layer was formed. The tungsten layer was then selectively etched to form a gate electrode. A polar layer was formed.

[0499] Next, a 100 nm thick silicon oxynitride film was formed on the gate electrode layer by CVD as a gate insulating layer. A base layer was formed.

[0500] Next, an In-Ga-Zn-O oxide semiconductor target was deposited on the gate insulating layer by sputtering. The thickness was 50 mm using a 50 mm thick film (molar ratio: In2O3:Ga2O3:ZnO=1:1:2). Here, the oxide semiconductor layer was selectively etched to form an island. A shaped oxide semiconductor layer was formed.

[0501] Next, the oxide semiconductor layer was subjected to a first etching treatment in a clean oven under a nitrogen atmosphere at 450° C. for 1 hour. Heat treatment was carried out.

[0502] Next, a titanium layer (thickness 150 The source electrode layer and the drain electrode layer were formed by a sputtering method. The channel length L of each thin film transistor is 3 μm and the channel width W is 50 μm. μm, and by connecting 200 pieces in parallel, L / W = 3 μm / 10,000 μm did.

[0503] Next, an oxide film was deposited by reactive sputtering as a protective insulating layer in contact with the oxide semiconductor layer. A silicon oxide layer was formed to a thickness of 300 nm. The silicon oxide layer, which was a protective layer, was selectively etched. Then, openings were formed on the gate electrode layer, the source electrode layer, and the drain electrode layer. Thereafter, a second heat treatment was carried out in a nitrogen atmosphere at 250° C. for 1 hour.

[0504] Then, before measuring the Vg-Id characteristics, the device was heated at 150° C. for 10 hours.

[0505] Through the above steps, a bottom gate thin film transistor was fabricated.

[0506] As shown in Figure 23, the thin film transistor is 1×10 -13 [A] is the level of the above work This is because the hydrogen concentration in the oxide semiconductor layer can be sufficiently reduced during the manufacturing process. The hydrogen concentration in the semiconductor layer is 1×10 16 atoms / cm 3 The following applies. In addition, oxides The hydrogen concentration in the semiconductor layer was measured by secondary ion mass spectrometry (SIMS). The data were obtained using Ion Mass Spectroscopy.

[0507] Although an example using an In-Ga-Zn-O-based oxide semiconductor has been shown, the present invention is not particularly limited and other oxide semiconductor materials, for example, In-Sn-Zn-O, Sn-Ga-Zn-O, Al -Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, In-Sn-O system, Sn-Zn-O, Al-Zn-O, In-O, Sn-O, Zn-O, etc. In addition, AlOx is mixed in an amount of 2.5 to 10 wt% as an oxide semiconductor material. In-Al-Zn-O system and In-Zn-O system containing 2.5 to 10 wt% SiOx can also be used.

[0508] The carrier density of the oxide semiconductor layer measured by a carrier measurement device was 1×10 14 / c m 3 Less than 1 x 10 12 / cm 3 That is, the carrier of the oxide semiconductor layer is The density can be made as close to zero as possible.

[0509] It is also possible to set the channel length L of the thin film transistor to 10 nm or more and 1000 nm or less. This allows for faster circuit operation and an extremely small off-state current, further reducing power consumption. It can also be electrified.

[0510] In addition, when the thin film transistor is in the off state, the oxide semiconductor layer can be regarded as an insulator, and the It is possible to carry out calculations.

[0511] Next, the temperature characteristics of the off-current of the thin film transistor manufactured in this embodiment were evaluated. The temperature characteristics are important for the environmental resistance of the final product that uses the thin-film transistor and for maintaining its performance. It is important to consider that the smaller the amount of change, the better. increases.

[0512] The temperature characteristics are measured using a thermostatic chamber at -30, 0, 25, 40, 60, 80, 100, and 120 The substrate on which the thin film transistor was formed was kept at a constant temperature of 100°C, and the drain voltage was The gate voltage was changed from -20V to +20V at 6V to obtain the Vg-Id characteristics.

[0513] Figure 25(A) shows the Vg-Id characteristics measured at each of the above temperatures, overlaid. The area of ​​the off-state current surrounded by the dotted line is shown enlarged in FIG. 25(B). The curve on the right side indicated by the mark is obtained at -30℃, and the curve on the left side is obtained at 120℃. The curves shown are located between these two. The on-current has almost no temperature dependence. As can be seen in the enlarged view of Figure 25(B), the gate current is At all temperatures, except for -12 [A] or below, There is no temperature dependence. That is, even at a high temperature of 120°C, the off-state current is 1×10 -12 [A] or less is maintained, and the channel width W is 10,000 μm. It can be seen that the off-state current is very small.

[0514] As described above, thin film transistors using highly purified oxide semiconductors (purified OS) The temperature dependence of the off-state current of a transistor is almost nonexistent. This is shown in the band diagram of Figure 19. As shown in the figure, by purifying the oxide semiconductor, the conductivity type becomes as close as possible to the intrinsic type. Since the Fermi level is located in the center of the forbidden band, it can be said that the temperature dependence is eliminated. In addition, this is because the band gap of the oxide semiconductor is 3 eV or more and thermally excited carriers are extremely Also, the source and drain regions are in a degenerate state. This is the reason why temperature dependency does not appear. Most of the carriers are injected into the oxide semiconductor from the source region. The lack of temperature dependence of rear density explains the above characteristics (no temperature dependence of off-current). It is possible.

[0515] A display device or the like is manufactured using a thin film transistor with an extremely small off-state current. In this case, the off-state current is small and there is almost no leakage, so the display data can be retained for a long time. It can be made easier. [Example]

[0516] In this example, the liquid crystal display device shown in FIG. 1 described in the above embodiment was actually manufactured, and a still image was displayed. The results of evaluation of the image signal retention characteristics during display will be described below.

[0517] First, regarding the top view layout diagram of a plurality of pixels provided in the pixel section, FIG. 27 shows a photograph of a device such as a film transistor taken from the back side.

[0518] From the pixel photograph shown in FIG. 27, rectangular pixels are provided, and gate lines 2701 and It can be seen that the signal lines 2702 are arranged perpendicular to each other. It can be seen that a capacitor line 2703 is provided at the position. In the area where the line 2703 and the signal line 2702 overlap, a separate insulator is provided to reduce parasitic capacitance. The liquid crystal display device shown in this example has a film, which is visible as a bump in FIG. This shows a transmissive liquid crystal display device, and the R (red) color filter 2704 R, G (green) color filter 2704G, B (blue) color filter 2704B In addition, in FIG. 27, a light-transmitting layer is provided in the area controlled by the gate line 2701. The semiconductor layer is an In-Ga-Zn-O based non-single crystal film, which is an oxide semiconductor. This forms a thin film transistor.

[0519] 28 shows the time series of each pixel shown in FIG. 27 when a still image is displayed according to the embodiment. 1 shows a graph of the change in brightness over time.

[0520] As can be seen from FIG. 28, in the case of the top surface layout of the pixel in FIG. 27, the image signal retention period Therefore, when displaying a still image, the same image signal is periodically A constant brightness can be maintained by supplying the light (refresh in the figure). As a result, the time during which voltage is applied to the transistors that make up the drive circuit section is significantly reduced. Since the deterioration of the drive circuit over time can be significantly delayed, This has the effect of improving reliability. [Example]

[0521] In this embodiment, the liquid crystal display device of FIG. 1 described in the above embodiment is configured differently from that of the first embodiment. The results of evaluation of the image signal retention characteristics when displaying a still image were as follows: explain.

[0522] First, regarding the top view layout diagram of a plurality of pixels provided in the pixel section, FIG. 29 shows a photograph of a device such as a film transistor taken from the back side.

[0523] From the pixel photograph shown in FIG. 29, rectangular pixels are provided, and gate lines 2901 and It can be seen that the signal line 2902 is arranged perpendicular to the gate line 2901. It can be seen that a capacitor line 2903 is provided at the position. In the area where the line 2903 and the signal line 2902 overlap, a separate insulator is provided to reduce parasitic capacitance. The liquid crystal display device shown in this example has a film, which is visible as a bump in FIG. The following shows a reflective LCD display device, which is superimposed on an R (red) color filter. Reflective electrodes 2904R and 2904G (B) are superimposed on the color filter of the reflective electrodes 2904R and 2904G (G) (green). A reflective electrode 2904B overlapping the (blue) color filter can be seen. In the region controlled by the gate line 2901, an oxide semiconductor is formed as a light-transmitting semiconductor layer. The substrate is an In-Ga-Zn-O non-single crystal film, which forms a thin film transistor. is doing.

[0524] 30 shows the time course of each pixel shown in FIG. 29 when a still image is displayed according to the above embodiment. 10 shows a graph of the change in brightness as a function of the temperature.

[0525] As can be seen from FIG. 30, in the case of the top surface layout of the pixel in FIG. 29, the image signal retention period As in the first embodiment, it can be seen that the time can be set to about 1 minute. The same image signal is supplied periodically (refresh in the figure) to maintain a constant brightness. As a result, when a voltage is applied to the transistors that make up the drive circuit section, The time required for the drive circuit to be degraded over time can be significantly reduced. Therefore, the reliability of the liquid crystal display device is improved. [Example]

[0526] In this example, the liquid crystal display device of FIG. 1 described in the above embodiment is used in Examples 1 and 2. We actually produced a different configuration and evaluated the image signal retention characteristics when displaying a still image. The results will be explained.

[0527] First, regarding the top view layout diagram of a plurality of pixels provided in the pixel section, FIG. 31 shows a photograph of a device such as a film transistor taken from the back side.

[0528] From the pixel photograph shown in FIG. 31, rectangular pixels are provided, and the gate line 3101 and It can be seen that the signal lines 3102 are arranged perpendicular to each other. It can be seen that the capacitance line 3103 is provided at the position. In the area where the line 3103 and the signal line 3102 overlap, a separate insulator is provided to reduce parasitic capacitance. The liquid crystal display device shown in this example has a film, which is visible as a bump in FIG. The following shows a liquid crystal display device using a polymer dispersed liquid crystal, and the reflective electrode 3104 In addition, in FIG. 31, the region controlled by the gate line 3101 is provided with a transparent property. As a semiconductor layer, an In-Ga-Zn-O-based non-single crystal film, which is an oxide semiconductor, is provided. This forms a thin film transistor.

[0529] 32 shows the time course of each pixel shown in FIG. 31 when a still image is displayed according to the above embodiment. 10 shows a graph of the change in brightness as a function of the temperature.

[0530] As can be seen from Figure 32, in the case of the top surface layout of the pixel in Figure 31, the polymer dispersed liquid crystal Since the image signal is retained for a longer period than in the first and second embodiments, Therefore, when displaying a still image, the same image signal is periodically supplied. As a result, the transistors that make up the drive circuit section are supplied with electricity. This significantly reduces the time that voltage is applied, significantly slowing down the deterioration of the drive circuit over time. Therefore, the reliability of the liquid crystal display device can be improved. [Example]

[0531] In this embodiment, the liquid crystal display device of FIG. 1 described in the above embodiment is used in Examples 1 to 3. The results of actually fabricating a different configuration from that of the above embodiment will be described. An example different from the top view layout diagrams of pixels described in 1 to 3 will be described. 1 shows a photograph of elements such as thin film transistors formed on a substrate, taken from the back side.

[0532] From the pixel photograph shown in FIG. 33, rectangular pixels are provided, and gate lines 3301 and It can be seen that the signal lines 3302 are arranged perpendicular to each other. Unlike the previously described pixel photograph, this shows the top view layout with the capacitance lines omitted. In the liquid crystal display device shown in the embodiment, a transmissive liquid crystal display device is shown, and the pixel electrode 33 33, the area controlled by the gate line 3301 is provided with a transparent As a semiconductor layer having the above structure, an In-Ga-Zn-O-based non-single crystal film, which is an oxide semiconductor, is provided. These are used to form thin film transistors. [Example]

[0533] In this embodiment, an example of a method for driving the liquid crystal display device shown in FIG. 1 described in the above embodiment will be described. Specifically, a driver circuit (this In this case, the driving circuit shown in Figs. 2 and 3 displays still images and moving images. or the operation of rewriting the voltage applied to the liquid crystal element (hereinafter referred to as refresh operation) The procedure for supplying or stopping the potential of each wiring to the driver circuit section during this period is shown in Figure 3. 34 is a circuit diagram for supplying a high power supply potential (VDD) to the shift register. line, wiring that supplies low power supply potential (VSS), wiring that supplies start pulse (SP), and wiring for supplying the first clock signal (CK1) to the fourth clock signal (CK4). 10 is a diagram showing changes in potential of a supply wiring before and after a period T1. FIG.

[0534] In the liquid crystal display device of this embodiment, a still image is displayed without constantly operating the drive circuit unit. Therefore, as shown in FIG. 34, a high power supply potential (VD D), the first clock signal (CK1) to the fourth clock signal (CK4), and the start There are periods when a control signal such as a pulse is supplied, and periods when no control signal is supplied. Note that the period T1 shown in FIG. 34 is the period during which the control signal is supplied, that is, the period during which the moving image is displayed. The period T2 shown in FIG. 34 corresponds to the period during which the control signal This corresponds to a period during which no signal is supplied, that is, a period during which a still image is displayed.

[0535] In FIG. 34, the period during which the high power supply potential (VDD) is supplied is not limited to the period T1. 34, the first clock During the period in which the signal (CK1) to the fourth clock signal (CK4) are supplied, the high power supply potential (V DD) is supplied until the high power supply potential (VDD) is stopped. There are.

[0536] As shown in FIG. 34, the first clock signal (CK1) to the fourth clock signal (CK 4) Before the period T1 begins, the signal is set to a high potential and then to a constant cycle of the clock signal. After the period T1 is over, the clock signal is set to a low potential and then the clock signal starts oscillating. It is sufficient to configure the process to end.

[0537] As described above, in the liquid crystal display device of this embodiment, a high power supply voltage is applied to the shift register during the period T2. a first clock signal (CK1) to a fourth clock signal (CK4), and The supply of control signals such as a start pulse is stopped. During this period, In this case, the signal output from the shift register is controlled by controlling the conduction or non-conduction of each transistor. Therefore, the power consumption and the pulse signal input to the shift register are reduced. The power consumed in the pixel unit driven by the shift register can be reduced. It becomes possible.

[0538] Please note that the above refresh operation may cause deterioration in the quality of the displayed still image. In the liquid crystal display device of this embodiment, the liquid crystal element of each pixel is printed with a liquid crystal. The transistor having the oxide semiconductor described above is used as a switching element for controlling the voltage applied. This allows the off-state current to be reduced dramatically, This makes it possible to reduce fluctuations in the voltage applied to the liquid crystal element of the pixel. This prevents deterioration of image quality even if the shift register operation is stopped for a long period of time. For example, even if the period is 3 minutes, the displayed still image can be reduced. It is possible to maintain the quality of the image. For example, an LCD that is rewritten 60 times per second When comparing a display device with an LCD display device that refreshes once every three minutes, the It is possible to reduce power consumption to 10,000.

[0539] Note that the above-mentioned stopping of the high power supply potential (VDD) means stopping the low power supply potential (V SS), and the high power supply potential (VDD) is stopped when the high power supply potential The potential of the wiring to be supplied may be set to a floating state.

[0540] In addition, the potential of the wiring to which the high power supply potential (VDD) is supplied is increased, that is, in the period T1 When increasing the power supply potential from a low power supply potential (VSS) to a high power supply potential (VDD) before It is preferable to control the potential change so that it is gentle. If the change in potential is steep, it will become noise and an incorrect pulse will be output from the shift register. The shift register may be a shift register included in the gate line driving circuit. In some cases, the illegal pulse is a signal that turns on a transistor. The voltage applied to the liquid crystal element may change due to the pulse, which may cause the image to change. In consideration of the above, in FIG. 34, the signal level at which the high power supply potential (VDD) is generated is The figure shows an example in which the rise is gentler than the fall. In the LCD device, when a still image is displayed in the pixel section, The supply of the high power supply potential (VDD) is stopped and resupplied as needed. If a change in the potential of the wiring that supplies the high power supply potential (VDD) affects the pixel section as noise, In this case, the noise directly leads to deterioration of the displayed image. In this case, the change in the potential of the wiring (especially the increase in the potential) must be prevented from entering the pixel area as noise. It is important to control this. [Explanation of symbols]

[0541] 1000 lcd display device 1001 Display panel 1002 Signal generation circuit 1003 Memory circuit 1004 Comparison circuit 1005 selection circuit 1006 Display control circuit 1007 Drive circuit section 1008 Pixel section 1010 frame memory 1009A Gate line driver circuit 1009B Signal line driver circuit

Claims

1. an oxide semiconductor layer having a channel formation region; First to fifth conductive layers, the oxide semiconductor layer has a region disposed above the first conductive layer, the second conductive layer has a region disposed above the oxide semiconductor layer, the third conductive layer has a region disposed above the oxide semiconductor layer, the fourth conductive layer has a region disposed above the oxide semiconductor layer via an insulating layer; the fifth conductive layer has a region disposed above the insulating layer; the second conductive layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the first conductive layer, the third conductive layer has a region in contact with the fifth conductive layer, the fourth conductive layer functions as a gate electrode, In a cross-sectional view, the oxide semiconductor layer has a region disposed between the first conductive layer and the third conductive layer, the oxide semiconductor layer overlaps with a periphery of the first conductive layer in a plan view; In a plan view, the fourth conductive layer has an opening, the oxide semiconductor layer overlaps with the opening, the channel formation region overlapping with the fourth conductive layer is surrounded by an outer edge of the first conductive layer in a plan view; Display device.

2. an oxide semiconductor layer having a channel formation region; First to fifth conductive layers, the oxide semiconductor layer has a region disposed above the first conductive layer, the second conductive layer has a region disposed above the oxide semiconductor layer, the third conductive layer has a region disposed above the oxide semiconductor layer, the fourth conductive layer has a region disposed above the oxide semiconductor layer via an insulating layer; the fifth conductive layer has a region disposed above the insulating layer; the second conductive layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the first conductive layer, the third conductive layer has a region in contact with the fifth conductive layer, an overlapping area between the oxide semiconductor layer and the first conductive layer is larger than an overlapping area between the oxide semiconductor layer and the second conductive layer; the fourth conductive layer functions as a gate electrode, In a cross-sectional view, the oxide semiconductor layer has a region disposed between the first conductive layer and the third conductive layer, the oxide semiconductor layer overlaps with a periphery of the first conductive layer in a plan view; In a plan view, the fourth conductive layer has an opening, the oxide semiconductor layer overlaps with the opening, the channel formation region overlapping with the fourth conductive layer is surrounded by an outer edge of the first conductive layer in a plan view; Display device.

3. an oxide semiconductor layer having a channel formation region; First to fifth conductive layers, the oxide semiconductor layer has a region disposed above the first conductive layer, the second conductive layer has a region disposed above the oxide semiconductor layer, the third conductive layer has a region disposed above the oxide semiconductor layer, the fourth conductive layer has a region disposed above the oxide semiconductor layer via an insulating layer; the fifth conductive layer has a region disposed above the insulating layer; the second conductive layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the first conductive layer, the third conductive layer has a region in contact with the fifth conductive layer, the fourth conductive layer functions as a gate electrode, In a cross-sectional view, the oxide semiconductor layer has a region disposed between the first conductive layer and the third conductive layer, the oxide semiconductor layer overlaps with a periphery of the first conductive layer in a plan view; In a plan view, the first conductive layer and the second conductive layer are spaced apart from each other, In a plan view, the fourth conductive layer has an opening, the oxide semiconductor layer overlaps with the opening, the channel formation region overlapping with the fourth conductive layer is surrounded by an outer edge of the first conductive layer in a plan view; Display device.

4. an oxide semiconductor layer having a channel formation region; First to fifth conductive layers, the oxide semiconductor layer has a region disposed above the first conductive layer, the second conductive layer has a region disposed above the oxide semiconductor layer, the third conductive layer has a region disposed above the oxide semiconductor layer, the fourth conductive layer has a region disposed above the oxide semiconductor layer via an insulating layer; the fifth conductive layer has a region disposed above the insulating layer; the second conductive layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the first conductive layer, the third conductive layer has a region in contact with the fifth conductive layer, an overlapping area between the oxide semiconductor layer and the first conductive layer is larger than an overlapping area between the oxide semiconductor layer and the second conductive layer; the fourth conductive layer functions as a gate electrode, In a cross-sectional view, the oxide semiconductor layer has a region disposed between the first conductive layer and the third conductive layer, the oxide semiconductor layer overlaps with a periphery of the first conductive layer in a plan view; In a plan view, the first conductive layer and the second conductive layer are spaced apart from each other, In a plan view, the fourth conductive layer has an opening, the oxide semiconductor layer overlaps with the opening, the channel formation region overlapping with the fourth conductive layer is surrounded by an outer edge of the first conductive layer in a plan view; Display device.

5. In any one of claims 1 to 4, the oxide semiconductor layer is an In—O-based oxide semiconductor layer; Display device.

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