Pixel electrode, array substrate, and display unit

Abstract

To provide a pixel electrode, an array substrate, and a display unit.SOLUTION: A pixel electrode 10 includes a first edge conducting part 101 and a second edge conducting part 102 arranged at an interval in a first direction Y, and a main conducting part including at least one first pair of sub-conducting parts and at least one second pair of sub-conducting parts. The first pair of sub-conducting parts has a first gap S1 with a first connection strip 103, and an end of the first gap S1 separated from the first connection strip 103 is an open end. The second pair of sub-conducting parts includes a second connection strip 105 located on a side of the first gap S1 separated from the first connection strip 103 and connected to the first pair of sub-conducting parts. The second pair of sub-conducting parts has a second gap S2, and an end of the second gap S2 separated from the second connection strip 105 is an open end. The sum of the lengths of the first connection strips 103 in the first pairs of sub-conducting parts is smaller than the sum of the lengths of the second connection strips 105 in the second pairs of sub-conducting parts.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the field of display technology, and in particular to a pixel electrode, an array substrate and a display device. [Background technology]

[0002] With the continuous development of LCD panels, products with high resolution are continuously developed. However, for pixels with high resolution such as 8K, the pixel pitch (i.e., dot pitch) is small and the storage capacitance (i.e., Cst) is small, so the pixel voltage is easily pulled by the data voltage, which easily causes asymmetric pulling on both sides of the pixel, which makes the grayscale V-type crosstalk (i.e., V-Crosstalk) more serious and affects the display effect. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION It is an object of the present invention to provide a pixel electrode, an array substrate and a display device that overcome, at least to some extent, one or more of the problems caused by the limitations and deficiencies of the related art discussed above. [Means for solving the problem]

[0004] According to a first aspect of the present invention, there is provided a pixel electrode, the pixel electrode including: first edge conductive portions and second edge conductive portions arranged at intervals in a first direction; and a main conductive portion, at least a portion of which is located between the first edge conductive portion and the second edge conductive portion, the main conductive portion being connected to the first edge conductive portion and the second edge conductive portion, respectively; the main conductive portion including at least one first set of sub-conductive portions and at least one second set of sub-conductive portions, the first set of sub-conductive portions and the second set of sub-conductive portions being arranged alternately in the first direction.

[0005] Here, the first set of sub-conductive portions includes a first connecting strip, the first connecting strip extending in the first direction and having a first surface and a second surface opposing each other in a second direction, the first set of sub-conductive portions has a first gap located on the side of the first surface away from the second surface, and the end of the first gap away from the first connecting strip is an open end.

[0006] Here, the second set of sub-conductive portions includes a second connecting strip located on the side of the first gap away from the first connecting strip and connected to the first set of sub-conductive portions, the second connecting strip extending in the first direction and having a third surface and a fourth surface opposing each other in the second direction, the third surface being located on the side of the fourth surface closer to the first surface, and the second set of sub-conductive portions has a second gap located on the side of the third surface away from the fourth surface, and the end of the second gap away from the second connecting strip is an open end.

[0007] Here, in the second direction, the pixel electrode is arranged so that its first connecting strip is closer to the transistor than the second connecting strip, and the end of the first edge conductive portion or the second edge conductive portion away from the second connecting strip is arranged so as to be connected to the transistor.

[0008] Here, the sum of the lengths of the first connecting strips in the at least one first set of sub-conductive portions is smaller than the sum of the lengths of the second connecting strips in the at least one second set of sub-conductive portions.

[0009] Here, the first direction intersects with the second direction.

[0010] In one exemplary embodiment of the present invention, The first set of sub-conductive portions further includes a plurality of first electrode strips arranged at intervals in the first direction, the plurality of first electrode strips being located at a position away from the second surface of the first surface and connected to the first surface, with the first gap between two adjacent first electrode strips.

[0011] The second set of sub-conductive portions further includes a plurality of second electrode strips arranged at intervals in the first direction, the plurality of second electrode strips being located at a position away from the fourth surface of the third surface and connected to the third surface, with the second gap between two adjacent second electrode strips.

[0012] Here, the third surface of the second connecting strip is connected to the end of the first electrode strip closest to the second set of sub-conductive portions, the end being remote from the first connecting strip.

[0013] In an exemplary embodiment of the present invention, the length of the first connecting strip is less than the length of the second connecting strip.

[0014] In an exemplary embodiment of the present invention, the main conductive portion includes one of the first set of sub-conductive portions and one of the second set of sub-conductive portions; The first edge conductive portion is located on a side of the plurality of first electrode strips away from the second set of sub-conductive portions and away from the second surface of the first surface of the first connecting strip, the first edge conductive portion is connected to the first surface and has a third gap with the first electrode strip adjacent thereto, and the end of the third gap away from the first connecting strip is an open end.

[0015] The second edge conductive portion is located on a side of the plurality of second electrode strips away from the first set of sub-conductive portions and at a position away from the fourth surface of the third surface of the second connecting strip, the second edge conductive portion is connected to the third surface and has a fourth gap with the second electrode strip adjacent thereto, and the end of the fourth gap away from the second connecting strip is an open end.

[0016] In one exemplary embodiment of the present invention, the extension directions of the first electrode strip, the first gap, and the third gap are the same and intersect with the first direction and the second direction, and the extension directions of the second electrode strip, the second gap, and the fourth gap are the same and intersect with the first direction and the second direction.

[0017] In an exemplary embodiment of the present invention, the widths of the first electrode strip, the second electrode strip, the first gap, the second gap, the third gap and the fourth gap are equal.

[0018] In an exemplary embodiment of the present invention, the first electrode strips and the second electrode strips extend in the same direction, and there is the second gap between the first electrode strips and the second electrode strips adjacent to each other.

[0019] In an exemplary embodiment of the present invention, the extending direction of the first electrode strips and the extending direction of the second electrode strips are arranged in a mirror image relationship with respect to the second direction.

[0020] In one exemplary embodiment of the present invention, the second set of sub-conductive portions further includes an adjustment portion located on a side of the plurality of second electrode strips closer to the first set of sub-conductive portions and away from the fourth surface of the third surface of the second connecting strip, and the adjustment portion is connected to the third surface of the second connecting strip.

[0021] Here, a fifth gap is formed between the adjustment portion and the first electrode strip adjacent thereto, and a sixth gap is formed between the adjustment portion and the second electrode strip adjacent thereto.

[0022] The ends of the fifth gap and the sixth gap that are remote from the second connecting strip are both open ends.

[0023] The fifth gap and the first gap extend in the same direction and have the same width, and the sixth gap and the second gap extend in the same direction and have the same width.

[0024] In one exemplary embodiment of the present invention, the adjustment portion includes a first adjustment strip and a second adjustment strip, and the fifth gap is formed between the first adjustment strip and the first electrode strip, and the sixth gap is formed between the second adjustment strip and the second electrode strip.

[0025] Here, the first adjusting strips and the first electrode strips extend in the same direction and have the same width, and the second adjusting strips and the second electrode strips extend in the same direction and have the same width.

[0026] One end of the first adjusting strip and the second adjusting strip in the extension direction is connected to the third surface of the second connecting strip, and the other end is connected to each other.

[0027] In one exemplary embodiment of the present invention, the ratio of the sum of the lengths of the first connecting strips in the at least one first set of sub-conductive portions to the sum of the lengths of the second connecting strips in the at least one second set of sub-conductive portions is 0.1 to 0.9.

[0028] According to a second aspect of the present invention, there is provided an array substrate, the array substrate including a first substrate and sub-pixels located on the first substrate and arranged in an array along a first direction and a second direction, wherein the sub-pixels include a transistor and a pixel electrode according to any one of the above claims, and an end of the first edge conductive portion or the second edge conductive portion of the pixel electrode away from the second connecting strip is connected to the transistor.

[0029] In the second direction, the transistor is arranged closer to the first connecting strip of the pixel electrode than to the second connecting strip.

[0030] In an exemplary embodiment of the present invention, an orthogonal projection of the transistor on the first substrate and an orthogonal projection of a first connecting strip of the pixel electrode on the first substrate are arranged opposite each other in the first direction.

[0031] In one exemplary embodiment of the present invention, in two of the pixel electrodes adjacent to each other in the second direction, The end of one of the first edge conductive portions remote from the second connecting strip is connected to the transistor and is closer to the transistor connected thereto than the second edge conductive portion.

[0032] The other end of the second edge conductive portion remote from the second connecting strip is connected to the transistor and is closer to the transistor connected thereto than the first edge conductive portion.

[0033] In one exemplary embodiment of the present invention, the array substrate further includes a plurality of data lines formed on the first substrate, the data lines extending in the first direction, and the data lines and the sub-pixels arranged alternately in the second direction.

[0034] Here, in the pixel electrode of the subpixel, the distance between the first connecting strip and the data line closest to it is a first pitch, and the distance between the second connecting strip and the data line closest to it is a second pitch, and the first pitch and the second pitch are equal.

[0035] In an exemplary embodiment of the present invention, each of the data lines is connected to the transistors of the sub-pixels adjacent to it and located on the same side in the second direction.

[0036] Here, the first and second poles of the transistor are provided in the same layer as the data line and are located on the side of the pixel electrode closer to the first substrate, the first pole of the transistor is connected to the data line, and the second pole of the transistor is connected to the second edge conductive portion or the first edge conductive portion of the pixel electrode via a relay via hole.

[0037] In one exemplary embodiment of the present invention, the first pole and the second pole of the transistor are arranged at an interval in the first direction, and the distance between the first pole and the second pole in the first direction is a third pitch.

[0038] Here, the ratio of the sum of the lengths of the first connecting strips in the at least one first set of sub-conductive portions to the third pitch is 2-20.

[0039] In an exemplary embodiment of the present invention, the sub-pixel further includes a common electrode, which is located on a side of the pixel electrode closer to the first substrate and is insulated from the pixel electrode.

[0040] Furthermore, the orthogonal projection of the common electrode on the first substrate overlaps with the orthogonal projection of the pixel electrode on the first substrate, and does not overlap with the orthogonal projection of the data line on the first substrate.

[0041] In one exemplary embodiment of the present invention, the array substrate further includes a plurality of scanning lines and a plurality of common lines formed on the first substrate and extending in the second direction, the scanning lines and the common lines are alternately arranged in the first direction, and the orthogonal projections of the scanning lines on the first substrate do not overlap with the orthogonal projections of the common lines on the first substrate.

[0042] Here, the scanning lines and the common lines are arranged in the same layer, and the scanning lines and the common lines are located on the side of the data lines closer to the first substrate and are arranged to be insulated from the data lines.

[0043] Here, one side of the sub-pixel in the first direction is adjacent to the common line, and the other side is adjacent to the scanning line.

[0044] Here, each of the scanning lines is connected to the gates of the transistors of the sub-pixels located on the same side in the first direction and adjacent to it.

[0045] Here, each of the common lines is connected to the common electrodes of the sub-pixels located on the same side in the first direction and adjacent to it.

[0046] In one exemplary embodiment of the present invention, a portion of the scan line constitutes the gate of the transistor, and the common electrode contacts the common line.

[0047] According to a third aspect of the present invention, there is provided a display device, the display device including the array substrate according to any one of the above aspects, and an opposing substrate provided corresponding to the array substrate.

[0048] Other features and advantages of the invention will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0049] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and are not intended to limit the present invention.

[0050] The following drawings are incorporated into the specification and constitute a part of this specification, illustrate embodiments according to the present invention, and are intended to explain the principles of the present invention together with the specification. Note that the drawings in the following description are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings from these drawings without any creative effort. [Brief explanation of the drawings]

[0051] [Figure 1]1 is a structural schematic diagram showing a pixel electrode according to an embodiment of the present invention; [Figure 2] FIG. 10 is a structural schematic diagram showing a pixel electrode according to another embodiment of the present invention. [Figure 3] FIG. 1 is a structural schematic diagram showing a pixel electrode according to a related art. [Figure 4] 1 is a structural schematic diagram showing a minimum repeating unit of an array substrate according to an embodiment of the present invention; [Figure 5] FIG. 10 is a structural schematic diagram showing the minimum repeating unit of an array substrate according to another embodiment of the present invention. [Figure 6] 1 is a schematic diagram showing a cross-sectional structure of an array substrate according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0052] The technical solution of the present invention will be described in more detail below by way of examples with reference to the accompanying drawings. In this specification, the same or similar symbols in the drawings indicate the same or similar structures. The following describes the embodiments of the present invention with reference to the accompanying drawings, which are intended to interpret the overall concept of the present invention and are not intended to limit the present invention.

[0053] Also, in the following detailed description, for purposes of ease of understanding, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present invention. However, it will be apparent that one or more embodiments may be practiced without these specific details.

[0054] The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements / components / etc. The terms "comprise" and "comprise" are used in an open-ended manner and mean to include further elements / components / etc. other than the listed elements / components.

[0055] It should be noted that the terms "first," "second," etc. are used herein to describe each region, layer, and / or portion, and these regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one region, layer, and / or portion from another.

[0056] 1 and 2, one embodiment of the present invention provides a pixel electrode 10, which can be applied to, but is not limited to, a liquid crystal display (LCD) product. Specifically, the pixel electrode 10 includes a first edge conductive portion 101 and a second edge conductive portion 102 spaced apart in a first direction Y, and a main conductive portion at least a portion of which is located between the first edge conductive portion 101 and the second edge conductive portion 102. The main conductive portion is connected to the first edge conductive portion 101 and the second edge conductive portion 102, respectively, and the main conductive portion may include at least one first set of sub-conductive portions and at least one second set of sub-conductive portions, which are alternately arranged in the first direction Y.

[0057] 1 and 2, the first set of sub-conductive portions may include a first connection strip 103 and a plurality of first electrode strips 104 spaced apart in a first direction Y. The first connection strip 103 extends in the first direction Y (i.e., the length direction of the first connection strip 103 is the first direction Y). The first connection strip 103 may have a first surface 103a and a second surface 103b that face each other in a second direction X. The first direction Y may intersect with the second direction X. Preferably, the first direction Y may be perpendicular to the second direction X. The plurality of first electrode strips 104 may be located at a distance from the second surface 103b of the first surface 103a and connected to the first surface 103a. Here, a gap is formed between two adjacent first electrode strips 104, and this gap may be defined as a first gap S1, and the ends of these two adjacent first electrode strips 104 remote from the first connecting strip 103 are separated from each other, that is, the end of the first gap S1 remote from the first connecting strip 103 is open. Here, for convenience of explanation, the end of the first gap S1 remote from the first connecting strip 103 can be defined as the open end.

[0058] 1 and 2, the second set of sub-conductive portions includes a second connecting strip 105 and a plurality of second electrode strips 106 spaced apart in the first direction Y, where the second connecting strip 105 extends in the first direction Y (i.e., the length direction of the second connecting strip 105 is the first direction Y). The second connecting strip 105 may have a third surface 105a and a fourth surface 105b opposing each other in the second direction X, where the third surface 105a of the second connecting strip 105 may be located on a side of the fourth surface 105b closer to the first surface 103a of the first connecting strip 103. The third surface 105a of the second connecting strip 105 may be connected to a first electrode strip 104 closer to the second set of sub-conductive portions, specifically, to an end of the first electrode strip 104 farther from the first connecting strip 103. The first electrode strip 104 closest to the second set of sub-conductive portions referred to here refers to the first electrode strip 104 closest to the second set of sub-conductive portions in the first set of sub-conductive portions. The second electrode strips 106 are located at a position away from the fourth surface 105b of the third surface 105a of the second connecting strip 105 and are connected to the third surface 105a of the second connecting strip 105. A gap is formed between two adjacent second electrode strips 106, and this gap may be defined as a second gap S2. The ends of the two adjacent second electrode strips 106 away from the second connecting strip 105 are separated from each other. That is, the ends of the second gap S2 away from the second connecting strip 105 are open. For ease of explanation, the ends of the second gap S2 away from the second connecting strip 105 may be defined as open ends.

[0059] In an embodiment of the present invention, the pixel electrode 10 may be connected to the transistor 20 (as shown in FIGS. 4 and 5) via the above-mentioned first edge conductive portion 101 or second edge conductive portion 102. Specifically, the end of the first edge conductive portion 101 or the second edge conductive portion 102 remote from the second connecting strip 105 may be arranged to be connected to the transistor 20, and the pixel electrode 10 is arranged in the second direction X such that its first connecting strip 103 is closer to the transistor 20 than the second connecting strip 105. It should be understood that the transistor 20 may be connected to the data line 40 adjacent thereto (as shown in FIGS. 4 and 5).

[0060] As can be seen from the above, in the embodiment of the present invention, the first gap S1 and the second gap S2 of the pixel electrode 10 are not completely closed on all four sides, i.e., the end of the first gap S1 close to the second connecting strip 105 is an open end, and the end of the second gap S2 close to the first connecting strip 103 is an open end. When the pixel electrode 10 according to the embodiment of the present invention is applied to a display product, the open ends of the first gap S1 and the open ends of the second gap S2 may be adjacent to the data lines 40 on both sides of the pixel electrode 10 (as shown in FIGS. 4 and 5 ). When this design is applied to a liquid crystal display product, compared to the pixel electrode 1 in the related art shown in FIG. 3 in which the gap 1 a is completely closed on all four sides, this design can effectively reduce the extent of the dark field region of the liquid crystal display product, thereby improving the transmittance of the liquid crystal display product.

[0061] 4 and 5, a lateral capacitance exists between the first pole 201 and the second pole 202 of the transistor 20, and in the second direction X, the transistor 20 is closer to the first connecting strip 103 than to the second connecting strip 105. That is, when the display product is driven, the side of the pixel electrode 10 where the first connecting strip 103 is located contains a lateral capacitance generated between the first pole 201 and the second pole 202 of the transistor 20, compared to the side where the second connecting strip 105 is located (the right side of the pixel electrode as shown in FIGS. 4 and 5). That is, the capacitance generated on the left side of the pixel electrode 10 as shown in Figures 4 and 5 may include the lateral capacitance generated between the first connecting strip 103 and the data line 40 and the lateral capacitance generated between the first pole 201 and the second pole 202 of the transistor 20, and the capacitance generated on the right side may include the lateral capacitance generated between the second connecting strip 105 and the data line 40. Therefore, it can be seen that the left side of the pixel electrode 10 as shown in Figures 4 and 5 further includes the lateral capacitance generated between the first pole 201 and the second pole 202 of the transistor 20 compared to the right side.

[0062] The sum of the lengths of the first connecting strips 103 of each first set of sub-conductive portions in the pixel electrode 10 is designed to be equal to or greater than the sum of the lengths of the second connecting strips 105 of each second set of sub-conductive portions. That is, the sum of the capacitances generated between each first connecting strip 103 of the pixel electrode 10 and its adjacent data line 40 is equal to or greater than the sum of the capacitances generated between each second connecting strip 105 and its adjacent data line 40. Compared with the side where the second connecting strip 105 is located, the side where the first connecting strip 103 of the pixel electrode 10 is located further includes a lateral capacitance generated between the first pole 201 and the second pole 202 of the transistor 20. Therefore, the total capacitance on the side where the first connecting strip 103 of the pixel electrode 10 is located is greater than the total capacitance on the side where the second connecting strip 105 is located. As a result, both sides of the pixel electrode 10 are pulled differently by the data voltage, resulting in a more severe grayscale V-shaped crosstalk phenomenon in display products. Based on this, in order to improve the grayscale V-shaped crosstalk phenomenon of the product, in an embodiment of the present invention, the sum of the lengths of the first connecting strips 103 of each first set of sub-conductive portions in the pixel electrode 10 can be designed to be smaller than the sum of the lengths of the second connecting strips 105 of each second set of sub-conductive portions, where the length referred to here refers to the length in the extension direction.

[0063] Alternatively, the ratio of the sum of the lengths of the first connecting strips 103 of each first set of sub-conductive portions in the pixel electrode 10 to the sum of the lengths of the second connecting strips 105 of each second set of sub-conductive portions may be 0.1 to 0.9, such as, but not limited to, 0.1, 0.3, 0.5, 0.7, 0.9, etc. For example, the range of the sum of the lengths of the first connecting strips 103 of each first set of sub-conductive portions in the pixel electrode 10 may be 30 μm to 90 μm, such as, but not limited to, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, etc. The sum of the lengths of the second connecting strips 105 of each first set of sub-conductive portions in the pixel electrode 10 may be in the range of 60 μm to 120 μm, for example, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 110 μm, etc., but is not limited thereto.

[0064] In addition, the ratio of the sum of the lengths of the first connecting strips 103 of each first set of sub-conductive portions in the pixel electrode 10 to the sum of the lengths of the second connecting strips 105 of each second set of sub-conductive portions in the pixel electrode 10 in the embodiment of the present invention, the sum of the lengths of the first connecting strips 103 of each first set of sub-conductive portions in the pixel electrode 10, and the sum of the lengths of the second connecting strips 105 of each first set of sub-conductive portions in the pixel electrode 10 are not limited to the above-mentioned numerical ranges, and may be specifically determined according to the size of the transistor 20. That is, when designing a product, the size of the transistor 20 in the product can be determined first, and in this way, the lateral capacitance generated between the first pole 201 and the second pole 202 of the transistor 20 can be first determined. Then, by designing and adjusting the length of the first connecting strip 103 and the length of the second connecting strip 105 of the pixel electrode 10, the total capacitance on the side where the first connecting strip 103 of the pixel electrode 10 is located is equal to or approximately equal to (i.e., does not exceed the error range of) the total capacitance on the side where the second connecting strip 105 is located, thereby improving the grayscale V-shaped crosstalk phenomenon of the product.

[0065] It should also be understood that the number of the first set of sub-conductive portions and the second set of sub-conductive portions in the main conductive portion of the pixel electrode 10 in an embodiment of the present invention may be the same, for example, one or two, but is not limited to this, and the number of the first set of sub-conductive portions and the second set of sub-conductive portions in the main conductive portion of the pixel electrode 10 may also be different, that is, the number of the first set of sub-conductive portions in the main conductive portion of the pixel electrode 10 may be greater or smaller than the number of the second set of sub-conductive portions.

[0066] Here, when the number of the first set of sub-conductive portions and the second set of sub-conductive portions in the pixel electrode 10 is the same, it can be understood that the sum of the lengths of the first connecting strips 103 of each first set of sub-conductive portions in the above-mentioned pixel electrode 10 is designed to be smaller than the sum of the lengths of the second connecting strips 105 of each second set of sub-conductive portions, and the length of the first connecting strips 103 of the first set of sub-conductive portions in the pixel electrode 10 is smaller than the length of the second connecting strips 105 of the second set of sub-conductive portions.

[0067] 1 and 2, the main conductive portion of the pixel electrode 10 according to the embodiment of the present invention may include one first set of sub-conductive portions and one second set of sub-conductive portions. The first edge conductive portion 101 of the pixel electrode 10 is located on a side away from the second set of sub-conductive portions of the plurality of first electrode strips 104 and away from the second surface 103b of the first surface 103a of the first connecting strip 103. The first edge conductive portion 101 may be connected to the first surface 103a and may have a third gap S3 between it and the adjacent first electrode strip 104. The adjacent first edge conductive portion 101 and the end of the first electrode strip 104 away from the first connecting strip 103 are separated from each other. That is, the end of the third gap S3 away from the first connecting strip 103 is open. For convenience of explanation, the end of the third gap S3 away from the first connecting strip 103 may be defined as the open end. The second edge conductive portion 102 is located on a side of the second electrode strips 106 that is away from the first set of sub-conductive portions and away from the fourth surface 105b of the third surface 105a of the second connecting strip 105. The second edge conductive portion 102 is connected to the third surface 105a and has a fourth gap S4 between it and the adjacent second electrode strip 106. The adjacent second edge conductive portion 102 and the end of the second electrode strip 106 that is away from the second connecting strip 105 are separated from each other. That is, the end of the fourth gap S4 that is away from the first connecting strip 103 is open. For ease of explanation, the end of the fourth gap S4 that is away from the second connecting strip 105 can be defined as the open end.

[0068] Optionally, to ensure display uniformity in the first set of sub-conductive portions of the pixel electrode 10, the first electrode strips 104, the first gaps S1, and the third gaps S3 extend in the same direction. Furthermore, the extension directions of the first electrode strips 104, the first gaps S1, and the third gaps S3 all intersect with the first direction Y and the second direction X, thereby reducing color shift. Similarly, to ensure display uniformity in the second set of sub-conductive portions of the pixel electrode 10, the second electrode strips 106, the second gaps S2, and the fourth gaps S4 extend in the same direction. Furthermore, the extension directions of the second electrode strips 106, the second gaps S2, and the fourth gaps S4 all intersect with the first direction Y and the second direction X, thereby reducing color shift.

[0069] Furthermore, to better ensure the uniformity of the product display, the first electrode strip 104, the second electrode strip 106, the first gap S1, the second gap S2, the third gap S3, and the fourth gap S4 have the same width, where the widths mentioned here are the sizes in the direction perpendicular to their extension directions.

[0070] 1, the extending directions of the first electrode strips 104 and the second electrode strips 106 may be the same, that is, the first electrode strips 104 and the second electrode strips 106 may extend in the same direction, that is, the pixel electrode 10 of the present invention may have a monodomain structure, which can reduce design difficulties. Note that in this embodiment, the gap between the adjacent first electrode strips 104 and second electrode strips 106 may be the above-mentioned second gap S2.

[0071] 2, the extension direction of the first electrode strips 104 and the extension direction of the second electrode strips 106 may be arranged in a mirror image relationship with respect to the second direction X, that is, the pixel electrode 10 of the present invention may have a dual-domain structure, thereby widening the viewing angle of the product. Note that in this embodiment of the present invention, the angle between the extension direction of the first electrode strips 104 and the extension direction of the second electrode strips 106 may be an acute angle.

[0072] Here, when the pixel electrode 10 has a dual domain structure, as shown in FIG. 2, the second set of sub-conductive portions of the pixel electrode 10 may further include an adjustment portion 107, which may be located on a side closer to the first set of sub-conductive portions of the plurality of second electrode strips 106 and away from the fourth surface 105b of the third surface 105a of the second connecting strip 105, and this adjustment portion 107 may be connected to the third surface 105a of the second connecting strip 105.

[0073] 2, a fifth gap S5 is formed between the adjustment portion 107 and the adjacent first electrode strip 104, and a sixth gap S6 is formed between the adjustment portion 107 and the adjacent second electrode strip 106. The ends of the adjacent adjustment portion 107 and the first electrode strip 104 that are distant from the second connecting strip 105 are separated from each other, and the ends of the adjacent adjustment portion 107 and the second electrode strip 106 that are distant from the second connecting strip 105 are also separated from each other. That is, the ends of the fifth gap S5 and the sixth gap S6 that are distant from the second connecting strip 105 are open. Here, for convenience of explanation, the ends of the fifth gap S5 and the sixth gap S6 that are distant from the second connecting strip 105 may be defined as open ends. Here, the fifth gap S5 and the first gap S1 may extend in the same direction and have the same width, while the sixth gap S6 and the second gap S2 extend in the same direction and have the same width. This design makes the electric field at the point where the first set of sub-conductive portions and the second set of sub-conductive portions of the pixel electrode 10 contact closer to the electric field at other points of the pixel electrode 10, thereby ensuring display uniformity.

[0074] 2, the adjusting portion 107 may include a first adjusting strip 107a and a second adjusting strip 107b, where the above-mentioned fifth gap S5 is formed between the first adjusting strip 107a and the first electrode strip 104, and the above-mentioned sixth gap S6 is formed between the second adjusting strip 107b and the second electrode strip 106. Here, the first adjusting strip 107a and the first electrode strip 104 may extend in the same direction and have the same width, and the second adjusting strip 107b and the second electrode strip 106 may extend in the same direction and have the same width, which can further ensure the uniformity of the electric field and the uniformity of the display.

[0075] One end of the first adjusting strip 107a and the second adjusting strip 107b in the extension direction may be connected to the third surface 105a of the second connecting strip 105, and the other end may be connected to each other. In addition, by designing a gap pattern to be formed between the first adjusting strip 107a and the second adjusting strip 107b according to the embodiment of the present invention, the dark field region can be reduced.

[0076] Here, if the width of the gap pattern formed between the first adjusting strip 107a and the second adjusting strip 107b is large, the gap pattern can be divided into a gap having the same width and extending in the same direction as the first gap S1 and another gap having the same width and extending in the same direction as the second gap S2 by further providing a separation portion (not shown) in the gap pattern connected to the third surface 105a of the second connecting strip 105. If the width of the gap pattern formed between the first adjusting strip 107a and the second adjusting strip 107b is small, the separation portion does not need to be provided.

[0077] Furthermore, it should be understood that even when the area of ​​the adjustment portion 107 in an embodiment of the present invention is small, the above-mentioned first adjustment strip 107a, second adjustment strip 107b and gap pattern are not provided, that is, the adjustment portion 107 may be an entire structure and may not have a gap pattern, and is determined according to specific circumstances.

[0078] As described above, the pixel electrode 10 according to the embodiment of the present invention may have a monolithic structure. For example, the pixel electrode 10 according to the embodiment of the present invention may be a transparent electrode, and its material may be, but is not limited to, an ITO (indium tin oxide) material, and may also be made of transparent materials such as indium zinc oxide (IZO) and zinc oxide (ZnO).

[0079] The present invention further provides an array substrate, which may be applicable to, but is not limited to, a liquid crystal display device. Referring to FIGS. 1, 2, and 4 to 6, the array substrate of the present invention may further include a first substrate 30, sub-pixels located on the first substrate 30 and arranged in an array along a first direction Y and a second direction X, a plurality of data lines 40 formed on the first substrate 30, a plurality of scan lines 60 and a plurality of common lines 70 formed on the first substrate 30. The first direction Y referred to in the embodiments of the present invention may be referred to as a column direction, and the second direction X may be referred to as a row direction.

[0080] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an array substrate according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0081] As shown in Figure 6, the first substrate 30 may have a single-layer structure, but is not limited to this. The first substrate 30 may further include a multi-layer structure. For example, the material of the first substrate 30 may be glass, but is not limited to this. The material of the first substrate 30 may also be other materials, such as polyimide (PI), and the material may be determined according to specific circumstances.

[0082] 4 and 5, the data lines 40 extend in a first direction Y (i.e., the column direction), and the data lines 40 and the sub-pixels may be arranged alternately in a second direction X (i.e., the row direction). In an embodiment of the present invention, each data line 40 is connected to its adjacent sub-pixels located on the same side in the second direction X, i.e., the data line 40 of each column is connected to its adjacent sub-pixels located in the same column, thereby providing data signals to the sub-pixels in the same column.

[0083] For example, the data line 40 may include a metal material or an alloy material, such as a single-layer or multi-layer structure of metals including molybdenum, aluminum, and titanium, for example, the multi-layer structure may be a multi-layer metal stack, such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti).

[0084] 4 and 5, the scan lines 60 and the common lines 70 extend in the second direction X, and the scan lines 60 and the common lines 70 may be alternately arranged in the first direction Y. Note that the orthogonal projection of the scan lines 60 on the first substrate 30 does not overlap with the orthogonal projection of the common lines 70 on the first substrate 30.

[0085] For example, the scan line 60 and the common line 70 are formed in the same layer. In the present invention, "formed in the same layer" refers to a layer structure formed by a single patterning step using the same mask after a filter layer for forming a specific pattern is formed by the same deposition process. That is, one patterning step corresponds to one mask (also called a photomask). Depending on the specific pattern, one patterning step may include multiple exposure, development, or etching steps. The specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may be located at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0086] 4 to 6, the scan lines 60 and the common lines 70 may be disposed on the side of the data lines 40 closer to the first substrate 30 and insulated from the data lines 40, i.e., a gate insulating layer 80 is disposed between the scan lines 60 and the data lines 40 and between the common lines 70 and the data lines 40. It should be understood that the gate insulating layer 80 is disposed as a whole.

[0087] 4 and 5, in an embodiment of the present invention, a pair of adjacent scan lines 60 and a pair of adjacent common lines 70 may be provided corresponding to a row of subpixels, i.e., one side of each row of subpixels in the first direction Y is adjacent to the common line 70, and the other side is adjacent to the scan line 60. Here, each scan line 60 may be connected to each subpixel located on the same side in the first direction Y and adjacent to it, i.e., each scan line 60 of each row may be connected to each subpixel located adjacent to it and located in the same row, thereby providing a scan signal to the subpixels in the same row. Each common line 70 is connected to each subpixel located on the same side in the first direction Y and adjacent to it, i.e., each common line 70 of each row may be connected to each subpixel located adjacent to it and located in the same row, thereby providing a common signal to the subpixels in the same row.

[0088] For example, the scan lines 60 and the common lines 70 may include metal or alloy materials, such as single or multi-layer metal structures made of molybdenum, aluminum, and titanium.

[0089] In the implementation of the present invention, a sub-pixel may include a pixel electrode 10, a transistor 20 and a common electrode 50, as shown in FIGS.

[0090] Here, the structure of the pixel electrode 10 can refer to the content described in any one of the above embodiments, and for the specific structure, refer to Figures 1 and 2, which will not be described again here.

[0091] As shown in Figures 4 and 5, in the pixel electrode 10 of a subpixel, the distance between the first connecting strip 103 and the data line 40 closest to it is a first pitch h1, and the distance between the second connecting strip 105 and the data line 40 closest to it is a second pitch h2. This first pitch h1 may be equal to the second pitch h2, which will facilitate the subsequent design of the sizes of the first connecting strip 103 and the second connecting strip 105 and reduce manufacturing difficulties. However, it should be understood that the first pitch h1 may not be equal to the second pitch h2 and will be determined according to specific circumstances.

[0092] 4 to 6, the transistor 20 may include an active layer 203, a gate, and a first electrode 201 and a second electrode 202 provided in the same layer. For example, the first electrode 201 and the second electrode 202 may be provided in the same layer as the data line 102. A gate insulating layer 80 may be further provided between the gate and the active layer 203 of the transistor 20, thereby insulating the gate and the active layer 203 from each other. The gate insulating layer 80 may be made of an inorganic material, such as silicon oxide or silicon nitride.

[0093] It should be noted that the gate and the aforementioned scanning line 60 may be provided in the same layer, and the gate may be a part of the aforementioned scanning line 60, that is, a part of the structure of the scanning line 60 may be used as the gate of the transistor 20 to realize the connection between the scanning line 60 and the transistor 20. The first pole 201 and the second pole 202 may be respectively connected to two doped regions (i.e., a source doped region and a drain doped region) of the active layer 203, and the first pole 201 may also be connected to the data line 40, thereby realizing the connection between the data line 40 and the transistor 20. The second pole 202 may be connected to the pixel electrode 10, specifically, the end of the first edge conductive portion 101 or the second edge conductive portion 102 of the pixel electrode 10 away from the second connecting strip 105 is connected to the second pole 202 of the transistor 20, thereby realizing the connection between the transistor 20 and the pixel electrode 10.

[0094] Here, as shown in Figures 4 and 5, by arranging the transistor 20 of each sub-pixel closer to the first connecting strip 103 than to the second connecting strip 105 of its pixel electrode 10 in the second direction X, the total capacitance on the side where the first connecting strip 103 of the pixel electrode 10 is located can be made equal to or approximately equal to the total capacitance on the side where the second connecting strip 105 is located, thereby improving the grayscale V-shaped crosstalk phenomenon of the product.

[0095] Furthermore, the orthogonal projection of the transistor 20 on the first substrate 30 and the orthogonal projection of the first connecting strip 103 of the pixel electrode 10 on the first substrate 30 are arranged to face each other in the first direction Y.

[0096] Optionally, as shown in Figures 4 and 5, two sub-pixels adjacent in the second direction X are taken as a minimum repeating unit, where in two pixel electrodes 10 adjacent in the second direction X, the end of one first edge conductive portion 101 remote from the second connecting strip 105 is connected to the transistor 20 and is closer to the transistor 20 connected thereto than its second edge conductive portion 102. The end of the other second edge conductive portion 102 remote from the second connecting strip 105 is connected to the transistor 20 and is closer to the transistor 20 connected thereto than its first edge conductive portion 101. 5, one second connecting strip 105 and the other first connecting strip 103 are adjacent to the data line 40 therebetween, and one first connecting strip 103 and the other second connecting strip 105 are both distant from the data line 40 therebetween. In other words, one of two adjacent pixel electrodes 10 in the second direction X may be vertically inverted (i.e., arranged in a mirror image relationship with respect to the second direction X) of the other. This design can reduce and balance the dark field area and widen the viewing angle of the product, but is not limited to this. The connection relationship between two adjacent pixel electrodes 10 and transistors 20 in the second direction X can also be the same, but this is determined according to specific circumstances.

[0097] In addition, the structures of the first edge conductive portion 101 or the second edge conductive portion 102 of one of two pixel electrodes 10 adjacent to each other in the second direction X can be designed to be exactly the same, but are not limited to this, and can be slightly adjusted according to actual conditions, as long as the total capacitance on the side where the first connecting strip 103 of the pixel electrode 10 is located and the total capacitance on the side where the second connecting strip 105 is located are equal or nearly equal to each other, thereby improving the grayscale V-shaped crosstalk phenomenon of the product.

[0098] For example, the transistor 20 according to the present invention may be a bottom-gate transistor, i.e., a gate may be first formed on the first substrate 30. The gate may include a metal or alloy material, such as molybdenum, aluminum, or titanium, to ensure good conductivity. Then, as shown in FIG. 6 , a gate insulating layer 80 is formed on the first substrate 30 to cover the gate. Then, an active layer 203 is formed on the gate insulating layer 80 on the side away from the first substrate 30. The active layer 203 is located on the side of the gate away from the first substrate 30, and the orthogonal projection of the active layer 203 on the first substrate 30 overlaps with the orthogonal projection of the gate on the first substrate 30. For example, the orthogonal projection of the active layer 203 on the first substrate 30 may be located within the orthogonal projection of the gate on the first substrate 30. After the active layer 203 is formed, a first pole 201 and a second pole 202 may be formed. Here, a portion of the first pole 201 is located on the side of the active layer 203 away from the first substrate 30 and can be in contact with the source doped region of the active layer 203, and a portion of the second pole 202 is located on the side of the active layer 203 away from the first substrate 30 and can be in contact with the drain doped region of the active layer 203.

[0099] The term "contact" used in the embodiments of the present invention means that the two components are directly bonded together without any filter layer between them, i.e., the two components do not need to be connected via any other structure (e.g., a relay via hole). The transistor according to the embodiments of the present invention is not limited to the bottom gate type described above, but may be a top gate type.

[0100] 4 and 5 , in an embodiment of the present invention, the first poles 201 and the second poles 202 of the transistor 20 may be spaced apart in the first direction Y, and the distance between the first poles 201 and the second poles 202 in the first direction Y may be a third pitch h3. Here, the design of the lengths of the first connecting strips 103 and the second connecting strips 105 in the pixel electrode 10 described above is related to the selection of the size of the transistor 20. Specifically, the ratio of the sum of the lengths of the first connecting strips 103 of each first set of sub-conductive portions in the pixel electrode 10 to the third pitch h3 may be 2 to 20, for example, 2, 5, 8, 11, 14, 17, 20, etc. For example, the third pitch h3 may be, but is not limited to, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, etc., and may be other values.

[0101] In addition, the sum of the lengths of the first connecting strips 103 of each first set of sub-conductive portions in the pixel electrode 10 is related not only to the third pitch S3 mentioned above but also to the thickness and length of the first pole 201 and the second pole 202, where the thickness, length and third pitch h3 of the first pole 201 and the second pole 202 are all key to determining the magnitude of the lateral capacitance generated between the first pole 201 and the second pole 202 in the transistor 20. That is, the design of the lengths of the first connecting strips 103 and the second connecting strips 105 in the pixel electrode 10 mainly depends on the lateral capacitance generated between the first pole 201 and the second pole 202 in the transistor 20.

[0102] For example, the thickness of the first pole 201 and the second pole 202 in the transistor 20 may be 3000 Å to 8000 Å, such as 3000 Å, 4000 Å, 5000 Å, 6000 Å, 7000 Å, 8000 Å, etc., but is not limited to this and may be other values. Also, the length of the first pole 201 and the second pole 202 in the transistor 20 may be 5 μm to 50 μm, such as 5 μm, 15 μm, 25 μm, 35 μm, 45 μm, 50 μm, etc., but is not limited to this and may be other values.

[0103] The first pole 201 and the second pole 202 of the transistor 20 are not limited to being arranged at an interval in the first direction Y, but may be arranged at an interval in the second direction X. When the first pole 201 and the second pole 202 of the transistor 20 are arranged at an interval in the second direction X, the above-mentioned third pitch h3 can be understood to be the distance between the first pole 201 and the second pole 202 in the second direction X.

[0104] Moreover, the length of the first pole 201 and the second pole 202 in the transistor 20 refers to the size in the direction perpendicular to the arrangement direction of the first pole 201 and the second pole 202.

[0105] In an embodiment of the present invention, as shown in FIG. 6, the first pole 201 and the second pole 202 of the transistor 20 can be located on the side of the pixel electrode 10 closer to the first substrate 30. That is, when manufacturing this array substrate, the first pole 201 and the second pole 202 of the transistor 20 can be manufactured first, and then the pixel electrode 10 can be manufactured.

[0106] 6, a passivation layer 90 may be further provided between the first pole 201 and the second pole 202 of the transistor 20 and the pixel electrode 10. This passivation layer 90 may be an inorganic filter layer such as silicon nitride, but is not limited thereto, and may also be an organic filter layer. In this case, the first edge conductive portion 101 or the second edge conductive portion 202 of the pixel electrode 10 may be connected to the second pole 202 of the transistor 20 through a relay via hole P.

[0107] 6, the common electrode 50 may be disposed on a side of the pixel electrode 10 closer to the first substrate 30 and insulated from the pixel electrode 10. For example, the common electrode 50 is specifically formed on the first substrate 30 before the active layer 203 is fabricated, i.e., the common electrode 50 and the pixel electrode 10 are insulated from each other by a gate insulating layer 80 and a passivation layer 90 that are stacked therebetween.

[0108] 4 and 6, the orthogonal projection of the common electrode 50 on the first substrate 30 may overlap with the orthogonal projection of the common line 70 on the first substrate 30. Here, the common electrode 50 may contact the above-mentioned common line 70. Specifically, the common electrode 50 may be formed on the first substrate 30 before the common line 70, but is not limited thereto, and may be formed on the first substrate 30 after the common line 70 is formed on the first substrate 30.

[0109] In addition, the orthogonal projection of the common electrode 50 on the first substrate 30 overlaps with the orthogonal projection of the pixel electrode 10 on the first substrate 30 , but does not overlap with the orthogonal projection of the data line 40 on the first substrate 30 .

[0110] For example, the material of the common electrode 50 may be the same as the material of the pixel electrode 10, and the common electrode 50 may be a transparent electrode, and the material may be, but is not limited to, ITO (indium tin oxide) material, and may also be made of transparent materials such as indium zinc oxide (IZO), zinc oxide (ZnO), etc.

[0111] In the embodiment of the present invention, the common electrode 50 may be a plate-shaped electrode, i.e., the common electrode 50 does not have a gap, but is not limited thereto, and may have a slit, which is determined according to specific circumstances.

[0112] The embodiments of the present invention further provide a display device, which may be, but is not limited to, a liquid crystal display device. The display device according to the embodiments of the present invention may include the array substrate described in any one of the above embodiments, which will not be described again here.

[0113] In addition, this display device may further include an opposing substrate (not shown) provided corresponding to the array substrate and a liquid crystal layer (not shown) located between the array substrate and the opposing substrate, and the liquid crystal molecules of this liquid crystal layer may be negative liquid crystal to increase transmittance, but are not limited to this and may also be positive liquid crystal.

[0114] In an embodiment of the present invention, the display device may further include a spacer, which may be assembled on the opposing substrate, but is not limited thereto, and may also be assembled on the array substrate, and is determined according to specific circumstances.

[0115] Here, the opposing substrate of the present invention may include a second substrate (not shown) and a black matrix layer (not shown) located on the second substrate closer to the array substrate. This black matrix layer may have a light-shielding region and a light-transmitting region. The orthogonal projection of the light-shielding region on the first substrate 30 may completely cover the data lines 40, scan lines 60, common lines 70, sub-pixel transistors 20, spacers, etc., and the light-shielding region may also cover edges of the common electrode 50 and pixel electrode 10. The orthogonal projection of the light-transmitting region on the first substrate 30 may be located within the orthogonal projection of the common electrode 50 and pixel electrode 10 on the first substrate 30.

[0116] In addition, the opposing substrate of the present invention may further include a color filter layer, and the color filter layer may include a red filter block, a green filter block, and a blue filter block.

[0117] The color filter layer is not limited to being assembled on the opposing substrate, but may be assembled on the array substrate, depending on the specific situation.

[0118] According to the embodiment of the present invention, the specific type of the display device is not particularly limited, and may be a display device commonly used in the field to which the present invention pertains. Specific examples include televisions, in-vehicle displays, etc. Those skilled in the art can appropriately select the type of display device depending on the specific application of the display device, and detailed description thereof will be omitted here.

[0119] The display device may further include other necessary components and configurations in addition to the array substrate, opposing substrate, and liquid crystal layer described above. For example, a display may further include a backlight module, a housing, a main circuit board, a power supply line, etc. However, those skilled in the art can appropriately add components according to specific usage requirements of the display device, so detailed description thereof will be omitted here.

[0120] Those skilled in the art will readily obtain other embodiments of the present invention through a reading of the specification and practice of the invention disclosed herein. The present invention includes any modification, use, or adaptation to the present invention, which modification, use, or adaptation follows the general principles of the present invention and includes known knowledge or ordinary technical means in the art that are not disclosed herein. The specification and examples are exemplary only, with the true scope and spirit of the invention being indicated by the following claims. [Explanation of symbols]

[0121] 10 pixel electrode 101 first edge conductive portion 102 second edge conductive portion 103 First connection strip 104 First electrode strip 105 Second Connection Strip 106 Second electrode strip

Claims

1. a first edge conductive portion (101) and a second edge conductive portion (102) arranged at an interval in a first direction (Y); and a main conductive portion at least a portion of which is located between the first edge conductive portion (101) and the second edge conductive portion (102), wherein the main conductive portion is connected to the first edge conductive portion (101) and the second edge conductive portion (102), respectively; the main conductive portion includes at least one first set of sub-conductive portions and at least one second set of sub-conductive portions, and the first set of sub-conductive portions and the second set of sub-conductive portions are arranged alternately in the first direction (Y); The first set of sub-conductive portions includes a first connecting strip (103), the first connecting strip (103) extending in the first direction (Y) and having a first surface (103a) and a second surface (103b) opposing each other in a second direction (X), the first set of sub-conductive portions has a first gap (S1) located on a side of the first surface (103a) away from the second surface (103b), and the end of the first gap (S1) away from the first connecting strip (103) is an open end; The second set of sub-conductive portions includes a second connecting strip (105) located on a side of the first gap (S1) away from the first connecting strip (103) and connected to the first set of sub-conductive portions, the second connecting strip (105) extending in the first direction (Y) and having a third surface (105a) and a fourth surface (105b) opposing each other in the second direction (X), the third surface (105a) being located on a side of the fourth surface (105b) closer to the first surface (103a), and the second set of sub-conductive portions has a second gap (S2) located on a side of the third surface (105a) away from the fourth surface (105b), and the end of the second gap (S2) away from the second connecting strip (105) is an open end; In the second direction (X), the pixel electrode (10) is arranged such that the first connecting strip (103) is closer to the transistor (20) than the second connecting strip (105), and an end of the first edge conductive portion (101) or the second edge conductive portion (102) remote from the second connecting strip (105) is arranged to be connected to the transistor (20); the sum of the lengths of the first connecting strips (103) in the at least one first set of sub-conductive portions is smaller than the sum of the lengths of the second connecting strips (105) in the at least one second set of sub-conductive portions; The first direction (Y) intersects with the second direction (X), The first set of sub-conductive portions further includes a plurality of first electrode strips (104) arranged at intervals in the first direction (Y), and has the first gap (S1) between two adjacent first electrode strips (104); The second set of sub-conductive portions further includes a plurality of second electrode strips (106) arranged at intervals in the first direction (Y), and has the second gap (S2) between two adjacent second electrode strips (106); the first edge conductive portion (101) has a third gap (S3) with the first electrode strip (104) adjacent thereto; the second edge conductive portion (102) has a fourth gap (S4) with the second electrode strip (106) adjacent thereto; The widths of the first electrode strip (104) and the second electrode strip (106) are equal, and the widths of the first gap (S1), the second gap (S2), the third gap (S3), and the fourth gap (S4) are equal. Pixel electrode (10).

2. the plurality of first electrode strips (104) are located on the first surface (103a) at a position away from the second surface (103b) and are connected to the first surface (103a); the plurality of second electrode strips (106) are located on the third surface (105a) at a position away from the fourth surface (105b) and are connected to the third surface (105a); The third surface (105a) of the second connecting strip (105) is connected to the end of the first electrode strip (104) closest to the second set of sub-conductive portions, the end being remote from the first connecting strip (103).

2. The pixel electrode (10) of claim 1.

3. 3. The pixel electrode (10) according to claim 2, wherein the length of the first connecting strip (103) is less than the length of the second connecting strip (105).

4. the main conductive portion includes one of the first set of sub-conductive portions and one of the second set of sub-conductive portions; the first edge conductive portion (101) is located on a side of the plurality of first electrode strips (104) away from the second set of sub-conductive portions and at a position of the first surface (103a) of the first connecting strip (103) away from the second surface (103b), the first edge conductive portion (101) is connected to the first surface (103a), and an end of the third gap (S3) away from the first connecting strip (103) is an open end; The second edge conductive portion (102) is located on a side of the plurality of second electrode strips (106) away from the first set of sub-conductive portions and is located at a position on the third surface (105a) of the second connecting strip (105) away from the fourth surface (105b), the second edge conductive portion (102) is connected to the third surface (105a), and an end of the fourth gap (S4) away from the second connecting strip (105) is an open end.

4. The pixel electrode (10) according to claim 3.

5. 5. The pixel electrode (10) of claim 4, wherein the extension directions of the first electrode strip (104), the first gap (S1), and the third gap (S3) are the same and intersect with the first direction (Y) and the second direction (X), and the extension directions of the second electrode strip (106), the second gap (S2), and the fourth gap (S4) are the same and intersect with the first direction (Y) and the second direction (X).

6. 6. The pixel electrode (10) of claim 5, wherein the first electrode strip (104) and the second electrode strip (106) extend in the same direction, and the second gap (S2) is provided between adjacent first electrode strips (104) and second electrode strips (106).

7. 6. The pixel electrode (10) according to claim 5, wherein the extension direction of the first electrode strips (104) and the extension direction of the second electrode strips (106) are arranged in a mirror image relationship with respect to the second direction (X).

8. the second set of sub-conductive portions further includes an adjustment portion (107), the adjustment portion (107) being located on a side of the plurality of second electrode strips (106) closer to the first set of sub-conductive portions and at a position away from the fourth surface (105b) of the third surface (105a) of the second connecting strip (105), the adjustment portion (107) being connected to the third surface (105a) of the second connecting strip (105); A fifth gap (S5) is formed between the adjustment portion (107) and the first electrode strip (104) adjacent thereto, and a sixth gap (S6) is formed between the adjustment portion (107) and the second electrode strip (106) adjacent thereto; The ends of the fifth gap (S5) and the sixth gap (S6) away from the second connecting strip (105) are both open ends; The fifth gap (S5) and the first gap (S1) extend in the same direction and have the same width, and the sixth gap (S6) and the second gap (S2) extend in the same direction and have the same width.

8. A pixel electrode (10) according to claim 7.

9. The adjustment portion (107) includes a first adjustment strip (107a) and a second adjustment strip (107b), and the fifth gap (S5) is formed between the first adjustment strip (107a) and the first electrode strip (104), and the sixth gap (S6) is formed between the second adjustment strip (107b) and the second electrode strip (106). the first adjusting strips (107a) and the first electrode strips (104) have the same extension direction and the same width, the second adjusting strips (107b) and the second electrode strips (106) have the same extension direction and the same width, One end of the first adjusting strip (107a) and the second adjusting strip (107b) in the extension direction is connected to the third surface (105a) of the second connecting strip (105), and the other end is connected to each other.

9. A pixel electrode (10) according to claim 8.

10. A pixel electrode (10) according to any one of claims 1 to 9, wherein the ratio of the sum of the lengths of the first connecting strips (103) in the at least one first set of sub-conductive portions to the sum of the lengths of the second connecting strips (105) in the at least one second set of sub-conductive portions is between 0.1 and 0.

9.

11. a first substrate (30); and sub-pixels located on the first substrate (30) and arranged in an array along a first direction (Y) and a second direction (X), the sub-pixels including a transistor (20) and a pixel electrode (10) according to any one of claims 1 to 10, wherein an end of a first edge conductive portion (101) or a second edge conductive portion (102) of the pixel electrode (10) remote from a second connecting strip (105) is connected to the transistor (20); In the second direction (X), the transistor (20) is arranged closer to the first connecting strip (103) than to the second connecting strip (105) of the pixel electrode (10). Array board.

12. 12. The array substrate of claim 11, wherein the orthogonal projection of the transistor (20) on the first substrate (30) and the orthogonal projection of the first connecting strip (103) of the pixel electrode (10) on the first substrate (30) are arranged opposite each other in the first direction (Y).

13. In two of the pixel electrodes (10) adjacent to each other in the second direction (X), an end of one of the first edge conductive portions (101) remote from the second connecting strip (105) is connected to the transistor (20) and is closer to the transistor (20) connected thereto than the second edge conductive portion (102); The other end of the second edge conductive portion (102) away from the second connecting strip (105) is connected to the transistor (20) and is closer to the transistor (20) connected thereto than the first edge conductive portion (101). The array substrate according to claim 12 .

14. The pixel further includes a plurality of data lines (40) formed on the first substrate (30), the data lines (40) extending in the first direction (Y), and the data lines (40) and the sub-pixels alternately arranged in the second direction (X); In the pixel electrode (10) of the sub-pixel, the distance between the first connecting strip (103) and the data line (40) closest thereto is a first pitch (h1), and the distance between the second connecting strip (105) and the data line (40) closest thereto is a second pitch (h2), and the first pitch (h1) and the second pitch (h2) are equal. The array substrate according to claim 13 .

15. Each of the data lines (40) is connected to the transistors (20) of the sub-pixels (20) located on the same side of the data line (40) in the second direction (X) and adjacent thereto; The first pole (201) and the second pole (202) of the transistor (20) are provided in the same layer as the data line (40) and are located on the side of the pixel electrode (10) closer to the first substrate (30), the first pole (201) of the transistor (20) is connected to the data line (40), and the second pole (202) of the transistor (20) is connected to the second edge conductive portion (102) or the first edge conductive portion (101) of the pixel electrode (10) through a relay via hole (P). The array substrate according to claim 14 .

16. The first pole (201) and the second pole (202) of the transistor (20) are arranged at an interval in the first direction (Y), and the distance between the first pole (201) and the second pole (202) in the first direction (Y) is a third pitch (h3); The ratio of the sum of the lengths of the first connecting strips (103) in the at least one first set of sub-conductive portions to the third pitch (h3) is between 2 and 20. The array substrate according to claim 15 .

17. The sub-pixel further includes a common electrode (50), the common electrode (50) being located on a side of the pixel electrode (10) closer to the first substrate (30) and being insulated from the pixel electrode (10); Furthermore, the orthogonal projection of the common electrode (50) on the first substrate (30) overlaps with the orthogonal projection of the pixel electrode (10) on the first substrate (30), and does not overlap with the orthogonal projection of the data line (40) on the first substrate (30). The array substrate according to claim 15 .

18. The array substrate further includes a plurality of scanning lines (60) and a plurality of common lines (70) formed on the first substrate (30) and extending in the second direction (X), the scanning lines (60) and the common lines (70) are alternately arranged in the first direction (Y), and the orthogonal projections of the scanning lines (60) on the first substrate (30) do not overlap with the orthogonal projections of the common lines (70) on the first substrate (30); The scanning lines (60) and the common lines (70) are provided in the same layer, and the scanning lines (60) and the common lines (70) are located on a side of the data lines (40) closer to the first substrate (30) and are insulated from the data lines (40); One side of the sub-pixel in the first direction (Y) is adjacent to the common line (70), and the other side is adjacent to the scanning line (60); Each of the scanning lines (60) is connected to the gate of the transistor (20) of each of the sub-pixels located on the same side in the first direction (Y) and adjacent thereto; Each of the common lines (70) is connected to the common electrodes (50) of the sub-pixels (50) located on the same side of the common line (70) in the first direction (Y) and adjacent to it.

18. The array substrate according to claim 17.

19. 19. The array substrate of claim 18, wherein a portion of the scan line (60) constitutes a gate of the transistor (20), and the common electrode (50) contacts the common line (70).

20. 20. A display device comprising: the array substrate according to claim 11; and an opposing substrate provided in correspondence with the array substrate.

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