Memory cell and memory cell array

Abstract

To provide a semiconductor device with a new structure that can retain memory contents even when power is not supplied during a memory retention period and has no limit in the number of times of writing.SOLUTION: A semiconductor device includes: a first transistor including a first source electrode and a first drain electrode, a first channel formation region electrically connected to the first source electrode and the first drain electrode and using an oxide semiconductor material, a first gate insulating layer on the first channel formation region, and a first gate electrode on the first gate insulating layer; and a capacitive element. One of the first source electrode and the first drain electrode of the first transistor and one of the electrodes of the capacitor are electrically connected.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile, meaning that the stored contents are lost when the power supply is cut off. and non-volatile memory, which retains its contents even when the power supply is cut off. .

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from transistors. By storing charge in the capacitor, information is stored.

[0004] According to the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Every time information is read, a write operation is required again. The transistor has leakage current, and charge flows out even when the transistor is not selected. Therefore, the data retention period is short. Refresh operation is required, making it difficult to sufficiently reduce power consumption. In addition, since the memory contents are lost when the power supply is cut off, magnetic fields are necessary for long-term memory retention. Therefore, alternative storage devices using electro-optical materials are required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store the memory contents. In order to retain data, no refresh operation is required, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, there is a problem that the memory contents are lost when the power supply is cut off. In this regard, it is no different from DRAM.

[0006] A typical example of a nonvolatile memory device is flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data retention period is extremely long. The advantage is that it lasts for a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. The point is as follows (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem in that the memory element will stop functioning after a certain number of writes. To mitigate the effect of this problem, for example, the number of writes to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to hold charge on the floating gate or to remove that charge. This requires a high voltage and a circuit for it. It takes a relatively long time to write or erase data, and it is not easy to speed up writing or erasing. There is also the problem that: [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, one embodiment of the disclosed invention is a method for preventing power supply during a memory retention period. A semiconductor device that can retain memory contents even in difficult situations and has no limit on the number of times it can be written to. One of the purposes is to provide [Means for solving the problem]

[0011] In the disclosed invention, a semiconductor device is formed using a highly purified oxide semiconductor. Since transistors using oxide semiconductors with SiO2 have extremely low leakage current, , it is possible to retain information for a long period of time.

[0012] In one embodiment of the disclosed invention, a first source electrode and a first drain electrode, The first drain electrode and the second source electrode are electrically connected to the first gate electrode and the second drain electrode, and an oxide semiconductor material is used. a first channel forming region, a first gate insulating layer on the first channel forming region, and a first a first transistor having a first gate electrode on the gate insulating layer; a capacitance element; a first source electrode or a first drain electrode of the first transistor; One of the electrodes of the quantum element is electrically connected to a semiconductor device.

[0013] In the above structure, the capacitor element includes a first source electrode or a first drain electrode, The first gate insulating layer and the capacitance element electrode on the first gate insulating layer are included. This can be done.

[0014] In the above configuration, the second source electrode and the second drain electrode are a second drain electrode electrically connected to the first electrode and the second drain electrode, the second drain electrode being made of an oxide semiconductor material; a second gate insulating layer on the second channel forming region; a second transistor having a second gate electrode on the gate insulating layer; a source line; and a bit line. a line, a word line, a first signal line, and a second signal line; a second gate electrode; and a first One of the source electrode and the first drain electrode is electrically connected to one of the electrodes of the capacitor element. The source line and the second source electrode are electrically connected, and the bit line and the second drain electrode are electrically connected. The first signal line is electrically connected to the first source electrode or the first drain electrode. The second signal line and the first gate electrode are electrically connected to each other. and the word line and the other electrode of the capacitor element are electrically connected to each other. can be done.

[0015] In this specification, the terms "above" and "below" refer to the positional relationship of a component "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" does not necessarily mean "directly below." " excludes those that include other components between the gate insulating layer and the gate electrode. Furthermore, the terms "upper" and "lower" are merely used for the convenience of explanation and are not to be specifically mentioned. Except in certain cases, this also includes cases where the top and bottom are reversed.

[0016] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0017] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification and the like, the terms "source" and "drain" may be used interchangeably. It shall be possible.

[0018] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0019] For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as [Effects of the Invention]

[0020] One embodiment of the present invention provides a semiconductor device including a transistor including an oxide semiconductor. Since a transistor using an oxide semiconductor has an extremely small off-state current, This allows the memory contents to be retained for an extremely long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations significantly. Therefore, power consumption can be reduced sufficiently. Even if the memory card is used, it is possible to retain the stored contents for a long period of time.

[0021] In addition, the semiconductor device according to the disclosed invention does not require a high voltage for writing information. There is no problem of degradation of the electrons in the floating gate as in conventional non-volatile memory. Since there is no need to inject or extract electrons from the floating gate, there is no degradation of the gate insulating layer. In other words, the semiconductor device according to the present invention does not have the same problems as the conventional nonvolatile semiconductor memory device. There is no limit to the number of times it can be rewritten, which is a problem with non-volatile memory, and reliability is dramatically improved. Furthermore, information is written depending on the on / off state of the transistor. Therefore, high-speed operation can be easily realized. In addition, there is no need to perform an operation to erase information. There are also benefits to this.

[0022] As described above, according to one embodiment of the disclosed invention, it is possible to preserve stored contents even in a situation where power is not supplied. Therefore, it is possible to provide a semiconductor device that can be maintained and has no limit on the number of times data can be written. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. [Figure 2] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 7] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 8] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 9] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 10] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 11] A diagram showing the results of a memory window width survey. DETAILED DESCRIPTION OF THE INVENTION

[0024] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0025] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual embodiment for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0026] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. The numbers are added to avoid confusion and are not intended to limit the number.

[0027] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. 1 and 2. In the circuit diagram, an oxide semiconductor is used. In order to indicate that the transistor is a transistor having a structure similar to that of the first embodiment, the symbol OS may also be added.

[0028] <Cross-sectional structure of semiconductor device> FIG. 1 shows an example of the configuration of a semiconductor device. FIGS. 1(A) to 1(D) show cross sections of the semiconductor device. The semiconductor device shown in FIG. 1 includes a transistor 162 using an oxide semiconductor and a capacitor. It has a capacitance element 164.

[0029] Although the above transistor will be described as an n-channel transistor, It goes without saying that a channel type transistor can be used. The technical essence of this is that an oxide semiconductor is used for the transistor 162 to store data. Therefore, the specific configuration of the semiconductor device does not need to be limited to that shown here.

[0030] The transistor 162 in FIG. 1A is provided over a substrate 200 with an insulating layer 138 interposed therebetween. The source or drain electrode 142a and the source or drain electrode 14 2b, a source or drain electrode 142a, and a source or drain electrode The oxide semiconductor layer 144 electrically connected to the source electrode or the drain electrode 142b The electrode 142a, the source electrode or the drain electrode 142b, and the gate electrode covering the oxide semiconductor layer 144 a gate insulating layer 146 and a gate insulating film 148 provided on the gate insulating layer 146 so as to overlap with the oxide semiconductor layer 144; and a gate electrode 148a.

[0031] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 144. It is desirable that the water be highly purified by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / c m 3Below 5×10 18 atoms / cm 3 Less than or equal to 5×10 1 7 atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 144 is as follows: Secondary Ion Mass Spectrometry (SIMS) As shown, the hydrogen concentration was sufficiently reduced to obtain a highly pure Defect levels in the energy gap due to oxygen deficiency are formed by the supply of sufficient oxygen. In the oxide semiconductor layer 144 in which the carrier concentration is reduced, the carrier concentration is 1×10 12 / cm 3 Less than, hope Preferably 1 x 10 11 / cm 3 Less than 1.45 × 10 10 / cm 3 less than For example, the off-current density at room temperature (off-current divided by the channel width of the transistor) is value) is 10zA / μm to 100zA / μm (1zA (zeptoampere) is 1×10 -2 1 In this way, the oxide semiconductor becomes i-type (intrinsic) or substantially i-type. By using a conductor, the transistor 162 can have excellent off-state current characteristics. do.

[0032] Note that in the transistor 162 in FIG. 1A, the oxide semiconductor layer 144 is not processed into an island shape. Therefore, contamination of the oxide semiconductor layer 144 due to etching during processing can be prevented.

[0033] The capacitor 164 includes a source electrode or a drain electrode 142a, an oxide semiconductor layer 144, a gate electrode 142b, and a gate insulating film 142c. The gate insulating layer 146 and the electrode 148b are the source or drain electrodes. The drain electrode 142a functions as one electrode of the capacitance element 164, and the electrode 148b functions as the capacitance element 164. This will function as the other electrode of the capacitor 164.

[0034] Note that in the capacitor 164 in FIG. 1A, the oxide semiconductor layer 144 and the gate insulating layer 146 By stacking, the source electrode or drain electrode 142a and the electrode 148b Therefore, the insulation properties can be sufficiently ensured.

[0035] Note that in the transistor 162 and the capacitor 164, the source electrode or the drain electrode electrode 142a, and the source or drain electrode 142b, and the end of the insulating layer 143 Preferably, the tapered shape is a tapered shape. Here, the taper angle is, for example, 30° or more. The taper angle is set to 0° or less. Alternatively, the drain electrode 142a) is formed in a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate). The angle of inclination between the side and bottom of the layer when observed from the source or drain electrode. The end of the electrode 142a, the source electrode or the drain electrode 142b is tapered. This improves the coverage of the oxide semiconductor layer 144 and prevents discontinuities. do.

[0036] In addition, an interlayer insulating layer 150 is provided on the transistor 162 and the capacitor element 164. An interlayer insulating layer 152 is provided on the interlayer insulating layer 150 .

[0037] The transistor and the capacitor illustrated in FIG. 1B are the same as those illustrated in FIG. This is one of the modified examples of the capacitance element.

[0038] The difference between the structure shown in FIG. 1B and the structure shown in FIG. 1A is that the oxide semiconductor layer is formed into an island shape. That is, in the structure illustrated in FIG. 1A, the oxide semiconductor layer 144 The edge layer 138, the source or drain electrode 142a, and the source or drain electrode In contrast, in the configuration shown in FIG. 1(B), the oxide film is formed in an island shape. The oxide semiconductor layer 144 is connected to the insulating layer 138, the source or drain electrode 142a, and The source electrode or the drain electrode 142b is partially covered. The end of the body layer 144 is preferably tapered. The taper angle is, for example, 30°. It is preferable that the angle be between 10° and 60°.

[0039] In addition, in the capacitor 164, the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked. This improves the insulation between the source or drain electrode 142a and the electrode 148b. can be sufficiently secured.

[0040] The transistor and the capacitor illustrated in FIG. 1C are the same as those illustrated in FIG. This is one of the modified examples of the capacitance element.

[0041] The difference between the structure shown in FIG. 1C and the structure shown in FIG. 1A is that the insulating layer 143 is The source or drain electrode 142a is formed on the source or drain electrode 142b. Furthermore, the oxide semiconductor layer 144 is formed on the insulating layer 143, the source electrode, or the The insulating film is formed to cover the drain electrode 142a and the source or drain electrode 142b. The oxide semiconductor layer 144 is formed through an opening in the insulating layer 143. The source electrode or drain electrode 142a is provided in contact with the source electrode or drain electrode 142a via the gate electrode 142b.

[0042] By providing the insulating layer 143, the gate electrode and the source electrode or the drain electrode are separated. This reduces the capacitance formed in the transistor, thereby enabling the transistor to operate at a higher speed.

[0043] The transistor and capacitor shown in FIG. 1D are the same as those shown in FIGS. 1B and 1C. This is one of the modified examples of the resistor and the capacitor element.

[0044] The difference between the structure shown in FIG. 1(D) and the structure shown in FIG. 1(B) is that the insulating layer 1 43 is a source or drain electrode 142a and a source or drain electrode Furthermore, the oxide semiconductor layer 144 is formed on the insulating layer 143. , the source or drain electrode 142a, and the source or drain electrode 142 b. In addition, the structure shown in FIG. 1(D) and the structure shown in FIG. 1(C) The difference from the structure shown in FIG. 1 is that the oxide semiconductor layer 144 is formed in an island shape. As a result, the effects of the configuration of FIG. 1(B) and the configuration of FIG. 1(C) can be obtained together. It is possible.

[0045] <Circuit Configuration and Operation of Semiconductor Device> Next, an example of the circuit configuration of the semiconductor device and its operation will be described. 1 is an example of a circuit configuration using the semiconductor device shown in FIG.

[0046] In the semiconductor device shown in FIG. 2(A-1), the first wiring (1st Line: source line) The source electrode of the transistor 160 is electrically connected to the second wiring (also referred to as 2n The drain electrode of the transistor 160 is electrically connected to the bit line (also called the bit line). Also, the third line (also called the first signal line) and the transceiver The fourth transistor 162 is electrically connected to either the source electrode or the drain electrode of the fourth transistor 162. The line (also called the 4th Line: second signal line) and the gate electrode of the transistor 162 , are electrically connected to the gate electrode of the transistor 160 and the The other of the source electrode and the drain electrode of the capacitor 162 is electrically connected to one of the electrodes of the capacitor 164. , and the fifth wiring (also called a word line) and the capacitor element 164 The other electrode is electrically connected.

[0047] Here, the transistor 160 and the transistor 162 are formed using the above-described oxide semiconductor. The above-described transistor using an oxide semiconductor has a low off-state current. Therefore, when the transistor 162 is turned off, This allows the potential of the gate electrode of the transistor 160 to be maintained for an extremely long period of time. By providing the capacitor 164, the gate of the transistor 160 This makes it easier to retain the charge given to the electrode, and also makes it easier to read out the retained information. Note that the transistor 162 including an oxide semiconductor has a channel length (L) of 10 nm. Since the thickness is set to 1000nm or less, power consumption is low and the operating speed is extremely fast. It has the following characteristics.

[0048] In the semiconductor device illustrated in FIG. 2A-1, the potential of the gate electrode of the transistor 160 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0049] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The transistor 162 is set to a potential that turns it on, thereby turning it on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 1 That is, a predetermined charge is applied to the gate electrode of the transistor 160. Here, the charge that gives two different potential levels (hereafter referred to as Low level) is Then, the fourth The potential of the wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 160, the charge applied to the gate electrode of the transistor 160 is retained. will be held (retained).

[0050] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long time.

[0051] Next, the reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wire, the gate of the transistor 160 The second wiring has a different potential depending on the amount of charge held in the transistor electrode. If the transistor 160 is an n-channel type, a high level is applied to the gate electrode of the transistor 160. Apparent threshold V for a given charge th_H is the gate of transistor 160 The apparent threshold voltage V when a low-level charge is applied to the gate electrode th_L Lower Here, the apparent threshold voltage is the voltage at which the transistor 160 is in the "on state." Therefore, the potential of the fifth wiring is V place th_H and V th_L By setting the potential V0 to the intermediate potential of The charge applied to the gate electrode can be determined. For example, in writing, If a charge is applied, the potential of the fifth wire is V0 (>V th_H ) then, The transistor 160 is in the "ON state." If a low level charge is applied, The potential of the fifth wire is V0( <V th_L ), transistor 160 remains in the "off state" Therefore, by checking the potential of the second wiring, the stored information can be read. You can put it out.

[0052] When memory cells are arranged in an array, only the information of the desired memory cell is read. In this way, it is necessary to read the information of a specific memory cell and To prevent the information in other memory cells from being read, a transistor 1 is placed between each memory cell. 60 are connected in parallel, the first memory cell that is not the object of reading For the wiring of 5, the transistor 160 is in the "off state" regardless of the state of the gate electrode. That is, V th_H In addition, each memory cell When the transistors 160 are connected in series between the channels, the For the fifth wiring of the memory cell that does not have a gate electrode, the transistor 1 The potential at which 60 is in the "on state," that is, V th_L A larger potential is applied to the fifth wire. Just give it to

[0053] Next, the rewriting of information will be described. That is, the potential of the fourth wiring is held when the transistor 162 is turned on. This turns on the transistor 162. (a potential related to new information) is applied to the gate electrode of the transistor 160 and the capacitor 164. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 162. By turning off the transistor 162, the gate voltage of the transistor 160 is The poles are given a charge related to the new information.

[0054] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. That is, high-speed operation of the semiconductor device is realized.

[0055] The source electrode or drain electrode of the transistor 162 is connected to the gate of the transistor 160. By electrically connecting the gate electrode to the flow cell, the flow cell can be used as a nonvolatile memory element. This has the same effect as the floating gate of a floating gate type transistor. In the figure, the source electrode or drain electrode of the transistor 162 and the gate electrode of the transistor 160 The part where the gate electrode is electrically connected is sometimes called the floating gate part FG. When the transistor 162 is off, the floating gate portion FG is buried in an insulator. This can be seen as a charge-holding effect, and the floating gate FG holds charge. The off-state current of the transistor 162 using The floating gate leakage current of transistor 162 is less than 1 / 0,000. It is possible to ignore the loss of charge stored in the FG. The transistor 162 can provide a nonvolatile memory device.

[0056] For example, if the off-state current density of transistor 162 at room temperature is 10 Ω (1 Ω (zeptoamperes) A) is 1 x 10 -21 A) and the capacitance value of the capacitance element 164 is about 1 pF There are at least 10 6 It is possible to hold data for more than 10 seconds. It goes without saying that this varies depending on the transistor characteristics and capacitance value.

[0057] In this case, the gate electrode, which has been pointed out in the conventional floating gate type transistor, There is no problem of deterioration of the gate insulating film (tunnel insulating film). This eliminates the degradation of the gate insulating film that occurs when electrons are injected into the floating gate. This means that there is no theoretical limit to the number of times you can write to it. In addition, the conventional floating gate transistor requires The high voltage that was previously required is no longer necessary.

[0058] The semiconductor device shown in FIG. 2(A-1) is a semiconductor device including elements such as transistors. can be replaced with a circuit like that shown in Figure 2(A-2) as including resistance and capacitance. That is, in FIG. 2(A-2), the transistor 160 and the capacitor 164 are Each is considered to be composed of a resistance and a capacitance. R1 and C1 are the resistance and capacitance values ​​of the capacitive element 164, respectively, and the resistance value R1 is the capacitance value of the capacitive element 164. R2 and C2 correspond to the resistance of the insulating layer that constitutes 64. The resistance and capacitance of the transistor 160 are R1 and R2, respectively. The capacitance C2 corresponds to the resistance value of the gate insulating layer in the gate This corresponds to the capacitance formed between the gate electrode and the source or drain electrode. The resistance value R2 is the resistance value between the gate electrode and the channel forming region of the transistor 160. Some of the connections are shown as dotted lines to clarify this point, as they are for illustration purposes only.

[0059] The resistance between the source and drain electrodes when the transistor 162 is in the off state (actual If R1 is ROS (also called effective resistance), then R1 and R2 must satisfy the following condition: R1 ≥ ROS (R1 is less than ROS). When R2≧ROS (R2 is equal to or greater than ROS), the charge retention period (information retention period) is The hold-up time (which can also be called the hold-up time) is mainly determined by the off-state current of the transistor 162. This will be the case.

[0060] On the other hand, if the relationship is not satisfied, the off-state current of the transistor 162 is sufficiently small. However, it becomes difficult to ensure a sufficient retention period. This is because the leakage current is large. It is desirable that the above relationship be satisfied.

[0061] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1≧C2 (C1 is equal to or greater than C2). By increasing C1, the potential of the floating gate part FG is controlled by the fifth wiring. When the fifth wiring is used (for example, when reading), the fluctuation of the potential of the fifth wiring can be suppressed. This is because.

[0062] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are controlled by the gate insulating layer of transistor 160 and transistor 162. The same applies to C1 and C2. Therefore, the material and thickness of the gate insulating layer It is desirable to appropriately set the above so as to satisfy the above relationship.

[0063] The semiconductor device shown in FIG. 2B does not include the transistor 160 in FIG. In the semiconductor device shown in FIG. 2B, the first wiring (1st Line (also called the first signal line) and the source electrode or drain electrode of the transistor 162 The second wiring (also called the second line: second signal line) is electrically connected to the first wiring. and the gate electrode of the transistor 162 are electrically connected. The other of the source electrode or the drain electrode of the capacitor 162 and one of the electrodes of the capacitor 164 are , and are electrically connected to a third wiring (also called a capacitance line) and a capacitance element 1 The other electrode of 64 is electrically connected.

[0064] Here, the transistor 162 is a transistor including an oxide semiconductor. The above-described transistor using an oxide semiconductor has an extremely low off-state current. Therefore, when the transistor 162 is turned off, the capacitor 164 It is possible to maintain a given potential for an extremely long period of time. The conductor transistor 162 has a channel length (L) of 10 nm or more and 1000 nm or less. Therefore, it has the characteristics of low power consumption and extremely high operating speed.

[0065] The semiconductor device illustrated in FIG. 2B has a feature that a potential applied to the capacitor 164 can be held. By utilizing this characteristic, it is possible to write, store, and read information as follows.

[0066] First, we will explain how to write and store information. For simplicity, we will use the third distribution The potential of the second wiring is fixed. This sets the potential at which the first transistor 162 is turned on, thereby turning on the first The potential of the wiring is applied to one of the electrodes of the capacitor 164. A predetermined charge is applied to the second wiring (write). By setting the potential at which the transistor 162 is turned off, the transistor 162 is turned off. The charge applied to the capacitor 164 is held (retained). As shown, the off-state current is extremely small, so that the charge can be retained for a long period of time.

[0067] Next, the reading of information will be described. In this state, when the potential of the second wiring is set to a potential that turns on the transistor 162, the capacitance element The first wiring has a different potential depending on the amount of charge held in the capacitor 164. By monitoring the potential of the first wiring, the stored data can be read out.

[0068] When the information is read, the charge of the capacitor element 164 is lost, so that the charge is not written again. It is important to note that the following will be carried out.

[0069] Next, the rewriting of information will be described. That is, the potential of the second wiring is held in the same manner as when the transistor 162 is turned on. This turns on the transistor 162. (a potential related to new data) is applied to one electrode of the capacitor 164. The potential of the wiring is set to a potential at which the transistor 162 is turned off. By turning off the capacitor 164, the capacitor 164 is in a state where a charge related to new information is given. It becomes a state of mind.

[0070] In this way, the semiconductor device according to the disclosed invention can directly write information again. This allows information to be rewritten, thereby enabling the semiconductor device to operate at high speed.

[0071] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of hole-capacitors instead of n-type transistors. It goes without saying that a p-type transistor can be used as a carrier.

[0072] (Embodiment 2) In this embodiment, a method for manufacturing a semiconductor device using an oxide semiconductor, specifically, a method for manufacturing a transistor using an oxide semiconductor will be described. A method for manufacturing the capacitor 162 will be described with reference to FIG.

[0073] First, an insulating layer 138 is formed on the substrate 200. Then, a conductive layer is formed on the insulating layer 138. The conductive layer is selectively etched to form a source electrode or a drain electrode 142a, A source or drain electrode 142b is formed (see FIG. 3(A)).

[0074] The substrate 200 may be, for example, a glass substrate. In addition to plates, insulating substrates made of insulators such as ceramic substrates, quartz substrates, and sapphire substrates are also available. a semiconductor substrate made of a semiconductor material such as silicon; a conductive substrate made of a conductor such as metal or stainless steel; The substrate, or a substrate whose surface is covered with an insulating material, can be used. Flexible substrates such as sticks generally tend to have low heat resistance, but they can be easily used in the subsequent manufacturing process. If the substrate 200 can withstand such a temperature, it can be used.

[0075] The insulating layer 138 functions as a base and is formed by using a PVD method, a CVD method, or the like. The insulating layer 138 can be made of silicon oxide, silicon oxynitride, or silicon nitride. The material used is an inorganic insulating material such as hafnium oxide, aluminum oxide, or tantalum oxide. The insulating layer 138 can be formed so as to contain as little hydrogen and water as possible. It is also possible to employ a structure in which the insulating layer 138 is not provided.

[0076] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed using a material such as aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the above elements Alloys containing manganese, magnesium, zirconium, beryllium, etc. can be used. Alternatively, a combination of these materials may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, an element selected from the above or a material that is a combination of two or more of these may be used.

[0077] The conductive layer may have a single layer structure or a laminated structure of two or more layers. single-layer structure of silicon film or titanium nitride film, single-layer structure of aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single layer structure of a titanium film or a titanium nitride film, a tapered shape is The source or drain electrode 142a and the source or drain electrode 142 It has the advantage of being easy to process into b.

[0078] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO), or these metal oxide materials It is possible to use a material containing silicon or silicon oxide.

[0079] The etching of the conductive layer is performed to form the source or drain electrode 142a and the source It is preferable to perform this process so that the end of the source or drain electrode 142b has a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The taper angle is the angle at which a layer having a tapered shape (for example, a source electrode or a drain electrode) 142a) from a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate). The inclination angle between the side and bottom surfaces of the layer is shown. The end of the electrode or drain electrode 142b is etched to have a tapered shape. This improves the coverage of the gate insulating layer 146 to be formed later, and prevents discontinuities. can.

[0080] The channel length (L) of the transistor is the distance from the bottom end of the source or drain electrode 142a to the , and the distance between the lower end of the source electrode or drain electrode 142b. The mask shape used when forming a transistor with a channel length (L) of less than 25 nm When performing exposure to light for the composition, extreme ultraviolet rays with a wavelength of several nm to several tens of nm are used. It is desirable to use ultraviolet light to form a mask. The exposure performed by this method has high resolution and a large depth of focus. It is also possible to set the channel length (L) to 10 nm or more and 1000 nm (1 μm) or less. Furthermore, miniaturization can reduce the power consumption of semiconductor devices. It is also possible to reduce

[0081] The source or drain electrode 142a and the source or drain electrode 1 An insulating layer may be formed on 42b. By providing the insulating layer, the insulating layer can be formed later. a gate electrode connected to the source or drain electrode 142a, and a source or drain electrode It is possible to reduce the parasitic capacitance between the drain electrode 142b and the drain electrode 142a.

[0082] Next, the source or drain electrode 142a and the source or drain electrode 142b are An oxide semiconductor layer 144 is formed to cover 42b (see FIG. 3B).

[0083] The oxide semiconductor layer 144 may be a quaternary metal oxide such as In—Sn—Ga—Zn—O, or a ternary metal oxide such as In—Sn—Ga—Zn—O. The metal oxides In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. Zn-Mg-O, Sn-Mg-O, In-Mg-O, and single-component metal oxides It can be formed using oxide semiconductors such as In-O, Sn-O, and Zn-O. .

[0084] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0085] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0, m is not necessarily a natural number). Also, instead of Ga, M Using InMO3(ZnO) m (m>0, m is not necessarily a natural number) There are oxide semiconductor materials that can be used for this purpose. Here, M is gallium (Ga), aluminum (Al), Selected from iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), etc. It represents one or more metal elements. For example, M can be Ga, Ga, and Al. , Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, etc. The above composition is derived from the crystal structure and is merely an example. It should be noted that this is merely

[0086] The oxide semiconductor layer 144 is formed by sputtering using a target such as In:Ga: The composition is expressed by the formula Zn=1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). For example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] In addition, a target having a composition ratio of In2O3:Ga2O 3:ZnO=1:1:1 [molar ratio] and In2O3:G A target with a composition ratio of a2O3:ZnO=1:1:4 [molar ratio] and In2O A target having a composition ratio of 3:ZnO=1:2 [molar ratio] can also be used.

[0087] In this embodiment, the amorphous oxide semiconductor layer 144 is made of an In—Ga—Zn—O-based metal. The film is formed by sputtering using a metal oxide target.

[0088] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more; More preferably, it is 99.9% or more. A metal oxide target with a high relative density is used. This makes it possible to form the oxide semiconductor layer 144 with a dense structure.

[0089] The oxide semiconductor layer 144 is formed in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the concentration has been reduced to 10 ppb or less. is.

[0090] When the oxide semiconductor layer 144 is formed, for example, the substrate is placed in a processing chamber maintained in a reduced pressure state. The substrate temperature is maintained at 100°C or higher and lower than 550°C, preferably 200°C or higher and 400°C or lower. Alternatively, the temperature of the substrate during the formation of the oxide semiconductor layer 144 is set to: The temperature may be room temperature. Then, the moisture in the processing chamber is removed, and the steam from which hydrogen, water, etc. are removed is A sputtering gas is introduced, and the oxide semiconductor layer 144 is formed using the target. By forming the oxide semiconductor layer 144 while heating, This can reduce impurities and damage caused by sputtering. To remove moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, ion pump, or titanium sublimation pump can be used. Alternatively, a turbo pump with a cold trap may be used. By using a pump or other device to evacuate the chamber, hydrogen and water can be removed. Therefore, the impurity concentration in the oxide semiconductor layer 144 can be reduced.

[0091] The oxide semiconductor layer 144 is formed under the conditions, for example, when the distance between the substrate and the target is 1 70 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen flow rate Argon (argon flow rate 100%) atmosphere, or acid The conditions that can be applied are a mixed atmosphere of hydrogen and argon. When using a DC power supply, the powdery substances (also called particles or dust) formed during film formation are removed. The thickness of the oxide semiconductor layer 144 is preferably 1n. 1 nm or more and 50 nm or less, preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 1 By using the oxide semiconductor layer 144 having such a thickness, it is possible to reduce the size of the oxide semiconductor layer 144. However, the short channel effect can be suppressed depending on the oxide semiconductor material and The appropriate thickness varies depending on the application of the semiconductor device, and the thickness is determined depending on the material used, the application, etc. You can also choose depending on the situation.

[0092] Before the oxide semiconductor layer 144 is formed by sputtering, argon gas is introduced. Then, reverse sputtering is performed to generate plasma, and the deposition of the formation surface (for example, the surface of the insulating layer 138) is performed. Here, the reverse sputtering is a method of removing the deposits in a normal sputtering process. Instead of bombarding the sputtering target with ions, the ions are bombarded on the surface to be treated. This refers to a method of modifying the surface by bombarding the surface with ions. The method involves applying a high frequency voltage to the surface to be treated in an argon atmosphere, creating a plasma near the substrate. In addition, nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. The atmosphere may be applied.

[0093] After that, the oxide semiconductor layer 144 is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (including water and a hydroxyl group) from the oxide semiconductor layer 144. ) to improve the structure of the oxide semiconductor layer and reduce the defect level in the energy gap. The temperature of the first heat treatment can be, for example, 300°C or higher and lower than 550°C, or 40 The temperature must be between 0℃ and 500℃.

[0094] The heat treatment is carried out by, for example, placing the object to be treated in an electric furnace using a resistance heating element, and heating the object in a nitrogen atmosphere. The heat treatment can be performed under conditions of 450° C. and 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the air. Do not allow leakage and prevent contamination with water or hydrogen.

[0095] Heat treatment equipment is not limited to electric furnaces, and may be heat conduction or heat radiation from a medium such as heated gas. For example, a device for heating the object to be treated may be used. pid Thermal Anneal equipment, GRTA (Gas Rapid The RTA (Rapid Thermal Anneal) equipment ) equipment can be used. The LRTA equipment uses halogen lamps, metal halide lamps, etc. , xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas used is argon. or an inert gas such as nitrogen that does not react with the material to be treated by heat treatment. It is used.

[0096] For example, in the first heat treatment, the workpiece is placed in a heated inert gas atmosphere and heated for several minutes. After the heating, the object to be treated may be taken out of the inert gas atmosphere and subjected to GRTA treatment. GRTA treatment allows high-temperature heat treatment in a short time. It is possible to apply this method even under temperature conditions exceeding 100°C. During the treatment, an inert gas is used instead of oxygen. By performing the first heat treatment in an atmosphere containing oxygen, This is because it is possible to reduce defect levels in the energy gap caused by oxygen deficiency. .

[0097] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing ) as the main component and not containing water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into a heat treatment device Purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0098] In either case, the first heat treatment reduces impurities and produces an i-type (intrinsic semiconductor) or i-type By forming the oxide semiconductor layer 144 that is as close to the This can be realized.

[0099] By the way, the above-mentioned heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc. This heat treatment can also be called a dehydration treatment or a dehydrogenation treatment. The dehydrogenation treatment is performed after the formation of an oxide semiconductor layer, after the formation of a gate insulating layer, or after the formation of a gate electrode. It is also possible to carry out the dehydration treatment at a timing such as after the dehydration treatment. The hydrogenation treatment may be carried out not only once but also multiple times.

[0100] Next, the gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144 (see FIG. 3C). The gate insulating layer 146 can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 146 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like. tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (Hf SixOy(x>0, y>0)), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0)), nitrogen-doped hafnium aluminate (H fAl x O y N z (x>0, y>0, z>0) The gate insulating layer 146 may have a single layer structure or a stacked layer structure. There is no particular limitation on the thickness, but when miniaturizing semiconductor devices, the thickness is determined based on the operation of the transistor. For example, when using silicon oxide, it is desirable to make it thin to ensure 1n The thickness can be set to m or more and 100 nm or less, preferably 10 nm or more and 50 nm or less.

[0101] As described above, when the gate insulating layer 146 is thinned, the gate resistance due to the tunneling effect or the like is reduced. To solve the gate leakage problem, the gate insulating layer 146 is provided with an oxide film. Hf, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy( x>0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x >0, y>0, z>0), nitrogen-doped hafnium aluminate (HfAl x O y N z (x>0, y>0, z>0)) By using a high-k material for the gate insulating layer 146, the electrical characteristics are maintained while It is possible to increase the film thickness to suppress gate leakage. a film containing a material, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, It may have a laminated structure with a film containing either aluminum oxide or the like.

[0102] After the gate insulating layer 146 is formed, a second thermal treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. When the gate insulating layer 146 contains oxygen, the oxide semiconductor layer 144 Oxygen is supplied to the oxide semiconductor layer 144 to compensate for oxygen vacancies in the oxide semiconductor layer 144, thereby forming an i-type (intrinsic) or Alternatively, an oxide semiconductor layer that is as close to i-type as possible can be formed.

[0103] In this embodiment, the second heat treatment is performed after the gate insulating layer 146 is formed. The timing of the second heat treatment is not particularly limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. Alternatively, the second heat treatment may be performed after the first heat treatment. The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. It's okay to let them sleep.

[0104] Next, a gate electrode is formed on the gate insulating layer 146 in a region overlapping with the oxide semiconductor layer 144. The gate electrode 148a is formed on the gate insulating layer 146 (see FIG. 3(D)). After forming a conductive layer on the substrate, the conductive layer is selectively etched to form the insulating layer. The conductive layer that becomes the gate electrode 148a can be formed by a PVD method such as a sputtering method. The source electrode can be formed by a CVD method such as a plasma CVD method. The same applies to the drain electrode 142a, etc., and the descriptions therefor can be taken into consideration. When the gate electrode 148a is formed, the electrode 14 of the capacitor element 164 in the previous embodiment is 8b can be formed together.

[0105] Next, an interlayer insulating layer 150 and an interlayer insulating layer 151 are formed on the gate insulating layer 146 and the gate electrode 148a. An insulating layer 152 is formed (see FIG. 3(E)). can be formed by using a PVD method, a CVD method, etc. Also, silicon oxide, oxynitride, etc. Inorganic materials such as silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide The insulating film can be formed using a material containing an insulating material. However, one embodiment of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of three or more layers. It is not necessary to provide

[0106] It is desirable that the interlayer insulating layer 152 be formed so that its surface is flat. By forming the interlayer insulating layer 152 so that the surface is flat, it is possible to Even in such a case, electrodes, wiring, and the like can be suitably formed on the interlayer insulating layer 152. The interlayer insulating layer 152 can be planarized by a method such as CMP (chemical mechanical polishing). This can be done using the method.

[0107] Through the above steps, the transistor 162 including the highly purified oxide semiconductor layer 144 is completed. (See Figure 3(E)).

[0108] The transistor 162 illustrated in FIG. 3E includes an oxide semiconductor layer 144 and an oxide semiconductor layer 14 4, a source electrode or drain electrode 142a electrically connected to the source electrode or drain electrode 142b. The oxide semiconductor layer 144, the source electrode or drain electrode 142a, and the a gate insulating layer 146 covering the source or drain electrode 142b; The gate electrode 148a on the upper side, the gate insulating layer 146 and the interlayer insulating layer on the gate electrode 148a The insulating layer 150 includes an insulating interlayer 152 on the insulating interlayer 150 .

[0109] In the transistor 162 described in this embodiment, the oxide semiconductor layer 144 is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5x 10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 below The carrier density of the oxide semiconductor layer 144 is 1 / 2 times that of a general silicon wafer. The carrier density (1×10 14 / cm 3 A sufficiently small value (e.g., 1 x10 12 / cm 3 less than 1.45 x 10 10 / cm 3 (less than) This results in a sufficiently small off-state current. The off-state current density (off-state current divided by the transistor channel width) is 10 zA / μm to 100zA / μm (1zA (zeptoampere) is 1×10 -21 A) It will be about the same.

[0110] By using the oxide semiconductor layer 144 that has been highly purified and made intrinsic, The off-state current of the transistor can be sufficiently reduced. This makes it possible to obtain a semiconductor device that can retain stored data for an extremely long period of time.

[0111] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0112] (Embodiment 3) In this embodiment, a transistor using an oxide semiconductor (particularly, an oxide semiconductor having an amorphous structure) is used. A method for manufacturing the transistor will be described with reference to FIG. This can be used in place of the transistor 162 in the embodiment. The transistor according to the embodiment has a part of the configuration in common with the transistor according to the previous embodiment. Therefore, the following mainly focuses on the differences. The explanation will be given using a top-gate transistor as an example. This is not limited to the T type.

[0113] First, an insulating layer 202 is formed on a substrate 200. Then, an oxide semiconductor is formed on the insulating layer 202. A layer 206 is formed (see FIG. 4(A)).

[0114] The substrate 200 may be, for example, the substrate 200 in the previous embodiment.

[0115] The insulating layer 202 corresponds to the insulating layer 138 in the previous embodiment and functions as a base. The above embodiment can be referred to for details. It is also possible to

[0116] The oxide semiconductor layer 206 corresponds to the oxide semiconductor layer 144 in the previous embodiment. For details of materials, manufacturing methods, and other details that can be used, please refer to the previous embodiments. do.

[0117] In this embodiment, the amorphous oxide semiconductor layer 206 is made of an In—Ga—Zn—O-based metal. It is formed by sputtering using a metal oxide target.

[0118] Next, the oxide semiconductor layer 206 is processed by a method such as etching using a mask. An island-shaped oxide semiconductor layer 206a is formed.

[0119] The oxide semiconductor layer 206 can be etched by either dry etching or wet etching. Of course, both of them can be used in combination. The etching conditions (etching time) are adjusted to suit the material so that the layer can be etched into the desired shape. The etching gas, etching solution, etching time, temperature, etc. are set appropriately.

[0120] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), Carbon (CCl4, etc.). Also, gases containing fluorine (fluorine-based gases, such as tetrafluoride Carbon (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane ( CHF3), hydrogen bromide (HBr), oxygen (O2), and helium (He ), or a gas to which a rare gas such as argon (Ar) is added, may also be used.

[0121] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the workpiece side) The amount of power to be used, the electrode temperature on the workpiece side, etc. are set appropriately.

[0122] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. That's fine.

[0123] The end portions of the oxide semiconductor layer 206a are preferably etched to have a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The taper angle is the angle at which a layer having a tapered shape (for example, the oxide semiconductor layer 206a) is formed. When observed from a direction perpendicular to the cross section (a plane perpendicular to the surface of the workpiece), the side of the layer The inclination angle between the bottom surface and the oxide semiconductor layer 206a is shown. By etching, the source electrode or drain electrode 208a, which will be formed later, The coverage of the source electrode or drain electrode 208b is improved, and step disconnection can be prevented. .

[0124] After that, the oxide semiconductor layer 206a is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (water or hydroxyl groups) from the oxide semiconductor layer 206a. The structure of the oxide semiconductor layer is adjusted to reduce the defect level in the energy gap. For details, please refer to the previous embodiment. In addition, when the heat treatment (first heat treatment) is performed after etching, wet etching is used. Even if the etching rate is high, etching can be performed at a high rate. This has the advantage of reducing the time required for etching.

[0125] The first heat treatment is performed on the oxide semiconductor layer 206 before it is processed into the island-shaped oxide semiconductor layer 206a. In this case, the substrate 200 is removed from the heating device after the first heat treatment. The wafer is then taken out and subjected to a photolithography process.

[0126] By the way, the above-mentioned heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc. This heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, or the like. The hydrogenation treatment is performed after the oxide semiconductor layer is formed or after a source electrode or a is formed after the drain electrode is laminated and after the gate insulating layer is formed. In addition, such dehydration and dehydrogenation treatments can be carried out not only once but also multiple times. You can go several times.

[0127] Next, a conductive layer is formed in contact with the oxide semiconductor layer 206a. The source or drain electrode 208a, the source or drain electrode A conductive layer, a source electrode, or a drain electrode is formed (see FIG. 4(B)). The electrode 208a, the source electrode or the drain electrode 208b, and other details are the same as those in the previous embodiment. Please refer to the description of the conductive layer, source electrode, drain electrode, etc. in the embodiments. .

[0128] Next, a gate insulating layer 212 is formed in contact with a part of the oxide semiconductor layer 206a (FIG. 4(C) For details of the gate insulating layer 212, see the gate insulating layer Please refer to the descriptions regarding the above.

[0129] After the gate insulating layer 212 is formed, a second thermal treatment is performed in an inert gas atmosphere or an oxygen atmosphere. It is desirable to perform the second heat treatment. For details of the second heat treatment, please refer to the previous embodiment. .

[0130] In this embodiment, the second heat treatment is performed after the gate insulating layer 212 is formed. The timing of the second heat treatment is not particularly limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. The heat treatment of 2 may be carried out.

[0131] Next, a gate electrode was formed on the gate insulating layer 212 in a region overlapping with the oxide semiconductor layer 206a. The gate electrode 214 is formed on the gate insulating layer 212 (see FIG. 4(D)). After forming a conductive layer, the conductive layer is selectively patterned to form the insulating film. For details, the above-described embodiment may be referred to. At this time, the electrodes of the capacitor element in the previous embodiment can also be formed.

[0132] Next, an interlayer insulating layer 216 and an interlayer insulating film 218 are formed on the gate insulating layer 212 and the gate electrode 214. An edge layer 218 is formed (see FIG. 4(E)). For details, the above embodiment may be referred to. The interlayer insulating layer does not necessarily have to be provided.

[0133] As a result, a transistor using the oxide semiconductor layer 206a with a highly purified amorphous structure was obtained. The oxide semiconductor layer 250 is completed (see FIG. 4(E)). There may be a small amount of crystalline components in 206a.

[0134] By using the oxide semiconductor layer 206a that has been highly purified and made intrinsic, The off-state current of the transistor can be sufficiently reduced. This allows for a semiconductor device that can retain memory contents for an extremely long period of time. .

[0135] In this embodiment, a top-gate transistor is used, and a source electrode and a drain electrode are formed on the top-gate transistor. The structure in which the lower part of the drain electrode and the upper part of the oxide semiconductor layer are in contact with each other has been described. The transistors to which the configuration of the embodiment can be applied are not limited to this. a source electrode and a drain electrode, and an oxide semiconductor layer A part of the configuration of this embodiment is applied to a configuration in which the upper and lower portions are in contact with each other (such as the configurations shown in FIGS. 1 and 3). Also, a bottom gate transistor can be used. The bottom of the drain electrode is in contact with the top of the oxide semiconductor layer, and a bottom-gate transistor is also used. A transistor having an upper portion of a source electrode and a drain electrode and a lower portion of an oxide semiconductor layer. A part of the configuration of this embodiment can also be applied to a configuration in which the That is, various transistors including an oxide semiconductor having an amorphous structure can be realized according to this embodiment. can be realized

[0136] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0137] (Fourth embodiment) In this embodiment, a method for manufacturing a transistor using an oxide semiconductor will be described with reference to FIGS. In this embodiment, a first oxide semiconductor layer having a crystalline region is used as the oxide semiconductor layer. a semiconductor layer and a second oxide semiconductor layer formed by crystal growth from the crystalline region of the first oxide semiconductor layer; The transistor in question is the same as that in the previous embodiment. This can be used in place of the transistor 162. The transistor has a part of the configuration in common with the transistor according to the previous embodiment. Therefore, the following mainly describes the differences.

[0138] In addition, if the necessary thickness can be ensured by the first oxide semiconductor layer alone, the second oxide semiconductor layer In the following, a top-gate type transistor will be used as an example. However, the transistor configuration is not limited to the top gate type.

[0139] First, an insulating layer 302 is formed on a substrate 300. Then, a first oxide film is formed on the insulating layer 302. forming a first oxide semiconductor layer, and performing a first heat treatment to form a first oxide semiconductor layer including a surface of the first oxide semiconductor layer; The region containing the oxide semiconductor layer 304 is crystallized to form the first oxide semiconductor layer 304 (see FIG. 5A).

[0140] For details of the substrate 300, the previous embodiment can be referred to.

[0141] The insulating layer 302 functions as a base. The details of the insulating layer 302 are also the same as those in the previous embodiment. Note that a structure in which the insulating layer 302 is not provided may be used.

[0142] The first oxide semiconductor layer is formed in a manner similar to that of the oxide semiconductor layer in the above embodiment. Therefore, the first oxide semiconductor layer and the method for forming the first oxide semiconductor layer will be described in detail below. However, in this embodiment, the first heat treatment In order to intentionally crystallize the oxide semiconductor layer, an oxide semiconductor that is easily crystallized is used. It is desirable to form a first oxide semiconductor layer. For example, ZnO can be mentioned. In-Ga-Zn-O based oxide semiconductors can also be mentioned. For example, a high concentration of Zn tends to crystallize, and metal elements (In, Ga, and Z) In n), the proportion of Zn in the alloy is 60 atom % or more, which is not desirable for this purpose. The thickness of the first oxide semiconductor layer is preferably greater than or equal to 1 nm and less than or equal to 10 nm. In this embodiment, the thickness is set to 3 nm as an example. The appropriate thickness varies depending on the material and the application of the semiconductor device. The selection may be made depending on the application.

[0143] The temperature of the first heat treatment is 550°C or higher and 850°C or lower, preferably 600°C or higher and 750°C or lower. The heat treatment time should preferably be between 1 minute and 24 hours. The temperature and time of the heat treatment vary depending on the type of oxide semiconductor.

[0144] The atmosphere for the first heat treatment is preferably an atmosphere that does not contain hydrogen, water, or the like. For example, nitrogen, oxygen, and rare gases (helium, neon, argon, etc.) from which water has been sufficiently removed. It can be an atmosphere.

[0145] Heat treatment equipment includes electric furnaces, as well as equipment that uses heat conduction from a medium such as heated gas or heat radiation. For example, a device for heating the object to be treated can be used. Rapid Thermal Anneal (GRTA) equipment, Gas Rapid Th RTA (Rapid Thermal Anneal) equipment l) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a The GRTA device is a device that performs heat treatment using high-temperature gas. Inert gases that do not react with the material to be treated by heat treatment, such as rare gases such as fluorine or nitrogen. is used.

[0146] By the first heat treatment, at least a region including the surface of the first oxide semiconductor layer is crystalline. The crystalline region extends from the surface of the first oxide semiconductor layer to the inside of the first oxide semiconductor layer. The crystalline region is formed by the progress of crystal growth toward the It may contain plate-like crystals with an average thickness of 1 nm to 10 nm. The oxide semiconductor layer may contain crystals whose c-axes are oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer. Here, "substantially parallel" refers to a state within ±10° from the parallel direction, and "substantially perpendicular" refers to a state within ±10° from the perpendicular direction. This refers to a state within ±10° of the direction.

[0147] Furthermore, the first heat treatment forms a crystalline region and also removes hydrogen from the first oxide semiconductor layer. It is desirable to remove hydrogen and other substances (including water and hydroxyl groups). Nitrogen and acid with a purity of 6N (99.9999%) or more (i.e., impurity concentration of 1 ppm or less) The first heat treatment is preferably performed in a nitrogen or rare gas (helium, neon, argon, etc.) atmosphere. More preferably, the purity is 7N (99.99999%) or more (i.e., the concentration of impurities is 0.1 In addition, it is preferable to use an ultra-dry atmosphere with H2O of 20 ppm or less. Alternatively, the first heat treatment may be carried out in ultra-dry air with an H2O concentration of 1 ppm or less.

[0148] Furthermore, the first heat treatment is performed to form a crystalline region and to supply oxygen to the first oxide semiconductor layer. For example, by using an oxygen atmosphere for the heat treatment, the first oxidation Oxygen can be supplied to the compound semiconductor layer.

[0149] In this embodiment, the first heat treatment is performed at 700° C. for 1 hour in a nitrogen atmosphere. After removing hydrogen and the like from the oxide semiconductor layer, the atmosphere was switched to an oxygen atmosphere. Oxygen is supplied to the inside of the oxide semiconductor layer. Note that the main purpose of the first heat treatment is to form a crystalline region. Since the structure is such that hydrogen removal and oxygen supply can be performed separately, For example, after heat treatment to remove hydrogen, etc., or treatment to supply oxygen, It is possible to carry out a heat treatment for crystallization.

[0150] By such a first heat treatment, a crystalline region is formed and hydrogen (including water and hydroxyl groups) is removed. The oxygen-supplied first oxide semiconductor layer is obtained.

[0151] Next, a first oxide semiconductor layer 304 having a crystalline region at least in a region including a surface thereof is formed with a A second oxide semiconductor layer 305 is formed (see FIG. 5B). If the necessary thickness can be ensured by the layer 304 alone, the second oxide semiconductor layer 305 is not necessary. In this case, the step of forming the second oxide semiconductor layer 305 can be omitted.

[0152] The second oxide semiconductor layer 305 is formed in a manner similar to that of the oxide semiconductor layer in the above embodiment. Therefore, the second oxide semiconductor layer 305 and a method for forming the second oxide semiconductor layer 305 will be described in detail below. The above embodiment can be referred to for the second oxide semiconductor layer 305. It is desirable to form the first oxide semiconductor layer 304 thicker than the first oxide semiconductor layer 304. The sum of the thicknesses of the oxide semiconductor layer 304 and the second oxide semiconductor layer 305 is preferably 1 nm or more and 50 nm or less. The second oxide semiconductor layer 305 can be formed to a thickness of 1 nm to 10 nm. In this embodiment, the thickness is set to 7 nm as an example. The appropriate thickness varies depending on the conductor material and the application of the semiconductor device. The material may be selected depending on the material and application.

[0153] The second oxide semiconductor layer 305 is made of a material having the same main component as the first oxide semiconductor layer 304. Therefore, it is desirable to use materials with close lattice constants after crystallization (mismatch of 1% or less). When such a material is used, the second oxide semiconductor layer 305 is crystallized. This facilitates crystal growth using the crystalline region of the first oxide semiconductor layer 304 as a seed. Furthermore, when the materials are the same main component, the interface properties and electrical characteristics are also improved.

[0154] If the desired film quality can be obtained by crystallization, a second film may be formed using a material with a different main component. Alternatively, the oxide semiconductor layer 305 may be formed as follows.

[0155] Next, the second oxide semiconductor layer 305 is subjected to a second heat treatment, and the first oxide semiconductor layer 304 The crystalline region is used as a seed for crystal growth to form a second oxide semiconductor layer 306 (FIG. 5( When the second oxide semiconductor layer 305 is not formed, this step can be omitted. can.

[0156] The temperature of the second heat treatment is 550°C or higher and 850°C or lower, preferably 600°C or higher and 750°C or lower. The heating time for the second heat treatment is 1 minute or more and 100 hours or less, preferably 5 hours or more. The heat treatment time is set to 20 hours or less, typically 10 hours. It is desirable that the atmosphere used for the process does not contain hydrogen, water, etc.

[0157] The details of the atmosphere and the effects of the heat treatment are the same as those of the first heat treatment. The heat treatment apparatus that can perform this is the same as that for the first heat treatment. The inside of the furnace is sometimes in a nitrogen atmosphere, and when cooling, the inside of the furnace is in an oxygen atmosphere. Hydrogen and the like can be removed in the atmosphere, and oxygen can be supplied in the oxygen atmosphere.

[0158] By performing the second heat treatment as described above, the oxide semiconductor layer 304 formed in the first oxide semiconductor layer 304 Crystal growth is promoted from the crystalline region to the entire second oxide semiconductor layer 305, and the second oxide semiconductor A conductor layer 306 can be formed. In addition, hydrogen (including water and hydroxyl groups) and the like are removed. In this case, the second oxide semiconductor layer 306 to which oxygen is supplied can be formed. The heat treatment can also improve the orientation of the crystalline region of the first oxide semiconductor layer 304. be.

[0159] For example, an In—Ga—Zn—O-based oxide semiconductor material is used for the second oxide semiconductor layer 306. In this case, the second oxide semiconductor layer 306 is InGaO3 (ZnO) m (m: What is a natural number? (In:Ga:Zn:O=2:2:) and In2Ga2ZnO7 (In:Ga:Zn:O=2:2: Such crystals may include crystals having a crystal ratio of 1:7 (atom ratio). According to the theory, the c-axis of the second oxide semiconductor layer 306 is aligned in a direction substantially perpendicular to the surface of the second oxide semiconductor layer 306. Orients to.

[0160] Here, the above-mentioned crystal has a lattice structure parallel to the a-axis and b-axis. Each layer contains either In, Ga, or Zn. Specifically, the crystal described above is composed of a layer containing In and a layer not containing In (Ga or a layer containing Zn) are stacked in the c-axis direction.

[0161] In the case of In-Ga-Zn-O based oxide semiconductor crystals, the in-plane direction of the layer containing In, That is, the conductivity in the direction parallel to the a-axis and b-axis is good. In a-Zn-O oxide semiconductor crystals, electrical conduction is mainly controlled by In. The 5s orbital of one In atom overlaps with the 5s orbital of the adjacent In atom, resulting in a carrier This is due to the formation of apses, etc.

[0162] In addition, the first oxide semiconductor layer 304 may have an amorphous region at the interface with the insulating layer 302. In the case of the structure, the second heat treatment is performed to form a thin film on the surface of the first oxide semiconductor layer 304. Crystal growth proceeds from the crystalline region toward the bottom of the first oxide semiconductor layer 304. In some cases, the amorphous region may be crystallized. Depending on the processing conditions, the amorphous regions may remain.

[0163] In addition, the first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 are made of oxides having the same main component. When an oxide semiconductor material is used, as shown in FIG. 5(C), a first oxide semiconductor layer 304 and The second oxide semiconductor layer 306 may have the same crystal structure as the first oxide semiconductor layer 304. In (C), the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 are shown by the dotted line. The boundary between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 becomes indistinguishable. can sometimes be considered to be the same layer.

[0164] Next, the first oxide semiconductor layer 304 and the The second oxide semiconductor layer 306 is processed to form the island-shaped first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b. A second oxide semiconductor layer 306a is formed (see FIG. 5D). After the treatment, processing into an island-shaped oxide semiconductor layer is performed. After processing, a second heat treatment may be performed. In this case, when wet etching is used, Even if the etching rate is high, etching can be performed. This has the advantage of reducing the time required for testing.

[0165] The etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 is performed using a driver. Either dry etching or wet etching may be used. The material can be used in combination so that the oxide semiconductor layer can be etched into a desired shape. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are adjusted to suit the material. ) is set appropriately. The etching can be performed in a manner similar to that of the oxide semiconductor layer in the above embodiment. For details, please refer to the above embodiment.

[0166] Note that a region of the oxide semiconductor layer that serves as a channel formation region has a flat surface. For example, it is desirable that the peak-to-valley (PV) of the surface of the second oxide semiconductor layer 306 is In the region overlapping with the gate electrode (channel forming region), the thickness is 1 nm or less (preferably 0.5 nm It is preferable that the height difference is, for example, 10 μm×10 μm. It can be measured in the area.

[0167] Next, a conductive layer is formed in contact with the second oxide semiconductor layer 306a. The conductive layer is selectively etched to form the source or drain electrode 308a, the source or drain electrode 308b, For details, refer to the previous embodiment. Just take the form into consideration.

[0168] Note that in the step shown in FIG. 5D, the first oxide semiconductor layer 304a or the second oxide semiconductor layer The source or drain electrode 308a of the semiconductor layer 306a The crystalline layer in contact with the electrode 308b may become amorphous. Not all regions of the oxide semiconductor layer 304a and the second oxide semiconductor layer 306a are crystalline. .

[0169] Next, a gate insulating layer 312 is formed in contact with a part of the second oxide semiconductor layer 306a. The above embodiment may be referred to for details. A gate electrode is formed in a region overlapping with the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a. Then, a layer is formed on the gate insulating layer 312 and the gate electrode 314. An interlayer insulating layer 316 and an interlayer insulating layer 318 are formed (see FIG. 5(E)). , the previous embodiments may be referred to.

[0170] After the gate insulating layer 312 is formed, a third heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the third heat treatment is preferably 200°C or higher and 450°C or lower. The temperature is 250°C or higher and 350°C or lower. For example, By performing the third heat treatment, the electrical characteristics of the transistor are improved. In addition, when the gate insulating layer 312 is an insulating layer containing oxygen, In this case, oxygen can be supplied to the second oxide semiconductor layer 306a.

[0171] In this embodiment, the third heat treatment is performed after the gate insulating layer 312 is formed. The timing of the third heat treatment is not limited to this. In addition, the timing of the third heat treatment may be set to other treatments such as the second heat treatment. Therefore, when oxygen is supplied to the second oxide semiconductor layer 306a, the third heat treatment can be omitted. It can be abbreviated.

[0172] In this manner, the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a were formed. The used transistor 350 is completed (see FIG. 5(E)).

[0173] The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are thus highly purified and made intrinsic. By using the compound semiconductor layer 306a, the off-state current of the transistor can be sufficiently reduced. By using such transistors, it is possible to retain memory contents for an extremely long period of time. Thus, a semiconductor device that can be held is obtained.

[0174] In this embodiment, a top-gate transistor is used, and a source electrode and a drain electrode are formed on the top-gate transistor. The structure in which the lower part of the drain electrode and the upper part of the oxide semiconductor layer are in contact with each other has been described. The transistors to which the configuration of the embodiment can be applied are not limited to this. a source electrode and a drain electrode, and an oxide semiconductor layer A part of the configuration of this embodiment is applied to a configuration in which the upper and lower portions are in contact with each other (such as the configurations shown in FIGS. 1 and 3). Also, a bottom gate transistor can be used. The bottom of the drain electrode is in contact with the top of the oxide semiconductor layer, and a bottom-gate transistor is also used. A transistor having an upper portion of a source electrode and a drain electrode and a lower portion of an oxide semiconductor layer. A part of the configuration of this embodiment can also be applied to a configuration in which the That is, according to this embodiment, various transistors including an oxide semiconductor layer having a crystalline region can be fabricated. This can be realized.

[0175] Furthermore, in this embodiment, the oxide semiconductor layer is a first oxide semiconductor having a crystalline region. The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are grown as crystals from the crystalline region of the first oxide semiconductor layer 304a. The use of the oxide semiconductor layer 306a improves the field effect mobility and provides good electrical characteristics. For example, a transistor having a field effect mobility μ > 100 cm can be realized. 2 This allows various logic circuits that require high-speed operation to be realized. The above transistor can also be applied to the above.

[0176] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0177] (Embodiment 5) In this embodiment, a method for manufacturing a transistor using an oxide semiconductor will be described with reference to FIGS. The transistor in question replaces the transistor 162 in the previous embodiment. The transistor according to this embodiment can be used in various ways. The configuration is the same as that of the transistor according to the previous embodiment. In the following, we will use a top-gate transistor as an example. As will be explained, the transistor configuration is not limited to the top gate type.

[0178] First, an insulating layer 402 is formed on a substrate 400. Then, an oxide semiconductor is formed on the insulating layer 402. The layer 406 is formed (see FIG. 6(A)). For details, please refer to the above embodiment. good.

[0179] Next, the oxide semiconductor layer 406 is processed by a method such as etching using a mask. An island-shaped oxide semiconductor layer 406a is formed, and a conductive film is formed to cover the oxide semiconductor layer 406a. An insulating layer 410 is formed on the conductive layer 408 (see FIG. 6(B)). Although it is not a necessary component, it can be used to selectively attach the side of the source electrode or drain electrode to be formed later. In addition, it is effective to oxidize the gate electrode and the source or drain electrode. This is also effective in reducing the capacitance between the

[0180] For details of the formation of the island-shaped oxide semiconductor layer 406a, the heat treatment, and the like, see the above embodiment. The above embodiment can be referred to for details of the conductive layer 408. That's fine.

[0181] The insulating layer 410 can be formed by a CVD method, a sputtering method, or the like. The insulating layer 410 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or oxide. It is preferable to form the insulating layer 4 so as to contain hafnium oxide, tantalum oxide, etc. The insulating layer 410 may have a single layer structure or a multilayer structure. Although not limited, it can be, for example, 10 nm or more and 200 nm or less.

[0182] The conductive layer 408 and insulating layer 410 are then selectively etched to form source or drain electrodes. A drain electrode 408a, a source or drain electrode 408b, an insulating layer 410a, an insulating layer 410b is formed (see FIG. 6(C)). The process is the same as the process for forming the drain electrode. Materials such as copper are suitable for subsequent plasma oxidation processes and are suitable for source or drain electrodes. It is suitable as a material for the source electrode 408a, the source electrode or the drain electrode 408b, etc.

[0183] Next, oxidation treatment is performed to supply oxygen to the oxide semiconductor layer 406a (see FIG. 6D). By this oxidation treatment, a part of the source electrode or the drain electrode 408a (particularly, its The oxide region 411a is formed on the side surface of the source electrode or drain electrode 408b. An oxidized region 411b is formed in a part of the substrate (particularly the part corresponding to the side surface) (FIG. 6(D) )). In addition, the oxidation treatment can be performed to remove the source electrode or drain electrode 408a and the An oxidized region is also formed on the outer periphery of the source or drain electrode 408b.

[0184] The oxidation process is carried out by using oxygen plasma excited by microwaves (300MHz to 300GHz). It is preferable to use an oxidation treatment using microwaves (plasma oxidation treatment). By exciting the plasma, a high density plasma is realized, and damage to the oxide semiconductor layer 406a is prevented. This is because the page size can be sufficiently reduced.

[0185] More specifically, for example, the frequency is 300 MHz to 300 GHz (typically 2.45 GHz). Hz), pressure is 50 Pa to 5000 Pa (typically 500 Pa), and the temperature of the workpiece is 2 The temperature is set to 00 to 400°C (typically 300°C), and the above-mentioned Processing can be performed.

[0186] By the oxidation treatment, oxygen is supplied to the oxide semiconductor layer 406a. The damage to the oxide semiconductor layer 406a is sufficiently reduced while the energy loss due to oxygen deficiency is reduced. In other words, the defect states in the oxide semiconductor layer 406a can be reduced. The characteristics can be further improved.

[0187] Note that the oxide semiconductor layer 406 can be formed by the oxidation treatment while sufficiently reducing damage to the oxide semiconductor layer 406a. If there is a method that can supply oxygen to a, it can be used for plasma oxidation treatment using microwaves. For example, a method such as heat treatment in an oxygen-containing atmosphere can be used. do.

[0188] In addition to the oxidation treatment, a treatment for removing water, hydrogen, and the like from the oxide semiconductor layer 406a may be performed. In this case, for example, a plasma treatment using a gas such as nitrogen or argon may be performed. It can be used.

[0189] The oxidized regions 411a and 411b formed by the above oxidation treatment are When the transistor 450 is miniaturized (for example, when the channel length is less than 1000 nm), As transistors become smaller, the gate insulating layer is becoming increasingly The thickness of the gate insulating layer needs to be reduced, but the presence of the oxide region makes it possible to reduce the thickness. The gate electrode and the source electrode or the drain electrode may be separated due to patterning or poor coverage. This is because it is possible to prevent short circuits of the silicon electrodes. A thickness of at least 10 nm is sufficient to be effective.

[0190] The oxidation treatment is also effective in improving the film quality of the exposed insulating layer 402 .

[0191] The source electrode or drain electrode 408a and the source electrode or drain electrode 408 The insulating layer 410a and the insulating layer 410b have an important role in preventing oxidation of the upper part of the insulating layer 410a. It is necessary to perform the above plasma treatment while leaving the mask used for etching. This is because it involves great difficulties.

[0192] Next, a gate insulating layer 406a was formed in contact with part of the oxide semiconductor layer 406a without being exposed to the air. Then, a gate insulating layer 412 is formed so as to overlap with the oxide semiconductor layer 406a over the gate insulating layer 412. A gate electrode 414 is formed in the region, and a layer is formed on the gate insulating layer 412 and the gate electrode 414. An interlayer insulating layer 416 and an interlayer insulating layer 418 are formed (see FIG. 6(E)). , the previous embodiments can be referred to.

[0193] Through the above steps, the transistor 450 including an oxide semiconductor is completed.

[0194] In this embodiment, in order to supply oxygen to the oxide semiconductor layer 406a, Oxygen plasma treatment is performed on the 06a. This improves the characteristics of the transistor 450. In addition, the area corresponding to the side of the source electrode or drain electrode is oxidized. Therefore, the gate electrode- It is possible to prevent a short circuit between the source electrode (or the drain electrode). 11a, the oxide region 411b creates a moderate offset region, so that the oxide semiconductor The change in the electric field from the layer to the interface with the source electrode (or drain electrode) is kept low. It is also possible to

[0195] In addition, by providing an insulating layer on the source electrode and the drain electrode, The capacitance (parasitic capacitance) formed between the drain electrode and the gate electrode is reduced, and further High speed operation can be achieved.

[0196] In this embodiment, a top-gate transistor is used, and a source electrode and a drain electrode are formed on the top-gate transistor. The structure in which the lower part of the drain electrode and the upper part of the oxide semiconductor layer are in contact with each other has been described. The transistors to which the configuration of the embodiment can be applied are not limited to this. a source electrode and a drain electrode, and a gate insulating film formed on the gate insulating film of an oxide semiconductor layer. A part of the configuration of this embodiment can be applied to the configuration in which the upper portion is in contact with the lower portion. According to this embodiment, a semiconductor device including an oxide semiconductor to which oxygen is supplied, an electrode having an oxidized region, and the like can be fabricated. Various transistors including

[0197] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0198] (Embodiment 6) In this embodiment, an application example of the semiconductor device shown in the previous embodiment will be described with reference to FIGS. 7 and 8. This will be used to explain.

[0199] 7(A) and 7(B) are diagrams illustrating the semiconductor device shown in FIG. 2(A-1) (hereinafter referred to as memory cell 1) 7A is a circuit diagram of a semiconductor device formed using a plurality of semiconductor devices (also referred to as 90). This is a circuit diagram of a so-called NAND type semiconductor device in which memory cells 190 are connected in series. FIG. 7B shows a so-called NOR type semiconductor device in which memory cells 190 are connected in parallel. FIG.

[0200] The semiconductor device shown in FIG. 7A includes a source line SL, a bit line BL, a first signal line S1, and m A second signal line S2, m word lines WL, and a plurality of memory cells 190(1, 1) to 19 0(m, 1) is arranged in a vertical array of m rows by 1 column. Although the configuration has one source line SL and one bit line BL, it is not limited to this. By having n source lines SL and n bit lines BL, the memory cell array has m vertical (rows) x n horizontal (columns) The memory cell array may have the above structure.

[0201] In each memory cell 190, the gate electrode of transistor 160 and the gate electrode of transistor 162 One of the source electrode and the drain electrode of the capacitor 164 is electrically connected to one of the electrodes of the capacitor 164. Also, the first signal line S1 and the source electrode or the drain electrode of the transistor 162 are connected. The other of the gate electrodes is electrically connected to the second signal line S2 and the gate of the transistor 162. The electrode of the capacitor 164 is electrically connected to the word line WL. The other is electrically connected.

[0202] The source electrode of the transistor 160 in the memory cell 190 is connected to the adjacent memory cell The drain electrode of the transistor 160 in the memory cell 190 is electrically connected to the drain electrode of the transistor 160 in the memory cell 190. The drain electrode of the transistor 160 is connected to the transistor of the adjacent memory cell 190. 160. However, the plurality of memory cells connected in series are electrically connected to the source electrode of the memory cell 160. The drain of the transistor 160 of the memory cell 190 provided at one end of the The electrode is electrically connected to a bit line. That is, the source electrode of the transistor 160 of the memory cell 190 provided at the other end is , and are electrically connected to the source line.

[0203] The semiconductor device shown in FIG. 7A performs writing and reading operations for each row. The write operation is performed as follows: Transistor 1 is connected to the second signal line S2 of the row to be written. 62 is applied with a potential to be turned on, and the transistor 162 of the row to be written is turned on. As a result, the gate electrodes of the transistors 160 in the specified row are connected to the first signal line S1. A potential is applied to the gate electrode, and a predetermined charge is applied to the gate electrode. Data can be written to the memory cells.

[0204] The read operation is performed as follows: First, the word lines WL other than the row from which the read is to be performed are connected. Therefore, the transistor 160 is turned on regardless of the charge on the gate electrode of the transistor 160. A potential is applied so that the transistors 160 in the rows other than the row to be read out are turned on. Then, the gate electrode of the transistor 160 is connected to the word line WL of the row to be read. The charge applied to the transistor 160 selects the on or off state. Then, a constant potential is applied to the source line SL, and a potential is applied to the bit line BL. The read circuit (not shown) connected to the source line SL is set to an operating state. The transistors 160 between the bit lines BL are in the on state except for the row to be read. The conductance between the source line SL and the bit line BL is 60. That is, the gate of the transistor 160 of the row to be read is determined by the The potential of the bit line BL read by the read circuit varies depending on the charge on the bit electrode. In this way, data can be read from the memory cells of a specified row.

[0205] The semiconductor device shown in FIG. 7B includes n source lines SL, bit lines BL, and first signal lines S. 1, m second signal lines S2 and word lines WL, and a plurality of memory cells 190(1, 1) ~190(m, n) are memory cells arranged in a matrix of m rows x n columns. The gate electrode of each transistor 160 and the gate electrode of the transistor 162 are connected to each other. One of the source electrode and the drain electrode is electrically connected to one of the electrodes of the capacitor 164. The source line SL and the source electrode of the transistor 160 are electrically connected. The bit line BL and the drain electrode of the transistor 160 are electrically connected. In addition, the first signal line S1 and the other of the source electrode and the drain electrode of the transistor 162 The second signal line S2 and the gate electrode of the transistor 162 are electrically connected. The word line WL and the other electrode of the capacitor element 164 are electrically connected. is connected to.

[0206] The semiconductor device shown in FIG. 7B performs writing and reading operations for each row. The write operation is performed in the same manner as in the semiconductor device shown in FIG. The read operation is performed as follows: First, a transistor 1 is connected to a word line WL other than the row where the read operation is performed. A potential is applied so that the transistor 160 is turned off regardless of the charge on the gate electrode of the transistor 60. Then, the transistors 160 other than the row to be read are turned off. The charge carried by the gate electrode of the transistor 160 is applied to the word line WL of the row in which the transistor 160 is to be applied. A potential (read potential) that selects the on or off state of the transistor 160 is applied. Then, a constant potential is applied to the source line SL, and the read The circuit (not shown) is set to an operating state. Here, the conduction between the source line SL and the bit line BL is The capacitance is determined by the state of the transistor 160 of the row being read. , the charge on the gate electrode of the transistor 160 in the row to be read out is The potential of the bit line BL read by the circuit is different. Data can be read from the memory cells.

[0207] Next, an example of a readout circuit that can be used in the semiconductor device shown in FIG. 7 will be described with reference to FIG. 8. This will be used to explain.

[0208] FIG. 8A shows a schematic diagram of the readout circuit. The readout circuit includes a transistor and a sense It has an amplifier circuit.

[0209] When reading, terminal A is connected to the bit line to which the memory cell to be read is connected. In addition, a bias potential Vbias is applied to the gate electrode of the transistor, and the potential at terminal A is The position is controlled.

[0210] The memory cell 190 exhibits different resistance values ​​depending on the data stored therein. When the transistor 160 of the selected memory cell 190 is in an on state, it is in a low resistance state. When the transistor 160 of the selected memory cell 190 is in an off state, it is in a high resistance state. .

[0211] When the memory cell is in a high resistance state, the potential at terminal A becomes higher than the reference potential Vref, and the sense The amplifier circuit outputs a potential (data "1") corresponding to the potential of terminal A. When the resistor is in a low resistance state, the potential at terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit The path outputs a potential (data "0") corresponding to the potential of terminal A.

[0212] In this way, data can be read from the memory cell by using the read circuit. Note that the read circuit of this embodiment is an example, and other known circuits may be used. Also, the read circuit may have a precharge circuit. Instead of the reference potential Vref, a reference bit line may be connected.

[0213] Fig. 8(B) shows a differential sense amplifier which is an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin(+ ) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output.

[0214] Fig. 8(C) shows a latch-type sense amplifier which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the control signal Sp is set to High and the control signal Sn is set to Low to cut off the power supply potential (Vdd ). Then, the potentials for comparison are applied to V1 and V2. After that, when the control signal Sp is set to Low and the control signal Sn is set to High to supply the power supply potential (Vdd), if the potentials V1in and V2in for comparison are in the relationship V1in > V2in, the output of V1 is High ​​​​​​​​​​​​​​​​(Embodiment 7) In this embodiment, an example of a semiconductor device including the transistor described in the above embodiment will be described. , which will be explained with reference to FIG.

[0217] Figure 9(A) shows a so-called DRAM (Dynamic Random Access Memory). An example of a semiconductor device having a structure corresponding to the memory cell array shown in FIG. The array 620 has a configuration in which a plurality of memory cells 630 are arranged in a matrix. The memory cell array 620 also has m first wirings and n second wirings. The memory cell 630 corresponds to the semiconductor device shown in FIG. In this embodiment, the first wiring in FIG. 2B is called a bit line BL, and the second wiring The wiring is called a word line WL.

[0218] The memory cell 630 includes a transistor 631 and a capacitor 632 . The gate electrode of the transistor 631 is connected to the first wiring (word line WL). In addition, one of the source electrode and the drain electrode of the transistor 631 is connected to the second wiring (bit line BL) and the other of the source electrode or the drain electrode of the transistor 631. is connected to one of the electrodes of the capacitor element. The other electrode of the capacitor element is connected to the capacitor line CL The transistor 631 is connected to the The transistor shown is applied.

[0219] The transistor described in the above embodiment has an extremely small off-state current. For this reason, the semiconductor device shown in FIG. 9(A) is recognized as a so-called DRAM. When applying such transistors, it is possible to obtain a substantially non-volatile memory.

[0220] Figure 9(B) shows a so-called SRAM (Static Random Access Memory) An example of a semiconductor device having a structure equivalent to that of a memory cell array shown in FIG. The memory cell 640 may have a configuration in which a plurality of memory cells 650 are arranged in a matrix. The memory cell array 640 also includes a first wiring (word line WL), a second wiring (bit line WL), The memory cell has a plurality of third wirings (inverted bit lines / BL) and a plurality of third wirings (inverted bit lines / BL).

[0221] The memory cell 650 includes a first transistor 651 to a sixth transistor 656. The first transistor 651 and the second transistor 652 are used as selection transistors. In addition, one of the third transistor 653 and the fourth transistor 654 The first transistor is an n-channel transistor (here, the fourth transistor 654), and the second transistor is a p-channel transistor. The third transistor 653 is a third channel transistor. The transistor 653 and the fourth transistor 654 form a CMOS circuit. Similarly, a fifth transistor 655 and a sixth transistor 656 form a CMOS circuit is configured.

[0222] A first transistor 651, a second transistor 652, a fourth transistor 654, The transistor 656 in the sixth embodiment is an n-channel transistor. The third transistor 653 and the fifth transistor 654 can be applied. The transistor 655 is a p-channel transistor made of an oxide semiconductor or other The insulating film can be formed using a material such as silicon.

[0223] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0224] (Embodiment 8) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 10. In this embodiment, telephones, mobile phone devices), portable information terminals (including portable game consoles and audio playback devices) (including digital cameras, digital video cameras, etc.), electronic paper, televisions The above-mentioned semiconductor devices are used in electronic equipment such as televisions or television receivers. This section explains the case where the device is applied.

[0225] FIG. 10A shows a notebook personal computer, which includes a housing 701, a housing 702, The display unit 703, the keyboard 704, etc. The semiconductor device shown in the previous embodiment is provided inside the semiconductor device. The device is capable of writing and reading information at high speed, retaining data for a long period of time, and being Power consumption is sufficiently reduced, so that writing and reading of information can be performed at high speed and for a long time. A notebook-type personal computer that can store data for a long period of time and consumes very little power. A computer is realized.

[0226] FIG. 10B shows a personal digital assistant (PDA), and a main body 711 includes a display unit 713 and an external An external interface 715, operation buttons 714, etc. are provided. The main body 711 is provided with a stylus 712 for operating the terminal. The semiconductor device described in the above embodiment is provided with a and readout is fast, long-term storage is possible, and power consumption is sufficiently reduced. Therefore, information can be written and read at high speed, and memory can be retained for a long period of time. Furthermore, a portable information terminal with sufficiently reduced power consumption is realized.

[0227] FIG. 10C shows an electronic book 720 that uses electronic paper. The electronic book 720 has a housing 721 and a housing 722. The display unit 721 and the display unit 723 are configured as two housings. 25 and a display unit 727 are provided. The housing 721 and the housing 723 are connected by a shaft portion 737. The housing 7 is connected to the shaft 737, and can be opened and closed around the shaft 737. 21 includes a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housings 723 is provided with the semiconductor device described in the above embodiment. The semiconductor device described in the above embodiment has high speed writing and reading of data and a long life. It is possible to retain memory and consumes very little power. It is a memory device that has high speed reading and writing, long-term memory retention, and sufficiently low power consumption. The child book is realized.

[0228] FIG. 10D shows a mobile phone that is composed of two housings, a housing 740 and a housing 741. Furthermore, the housing 740 and the housing 741 slide and are unfolded as shown in FIG. 10(D). It can be folded from a folded state to an overlapping state, making it possible to make it compact and suitable for portability. The housing 741 also includes a display panel 742, a speaker 743, a microphone 744, Operation keys 745, pointing device 746, camera lens 747, external connection terminal The housing 740 also includes a solar cell 748 for charging the mobile phone. 49, an external memory slot 750, etc. The antenna is also provided inside the housing 741. At least one of the housing 740 and the housing 741 contains the semiconductor device shown in the previous embodiment. The semiconductor device described in the above embodiment is a semiconductor device having a write / read function. It has high speed readout, long-term memory retention, and low power consumption. Therefore, it is possible to write and read information at high speed, retain data for a long period of time, and consume little A mobile phone with significantly reduced power consumption is realized.

[0229] FIG. 10(E) shows a digital camera, which includes a main body 761, a display unit 767, an eyepiece unit 763, and an operation unit. It is composed of an operation switch 764, a display unit 765, a battery 766, etc. The semiconductor device shown in the previous embodiment is provided in the semiconductor device 761. The semiconductor device has high speed writing and reading of information and can retain memory for a long period of time. Moreover, power consumption is sufficiently reduced, so writing and reading of information can be done at high speed. This will realize a digital camera that can store data for a long period of time and consumes very little power. will be done.

[0230] FIG. 10F shows a television device 770, which includes a housing 771, a display portion 773, a stand, and the like. The television device 770 is operated by a switch provided in the housing 771. This can be done using a switch or a remote control 780. The device 780 is equipped with the semiconductor device described in the previous embodiment. The semiconductor device shown in the present specification is capable of writing and reading information at high speed and retaining information for a long period of time. Furthermore, power consumption is sufficiently reduced. A television device capable of high speed, long-term storage, and sufficiently reduced power consumption is provided. It will be realized.

[0231] As described above, the electronic device described in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for the realization of electronic devices with reduced power consumption. [Example]

[0232] The number of times that a semiconductor device according to one embodiment of the disclosed invention can be rewritten was investigated. The survey results will now be explained with reference to FIG.

[0233] The semiconductor device used in the investigation has a circuit configuration shown in FIG. An oxide semiconductor is used for the transistor corresponding to the transistor 162. The capacitance element corresponding to the capacitor 164 had a capacitance of 0.33 pF.

[0234] The investigation involves setting the initial memory window width and holding and writing data a predetermined number of times. This is done by comparing the memory window width after each iteration. Data is written by applying 0V or Apply either 0V or 5V to the wire corresponding to the fourth wire. When the potential of the wiring corresponding to the fourth wiring is 0V, the transistor Since the transistor corresponding to the transistor 162 is in the off state, the floating gate portion FG If the potential of the wiring corresponding to the fourth wiring is 5V, the transistor Since the transistor corresponding to the third wiring is turned on, the transistor corresponding to the third wiring is turned on. The potential of the line is applied to the floating gate portion FG.

[0235] The memory window width is one of the indicators that show the characteristics of a memory device. Between the states, the potential Vcg of the wiring corresponding to the fifth wiring and the potential Vcg of the wiring corresponding to the transistor 160 The shift of the curve (Vcg-Id curve) showing the relationship between the drain current Id of the transistor The different memory states are when 0V is applied to the floating gate FG. (hereinafter referred to as the Low state) and when 5V is applied to the floating gate FG. This refers to a given state (hereinafter referred to as the High state). In other words, the memory window width is This can be confirmed by sweeping the potential Vcg in the low and high states. In either case, Vds=1V.

[0236] Figure 11 shows the initial memory window width and the 1×10 9 Notes after writing The results of the investigation of the re-window width are shown in Figure 11. In Figure 11, the solid line indicates the first write. The dashed line is 1×10 9 The left curve in both the solid and dashed lines indicates the The line indicates writing a high state, and the curve on the right indicates writing a low state. The horizontal axis indicates Vcg (V) and the vertical axis indicates Id (A). 9 Writing times Before and after writing, the potential Vcg was swept in the High and Low states. It can be seen that the window width has not changed. 9 Before and after writing the notes The fact that the re-window width does not change means that the characteristics of the semiconductor device will not change at least during this period. This indicates that the

[0237] As described above, the semiconductor device according to one embodiment of the disclosed invention can store and write data many times. The characteristics do not change even after repeated use. In other words, one embodiment of the disclosed invention provides extremely reliable It can be said that a highly efficient semiconductor device can be realized. [Explanation of symbols]

[0238] 138 Insulating Layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 143 Insulating Layer 144 Oxide semiconductor layer 146 Gate insulating layer 148a Gate electrode 148b Electrode 150 Interlayer insulation layer 152 Interlayer insulation layer 160 transistors 162 transistors 164 Capacitor 181 Memory Cell Array 190 memory cells 200 boards 202 Insulating layer 206 Oxide semiconductor layer 206a Oxide semiconductor layer 208a Source electrode or drain electrode 208b Source electrode or drain electrode 212 Gate insulating layer 214 gate electrode 216 Interlayer insulating layer 218 Interlayer Insulation Layer 250 transistors 300 boards 302 Insulation layer 304 First oxide semiconductor layer 304a First oxide semiconductor layer 305 Second oxide semiconductor layer 306 Second oxide semiconductor layer 306a Second oxide semiconductor layer 308a Source electrode or drain electrode 308b Source electrode or drain electrode 312 Gate insulating layer 314 Gate electrode 316 Interlayer insulation layer 318 Interlayer Insulation Layer 350 transistors 400 boards 402 Insulating layer 406 Oxide semiconductor layer 406a Oxide semiconductor layer 408 Conductive Layer 408a Source electrode or drain electrode 408b Source electrode or drain electrode 410 Insulating layer 410a Insulating layer 410b insulating layer 411a Oxidized area 411b Oxidized region 412 Gate insulating layer 414 Gate electrode 416 Interlayer insulation layer 418 Interlayer Insulation Layer 450 transistors 620 Memory Cell Array 630 memory cells 631 Transistor 632 Capacitor element 640 memory cell array 650 memory cells 651 Transistor 652 transistors 653 Transistor 654 Transistor 655 Transistor 656 Transistor 701 Case 702 Case 703 Display section 704 keyboard 711 Main Unit 712 Stylus 713 Display section 714 Operation Button 715 external interface 720 e-books 721 Case 723 Case 725 Display section 727 Display section 731 Power supply 733 Operation Key 735 Speaker 737 Shaft 740 chassis 741 Case 742 Display Panel 743 Speaker 744 microphone 745 Operation Key 746 Pointing Device 747 Camera Lens 748 External connection terminal 749 Solar Cells 750 external memory slot 761 Main Unit 763 Eyepiece 764 Operation Switch 765 Display section 766 Battery 767 Display section 770 Television Equipment 771 Case 773 Display section 775 Stand 780 Remote Controlled Machine

Claims

1. A memory cell having a first transistor and a second transistor, a portion where a source electrode or a drain electrode of the first transistor and a gate electrode of the second transistor are electrically connected; data is written to the portion via the first transistor; The first transistor is turned off, thereby retaining the data; the first transistor has a channel formation region in a first oxide semiconductor layer; the second transistor has a channel formation region in a second oxide semiconductor layer; the first oxide semiconductor layer has crystals whose c-axes are oriented along a direction perpendicular to a surface of the first oxide semiconductor layer; the second oxide semiconductor layer has crystals whose c-axes are oriented along a direction perpendicular to a surface of the second oxide semiconductor layer; The memory cell, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are In—Ga—Zn—O-based oxide semiconductor layers.

2. A memory cell having a first transistor and a second transistor, a floating gate portion in which a source electrode or a drain electrode of the first transistor and a gate electrode of the second transistor are electrically connected; the first transistor has a channel formation region in a first oxide semiconductor layer; the second transistor has a channel formation region in a second oxide semiconductor layer; the first oxide semiconductor layer has crystals whose c-axes are oriented along a direction perpendicular to a surface of the first oxide semiconductor layer; the second oxide semiconductor layer has crystals whose c-axes are oriented along a direction perpendicular to a surface of the second oxide semiconductor layer; The memory cell, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are In—Ga—Zn—O-based oxide semiconductor layers.

3. A memory cell having a first transistor and a second transistor, a portion where a source electrode or a drain electrode of the first transistor and a gate electrode of the second transistor are electrically connected; data is written to the portion via the first transistor; The first transistor is turned off, thereby retaining the data; the first transistor has a channel formation region in a first oxide semiconductor layer; the second transistor has a channel formation region in a second oxide semiconductor layer; the first oxide semiconductor layer has crystals whose c-axes are oriented along a direction perpendicular to a surface of the first oxide semiconductor layer; the second oxide semiconductor layer has crystals whose c-axes are oriented along a direction perpendicular to a surface of the second oxide semiconductor layer; a capacitance element electrically connected to a gate electrode of the second transistor; The memory cell, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are In—Ga—Zn—O-based oxide semiconductor layers.

4. A memory cell having a first transistor and a second transistor, a floating gate portion in which a source electrode or a drain electrode of the first transistor and a gate electrode of the second transistor are electrically connected; the first transistor has a channel formation region in a first oxide semiconductor layer; the second transistor has a channel formation region in a second oxide semiconductor layer; the first oxide semiconductor layer has crystals whose c-axes are oriented along a direction perpendicular to a surface of the first oxide semiconductor layer; the second oxide semiconductor layer has crystals whose c-axes are oriented along a direction perpendicular to a surface of the second oxide semiconductor layer; a capacitance element electrically connected to a gate electrode of the second transistor; The memory cell, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are In—Ga—Zn—O-based oxide semiconductor layers.

5. 5. A memory cell array having a plurality of memory cells according to claim 1 arranged in a matrix.

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