Audio circuit, electronic device using the same, and in-vehicle audio system

Abstract

To suppress common-mode offset variations.SOLUTION: An integrator 332 includes a first resistor string RSTR1 and a second resistor R2. The first resistor string RSTR1 includes a plurality of first resistors R11 to R16 connected in series. A gain selection circuit 336 includes a plurality of first switches SW11 to SW16. First ends of the plurality of first switches SW11 to SW16 are commonly connected to the inverting input node of an operational amplifier OA1, and second ends of the plurality of first switches SW11 to SW16 are connected to corresponding ones of the plurality of first taps T11 to T16 of the first resistor string RSTR1.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to an audio amplifier circuit that drives a speaker or a headphone. [Background technology]

[0002] Highly efficient class-D amplifiers are used as power amplifiers to drive electroacoustic transducers such as speakers and headphones. Fig. 1 is a block diagram of an audio system 100R that uses a class-D amplifier. The audio system 100R mainly includes a speaker 102, a filter 104, and a class-D amplifier circuit 900.

[0003] The class D amplifier circuit 900 receives an input audio signal S IN A pulse signal S having a duty ratio according to OUT The filter 104 generates the output signal S OUT The high frequency components are removed and the signal is supplied to the speaker 102.

[0004] 1 includes an output stage 902, an integrator 904, a comparator 906, and a driver 908. The integrator 904 converts an input audio signal S IN and the output signal S OUT The feedback signal S according to FB The comparator 906 compares the output of the integrator 904 with the carrier wave CLK and outputs a pulse signal S D The driver 908 outputs the pulse signal S D , and drives the output stage 902 accordingly.

[0005] In automotive and television audio systems, a high voltage of 12 V or more is used as the power supply for the class-D amplifier circuit 900. In this case, the power transistor of the output stage 902 of the class-D amplifier circuit 900 cannot be configured with a MOSFET with a withstand voltage of 5 V, and must be configured with a DMOS (Double-Diffused MOS) with a high drain-source withstand voltage (for example, 20 V).

[0006] One of the speaker driving methods is BTL (Balanced Transformer Less or Bridge-Tied Load) driving. In BTL driving, two sets of class-D amplifiers 900 shown in FIG. 1 are used. One class-D amplifier 900 is connected to one end of the speaker 102, and the other class-D amplifier 900 is connected to the other end of the speaker 102. The two class-D amplifiers receive an input audio signal S IN is supplied. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent Publication No. 2021-071930

[0008] [overview] The present disclosure has been made in this situation, and one exemplary purpose of an embodiment thereof is to provide an audio circuit in which common-mode offset variations between two class-D amplifiers are suppressed.

[0009] An audio circuit according to one embodiment of the present disclosure includes a first output terminal and a second output terminal to be connected to an electro-acoustic transducer via a BTL (Balanced Transformer Less) connection, a first pulse-width modulator that pulse-width modulates a positive-phase input signal to generate a first pulse-width modulated signal, a second pulse-width modulator that pulse-width modulates a negative-phase input signal to generate a second pulse-width modulated signal, a first output stage that switches in response to the first pulse-width modulated signal, and a second output stage that switches in response to the second pulse-width modulated signal. Each of the first pulse-width modulator and the second pulse-width modulator includes an integrator that integrates the error between the corresponding input signal and the signal at the corresponding output terminal, and a comparator that compares the output of the integrator with a carrier wave. The integrator includes an input node that receives an input signal, a feedback node that receives a signal from the output terminal, a first resistor string that includes a plurality of first resistors connected in series and has a first end connected to the input node, and that is provided with a plurality of first taps, a second resistor connected between a second end of the first resistor string and the feedback node, an operational amplifier that receives a bias voltage at a non-inverting input node, a capacitor connected between the inverting input node and the output node of the operational amplifier, and a gain selection circuit that includes a plurality of first switches, the first ends of which are commonly connected to the inverting input node of the operational amplifier, and the second ends of which are connected to corresponding ones of the plurality of first taps.

[0010] Any combination of the above components, and any transformation of the present invention into a method, device, or the like, are also valid aspects of the present invention. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram of an audio system using a class-D amplifier. [Figure 2] FIG. 2 is a block diagram of an audio system according to the embodiment. [Figure 3] FIG. 3 is a level diagram of a signal in the audio system of FIG. [Figure 4] FIG. 4 is a circuit diagram of an integrator according to the embodiment. [Figure 5] FIG. 5 is a circuit diagram of a bias circuit that generates the bias voltage FILP. [Figure 6] FIG. 6 is a diagram illustrating the operation of the integrator according to the embodiment. [Figure 7] FIG. 7 is a diagram illustrating the layout of resistors in the first PWM circuit and the second PWM circuit.

[0012] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0013] An audio circuit according to one embodiment of the present disclosure includes a first output terminal and a second output terminal to be connected to an electro-acoustic transducer via a BTL (Balanced Transformer Less) connection, a first pulse-width modulator that pulse-width modulates a positive-phase input signal to generate a first pulse-width modulated signal, a second pulse-width modulator that pulse-width modulates a negative-phase input signal to generate a second pulse-width modulated signal, a first output stage that switches in response to the first pulse-width modulated signal, and a second output stage that switches in response to the second pulse-width modulated signal. Each of the first pulse-width modulator and the second pulse-width modulator includes an integrator that integrates the error between the corresponding input signal and the signal at the corresponding output terminal, and a comparator that compares the output of the integrator with a carrier wave. The integrator includes an input node that receives an input signal, a feedback node that receives a signal from the output terminal, a first resistor string that includes a plurality of first resistors connected in series and has a first end connected to the input node, and that is provided with a plurality of first taps, a second resistor connected between a second end of the first resistor string and the feedback node, an operational amplifier that receives a bias voltage at a non-inverting input node, a capacitor connected between the inverting input node and the output node of the operational amplifier, and a gain selection circuit that includes a plurality of first switches, the first ends of which are commonly connected to the inverting input node of the operational amplifier, and the second ends of which are connected to corresponding ones of the plurality of first taps.

[0014] This configuration reduces the effect of the on-resistance of the multiple first switches included in the gain selection circuit on the gain of the integrator, thereby improving common-mode offset variation. Although this configuration requires the use of high-voltage elements as the first switches, the element size can be reduced because a large on-resistance is tolerated, and therefore the increase in chip size (layout area) due to the use of high-voltage elements does not pose a problem.

[0015] In one embodiment, the integrator may further include a Zener diode connected between the inverting input node of the operational amplifier and ground.

[0016] In one embodiment, the plurality of first resistors of the first pulse width modulator and the plurality of first resistors of the second pulse width modulator may be arranged adjacent to each other in an alternating manner.

[0017] In one embodiment, the second resistor may include a plurality of resistive elements connected in series, and the plurality of resistive elements of the first pulse width modulator and the plurality of resistive elements of the second pulse width modulator may be arranged adjacent to each other in an alternating manner.

[0018] In one embodiment, the plurality of first resistors of the first pulse width modulator and the plurality of first resistors of the second pulse width modulator may be arranged adjacent to each other in a first direction within a first region. The second resistor may include a plurality of resistive elements connected in series. The plurality of resistive elements of the first pulse width modulator and the plurality of resistive elements of the second pulse width modulator may be arranged adjacent to each other in a second region adjacent to the first region in a second direction.

[0019] In one embodiment, the audio circuit may further include a bias circuit that generates a bias voltage. The bias circuit may include a second resistor string including a third resistor and a fourth resistor connected in series between a power supply line and a ground line, and a plurality of fifth resistors connected in series, the second resistor string receiving a reference voltage at a first end thereof and having a plurality of second taps, and a bias level selection circuit including a plurality of second switches, the first end of each of the plurality of second switches being commonly connected to a connection node between the third resistor and the fourth resistor, and the second end of each of the plurality of second switches being connected to a corresponding one of the plurality of second taps.

[0020] In one embodiment, the audio circuit may be monolithically integrated on a single substrate. "Monolithically integrated" includes cases where all of the circuit components are formed on the substrate, or where the main circuit components are monolithically integrated, and some resistors, capacitors, etc. may be provided outside the substrate to adjust the circuit constants. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be maintained uniformly.

[0021] An electronic device according to an embodiment may include any of the audio circuits described above.

[0022] An in-car audio system according to an embodiment may include any of the audio circuits described above.

[0023] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are merely examples and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0024] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0025] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0026] 2 is a block diagram of an audio system 100 according to an embodiment. The audio system 100 includes a speaker 102, filters 104P and 104N, and an audio circuit 300. The audio system 100 may be an in-vehicle audio system, or may be an audio system built into an electronic device such as a television, a smartphone, a tablet terminal, or a notebook PC.

[0027] The audio circuit 300 has input terminals INN and INP and output terminals OUTP and OUTN. The output terminals OUTP and OUTN are connected to the speaker 102, which is a load, via filters 104P and 104N via a BTL (Bridge-Tied Load or Balanced Transformer Less) connection. The audio circuit 300 is an IC (Integrated Circuit) integrated on a single semiconductor chip (semiconductor substrate).

[0028] The audio circuit 300 is configured with a so-called class D amplifier architecture. The audio circuit 300 receives positive and negative phase audio signals S INP ,S INN The audio circuit 300 receives the reverse-phase audio signal S INN In response to this, a first output signal S, which is a pulse-width modulated positive-phase pulse signal, is output to the first output terminal OUTP. OUTP Similarly, the audio circuit 300 generates a positive-phase audio signal S INP In response to this, a second output signal S, which is a pulse width modulated pulse signal with an opposite phase, is output to the second output terminal OUTN. OUTN occurs.

[0029] The audio circuit 300 has a three-stage configuration: an input stage 320, a pulse width modulation (PWM) circuit 330, and an output stage 310. The output stage 310 is connected to a power supply voltage V CC For example, the power supply voltage V CC is, for example, 12 V or a higher voltage. The output stage 310 includes a first output stage 310P and a second output stage 310N. The first output stage 310P receives the first PWM signal S from the previous PWM circuit 330. PWMP When the power supply voltage V CC The first output signal S OUTP The second output stage 310N generates the second PWM signal S from the previous PWM circuit 330 at the first output terminal OUTP. PWMN When the power supply voltage V CC The second output signal S OUTNis generated at the second output terminal OUTN.

[0030] The input stage 320 and the PWM circuit 330 operate using an internal power supply voltage VREG that is lower than 12 V as a power supply. For example, the internal power supply voltage V REG The input stage 320 receives the audio signal S INP ,S INN Amplify.

[0031] The input stage 320 includes a first gain circuit 320P and a second gain circuit 320N. The first gain circuit 320P amplifies the audio signal S with respect to a reference voltage FIL. INN and amplifies the audio signal S MIDN The reference voltage FIL may be half the voltage of the internal power supply voltage VREG. The second gain circuit 320N outputs the audio signal S INP and amplifies the audio signal S MIDP The first gain circuit 320P and the second gain circuit 320N are configured as non-inverting amplifiers.

[0032] The PWM circuit 330 outputs the amplified audio signal S MIDN ,S MIDP is pulse width modulated to generate a PWM signal S PWMP ,S PWMN The PWM circuit 330 includes a first PWM circuit 330P, a second PWM circuit 330N, and an oscillator 350.

[0033] Each of the first PWM circuit 330P and the second PWM circuit 330N includes an integrator 332 and a PWM comparator 334. The integrator 332 receives a corresponding input signal S MIN# and the corresponding output signal S OUT# Integrate the error of . # represents P or N.

[0034] The integrator 332 includes an input resistor Ri, a feedback resistor Rf, and an operational amplifier OA1. The integrator 332 is supplied with a bias voltage FILP generated by a bias circuit 360.

[0035] The integrator 332 forms an inverting amplifier, and its gain g is g=-Rf / Ri Therefore, the polarity is reversed between the input and the output. As will be described later, the gain g of the integrator 332 is switchable.

[0036] The PWM comparator 334 is connected to the output S of the integrator 332. INT# is compared with the carrier wave generated by oscillator 350 to generate the PWM signal S PWM# Generate.

[0037] FIG. 3 is a level diagram of signals in the audio system 100 of FIG.

[0038] 4 is a circuit diagram of an integrator 332 according to an embodiment. The integrator 332 includes an input node IN, a feedback node FB, a first resistor string RSTR1, a second resistor R2, an operational amplifier OA1, a capacitor C1, Zener diodes ZD1 and ZD2, and a gain selection circuit 336.

[0039] The input node IN receives the corresponding input signal S MIN# The feedback node FB receives the signal S OUT# is entered.

[0040] A first end of the first resistor string RSTR1 is connected to the input node IN. The first resistor string RSTR1 includes a plurality of n (n≧2) first resistors R11 to R1 n Here, the number n of resistors is 6, and the gain of the integrator 332 can be switched in n=6 stages in 1 dB increments: 9 dB, 10 dB, 11 dB, 12 dB, 13 dB, and 14 dB. However, the present disclosure is not limited thereto, and the number of gain stages is arbitrary. Therefore, the number n of resistors may be determined according to the number of gain stages. The first resistor string RSTR1 is provided with a plurality of n first taps T11 to T16 corresponding to the respective nodes of the plurality of first resistors R11 to R16.

[0041] The second resistor R2 is connected between the second end of the first resistor string RSTR1 and the feedback node FB.

[0042] The capacitor C1 is connected between the inverting input node (-) and the output node of the operational amplifier OA.

[0043] The gain selection circuit 336 includes a plurality of n first switches SW11 to SW16. The first switches SW11 to SW16 are analog switches (also called transfer gates or CMOS switches). The first terminals of the plurality of first switches SW11 to SW16 are commonly connected to the inverting input node (-) of the operational amplifier OA1. The i-th (1≦i≦6) first switch SW1 i The second end of the resistor string RSTR1 is connected to a corresponding first tap T1 among the plurality of first taps T11 to T16 of the first resistor string RSTR1. i and is connected.

[0044] The gain of the integrator 332 is: 14dB when SW11 is on and the rest are off 13dB when SW12 is on and the rest are off 12dB when SW13 is on and the rest are off 11dB when SW14 is on and the rest are off 10dB when SW15 is on and the rest are off 9dB ​​when SW16 is on and the rest are off

[0045] A bias voltage FILP is supplied to the non-inverting input node (+) of the operational amplifier OA1. This bias voltage FILP is generated so as to satisfy equation (1). FILP=V REG / 2+(V CC / 2-V REG / 2) × Ri / (Ri + Rf) …(1) i-th first switch SW1 i When is on, Ri is i is the sum of Rf and R1 i+1 ~R1n and the sum of R2. Ri=Σ j=1~i R1 j Rf=Σ j=i+1~n R1 j +R2 FIG. 4 shows the resistances Ri and Rf when the j=4th first switch SW14 is on.

[0046] The Zener diode ZD1 is connected between the inverting input node (-) of the operational amplifier OA1 and ground, and the Zener diode ZD2 is connected between the connection node of the first resistor string RSTR1 and the second resistor R2 and ground.

[0047] The above is the configuration of the integrator 332.

[0048] 5 is a circuit diagram of a bias circuit 360 that generates a bias voltage FILP. The bias circuit 360 includes a second resistor string RSTR2, a third resistor R3, a fourth resistor R4, and a bias level selection circuit 362.

[0049] The third resistor R3 and the fourth resistor R4 are connected in series between the power supply line and the ground line. The second resistor string RSTR2 includes a plurality of n (n=6) fifth resistors R51 to R56 connected in series. A reference voltage FIL is input to a first end of the second resistor string RSTR2. The second resistor string RSTR2 is provided with a plurality of second taps T21 to T26 corresponding to the nodes of the plurality of second resistors R51 to R56.

[0050] The bias level selection circuit 362 includes a plurality of second switches SW21 to SW26. A first terminal of each of the plurality of second switches SW21 to SW26 is commonly connected to a connection node between the third resistor R3 and the fourth resistor R4. The i-th (1≦i≦n) second switch SW2 i The second end of the second tap T2 is connected to a corresponding second tap T2 among the plurality of second taps T21 to T26. iThe state of the bias level selection circuit 362 is controlled in conjunction with the state of the gain selection circuit 336. Specifically, in the gain selection circuit 336, the j-th first switch SW1 j is on, the j-th second switch SW2 corresponding to the j-th second switch SW2 in the bias level selection circuit 362 j This allows the bias voltage FILP that satisfies equation (1) to be generated.

[0051] Next, the advantages of the integrator 332 in FIG. 4 will be described.

[0052] 4, one end of each of the first switches SW11 to SW16 is connected to the input node of the operational amplifier OA1. Because the input node of the operational amplifier OA has high impedance, the average current flowing through the first switches SW11 to SW16 is zero. Therefore, the on-resistance of the first switches SW11 to SW16 does not affect the gain of the integrator 332, and fluctuations in the gain of the integrator 332 due to manufacturing variations are suppressed. As a result, it is possible to suppress common-mode offset variations between the first PWM circuit 330P and the second PWM circuit 330N.

[0053] 6 is a diagram illustrating the operation of the integrator 332 according to the embodiment. The left side of FIG. 6 shows the characteristics when the gain is set to 14 dB, and the right side of FIG. 6 shows the characteristics when the gain is set to 9 dB. The horizontal axis represents the power supply voltage V CC The vertical axis indicates various voltages. T16 and T11 indicate the terminal voltages of the first taps T16 and T11, respectively.

[0054] Here, the power supply voltage V CC When this voltage rises, the voltage of the first tap T16 rises to the power supply voltage V of the first switches SW11 to SW16. REGTherefore, the first switches SW11 to SW16 must be configured with high-voltage elements. Generally, when a low-voltage element and a high-voltage element having the same on-resistance are compared, the high-voltage element has a larger area. However, in this embodiment, the on-resistance does not affect the gain, so the first switches SW11 to SW16 can be designed with a large on-resistance, that is, with a small area. This makes it possible to suppress an increase in area due to the use of high-voltage elements.

[0055] FIG. 7 is a diagram illustrating the layout of resistors in the first PWM circuit 330P and the second PWM circuit 330N.

[0056] 7, PR1 is a resistive element that constitutes the first resistors R11 to R16 of the first resistor string RSTR1 in the first PWM circuit 330P. NR1 is a resistive element that constitutes the first resistors R11 to R16 of the first resistor string RSTR1 in the second PWM circuit 330N.

[0057] In the first PWM circuit 330P and the second PWM circuit 330N, the second resistor R2 is divided into a plurality of n resistor elements connected in series. PR2 corresponds to the plurality of resistor elements that make up the second resistor R2 in the first PWM circuit 330P. NR2 corresponds to the plurality of resistor elements that make up the second resistor R2 in the second PWM circuit 330N.

[0058] The first resistors R11 to R16 in the first PWM circuit 330P and the first resistors R11 to R16 in the second PWM circuit 330N are formed in a first region 400 on a semiconductor chip. In the first region 400, the resistive element PR1 on the first PWM circuit 330P side and the resistive element NR1 on the second PWM circuit 330N side are alternately arranged adjacent to each other so as to line up in a first direction (the x-axis direction in the figure).

[0059] The second resistor R2 in the first PWM circuit 330P and the second resistor R2 in the second PWM circuit 330N are formed in a second region 402 on the semiconductor chip. The second region 402 is adjacent to the first region 400 in the second direction (the y-axis direction in the figure).

[0060] In the second region 402, the resistance element PR2 on the first PWM circuit 330P side and the resistance element NR2 on the second PWM circuit 330N side are alternately arranged adjacent to each other so as to line up in the first direction (the x-axis direction in the drawing).

[0061] According to the layout of FIG. 7, the gain of the integrator 332 on the first PWM circuit 330P side and the gain of the integrator 332 on the second PWM circuit 330N side can be made equal, thereby further suppressing common-mode offset variations.

[0062] (Addendum) One aspect of the technology disclosed in this disclosure can be understood as follows.

[0063] (Item 1) a first output terminal and a second output terminal to be connected to the electroacoustic conversion element in a BTL (Balanced Transformer Less) manner; a first pulse width modulator that pulse-width modulates a positive-phase input signal to generate a first pulse-width modulated signal; a second pulse width modulator that pulse-width modulates an input signal of a reverse phase to generate a second pulse-width modulated signal; a first output stage that switches in response to the first pulse width modulated signal; a second output stage that switches in response to the second pulse width modulated signal; Equipped with The first pulse width modulator and the second pulse width modulator each include: an integrator for integrating the error between a corresponding input signal and a signal at a corresponding output terminal; a comparator for comparing the output of the integrator with a carrier wave; Including, The integrator an input node for receiving the input signal; a feedback node receiving a signal from the output terminal; a first resistor string having a first end connected to the input node, the first resistor string including a plurality of first resistors connected in series, and having a plurality of first taps; a second resistor connected between a second end of the first resistor string and the feedback node; an operational amplifier receiving a bias voltage at a non-inverting input node; a capacitor connected between the inverting input node and the output node of the operational amplifier; a gain selection circuit including a plurality of first switches, a first terminal of each of the plurality of first switches being commonly connected to the inverting input node of the operational amplifier, and a second terminal of each of the plurality of first switches being connected to a corresponding one of the plurality of first taps; , an audio circuit.

[0064] (Item 2) The integrator Item 10. The audio circuit of item 1, further comprising a Zener diode connected between the inverting input node of the operational amplifier and ground.

[0065] (Item 3) 3. The audio circuit of claim 1, wherein the plurality of first resistors of the first pulse width modulator and the plurality of first resistors of the second pulse width modulator are arranged adjacent to each other in an alternating manner.

[0066] (Item 4) the second resistor includes a plurality of resistor elements connected in series; 3. The audio circuit according to item 1 or 2, wherein the plurality of resistive elements of the first pulse width modulator and the plurality of resistive elements of the second pulse width modulator are alternately arranged adjacent to each other.

[0067] (Item 5) the plurality of first resistors of the first pulse width modulator and the plurality of first resistors of the second pulse width modulator are arranged adjacent to each other alternately in a first direction within a first region; the second resistor includes a plurality of resistor elements connected in series; 3. The audio circuit of claim 1, wherein the plurality of resistive elements of the first pulse width modulator and the plurality of resistive elements of the second pulse width modulator are arranged adjacent to each other in the first direction within a second region adjacent to the first region in the second direction.

[0068] (Item 6) a bias circuit for generating the bias voltage; The bias circuit a third resistor and a fourth resistor connected in series between the power supply line and the ground line; a second resistor string including a plurality of fifth resistors connected in series, the second resistor string receiving the reference voltage at a first end thereof and having a plurality of second taps; a bias level selection circuit including a plurality of second switches, a first terminal of each of the plurality of second switches being commonly connected to a connection node between the third resistor and the fourth resistor, and a second terminal of each of the plurality of second switches being connected to a corresponding one of the plurality of second taps; 6. The audio circuit according to any one of items 1 to 5, comprising:

[0069] (Item 7) 7. The audio circuit according to any one of items 1 to 6, which is monolithically integrated on a single substrate.

[0070] (Item 8) 8. An electronic device comprising the audio circuit according to any one of items 1 to 7.

[0071] (Item 9) 8. An in-vehicle audio system comprising the audio circuit according to any one of items 1 to 7. [Explanation of symbols]

[0072] 100 Audio System 102 Speaker 104 filters 300 Audio Circuit 310 Output Stage 310P 1st output stage 310N 2nd output stage 320 Input Stage 320P 1st gain circuit 320N 2nd gain circuit 330 PWM circuit 330P 1st PWM circuit 330N 2nd PWM circuit 332 Integrator 334 PWM Comparator OA1 operational amplifier C1 capacitor ZD1, ZD2 Zener diodes RSTR1 First resistor string RSTR2 Second resistor string R1 First resistor R2 2nd resistor R3 3rd resistor R4 4th resistor R5 5th resistor 336 Gain selection circuit 350 Oscillators 360 Bias Circuit 362 Bias level selection circuit 900 Class D amplifier circuit 902 output stage 904 Integrator 906 Comparator 908 Driver

Claims

1. a first output terminal and a second output terminal to be connected to the electroacoustic transducer in a BTL (Balanced Transformer Less) manner; a first pulse width modulator that pulse-width modulates a positive-phase input signal to generate a first pulse-width modulated signal; a second pulse width modulator that pulse-width modulates an input signal of a reverse phase to generate a second pulse width modulated signal; a first output stage that switches in response to the first pulse width modulated signal; a second output stage that switches in response to the second pulse width modulated signal; Equipped with The first pulse width modulator and the second pulse width modulator each include: an integrator for integrating the error between a corresponding input signal and a signal at a corresponding output terminal; a comparator for comparing the output of the integrator with a carrier wave; Including, The integrator an input node for receiving the input signal; a feedback node receiving a signal from the output terminal; a first resistor string including a plurality of n first resistors connected in series, the first end of the first resistor string being connected to the input node, and having a plurality of first taps; a second resistor connected between a second end of the first resistor string and the feedback node; an operational amplifier receiving a bias voltage at a non-inverting input node; a capacitor connected between the inverting input node and the output node of the operational amplifier; a gain selection circuit including a plurality of first switches, a first terminal of each of the plurality of first switches being commonly connected to the inverting input node of the operational amplifier, and a second terminal of each of the plurality of first switches being connected to a corresponding one of the plurality of first taps; , an audio circuit.

2. The integrator 2. The audio circuit of claim 1, further comprising a Zener diode connected between the inverting input node of the operational amplifier and ground.

3. 3. The audio circuit according to claim 1, wherein the plurality of first resistors of the first pulse width modulator and the plurality of first resistors of the second pulse width modulator are alternately arranged adjacent to each other.

4. the second resistor includes a plurality of resistor elements connected in series; 3. The audio circuit according to claim 1, wherein the plurality of resistive elements of the first pulse width modulator and the plurality of resistive elements of the second pulse width modulator are alternately arranged adjacent to each other.

5. the plurality of first resistors of the first pulse width modulator and the plurality of first resistors of the second pulse width modulator are arranged adjacent to each other alternately in a first direction within a first region; the second resistor includes a plurality of resistor elements connected in series; 3. The audio circuit according to claim 1, wherein the plurality of resistive elements of the first pulse width modulator and the plurality of resistive elements of the second pulse width modulator are arranged adjacent to each other in the first direction within a second region adjacent to the first region in the second direction.

6. a bias circuit for generating the bias voltage; The bias circuit a third resistor and a fourth resistor connected in series between the power supply line and the ground line; a second resistor string including a plurality of fifth resistors connected in series, the second resistor string receiving the reference voltage at a first end thereof and having a plurality of second taps; a bias level selection circuit including a plurality of second switches, a first terminal of each of the plurality of second switches being commonly connected to a connection node between the third resistor and the fourth resistor, and a second terminal of each of the plurality of second switches being connected to a corresponding one of the plurality of second taps; 3. An audio circuit according to claim 1, comprising:

7. 3. The audio circuit according to claim 1, wherein the audio circuit is monolithically integrated on a single substrate.

8. An electronic device comprising the audio circuit according to claim 1 or 2.

9. An in-vehicle audio system comprising the audio circuit according to claim 1 or 2.

Images