Image sensor and method for driving image sensor

Abstract

To provide an image sensor that operates in high-light environments.SOLUTION: An image sensor according to the present invention includes a pixel including a photoelectric element that generates photocharges, a charge storage element connected to the photoelectric element and storing the photocharges, a drive transistor that generates a pixel signal on the basis of a voltage of a first node connected to the photoelectric element, a transfer transistor including a vertical transfer gate connected between the first node and a second node, a first region doped with a first doping concentration and disposed on one side of the transfer transistor, a second region doped with a second doping concentration different from the first doping concentration and disposed on the other side of the transfer transistor, and an overflow transistor disposed between the second node and the charge storage element, and a row driver connected to the pixel and controlling the pixel.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an image sensor and a method for driving an image sensor, and more particularly to an image sensor that operates in a high-illumination environment and a method for driving an image sensor. [Background technology]

[0002] An image sensor is a device for capturing two-dimensional or three-dimensional images of an object. An image sensor generates an image of an object using photoelectric conversion elements that respond according to the intensity of light reflected from the object. In recent years, CMOS (Complementary Metal-Oxide Semiconductor) technology has developed, and CMOS image sensors using CMOS have come into widespread use.

[0003] In addition, in recent years, image sensors have been installed in various devices, and there is a demand for image sensors that have high dynamic range (HDR) characteristics in low and high illumination and improved signal-to-noise ratio (SNR) characteristics. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned problems with conventional image sensors, and an object of the present invention is to provide an image sensor that operates in a high-illumination environment. [Means for solving the problem]

[0005] In order to achieve the above object, an image sensor according to the present invention includes a photoelectric element that generates photocharges, a charge storage element connected to the photoelectric element and storing the photocharges, a drive transistor that generates a pixel signal based on a voltage of a first node connected to the photoelectric element, a transfer transistor including a vertical transfer gate connected between the first node and a second node, a pixel including a first region doped with a first doping concentration on one side of the transfer transistor, a second region doped with a second doping concentration different from the first doping concentration on the other side of the transfer transistor, and an overflow transistor disposed between the second node and the charge storage element, and a row driver connected to the pixel and controlling the pixel.

[0006] In order to achieve the above object, an image sensor according to the present invention includes: a semiconductor substrate having a photoelectric conversion region and a first floating diffusion region; a first vertical transfer transistor extending in a thickness direction of the semiconductor substrate to penetrate at least a portion of the semiconductor substrate; a first region having a first conductivity type and disposed between the first floating diffusion region and the photoelectric conversion region on one side of the first vertical transfer transistor; a second region having a second conductivity type on the other side of the first vertical transfer transistor; a charge storage element disposed on the other side of the first vertical transfer transistor; and an overflow transistor disposed between the first vertical transfer transistor and the charge storage element.

[0007] In order to achieve the above object, a method for driving an image sensor according to the present invention includes the steps of: generating first photocharges in a photoelectric element connected to a first node during a first interval; transferring the first photocharges to a charge storage element connected to the first node through a first region having a first conductivity type and disposed on one side of a vertical transmission gate; generating second photocharges in the photoelectric element during a second interval; transferring the second photocharges to a second node through a second region having a second conductivity type and disposed on the other side of the vertical transmission gate; and generating a pixel signal based on the charges stored in the second node. [Effects of the Invention]

[0008] According to the image sensor and the driving method of the image sensor according to the present invention, in a low illumination environment where the amount of incident light is relatively small, photocharges are stored in one floating diffusion node, and in a high illumination environment where the amount of incident light is relatively large, the photocharges are divided and stored in a certain proportion in the photoelectric element, the storage gate transistor, and the second capacitor. Therefore, the image sensor including the pixels can sense the image signal even in a relatively bright environment, thereby ensuring a wide dynamic range. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 3] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 4] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 5] FIG. 2 is a plan view schematically illustrating a pixel according to an embodiment of the present invention. [Figure 6] 6 is a schematic cross-sectional view of the pixel according to FIG. 5; [Figure 7] FIG. 2 is a plan view schematically illustrating a pixel according to an embodiment of the present invention. [Figure 8] 8 is a schematic cross-sectional view of the pixel according to FIG. 7; [Figure 9] FIG. 2 is a plan view schematically illustrating a pixel according to an embodiment of the present invention. [Figure 10] 10 is a schematic cross-sectional view of the pixel according to FIG. 9; [Figure 11] 4 is a timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. [Figure 12] FIG. 10 is a diagram showing a change in a potential level in a pixel. [Figure 13] FIG. 10 is a diagram showing a change in a potential level in a pixel. [Figure 14] 12 is a graph showing the amount of charge over time for the operation of the image sensor of FIG. 11. [Figure 15] 4 is a timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. [Figure 16] 16 is a graph showing the amount of charge as a function of time for the operation of the image sensor of FIG. 15. [Figure 17] 4 is a timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. [Figure 18] 18 is a graph showing the amount of charge over time for the operation of the image sensor of FIG. 17. [Figure 19] 4 is a timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. [Figure 20] 20 is a graph showing the amount of charge over time for the operation of the image sensor of FIG. 19. [Figure 21] 4 is a timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. [Figure 22] 22 is a graph showing the amount of charge over time for the operation of the image sensor of FIG. 21. [Figure 23] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 24] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 25] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 26] 4 is a timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. [Figure 27] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 28] 28 is a schematic cross-sectional view of the pixel according to FIG. 27. [Figure 29] 1 is a block diagram showing a schematic configuration of an electronic device according to an embodiment of the present invention. [Figure 30] FIG. 30 is a detailed block diagram of the camera module according to FIG. 29. DETAILED DESCRIPTION OF THE INVENTION

[0010] Next, specific examples of embodiments for carrying out an image sensor and a method for driving an image sensor according to the present invention will be described with reference to the drawings.

[0011] The same reference numerals are used for the same components in the drawings, and redundant explanations thereof will be omitted. The embodiments described herein are exemplary embodiments, and therefore the present invention is not limited thereto. Hereinafter, terms such as first, second, third, fourth, etc. will be used to describe various elements, components, regions, layers and / or sections (commonly referred to as "elements"), but it should be understood that such elements are not limited to these terms. These terms are only used to distinguish one element from another. Thus, what is described as a first element in the description may be called a second element in the claims, or vice versa, without departing from the present disclosure.

[0012] When an element or layer is referred to as being "on," "upper," "on top of," "under," "below," "beneath," "underlying," "connected to," or "coupled" with another element or layer, it is understood that the element or layer in question may be directly on, below, or connected or coupled to the different element or layer, or that there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly above," "directly on top of," "directly below," "directly below," "directly below," "directly connected to," or "directly coupled to" another element or layer, it means that there are no intervening elements or layers present. As used herein, when the phrase "at least one" is used before a list of elements, it should be understood that this phrase modifies the elements of the list as a whole, and not the individual elements of the list. For example, the phrase "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, and all of a, b, and c.

[0013] FIG. 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. As shown in FIG. 1, the image sensor 100 includes a controller 110, a timing generator 120, a row driver 130, a pixel array 140, a readout circuit 150, a ramp signal generator 160, a data buffer 170, and an image signal processor 180. Although image sensor 100 is shown in FIG. 1 as including image signal processor 180, the present invention is not limited thereto, and image signal processor 180 may be located external to image sensor 100.

[0014] The image sensor 100 can be installed in an electronic device having image or light sensing capabilities. For example, the image sensor 100 is attached to electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) devices, home appliances, tablet PCs (Personal Computers), PDAs (Personal Digital Assistants), PMPs (Portable Multimedia Players), navigation devices, drones, and advanced driver assistance systems (ADAS). Alternatively, the image sensor 100 may be mounted in an electronic device that is provided as a component in a vehicle, furniture, manufacturing equipment, a door, various measuring instruments, and the like.

[0015] The controller 110 controls all of the components (120, 130, 140, 150, 160, 170, and 180) included in the image sensor 100. The controller 110 uses control signals to control the operation timing of each component (120, 130, 140, 150, 160, 170, 180). In one embodiment, the controller 110 controls the ramp signal generator 160 to adjust the reference signal RAMP generated by the ramp signal generator 160 . In one embodiment, the controller 110 controls the timing controller 120 to adjust the floating diffusion (FD) capacitance of the pixel circuits in the pixel array 140 via the row driver 130 . In one embodiment, the controller 110 controls the timing controller 120 to adjust the operation timing of elements in the pixel array 140 via the row driver 130 .

[0016] The timing controller 120 generates signals that act as a reference for the operation timing of the components of the image sensor 100 . The timing controller 120 controls the timing of the row driver 130 , the readout circuit 150 , and the ramp signal generator 160 . The timing controller 120 provides control signals that control the timing of the row driver 130 , the readout circuit 150 , and the ramp signal generator 160 . The timing controller 120 controls the timing of the elements in the pixel PX in the reset period, the integration period, and the readout period. The reset period is a period in which the charge accumulated in the floating diffusion node in the pixel PX is reset. The integration section is the section where the photosensitive element is exposed to light and photocharges are generated. The readout section is a section in which photoelectric charges generated from the photoelectric element are transferred to the readout circuit 150 . In one embodiment, the controller 110 controls the timing controller 120 to divide and transfer the photoelectric charges generated by the photoelectric elements during the integration interval to multiple nodes connected to the photoelectric elements. For example, the controller 110 controls the timing controller 120 to transfer photocharges to a first node during a first interval of the integration interval and to transfer photocharges to a second node during a second interval of the integration interval. In one embodiment, a charge storage element may be coupled to the second node.

[0017] The pixel array 140 includes a plurality of pixels PX, and a plurality of row lines RL and a plurality of column lines CL connected to the plurality of pixels PX, respectively. In one embodiment, each pixel PX includes at least one photosensitive element (also called a photosensitive element). The photoelectric element senses incident light and converts the incident light into an electrical signal corresponding to the amount of light, that is, a plurality of analog pixel signals. The level of the analog pixel signal output from the photoelectric element increases as the amount of charge output from the photoelectric element increases. That is, the level of the analog pixel signal output from the photosensitive element increases as the amount of light received within pixel array 140 increases.

[0018] A plurality of row lines (RL1 to RLn-1) (RL) extend in a first direction (X direction) and are connected to a plurality of pixels arranged along the first direction (X direction). For example, a plurality of row lines RL transmit control signals output from the row driver 130 to elements, such as transistors, included in the pixels. In addition to the row lines RL, other signal lines are arranged in the first direction (X direction). The plurality of column lines (CL1 to CLm-1) (CL) extend in a second direction intersecting the first direction (X direction) and are connected to the plurality of pixels PX arranged along the second direction. The column lines CL transmit pixel signals output from the plurality of pixels PX to the readout circuit 150 .

[0019] The row driver 130 generates control signals for driving the pixel array 140 in response to control signals from the timing controller 120, and provides the control signals to the pixels PX of the pixel array 140 via the row lines RL. In one embodiment, the row driver 130 controls the pixels PX to sense incident light on a row-by-row basis. A row line unit includes at least one row line RL.

[0020] In response to a control signal from the timing controller 120, the readout circuit 150 converts a pixel signal (or an electrical signal) from a pixel PX connected to a row line RL selected from among the plurality of pixels PX into a pixel value indicating the amount of light. The readout circuit 150 may include a correlated double sampling circuit, an analog-to-digital converter (ADC) circuit, and the like. The Correlated Double Sampling (CDS) circuit includes multiple comparators, each of which compares a pixel signal received from the pixel array 140 via multiple column lines CL with a reference signal (RAMP) from the ramp generator 160. For example, the correlated double sampling circuit 151 compares the received pixel signal with a reference signal (RAMP) and outputs the comparison result to the analog-to-digital conversion circuit.

[0021] The multiple pixel signals output from the multiple pixels PX have deviations due to the inherent characteristics of each pixel (e.g., fixed pattern noise (FPN) etc.) and / or deviations due to differences in the characteristics of the pixel circuit for outputting the pixel signals from the pixel PX (e.g., a transistor for outputting the charge stored in the photoelectric conversion element within the pixel). In order to compensate for deviations between multiple pixel signals output through multiple column lines CL, correlated double sampling is used to determine a reset component (e.g., reset voltage) and a sensing component (e.g., sensing voltage) for the pixel signal, and extract the difference (e.g., the difference between the reset voltage and the sensing voltage) as an effective signal component. The correlated double sampling circuit outputs a comparison result obtained by applying the correlated double sampling technique to the received pixel signal. The analog-to-digital conversion circuit converts the comparison result of the correlated double sampling circuit into digital data, thereby generating and outputting pixel values ​​corresponding to a plurality of pixels on a row-by-row basis. The analog-to-digital conversion circuit includes a plurality of counters. The counter may be realized as an up counter and an arithmetic circuit whose count value increases sequentially based on a count clock signal, or as an up / down counter, or as a bit-wise inversion counter. A plurality of counters are connected to the outputs of each of the plurality of comparators. Each of the plurality of counters counts the comparison results output from the corresponding comparator, and outputs digital data (for example, pixel values) according to the count results.

[0022] The ramp signal generator 160 generates a reference signal (RAMP) and transmits it to the readout circuit 150 . The ramp signal generator 160 includes a current source, a resistor, and a capacitor. The ramp signal generator 160 adjusts the current magnitude of the variable current source or the resistance value of the variable resistor, and adjusts the ramp voltage, which is the voltage applied to the ramp resistor, to generate a plurality of ramp signals that rise or fall at a slope determined according to the current magnitude of the variable current source or the resistance value of the variable resistor.

[0023] The data buffer 170 stores pixel values ​​of a plurality of pixels PX connected to a selected column line CL transmitted from the readout circuit 150 . In response to an enable signal from the controller 110, the data buffer 170 outputs the stored pixel values ​​to the image signal processor 180 as an image output signal IMS.

[0024] The image signal processor 180 performs image signal processing on the image output signal IMS received from the data buffer 170 . For example, the image signal processor 180 receives a plurality of image output signals IMS from the data buffer 170 and synthesizes the received image output signals IMS to generate image data IDS.

[0025] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. As shown in FIG. 2, pixel PX1 includes a photosensitive element PD1 that generates an electric charge in response to light, and a pixel circuit that processes the electric charge generated by photosensitive element PD1 and outputs an electric signal. The photoelectric element PD1 generates a photoelectric charge that varies depending on the intensity of light. For example, the cathode of the photoelectric element PD1 is connected to the first floating diffusion node FN1 via the first transfer transistor TX1, and the anode of the photoelectric element PD1 is grounded.

[0026] The pixel circuit includes a plurality of transistors, for example, a first transfer transistor TX1, a first reset transistor RX1, a first drive transistor DX1, a first select transistor SX1, a first switch transistor SWX1, a first overflow transistor OX1, and a storage gate transistor SGX1. Control signals (TG1, RG1, SEL1, SW1, OG1, SG1) are applied to pixel PX1. In one embodiment, the control signals are generated in the row driver ( 130 in FIG. 1) under the control of the timing controller 120 . The transistors (TX1, RX1, SX1, SWX1, OX1, SGX1) in the pixel circuit operate in response to control signals provided from the row driver 130, such as a transmission control signal TG1, a reset control signal RG1, a selection signal SEL1, a switch control signal SW1, an overflow control signal OG1, and a storage control signal SG1.

[0027] The first transfer transistor TX1 is connected between the photoelectric element PD1 and the first floating diffusion node FN1. The first transmission transistor TX1 is controlled by a transmission control signal TG1. When the first transfer transistor TX1 is turned on, the charges generated by the photoelectric element PD1 are transferred to the first floating diffusion node FN1. The voltage of the first floating diffusion node FN1 is determined according to the amount of charge stored in the first floating diffusion node FN1. A conversion gain, which is the rate at which charges are converted into voltage, is inversely proportional to the capacitance of the first floating diffusion node FN1. For example, if the capacitance of the first floating diffusion node FN1 increases, the conversion gain decreases, and if the capacitance decreases, the conversion gain increases.

[0028] In one embodiment, the first transfer transistor TX1 includes a vertical transfer gate. The gate electrode of the first transfer transistor TX1 extends along the thickness direction of the conductive substrate. One side of the first transfer transistor TX1 has a first potential, and the other side of the first transfer transistor TX1 has a second potential different from the first potential. In one embodiment, the doping concentration on one side of the first transfer transistor TX1 is different from the doping concentration on the other side. For example, a first region R1 of the first transfer transistor TX1 between the photoelectric element PD1 and the overflow transistor OX1 has a first doping concentration, and a second region R2 of the first transfer transistor TX1 between the photoelectric element PD1 and the first floating diffusion node FN1 has a second doping concentration.

[0029] In one embodiment, the first region R1 is a region doped with n-type impurities. For example, the first region R1 is doped with n-type impurities via an ion implantation process. As will be described later, photo-generated charges from the photoelectric element PD1 are transferred to the storage gate transistor SGX1 via the first region R1. In one embodiment, the second region R2 is a region doped with p-type impurities. For example, the second region R2 is doped with p-type impurities via an ion implantation process. For example, the second region R2 acts as a p-well region for the first transfer transistor TX1. In one embodiment, the oxide thickness on one side of the gate electrode of the first transfer transistor TX1 may be different from the oxide thickness on the other side of the gate electrode.

[0030] The first reset transistor RX1 is connected between a power supply voltage line that supplies a power supply voltage VDD and a first floating diffusion node FN1. The first reset transistor RX1 is controlled by a reset control signal RG1. When the first reset transistor RX1 is turned on, the power supply voltage VDD is applied to the first floating diffusion node FN1, resetting the first floating diffusion node FN1. The gate of the first drive transistor DX1 is connected to the first floating diffusion node FN1. The first driver transistor DX1 operates as a source-follower amplifier for the voltage of the first floating diffusion node FN1. The first driving transistor DX1 outputs the pixel signal VOUT to the column line CL through the first selection transistor SX1 in response to the voltage of the first floating diffusion node FN1.

[0031] The first selection transistor SX1 is connected to the first terminal of the first drive transistor DX1 and the column line CL, and is controlled by a selection control signal SEL1. When the first selection transistor SX1 is turned on, the pixel voltage VOUT output from the first driving transistor DX1 is output to the readout circuit (150 in FIG. 1) via the column line CL connected to the first selection transistor SX1. For example, in a readout operation, when the first selection transistor SX1 is turned on, a pixel signal including a reset signal corresponding to a reset operation or an image signal corresponding to a charge accumulation operation is output via the column line CL. The first switch transistor SWX1 is connected between the first floating diffusion node FN1 and the fourth node N14. The first switch transistor SWX1 is controlled by a switch control signal SW1.

[0032] The first overflow transistor OX1 is connected between the photoelectric element PD1 and the third node N13. The first overflow transistor OX1 is controlled by an overflow control signal OG1. When the first overflow transistor OX1 is turned on, it transfers the charges generated by the photoelectric element PD1 to the third node N13. In one embodiment, the amount of charge generated in the photoelectric element PD1 and transferred to the third node N13 is controlled based on the magnitude of the overflow control signal OG1 applied to the first overflow transistor OX1. In one embodiment, the first overflow transistor OX1 is used to control the transfer of photocharges generated by the photosensitive element PD1 to the storage gate transistor SGX1. For example, the first overflow transistor OX1 controls a portion of the photocharges that exceed the capacity of the photoelectric element PD1 from overflowing from the storage gate transistor SGX1. For example, in a high-illuminance environment where the intensity of incident light incident on the pixel PX1 is relatively very high, the first overflow transistor OX1 transfers a portion of the photocharges overflowing from the photosensitive element PD1 to the storage gate transistor SGX1.

[0033] The storage gate transistor SGX1 is connected between the third node N13 and the fourth node N14. The storage gate transistor SGX1 is controlled by a storage control signal SG1. The storage gate transistor SGX1 is a charge storage element that can store the photocharges generated by the photoelectric element PD1. The storage gate transistor SGX1 is controlled by a storage gate signal SG1. In one embodiment, based on the storage gate signal SG1, the amount of charge that can be stored in the storage gate transistor SGX1 can be varied. In one embodiment, the storage gate transistor SGX1 may have a structure including an additional storage diode underneath.

[0034] FIG. 3 is a circuit diagram of a pixel according to an embodiment of the present invention. As shown in FIG. 3, pixel PX2 includes a photosensitive element PD1 and a pixel circuit that processes the charge generated by photosensitive element PD1 and outputs an electrical signal. The pixel circuit includes a plurality of transistors, for example, a first transfer transistor TX1, a first reset transistor RX1, a first drive transistor DX1, a first select transistor SX1, a first switch transistor SWX1, a first overflow transistor OX1, and a storage gate transistor SGX1.

[0035] In one embodiment, the pixel circuit further includes a dual conversion gain circuit 301 . For example, the dual conversion gain circuit 301 is connected in series with the first reset transistor RX1. Specifically, the dual conversion gain circuit 301 includes a first gain control transistor DCX1 and a first capacitor C1. The first gain control transistor DCX1 is connected between the first floating diffusion node FN1 and a fifth node N15. The first gain control transistor DCX1 is controlled by a gain control signal DCG1. When the first gain control transistor DCX1 is turned on, the first floating diffusion node FN1 and the first capacitor C1 are connected, the capacitance of the first floating diffusion node FN1 increases, and the conversion gain, which is the rate at which charge is converted to voltage, decreases. For example, when the first gain control transistor DCX1 is turned on, the converter operates in a low conversion gain (LCG) mode. On the other hand, when the first gain control transistor DCX1 is turned off, the converter operates in a high conversion gain (HCG) mode.

[0036] FIG. 4 is a circuit diagram of a pixel according to an embodiment of the present invention. As shown in FIG. 4, pixel PX4 includes a photosensitive element PD1 and a pixel circuit that processes the charge generated by photosensitive element PD1 and outputs an electrical signal. The pixel circuit includes a plurality of transistors, for example, a first transfer transistor TX1, a first reset transistor RX1, a first drive transistor DX1, a first select transistor SX1, a first switch transistor SWX1, a first overflow transistor OX1, and a storage gate transistor SGX1.

[0037] In one embodiment, the pixel circuit further includes a dual conversion gain circuit 401 . For example, the dual conversion gain circuit 401 is connected in parallel with the first reset transistor RX1. Specifically, the dual conversion gain circuit 401 includes a second gain control transistor DCX2 and a second capacitor C2. The second gain control transistor DCX2 is connected between the first floating diffusion node FN1 and the sixth node N16. The second gain control transistor DCX2 is controlled by a gain control signal DCG2. When the second gain control transistor DCX2 is turned on, the first floating diffusion node FN1 and the second capacitor C2 are connected, the capacitance of the first floating diffusion node FN1 increases, and the conversion gain, which is the rate at which charge is converted to voltage, decreases. That is, when the second gain control transistor DCX2 is turned on, the converter operates in a low conversion gain LCG mode. On the other hand, when the second gain control transistor DCX2 is turned off, the converter operates in the high conversion gain HCG mode.

[0038] FIG. 5 is a plan view schematically illustrating a pixel according to an embodiment of the present invention, and FIG. 6 is a schematic cross-sectional view of the pixel according to FIG. Specifically, FIG. 6 is a cross-sectional view of pixel PXa of FIG. 5 taken along line AA'. Referring to FIG. 5, pixel PXa includes a plurality of transistors, such as a first transfer transistor TX1 (1009), a first reset transistor RX1 (1013), a first drive transistor DX1 (1003), a first selection transistor SX1 (1001), a first switch transistor SWX1 (1017), a first overflow transistor OX1 (1007), a storage gate transistor SGX1 (1005), and a second gain control transistor DCX2 (1011).

[0039] 6, the pixel array 200 includes a microlens ML, a color filter layer CF, a surface insulating layer 210, a semiconductor substrate 220, a pixel separating pattern 221, and an insulating layer 230. The microlenses ML have a convex shape and a predetermined radius of curvature. The microlenses ML are arranged to correspond to each pixel area. The color filter layer CF is disposed below the microlenses ML. A color filter layer CF may be disposed on the surface insulating layer 210 . The color filters CF may be arranged to correspond to each unit pixel. The color filters CF are arranged two-dimensionally from the top plan view. The color filter layer CF transmits reflected light incident via the microlenses ML, and allows only light of a necessary wavelength to enter the photoelectric conversion region 241 . The color filter layer CF may be called a color filter array. In some embodiments, the color filter layer CF may be omitted in order to acquire only color, infrared or depth images.

[0040] The surface insulating layer 210 is laminated on the second surface SF2 of the semiconductor substrate 220. The color filter grid 270 is arranged in a mesh shape between the color filters CF. The color filter grid 270 defines the area in which the color filters CF are placed. In one embodiment, at least a portion of the color filter grid 270 overlaps with the pixel separating pattern 221 in the third direction (Z direction). A color filter grid 270 is formed on the surface insulating layer 210 . The color filter grid 270 includes, for example, a metal pattern 271 and a low refractive index pattern 272 . The metal pattern 271 and the low refractive index pattern 272 are sequentially stacked on the surface insulating layer 210 .

[0041] The semiconductor substrate 220 is, for example, bulk silicon or silicon-on-insulator (SOI). The semiconductor substrate 220 may be a silicon substrate or may include other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the semiconductor substrate 220 may be a base substrate with an epitaxial layer formed thereon. In some embodiments, the semiconductor substrate 220 has a first conductivity type. For example, the first conductivity type is p-type. The semiconductor substrate 220 includes a first surface SF1 and a second surface SF2 that face each other. The first surface SF1 may be referred to as the front side of the semiconductor substrate 220, and the second surface SF2 may be referred to as the back side of the semiconductor substrate 220. In some embodiments, the second surface SF2 of the semiconductor substrate 220 is a light-receiving surface onto which light is incident and the photoelectric conversion region 241 is exposed.

[0042] The semiconductor substrate 220 includes a photoelectric conversion region 241, and the photoelectric conversion region 241 has a second conductivity type. For example, the second conductivity type is n-type. The photoelectric conversion element PD is formed by a PN junction between the n-type photoelectric conversion region 241 and the p-type substrate 220 . The semiconductor substrate 220 includes a P-type barrier PB. The P-type barrier PB is disposed at a certain distance from the photoelectric conversion region 241 . For example, each P-type barrier PB is formed to be spaced apart from the corresponding photoelectric conversion region 241 in the first direction (X direction) and the second direction (Y direction). The P-type barrier PB may also be extended along the electric conversion region 241 in the third direction (Z direction). That is, the P-type barrier PB may be formed vertically in the semiconductor substrate 220 . The P-type barrier PB is doped with p-type impurities.

[0043] The pixel separating pattern 221 is disposed between the outer surface of the semiconductor substrate 220 and the plurality of pixels. The pixel separating pattern 221 may be an insulator made of, for example, oxide, nitrate, acid nitrate, or a combination thereof. In one embodiment, the pixel separating pattern 221 is composed of a conductive material layer and a cover insulating layer that encases the conductive material layer. For example, the conductive material layer may include polysilicon, a metal, or an oxide such as a metal nitrate or SiO2, and the cover insulating layer may include an oxide, a nitrate, an acid nitrate, or a combination thereof. A pixel separating pattern 221 may be disposed in the semiconductor substrate 220 . The pixel separation pattern 221 defines a plurality of unit pixels. The unit pixels are arranged two-dimensionally from a top plan view point. For example, the pixel separating pattern 221 is formed in a grid shape from a top plan view, and separates unit pixels from each other.

[0044] The pixel separating pattern 221 is formed by filling an insulating material into deep trenches formed by patterning the semiconductor substrate 220 . In one embodiment, the pixel separating pattern 221 includes an insulating spacer film 222 and a conductive filling pattern 223 . The insulating spacer layer 222 conformally extends along the sidewalls of the trench in the semiconductor substrate 220 . A conductive filling pattern 223 is formed on the insulating spacer layer 222 and fills a portion of the trench in the semiconductor substrate 220 . In one embodiment, pixel isolation pattern 221 is frontside deep trench-isolation (FDTI). Meanwhile, FIG. 6 exemplarily shows a frontside deep trench isolation (FDTI) pattern in which the pixel isolation pattern 221 extends through the substrate 110 from the first surface SF1 to the second surface SF2 of the semiconductor substrate 220, but the present invention is not limited thereto, and the pixel isolation pattern 221 may be a backside deep trench isolation (BDTI).

[0045] The insulating layer 230 includes a first transistor TR1, a second transistor TR2, a third transistor TR3, and so on. In one embodiment, the first transistor TR1 is disposed on the first surface SF1 of the semiconductor substrate 220. The first transistor TR1 is a transfer transistor of the image sensor (100 in FIG. 1). Referring to FIG. 5, a second gain control transistor DCX2 (1011) and a first reset transistor RX1 (1013) are spaced apart with a floating diffusion region FD interposed therebetween. The first transistor TR1 may be the first transfer transistor TX1 (1009) in FIG. As will be described later, the overflow transistor OX1 (1007) is disposed on one side of the first transfer transistor TX1 (1009), and the floating diffusion region FD is disposed on the other side.

[0046] In one embodiment, the first transistor TR1 may be implemented as a Vertical Transfer Gate (VTG) structure. The first transistor TR1 transfers a sensing signal (charge) generated in the corresponding photoelectric conversion region 241 to a floating diffusion. The impurity region corresponding to the source / drain of the transfer transistor according to some embodiments may be a floating diffusion FD. The first transistor TR1 includes a gate insulating film 242, a gate electrode 243, a gate spacer 244, a first region R1, and a second region R2. The gate insulating film 242 is formed along the trench formed in the semiconductor substrate 220 . The gate electrode 243 fills the area defined by the gate insulating film 242 and the gate spacer 244 .

[0047] In one embodiment, the first region R1 may be a region in the semiconductor substrate 220 doped with n-type ions, and the second region R2 may be a region in the semiconductor substrate 220 doped with p-type ions. In one embodiment, the first region R1 may be a region in the semiconductor substrate 220 that is doped with p-type ions, and the second region R2 may be a region in the semiconductor substrate 220 that is heavily doped with p-type ions. The gate electrode 243 functions as the gate of the first transistor TR1. For example, the gate electrode 243 may include polysilicon (Poly-Si) or a metal such as tungsten (W) and / or a conductive metal nitrate. On the other hand, although the gate electrode 243 of the first transistor TR1 is shown in FIG. 6 as having oxide layers of the same thickness on both sides, the gate electrode 243 may have oxide layers of different thicknesses on both sides.

[0048] In one embodiment, the second transistor TR2 is disposed on the first surface SF1 of the semiconductor substrate 220. The second transistor TR2 is an overflow transistor (OX1 in FIG. 4) of the image sensor (100 in FIG. 1). The second transistor TR2 is the overflow transistor OX1 (1007) in FIG. Referring to FIG. 5, a first storage gate transistor SGX1 (1005) and an overflow transistor OX1 (1007) are disposed on one side of the first transfer transistor TX1 (1009). A photoelectric conversion region 241 is disposed on at least a portion of the second transistor TR2. The second transistor TR2 includes a gate insulating film 252, a gate electrode 253, and a gate spacer 254. The gate electrode 253 fills the area defined by the gate insulating film 252 and the gate spacer 254 . The gate electrode 253 functions as the gate of the second transistor TR2.

[0049] The second metal layers (ML2_1 to ML2_2) are formed in the insulating layer 230 and extend in the first direction (X direction) or the second direction (Y direction). The second metal layers (ML2_1 to ML2_2) are arranged in order from the first surface SF1 of the semiconductor substrate 220 where the second transistor TR2 is located. For example, the (2_1)th metal layer (ML2_1) is disposed closest to the second transistor TR2, and the (2_2)th metal layer (ML2_2) is disposed farthest from the second transistor TR2. The second metal layers (ML2_1 to ML2_2) have the same thickness, but the embodiment according to the technical idea of ​​the present invention is not limited thereto. In FIG. 6, two second metal layers (ML2_1 to ML2_2) are shown in the drawing, but the present invention is not limited to this, and there may be a plurality of second metal layers (ML2_1 to ML2_2). The second metal layers (ML2_1 to ML2_2) are connected by a plurality of second contacts (C2_1 to C2_2). For example, the second metal layer (ML2_1) is connected to the second metal layer (ML2_2) by the (2_1)th contact (C2_1) extending in the third direction (Z direction). In one embodiment, pixel array 200 further includes impurity-implanted regions 245 . The impurity implanted region 245 is a region doped in the semiconductor substrate 220 corresponding to the second transistor TR2 for adjusting the threshold voltage of the second transistor TR2.

[0050] The third transistor TR3 is disposed on the first surface SF1 of the semiconductor substrate 220. The third transistor TR3 is a storage gate transistor (SGX1 in FIG. 4) of the image sensor (100 in FIG. 1). The third transistor TR3 includes a gate insulating film 262, a gate electrode 263, a gate spacer 264, and a charge storage region 265. The area of ​​the first storage gate transistor SGX1 (1005) is larger than the area of ​​the first transfer transistor TX1 (1009).

[0051] A charge storage region 265 is disposed in the semiconductor substrate 220 below the third transistor TR3. The charge storage region 265 has a first conductivity type. For example, the charge storage region 265 is disposed between the first surface SF1 and the barrier impurity region at a position vertically overlapping the third transistor TR3, and is a temporary charge storage region in which photocharges generated in the photoelectric conversion region 241 are temporarily stored before being transmitted to the floating diffusion region FD. At least a portion of the charge storage region 265 overlaps with the photoelectric conversion region 241 in the third direction (Z direction). Meanwhile, in one embodiment, although not shown in FIG. 6, a storage diode may be formed below the third transistor TR3. Here, the first overflow transistor OX1 generates an overflow path between the photoelectric conversion region 241 and the storage diode. This allows the impurity implantation region 245 to be disposed between the gate electrode 253 of the first overflow transistor OX1 and the photoelectric conversion region 241, and between the gate electrode 253 and the storage diode.

[0052] Referring to FIG. 5, the overflow transistor OX1 (1007) controls the transfer of photocharges temporarily stored in the charge storage region 265 of the first storage gate transistor SGX1 (1005) to the floating diffusion region 1015. The overflow transistor OX1 (1007) is disposed between the first storage gate transistor SGX1 (1005) and the first transfer transistor TX1 (1009). For example, the overflow transistor OX1 (1007) is disposed apart from the first storage gate transistor SGX1 (1005) in the first direction (X direction). The switch transistor SWX1 (1017) is spaced apart in the first direction (X direction) from the first storage gate transistor SGX1 (1005), and is spaced apart from the overflow transistor OX1 (1007) in the second direction. The first drive transistor DX1 (1003) is connected between a conductor to which a power supply voltage VDD is supplied and the first selection transistor SX1 (1001). The first selection transistor SX1 (1001) is connected to the first drive transistor DX1 (1003).

[0053] FIG. 7 is a plan view schematically illustrating a pixel according to an embodiment of the present invention, and FIG. 8 is a schematic cross-sectional view of the pixel according to FIG. Specifically, FIG. 8 is a cross-sectional view of pixel PXb taken along line BB' in FIG. Referring to FIG. 7, pixel PXb includes a plurality of transistors, such as a first transfer transistor TX1 (2009), a first reset transistor RX1 (2013), a first drive transistor DX1 (2003), a first selection transistor SX1 (2001), a first switch transistor SWX1 (2017), a first overflow transistor OX1 (2007), a storage gate transistor SGX1 (2005), and a second gain control transistor DCX2 (2011).

[0054] Referring to FIG. 8, the pixel array 300 includes a microlens ML, a color filter layer CF, a surface insulating layer 310, a semiconductor substrate 320, a pixel separating pattern 321, and an insulating layer 330. Unless otherwise specified, the contents described with reference to FIG. 6 for the microlens ML, color filter layer CF, surface insulating layer 210, semiconductor substrate 220, pixel separating pattern 221, and insulating layer 230 may be applied identically or similarly to the microlens ML, color filter layer CF, surface insulating layer 310, semiconductor substrate 320, pixel separating pattern 321, and insulating layer 330 in FIG. 8.

[0055] Referring to FIG. 7, a second gain control transistor DCX2 (2011) and a first reset transistor RX1 (2013) are spaced apart from each other with a floating diffusion region FD interposed therebetween. An overflow transistor OX1 (2007) is disposed on one side of the first transfer transistor TX1 (2009), and a floating diffusion region FD is disposed on the other side. The first transfer transistor TX1 (2009) is disposed at a distance from the overflow transistor OX1 (2007) in the first direction (X direction). The first storage gate transistor SGX1 (2005) is disposed at a distance from the overflow transistor OX1 (2007) in a second direction perpendicular to the first direction (X direction). The first storage gate transistor SGX1 (2005) is arranged in a vertical form based on the form of the pixel isolation pattern 321. This allows the area of ​​the first storage gate transistor SGX1 (2005) to be increased, allowing more photocharges to be stored.

[0056] The third transistor TR3 is disposed on the first surface SF1 of the semiconductor substrate 320. The third transistor TR3 is a storage gate transistor (SGX1 in FIG. 4) of the image sensor (100 in FIG. 1). The third transistor TR3 extends from the first surface SF1 of the semiconductor substrate 320 toward the second surface SF2 of the semiconductor substrate 320, and the gate insulating film 362 covers the sidewalls and bottom surface of the third transistor TR3. A charge storage region 365 is disposed in the semiconductor substrate 320 below the third transistor TR3. The charge storage region 365 has a first conductivity type. For example, the charge storage region 365 is disposed between the third transistor TR3 and the pixel isolation pattern 321 at a position vertically overlapping the third transistor TR3, and is a temporary charge storage region in which photocharges generated in the photoelectric conversion region 341 are temporarily stored before being transferred to the floating diffusion region FD. The charge storage region 365 is spaced apart from the photoelectric conversion region 341 in the first direction X.

[0057] As shown in FIG. 8, a P-type barrier PB is disposed on at least one side of the charge storage region 365 . The P-type barrier PB is disposed at a predetermined distance from the charge storage region 365 and the photoelectric conversion region 241 . For example, each P-type barrier PB is formed spaced apart from the charge storage region 365 and the photoelectric conversion element PD in a first direction (X direction) and a second direction (Y direction). In addition, the P-type barrier PB may extend in the third direction (Z direction) along the charge storage region 365 and the photoelectric conversion region 241. That is, the P-type barrier PB may be formed vertically in the semiconductor substrate 220 . The P-type barrier PB is doped with p-type impurities.

[0058] Meanwhile, in one embodiment, a storage diode 367 is disposed on one side of the charge storage region 365 of the third transistor TR3. In one embodiment, the storage diode 367 is formed along the third direction (Z direction) on the side opposite to the side on which the P-type barrier PB is disposed, with respect to the charge storage region 365. Here, the first overflow transistor OX1 generates an overflow path between the photoelectric conversion region 341 and the storage diode. For this purpose, impurity-implanted regions 345 are disposed between the gate electrode 353 of the first overflow transistor OX1 and the photoelectric conversion region 341, and between the gate electrode 353 and the storage diode. Although the pixel array 300 is shown in FIG. 8 as including a storage diode 367, the present invention is not limited thereto, and the pixel array 300 does not necessarily have to include a storage diode 367.

[0059] Referring also to FIG. 7, the overflow transistor OX1 (2007) controls the transfer of photocharges temporarily stored in the charge storage region 365 of the first storage gate transistor SGX1 (2005) to the floating diffusion region 2015. An overflow transistor OX1 (2007) is disposed at one end of the first storage gate transistor SGX1 (2005), and a switch transistor SWX1 (2017) is disposed at the other end of the first storage gate transistor SGX1 (2005). The first drive transistor DX1 (2003) is connected between a conductor to which a power supply voltage VDD is supplied and the first selection transistor SX1 (2001). The first selection transistor SX1 (2001) is connected to the first drive transistor DX1 (2003).

[0060] FIG. 9 is a plan view that schematically illustrates a pixel according to an embodiment of the present invention, and FIG. 10 is a schematic cross-sectional view of the pixel according to FIG. Specifically, FIG. 10 is a cross-sectional view of the pixels PXc of FIG. 9 taken along line CC'. Referring to FIG. 9, pixel PXc includes a plurality of transistors, such as a first transfer transistor TX1 (2009), a first reset transistor RX1 (2013), a first drive transistor DX1 (2003), a first selection transistor SX1 (2001), a first switch transistor SWX1 (2017), a first overflow transistor OX1 (2007), a storage gate transistor SGX1 (2005), and a second gain control transistor DCX2 (2011). Unless otherwise specified, the explanations for the arrangement of pixel PXa described with reference to FIG. 5 can be applied identically or similarly to pixel PXc.

[0061] 9 and 10, the pixel array 400 includes a microlens ML, a color filter layer CF, a surface insulating layer 410, a semiconductor substrate 420, a pixel separating pattern 426, and an insulating layer 430. Unless otherwise specified, the contents described with reference to FIG. 6 for the microlens ML, color filter layer CF, surface insulating layer 410, semiconductor substrate 420, and insulating layer 430 may be applied identically or similarly to the microlens ML, color filter layer CF, surface insulating layer 410, semiconductor substrate 420, and insulating layer 430 in FIG. 10.

[0062] The pixel separation patterns 426 are disposed on the outer surface of the semiconductor substrate 420 or between multiple pixels. The pixel separating pattern 426 may be an insulator made of, for example, an oxide, a nitrate, an acid nitrate, or a combination thereof. In one embodiment, the pixel separating pattern 426 is comprised of a conductive material layer and a cover insulating layer that encases the conductive material layer. For example, the conductive material layer may include polysilicon, a metal, or a metal nitrate, or an oxide such as SiO2, and the cover insulating layer may include an oxide, a nitrate, an acid nitrate, or a combination thereof. A pixel separating pattern 426 is disposed in the semiconductor substrate 420 . In one embodiment, the pixel separating pattern 426 includes an insulating spacer film 427 and a conductive filling pattern 428 . The insulating spacer layer 427 conformally extends along the sidewalls of the trench in the semiconductor substrate 420 . A conductive filling pattern 428 is formed on the insulating spacer film 427 and fills a portion of the trench in the semiconductor substrate 420 .

[0063] The pixel separating pattern 426 may be formed from the rear surface of the semiconductor substrate 420 . That is, a trench may be formed on the rear surface of the semiconductor substrate 420, an insulating spacer layer 426 may be formed in the formed trench, and a conductive filling pattern 427 may be filled on the insulating spacer layer 426 to form the pixel separating pattern 426. The pixel separating pattern 426 may not contact the front surface of the semiconductor substrate 420 . Here, the pixel isolation pattern 426 can be BDTI (backside deep trench-isolation). On the other hand, the pixel separation pattern 426 defines a plurality of unit pixels. In one embodiment, the unit pixels are arranged across a plurality of pixel separation patterns 426 . For example, multiple transistors (SX1, SGX1, SWX1, RX1) are disposed below the pixel isolation pattern 426.

[0064] The third transistor TR3 is disposed on the first surface SF1 of the semiconductor substrate 420. The third transistor TR3 is a storage gate transistor (SGX1 in FIG. 4) of the image sensor (100 in FIG. 1). The third transistor TR3 includes a gate insulating film 462, a gate electrode 463, a gate spacer 464, and a charge storage region 465. A charge storage region 465 is disposed in the semiconductor substrate 420 below the third transistor TR3. The charge storage region 465 has a first conductivity type. For example, the charge storage region 465 is disposed between the first surface SF1 and the barrier impurity region at a position vertically overlapping the third transistor TR3, and is a temporary charge storage region in which photocharges generated in the photoelectric conversion region 441 are temporarily stored before being transmitted to the floating diffusion region FD.

[0065] In one embodiment, the charge storage region 465 and the pixel separating pattern 426 are positioned overlapping one another. Meanwhile, in one embodiment, a storage diode may be formed below the third transistor TR3. Here, the first overflow transistor OX1 generates an overflow path between the photoelectric conversion region 441 and the storage diode. For this purpose, impurity-implanted regions 445 may be disposed between the gate electrode 453 of the first overflow transistor OX1 and the photoelectric conversion region 441, and between the gate electrode 453 and the storage diode.

[0066] FIG. 11 is a timing diagram showing the operation of an image sensor according to an embodiment of the present invention, and FIGS. 12 and 13 are diagrams showing changes in potential levels within a pixel. Specifically, FIG. 11 shows one scan interval for driving pixel PX3 according to FIG. One scanning period includes a reset period (RESET), an integration period (INTEGRATION), and a readout period (READOUT) in this order.

[0067] In the reset period (RESET), the charges stored in the first floating diffusion node FN1, the second node N12, the third node N13, and the sixth node N16 are reset. Specifically, in the reset period (RESET), the reset control signal RG1, the transmission control signal TG1, the overflow control signal OG1, the switch control signal SW1, and the gain control signal DCG2 all have a high level (H). The storage control signal SG1 and the selection signal SEL1 have a low level (L). As a result, the first floating diffusion node FN1, the second node N12, the third node N13, and the sixth node N16 are all reset to the power supply voltage VDD.

[0068] The integration section is a section in which the photoelectric element PD is exposed to light and generates charges. The integration section includes a first integration section T201 and a second integration section T203. First, the reset control signal RG1, the transmission control signal TG1, and the switch control signal SW1 transition from high level (H) to low level (L). The storage control signal SG1 transitions from low level (L) to high level (H). The overflow control signal OG1 and the gain control signal DCG2 remain at high level (H). In the first integration period T201, the overflow control signal OG1, the gain control signal DCG2, and the storage control signal SG1 have a high level (H), and the reset control signal RG1, the transmission control signal TG1, the switch control signal SW1, and the selection signal SEL1 have a low level (L).

[0069] Regarding the operation of pixel PX3 in the first integration interval T201, please also refer to FIG. FIG. 12 shows the potential levels of the elements in pixel PX3 in the first integration section T201. The potential of each channel is indicated by the height in the D1 direction. The capacitance of each channel is indicated by the width in the D2 direction. FIG. 12 shows the potential levels of the storage gate transistor SGX1, the photoelectric element PD1, the first floating diffusion node FN1, and the power supply voltage VDD in the pixel PX3. The regions of the first overflow transistor OX1, the first transfer transistor TX1, and the first reset transistor RX1 are also shown in the figure.

[0070] The potential level of the channel region of the first overflow transistor OX1 fluctuates between a first turn-on potential ON1 and a first turn-off potential OFF1 in response to the logic level of the overflow control signal OG1. In one embodiment, the first turn-on potential ON1 is −0.5V and the first turn-off potential OFF1 is −1.8V. The potential level of the second region (R2 in FIG. 4) channel region of the first transmission transistor TX1 varies between a second turn-on potential ON2 and a second turn-off potential OFF2 in response to the logic level of the transmission control signal TG1. The potential level of the first region (R1 in FIG. 4) channel region of the first transmission transistor TX1 varies between a third turn-on potential ON3 and a third turn-off potential OFF3 in response to the logic level of the transmission control signal TG1.

[0071] Here, the second turn-off potential OFF2 and the third turn-off potential OFF3 vary based on the doping concentrations of the first region R1 and the second region R2, respectively. For example, when the first region R1 is doped with n-type ions, the third turn-off potential OFF3 decreases. When the second region R2 is doped with p-type ions, the second turn-off potential OFF2 increases. The potential level of the channel region of the first reset transistor RX1 fluctuates between a fourth turn-on potential ON4 and a fourth turn-off potential OFF4 in response to the logic level of the reset control signal RG1.

[0072] The first turn-on potential ON1 has a value greater than the second turn-off potential OFF2, and the first turn-off potential OFF1 has a value smaller than the second turn-off potential OFF2. When the overflow control signal OG1 is at a high level (H), the overflow transistor OX1 has a first turn-on potential ON1, and when the transmission control signal TG1 is at a low level (L), the second region R2 of the first transmission transistor TX1 has a second turn-off potential OFF2, and the first region R1 of the first transmission transistor TX1 has a third turn-off potential OFF3. Here, the photocharge gradient generated by the photoelectric element PD1 corresponds to the total area of ​​the gradient portion. The photoelectric element PD1 generates enough photocharges to exceed the second turn-off potential OFF2 of the second region R2 of the transfer transistor TX1. Photocharges exceeding the second turn-off potential OFF2 of the transfer transistor TX1 pass through the overflow transistor OX1 and are stored in the storage gate transistor SGX1.

[0073] However, since the third turn-off potential OFF3 has a value smaller than the second turn-off potential OFF2, the photo-generated charges from the photoelectric element PD1 do not flow to the first floating diffusion node FN1. Meanwhile, the total area of ​​the first floating diffusion node FN1 and the portion filled in the power supply voltage VDD region represents the amount of charge corresponding to the kTC noise that randomly occurs during the reset period (RESET). However, the embodiment is not limited to this, and for example, as described below, the photocharges may be photocharges that exceed the capacity of the storage gate transistor SGX1 and overflow from the storage gate transistor SGX1 and accumulate in the first floating diffusion node FN1.

[0074] Referring again to FIG. 11, the overflow control signal OG1 transitions from high level (H) to low level (L) after the first integration interval T201. In the second integration period T203, the gain control signal DCG2 and the storage control signal SG1 have a high level (H), and the overflow control signal OG1, the reset control signal RG1, the transmission control signal TG1, the switch control signal SW1, and the selection signal SEL1 have a low level (L). Referring also to Figure 13, when the overflow control signal OG1 is at a low level (L), the overflow transistor OX1 has a first turn-off potential OFF1, and when the transmission control signal TG1 is at a low level (L), the second region R2 of the first transmission transistor TX1 has a second turn-off potential OFF2, and the first region R1 of the first transmission transistor TX1 has a third turn-off potential OFF3.

[0075] The photoelectric element PD1 can generate enough photocharges to exceed the third turn-off potential OFF3 of the first region R1 of the transfer transistor TX1. Photocharges exceeding the third turn-off potential OFF3 of the transfer transistor TX1 are accumulated in the first floating diffusion node FN1. Since the first turn-off potential OFF1 has a value smaller than the third turn-off potential OFF3, the photocharges generated by the photoelectric element PD1 do not flow into the storage gate transistor SGX1. In one embodiment, the ratio between the amount of charge transferred to the storage gate transistor SGX1 and the amount of charge transferred to the first floating diffusion node FN1 is controlled based on the ratio between the first integration section T201 and the second integration section T203. Thus, the operation of the overflow transistor OX1 is controlled via the overflow control signal OG1, so that the charges generated from the photoelectric element PD can be appropriately transferred to the storage gate transistor SGX1 or the first floating diffusion node FN1.

[0076] Referring again to FIG. 11, the readout section (READOUT) is a section in which the pixel signal VOUT generated in the pixel PX3 is transmitted to the readout circuit (150 in FIG. 1). One lead-out section (READOUT) includes a first lead-out section T301, a second lead-out section T303, a third lead-out section T305, a fourth lead-out section T307, a fifth lead-out section T309, a sixth lead-out section T311, a seventh lead-out section T313, an eighth lead-out section T315, a ninth lead-out section T317, and a tenth lead-out section T319. In the read-out section (READOUT), the selection control signal SEL1 transitions from a low level (L) to a high level (H). When the selection control signal SEL1 is maintained at a high level (H), the pixel PX3 reads out the pixel signal VOUT.

[0077] The pixel PX3 in the first read-out section T301 outputs a signal corresponding to the charge accumulated in the first floating diffusion node FN1 as a pixel signal VOUT. In the first read-out section T301, the gain control signal DCG2 and the storage control signal SG1 have a high level (H), and the overflow control signal OG1, the reset control signal RG1, the transmission control signal TG1, and the switch control signal SW1 have a low level (L). A high level (H) of the gain control signal DCG2 causes the pixel PX3 to operate in the LCG mode. Thereafter, the reset control signal RG1 transitions from low level (L) to high level (H).

[0078] The second read-out section T303 is a section for resetting the charge accumulated in the first floating diffusion node FN1. In the second read-out section T303, the reset control signal RG1, the gain control signal DCG2, and the storage control signal SG1 have a high level (H), and the overflow control signal OG1, the transmission control signal TG1, and the switch control signal SW1 have a low level (L). During the third read-out period T305, the pixel PX3 outputs a signal corresponding to the reset charge of the first floating diffusion node FN1 as the pixel signal VOUT. Here, the pixel PX3 operates in the LCG mode due to the high level (H) of the gain control signal DCG2. The fourth read-out section T307 is a section in which the charge stored in the storage gate transistor SGX1 is transferred to the first floating diffusion node FN1.

[0079] For example, the switch control signal SW1 transitions from a low level (L) to a high level (H). While the switch control signal SW1 maintains a high level (H), the storage control signal SG1 transitions from a high level (H) to a low level (L). Therefore, all the photo-induced charges stored in the storage gate transistor SGX1 are transferred to the first floating diffusion node FN1. Thereafter, the switch control signal SW1 transitions from high level (H) to low level (L), and the storage control signal SG1 transitions from low level (L) to high level (H). During the fifth read-out period T309, the pixel PX3 outputs a signal corresponding to the charge of the first floating diffusion node FN1 as the pixel signal VOUT. Here, the first floating diffusion node FN1 accumulates charges transferred from the storage gate transistor SGX1. A high level (H) of the gain control signal DCG2 causes the pixel PX3 to operate in the LCG mode.

[0080] In the sixth lead-out section T311, the gain control signal DCG2 transitions from a high level (H) to a low level (L). The seventh read-out section T313 is a section for resetting the charge accumulated in the first floating diffusion node FN1. In the seventh lead-out section T313, the reset control signal RG1 and the storage control signal SG1 have a high level (H), and the overflow control signal OG1, the transmission control signal TG1, the switch control signal SW1, and the gain control signal DCG2 have a low level (L). During the eighth read-out period T315, the pixel PX3 outputs a signal corresponding to the charge of the reset first floating diffusion node FN1 as the pixel signal VOUT. Here, the pixel PX3 operates in the HCG mode due to the gain control signal DCG2 being at a low level (L).

[0081] The ninth read-out section T317 is a section in which the charges accumulated in the photoelectric element PD1 are transferred to the first floating diffusion node FN1. For example, the transmission control signal TG1 transitions from a low level (L) to a high level (H). During the ninth read-out section T317, the transmission control signal TG1 and the storage control signal SG1 have a high level (H), and the reset control signal RG1, the overflow control signal OG1, the switch control signal SW1, and the gain control signal DCG2 have a low level (L). During the tenth read-out interval T319, the pixel PX3 outputs a signal corresponding to the charge of the first floating diffusion node FN1 as the pixel signal VOUT. Here, the first floating diffusion node FN1 may accumulate charges transferred from the photoelectric element PD1. A low level (L) gain control signal DCG2 causes pixel PX3 to operate in the HCG mode.

[0082] In FIG. 11, the fourth read-out section T307 is described as being included in the operation, but the present invention is not limited to this, and various methods for transferring the charge stored in the storage gate transistor SGX1 to the first floating diffusion node FN1 may also be used. Also, in FIG. 11, it has been described that multiple transistors are enabled when a high level (H) signal is applied, but the present invention is not limited to this, and any transistor may be enabled when a low level (L) signal is applied.

[0083] The image sensor (100 in FIG. 1) including the pixel PX3 senses an image signal using photocharges generated by one photoelectric element PD1. Specifically, in a low-illuminance environment where the amount of incident light is relatively small, photo-induced charges are stored in one floating diffusion node (first floating diffusion node FN1 in FIG. 4). In a high-illuminance environment where the amount of incident light is relatively large, photocharges are stored in the photoelectric element PD1, the storage gate transistor SGX1, and the second capacitor C2 in a certain proportion. Therefore, the image sensor 100 including the pixel PX3 can sense an image signal even in a relatively bright environment, thereby ensuring a wide dynamic range. On the other hand, in FIG. 11, the magnitude of the high level (H) of all the control signals (TG1, RG1, SEL1, SW1, OG1, SG1) is shown to be the same, but the present invention is not limited to this, and the strength of each signal may be set to be different for each of the multiple transistors.

[0084] FIG. 14 is a graph showing the amount of charge over time for operation of the image sensor of FIG. In a first integration period T201 in a relatively high illuminance environment, photocharges are accumulated according to the first graph L11 and the second graph L12. For example, the first graph L11 represents the charge stored in the photoelectric element PD1. Here, point A is a point that indicates the maximum capacity of photocharges that can be accumulated in the photoelectric element PD1. The second graph L12 represents the charge stored in the storage gate transistor SGX1. For example, once the photocharges generated by the photoelectric element PD1 exceed the capacity of the photocharges that can be stored in the photoelectric element PD1, the photocharges overflow into the storage gate transistor SGX1 and are stored therein. Thereafter, photocharges are accumulated up to the capacity of the storage gate transistor SGX1.

[0085] In the second integration section T203 in a relatively high illumination environment, photocharges are accumulated according to the third graph L13. For example, the third graph L13 represents the charge stored in the first floating diffusion node FN1. At this time, the first value K0 represents the amount of photocharges that have overflowed from the storage gate transistor SGX1. For example, the third graph L12 represents the photocharges having the first value K0 as well as the photocharges generated in the photoelectric element PD1 and transferred to the first floating diffusion node FN1. On the other hand, in a relatively low-illuminance environment, photocharges are accumulated according to the fourth graph L14 in the first integration interval T201 and the second integration interval T203. For example, the fourth graph L14 is a graph showing the charge accumulated in the first floating diffusion node FN1 in a relatively low-illuminance environment.

[0086] FIG. 15 is a timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. For example, FIG. 15 shows one scan interval for driving pixel PX3 according to FIG. One scanning period includes a reset period (RESET), an integration period (INTEGRATION), and a readout period (READOUT) in this order. The explanation of the reset section (RESET), integration section (INTEGRATION), and read-out section (READOUT) that overlaps with the explanation of FIG. 11 will be omitted.

[0087] The integration section is a section in which the photoelectric element PD is exposed to light and generates charges. The integration section includes a first integration section T211 and a second integration section T213. In the first integration period T211, the reset control signal RG1, the overflow control signal OG1, the gain control signal DCG2, and the storage control signal SG1 have a high level (H), and the transmission control signal TG1, the switch control signal SW1, and the selection signal SEL1 have a low level (L). The first reset transistor RX1 is turned on by the high level (H) reset control signal RG1, the power supply voltage VDD is applied to the first floating diffusion node FN1, and the first floating diffusion node FN1 is reset.

[0088] During the first integration period T211, when photoelectric charge generated from the photoelectric element PD1 exceeds the turn-off potential of the transfer transistor TX1, the photoelectric charge exceeding the turn-off potential of the transfer transistor TX1 passes through the overflow transistor OX1 and is stored in the storage gate transistor SGX1. Thereafter, when photocharges are generated in the photoelectric element PD1 to an extent that the capacity of the storage gate transistor SGX1 is exceeded, the excess photocharges overflow from the storage gate transistor SGX1 and are accumulated in the first floating diffusion node FN1. The photocharges accumulated in the first floating diffusion node FN1 may result in a noisy signal or may act as a signal loss.

[0089] On the other hand, since the first floating diffusion node FN1 is connected to the power supply voltage VDD, the photocharges that have overflowed from the storage gate transistor SGX1 to the first floating diffusion node FN1 are reset by the power supply voltage VDD. After the first integration period T201, the reset control signal RG1 and the overflow control signal OG1 transition from high level (H) to low level (L). In the second integration period T213, the gain control signal DCG2 and the storage control signal SG1 have a high level (H), and the overflow control signal OG1, the reset control signal RG1, the transmission control signal TG1, the switch control signal SW1, and the selection signal SEL1 have a low level (L).

[0090] FIG. 16 is a graph showing the amount of charge over time for operation of the image sensor of FIG. In a first integration period T211 under a relatively high illuminance environment, photocharges are accumulated according to the first graph L21 and the second graph L22. For example, the first graph L21 represents the charge accumulated on the photoelectric element PD1. Here, point A is a point that indicates the maximum capacity of photocharges that can be accumulated in the photoelectric element PD1. The second graph L22 represents the charge stored in the storage gate transistor SGX1. For example, once the photocharges generated by the photoelectric element PD1 exceed the capacity of the photocharges that can be stored in the photoelectric element PD1, the photocharges overflow into the storage gate transistor SGX1 and are stored therein. Thereafter, photocharges are accumulated up to the capacity of the storage gate transistor SGX1.

[0091] In the second integration section T213 in a relatively high illuminance environment, photocharges are accumulated according to the third graph L23. For example, the third graph L23 represents the charge stored in the first floating diffusion node FN1. At this time, the photoelectric charges overflowing from the photoelectric element PD1 and storage gate transistor SGX1 during the first integration period T211 are reset by the power supply voltage VDD, so only the photoelectric charges overflowing from the photoelectric element PD1 and storage gate transistor SGX1 during the second integration period T213 are accumulated in the first floating diffusion node FN1. Therefore, the image sensor 100 can measure the image signal more accurately. On the other hand, in a relatively low-illuminance environment, photocharges are accumulated in the first integration interval T211 and the second integration interval T213 according to the fourth graph L24. For example, the fourth graph L24 is a graph showing the charge accumulated in the first floating diffusion node FN1 in a relatively low-illuminance environment.

[0092] FIG. 17 is a timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. Specifically, FIG. 17 shows one scan interval for driving pixel PX3 according to FIG. One scanning period includes a reset period (RESET), an integration period (INTEGRATION), and a readout period (READOUT) in this order. The explanation of the reset section (RESET), integration section (INTEGRATION), and read-out section (READOUT) that overlaps with the explanation of the reset section (RESET), integration section (INTEGRATION), and read-out section (READOUT) that were described with reference to FIG. 15 will be omitted.

[0093] The integration section is a section in which the photoelectric element PD is exposed to light and generates charges. The integration section includes a first integration section T221 and a second integration section T223. In the first integration period T221, the reset control signal RG1, the gain control signal DCG2, and the storage control signal SG1 have a high level (H), and the transmission control signal TG1, the switch control signal SW1, and the selection signal SEL1 have a low level (L). The overflow control signal OG1 toggles at regular intervals. The row driver (130 in FIG. 1) adjusts the ratio between the period during which the overflow control signal OG1 is at a high level (H) and the period during which the overflow control signal OG1 is at a low level (L), thereby controlling the transfer of a portion of the charge generated from the photoelectric element PD1 to the storage gate transistor SGX1. Therefore, the row driver (130 in FIG. 1) can achieve a similar effect to adjusting the sensitivity of pixel PX3.

[0094] For example, the ratio of the period during which the overflow control signal OG1 is at a high level (H) to the period during which the overflow control signal OG1 is at a low level (L) may be approximately 10%, but the present invention is not limited to this. After the first integration period T221, the reset control signal RG1 may transition from high level (H) to low level (L), and the overflow control signal OG1 may stop toggling and transition to low level (L). In the second integration period T223, the gain control signal DCG2 and the storage control signal SG1 may have a high level (H), and the overflow control signal OG1, the reset control signal RG1, the transmission control signal TG1, the switch control signal SW1, and the selection signal SEL1 may have a low level (L).

[0095] FIG. 18 is a graph showing the amount of charge over time for operation of the image sensor of FIG. In a first integration interval T221 in a relatively high illuminance environment, photocharges are accumulated according to the first graph L31 and the second graph L32. For example, the first graph L31 represents the charge accumulated on the photoelectric element PD1. Here, point A is a point that indicates the maximum capacity of photocharges that can be accumulated in the photoelectric element PD1. A second graph L32 represents the charge stored in the storage gate transistor SGX1. For example, once the photocharges generated by the photoelectric element PD1 exceed the capacity of the photocharges that can be stored in the photoelectric element PD1, the photocharges overflow into the storage gate transistor SGX1 and are stored therein. Meanwhile, in the first integration period T221, the overflow control signal OG1 toggles, so that the photocharges overflowing from the photoelectric element PD1 are alternately transferred to the first floating diffusion node FN1 and the storage gate transistor SGX1. Here, the photo-induced charges transferred to the first floating diffusion node FN1 are reset by the power supply voltage VDD.

[0096] Thereafter, photocharges are stored up to the capacity of the storage gate transistor SGX1. Photocharges generated beyond the capacity of storage gate transistor SGX1 cannot be stored in storage gate transistor SGX1, and therefore the amount of photocharges in that portion may not be measured accurately. However, according to the operation of the image sensor shown in FIG. 17, a portion of the photocharges generated from the photoelectric element PD1 can be transferred to the storage gate transistor SGX1. Therefore, the total amount of photocharge is estimated based on the amount of photocharge accumulated in the storage gate transistor SGX1.

[0097] In the second integration section T223 in a relatively high illumination environment, photocharges are accumulated according to the third graph L33. For example, the third graph L33 represents the charge stored in the first floating diffusion node FN1. During the first integration period T221, the photocharges overflowing from the photoelectric element PD1 and storage gate transistor SGX1 are reset by the power supply voltage VDD, so that only the photocharges overflowing from the photoelectric element PD1 and storage gate transistor SGX1 are stored in the first floating diffusion node FN1 during the second integration period T223. Therefore, the image sensor 100 can measure the image signal more accurately. On the other hand, in a relatively low-illuminance environment, photocharges are accumulated in the first integration interval T221 and the second integration interval T223 according to the fourth graph L34. For example, the fourth graph L34 is a graph showing the charge accumulated in the first floating diffusion node FN1 in a relatively low-illuminance environment.

[0098] FIG. 19 is a timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. For example, FIG. 19 shows one scan interval for driving pixel PX3 according to FIG. One scanning period includes a reset period (RESET), an integration period (INTEGRATION), and a readout period (READOUT) in this order. The explanation of the reset section (RESET), integration section (INTEGRATION), and read-out section (READOUT) that overlaps with the explanation of the reset section (RESET), integration section (INTEGRATION), and read-out section (READOUT) that were described with reference to FIG. 15 will be omitted. The integration section is a section in which the photoelectric element PD is exposed to light and generates charges. The integration section includes a first integration section T231, a second integration section T232, and a third integration section T233.

[0099] In the first integration period T231, the reset control signal RG1, the gain control signal DCG2, and the storage control signal SG1 have a high level (H), and the transmission control signal TG1, the overflow control signal OG1, the switch control signal SW1, and the selection signal SEL1 have a low level (L). After the first integration period T231, the overflow control signal OG1 transitions from low level (L) to high level (H).

[0100] In the second integration period T232, the reset control signal RG1, the overflow control signal OG1, the gain control signal DCG2, and the storage control signal SG1 have a high level (H), and the transmission control signal TG1, the switch control signal SW1, and the selection signal SEL1 have a low level (L). During the second integration period T232, when photoelectric charge generated from the photoelectric element PD1 exceeds the turn-off potential of the transfer transistor TX1, the photoelectric charge exceeding the turn-off potential of the transfer transistor TX1 passes through the overflow transistor OX1 and is stored in the storage gate transistor SGX1. Photocharges generated by the photoelectric element PD1 are transferred to the storage gate transistor SGX1 during a second integration interval T232, which is shorter than the first integration interval T231. The total amount of photocharge is estimated based on the amount of photocharge accumulated in the storage gate transistor SGX1. After the second integration period T232, the reset control signal RG1 and the overflow control signal OG1 transition from high level (H) to low level (L).

[0101] In the third integration period T233, the gain control signal DCG2 and the storage control signal SG1 have a high level (H), and the overflow control signal OG1, the reset control signal RG1, the transmission control signal TG1, the switch control signal SW1, and the selection signal SEL1 have a low level (L). The row driver (130 in FIG. 1) adjusts the ratio between the period during which the overflow control signal OG1 is at a high level (H) and the period during which the overflow control signal OG1 is at a low level (L), thereby controlling the transfer of a portion of the charge generated from the photoelectric element PD1 to the storage gate transistor SGX1. Therefore, the row driver (130 in FIG. 1) can achieve a similar effect to adjusting the sensitivity of pixel PX3. For example, the ratio of the period during which the overflow control signal OG1 is at high level (H) to the period during which the overflow control signal OG1 is at low level (L) is about 10%, but the present invention is not limited to this.

[0102] FIG. 20 is a graph showing the amount of charge over time for operation of the image sensor of FIG. In a first integration interval T231 under a relatively high illumination environment, photocharges are accumulated according to a first graph L41. For example, the first graph L21 represents the charge accumulated on the photoelectric element PD1. Here, point A is a point that indicates the maximum capacity of photocharges that can be accumulated in the photoelectric element PD1. Photoelectric charges generated during the first integration interval T231 exceeding the maximum amount of photoelectric charge that can be accumulated in the photoelectric element PD1 are reset by the power supply voltage VDD at the first floating diffusion node FD1.

[0103] In the second integration interval T232 in a relatively high illumination environment, photocharges are accumulated according to the second graph L42. For example, the second graph L42 represents the charge stored in the storage gate transistor SGX1. During the second integration period T232, which is shorter than the first integration period T231, photocharges are transferred to the storage gate transistor SGX1, so that the photocharges are accumulated in the storage gate transistor SGX1 without exceeding the maximum capacity of the storage gate transistor SGX1. Therefore, the image sensor 100 can measure the image signal more accurately.

[0104] In the third integration interval T233 under a relatively high illumination environment, photocharges are accumulated according to the third graph L43. For example, the third graph L43 represents the charge stored in the first floating diffusion node FN1. On the other hand, in a relatively low-illuminance environment, photocharges are accumulated according to the fourth graph L44 in the first integration interval T231, the second integration interval T232, and the third integration interval T233. For example, the fourth graph L44 is a graph showing the charge accumulated in the first floating diffusion node FN1 in a relatively low-illuminance environment.

[0105] FIG. 21 is a timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. For example, FIG. 21 shows one scan interval for driving pixel PX3 according to FIG. One scanning period includes a reset period (RESET), an integration period (INTEGRATION), and a readout period (READOUT) in this order. The explanation of the reset section (RESET), integration section (INTEGRATION), and read-out section (READOUT) that overlaps with the explanation of the reset section (RESET), integration section (INTEGRATION), and read-out section (READOUT) that were described with reference to FIG. 19 will be omitted. The integration section is a section in which the photoelectric element PD is exposed to light and generates charges. The integration section includes a first integration section T241 and a second integration section T243.

[0106] In the first integration period T241, the gain control signal DCG2 and the storage control signal SG1 have a high level (H), and the reset control signal RG1, the transmission control signal TG1, the overflow control signal OG1, the switch control signal SW1, and the selection signal SEL1 have a low level (L). The photoelectric element PD1 can generate photocharges that exceed the turn-off potential of the first region R1 of the transfer transistor TX1. Photocharges exceeding the turn-off potential of the first region R1 of the transfer transistor TX1 are accumulated in the first floating diffusion node FN1. The turn-off potential of the overflow transistor is smaller than the turn-off potential of the first region R1 of the first transfer transistor TX1, so that the photocharges generated from the photoelectric element PD1 do not flow to the storage gate transistor SGX1. For example, photocharges generated in excess of the capacitance of the photoelectric element PD1 during the first integration period T241 are transferred to and accumulated at the first floating diffusion node FN1. After the first integration interval T231, the overflow control signal OG1 transitions from low level (L) to high level (H).

[0107] In the second integration period T243, the overflow control signal OG1, the gain control signal DCG2, and the storage control signal SG1 have a high level (H), and the reset control signal RG1, the transmission control signal TG1, the switch control signal SW1, and the selection signal SEL1 have a low level (L). During the second integration period T243, when photoelectric charge generated from the photoelectric element PD1 exceeds the turn-off potential of the transfer transistor TX1, the photoelectric charge exceeding the turn-off potential of the transfer transistor TX1 passes through the overflow transistor OX1 and is stored in the storage gate transistor SGX1. Photocharges generated by the photoelectric element PD1 are transferred to the storage gate transistor SGX1 during a second integration interval T243, which is shorter than the first integration interval T241. The total amount of photocharge is estimated based on the amount of photocharge accumulated in the storage gate transistor SGX1.

[0108] The row driver (130 in FIG. 1) adjusts the ratio between the period during which the overflow control signal OG1 is at a high level (H) and the period during which the overflow control signal OG1 is at a low level (L), thereby controlling the transfer of a portion of the charge generated from the photoelectric element PD1 to the storage gate transistor SGX1. Therefore, the row driver (130 in FIG. 1) can achieve a similar effect to adjusting the sensitivity of pixel PX3. For example, the ratio of the period during which the overflow control signal OG1 is at high level (H) to the period during which the overflow control signal OG1 is at low level (L) is about 10%, but the present invention is not limited to this.

[0109] FIG. 22 is a graph showing the amount of charge over time for operation of the image sensor of FIG. In a first integration interval T241 under a relatively high illuminance environment, photocharges are accumulated according to the first graph L51 and the third graph L53. For example, the first graph L51 represents the charge accumulated in the photoelectric element PD1. Here, point A is a point that indicates the maximum capacity of photocharges that can be accumulated in the photoelectric element PD1. The third graph L53 represents the charge stored in the first floating diffusion node FN1.

[0110] In the second integration section T243 in a relatively high illuminance environment, photocharges are accumulated according to the second graph L52. A second graph L52 represents the charge stored in the storage gate transistor SGX1. For example, photocharges generated by the photoelectric element PD1 are accumulated in the photoelectric element PD1, transferred to the first floating diffusion node FN1, and then transferred to the storage gate transistor SGX1. Photocharges generated by the photoelectric element PD1 are transferred to the storage gate transistor SGX1 during a second integration interval T243, which is shorter than the first integration interval T241. The total amount of photocharge is estimated based on the amount of photocharge accumulated in the storage gate transistor SGX1. In a relatively low-light environment, photocharges are accumulated in the first integration interval T241 and the second integration interval T243 according to the fourth graph L54. For example, the fourth graph L54 is a graph showing the charge accumulated in the first floating diffusion node FN1 in a relatively low-illuminance environment.

[0111] FIG. 23 is a circuit diagram of a pixel according to an embodiment of the present invention. As shown in FIG. 23, pixel PX4 includes a photosensitive element PD1 and a pixel circuit that processes the charge generated by photosensitive element PD1 and outputs an electrical signal. The pixel circuit includes a plurality of transistors, for example, a first transfer transistor TX1, a first reset transistor RX1, a first drive transistor DX1, a first select transistor SX1, a first switch transistor SWX1, a first overflow transistor OX1, and a storage diode SD.

[0112] The storage diode SD is a charge storage element that can store the photoelectric charge generated by the photoelectric element PD. The cathode of the storage diode SD becomes the storage diode region. In one embodiment, the storage diode SD may further be disposed in the semiconductor substrate. In one embodiment, a storage gate for controlling the storage diode SD may further be disposed on the storage diode SD. In one embodiment, the storage diode SD stores a portion of the photocharge generated from the photosensitive element PD. The storage diode SD is realized by doping n-type impurities into a semiconductor substrate. The storage diode SD has a small dark current that can be generated when reading out pixel signals, and is capable of performing a readout operation using a correlated double sampling (CDS) method. Also, when resetting with the power supply voltage, there is little charge remaining in the storage diode SD.

[0113] FIG. 24 is a circuit diagram of a pixel according to an embodiment of the present invention. As shown in FIG. 24, pixel PX5 includes a photosensitive element PD1 and a pixel circuit that processes the charge generated by photosensitive element PD1 and outputs an electrical signal. The pixel circuit includes a plurality of transistors, for example, a first transfer transistor TX1, a first reset transistor RX1, a first drive transistor DX1, a first select transistor SX1, a first switch transistor SWX1, a first overflow transistor OX1, and a fifth capacitor C5. In one embodiment, the fifth capacitor C5 includes a Lateral Overflow Integration Capacitor (LOFIC). In one embodiment, the fifth capacitor C5 may be a MIM (Metal Insulator Metal) type or a cylinder type capacitor used in DRAM.

[0114] FIG. 25 is a circuit diagram of a pixel according to an embodiment of the present invention. As shown in FIG. 25, pixel PX6 includes a photosensitive element PD2 that generates an electric charge in response to light, and a pixel circuit that processes the electric charge generated by photosensitive element PD2 and outputs an electric signal. The photoelectric element PD2 generates a photoelectric charge that varies depending on the intensity of the light. For example, the cathode of the photoelectric element PD2 is connected to the floating node FN2 via the second transfer transistor TX2, and the anode of the photoelectric element PD2 is grounded. Control signals (TG2, RG2, SEL2, OG2, SG2, DCG3) are applied to pixel PX6.

[0115] In one embodiment, the control signals are generated in the row driver ( 130 in FIG. 1) under the control of the timing controller 120 . The transistors (TX2, RX2, SX2, OX2, SGX2, DCX3) in the pixel circuit operate in response to control signals provided from the row driver 130, such as a transmission control signal TG2, a reset control signal RG2, a selection signal SEL2, an overflow control signal OG2, and a storage control signal SG2. The pixel circuit includes a first circuit for processing photocharges generated from the photosensitive element PD2, a second circuit 601 for storing the photocharges, and a third circuit for outputting an electrical signal. For example, the first circuit includes a plurality of transistors, such as a second transfer transistor TX2, a second overflow transistor OX2, and a storage gate transistor SGX2.

[0116] The second transfer transistor TX2 is connected between the photoelectric element PD2 and the second floating diffusion node FN2. The second transmission transistor TX2 is controlled by a transmission control signal TG2. When the second transfer transistor TX2 is turned on, the charges generated by the photoelectric element PD2 are transferred to the second floating diffusion node FN2. In one embodiment, the second transfer transistor TX2 includes a vertical transfer gate. The gate electrode of the second transfer transistor TX2 may extend along the thickness direction of the semiconductor substrate. The doping concentration on one side of the second transfer transistor TX2 may be different from the doping concentration on the other side. For example, a first region R21 between the second transfer transistor TX2 and the overflow transistor OX2 has a first doping concentration, and a second region R22 between the second transfer transistor TX2 and the second floating diffusion node FN2 has a second doping concentration.

[0117] In one embodiment, the first region R21 is a region doped with n-type impurities. For example, the first region R21 is doped with n-type impurities via an ion implantation process. As will be described later, photo-generated charges from the photoelectric element PD2 are transferred to the storage gate transistor SGX2 via the first region R21. In one embodiment, the second region R22 is a region doped with p-type impurities. For example, the second region R22 is doped with p-type impurities via an ion implantation process. For example, the second region R22 is provided as a p-well region for the second transfer transistor TX2.

[0118] The second overflow transistor OX2 is connected between the photoelectric element PD2 and a third node N23. The second overflow transistor OX2 is controlled by an overflow control signal OG2. When the second overflow transistor OX2 is turned on, the charges generated by the photoelectric element PD2 are transferred to the third node N23. In one embodiment, the amount of charge generated in the photoelectric element PD2 and transferred to the third node N23 can be controlled based on the magnitude of the overflow control signal OG2 applied to the second overflow transistor OX2. In one embodiment, the second overflow transistor OX2 may be used to control the transfer of photocharges generated by the photosensitive element PD2 to the storage gate transistor SGX2. For example, the second overflow transistor OX2 controls a portion of the photocharges that exceed the capacity of the photoelectric element PD2 from overflowing into the storage gate transistor SGX2. For example, in a high illumination environment where the intensity of incident light incident on the pixel PX6 is very high, the second overflow transistor OX2 transfers a part of the photocharges overflowing from the photosensitive element PD2 to the storage gate transistor SGX2.

[0119] The storage gate transistor SGX2 is connected between the third node N23 and the ground power supply. The storage gate transistor SGX2 is controlled by a storage control signal SG2. The storage gate transistor SGX2 is a charge storage element that can store the photocharges generated by the photoelectric element PD2. The storage gate transistor SGX2 is controlled by a storage gate signal SG2. In one embodiment, the amount of charge that can be stored in storage gate transistor SGX2 varies based on storage gate signal SG2. In one embodiment, the storage gate transistor SGX2 may have a structure that includes an additional storage diode underneath.

[0120] The second circuit 603 includes a dual conversion gain circuit 603 . For example, the dual conversion gain circuit 603 is connected in parallel with the second reset transistor RX2. Specifically, the dual conversion gain circuit 603 includes a third gain control transistor DCX3 and a sixth capacitor C6. The third gain control transistor DCX3 is connected between the second floating diffusion node FN2 and the fourth node N24. The third gain control transistor DCX3 is controlled by a gain control signal DCG3. When the third gain control transistor DCX3 is turned on, the second floating diffusion node FN2 and the sixth capacitor C6 are connected, increasing the capacitance of the second floating diffusion node FN2 and decreasing the conversion gain, which is the rate at which charge is converted to voltage. That is, when the third gain control transistor DCX3 is turned on, the converter operates in a low conversion gain LCG mode. On the other hand, when the third gain control transistor DCX3 is turned off, the converter operates in the high conversion gain HCG mode.

[0121] The third circuit 605 includes a second reset transistor RX2, a second drive transistor DX2, and a second select transistor SX2. The second reset transistor RX2 is connected between a power supply voltage line that supplies a power supply voltage VDD and a second floating diffusion node FN2. The second reset transistor RX2 is controlled by a reset control signal RG2. When the second reset transistor RX2 is turned on, the power supply voltage VDD is applied to the second floating diffusion node FN2, resetting the second floating diffusion node FN2. The gate of the second driver transistor DX2 is connected to the second floating diffusion node FN2. The second driver transistor DX2 operates as a source-follower amplifier for the voltage of the second floating diffusion node FN2. The second driving transistor DX2 outputs the pixel signal VOUT to the column line CL through the second selection transistor SX2 in response to the voltage of the second floating diffusion node FN2.

[0122] The second selection transistor SX2 is connected to the first terminal of the second drive transistor DX2 and the column line CL, and is controlled by a selection control signal SEL2. When the second selection transistor SX2 is turned on, the pixel voltage VOUT output from the second driving transistor DX2 is output to the readout circuit (150 in FIG. 1) via the column line CL connected to the second selection transistor SX2. On the other hand, in FIG. 25, pixel PX6 is shown as including a dual conversion gain circuit 603 in parallel with the second reset transistor RX2, but the present invention is not limited to this, and pixel PX6 may include a dual conversion gain circuit 603 connected in series with the second reset transistor RX2, or may not include a dual conversion gain circuit 603.

[0123] FIG. 26 is a timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. For example, FIG. 26 shows one scan interval for driving pixel PX6 according to FIG. One scanning period includes a reset period (RESET), an integration period (INTEGRATION), and a readout period (READOUT) in this order. In the reset period (RESET), the charges stored in the second floating diffusion node FN2, the second node N22, the third node N23, and the fourth node N24 are reset. For example, in the reset period (RESET), the reset control signal RG2, the transmission control signal TG2, the overflow control signal OG2, and the gain control signal DCG3 all have a high level (H). The storage control signal SG2 and the selection signal SEL2 have a low level (L). Therefore, the second floating diffusion node FN2, the second node N22, the third node N23, and the fourth node N24 are all reset to the power supply voltage VDD.

[0124] The integration period is a period in which the photoelectric element PD2 is exposed to light and generates charges. The integration section includes a first integration section T251, a second integration section T252, and a third integration section T253. In the first integration period T251, the reset control signal RG2, the gain control signal DCG3, and the storage control signal SG2 have a high level (H), and the transmission control signal TG2, the overflow control signal OG2, and the selection signal SEL2 have a low level (L). After the first integration interval T251, the overflow control signal OG2 transitions from low level (L) to high level (H).

[0125] In the second integration period T252, the reset control signal RG2, the overflow control signal OG2, the gain control signal DCG3, and the storage control signal SG2 have a high level (H), and the transmission control signal TG2 and the selection signal SEL2 have a low level (L). During the second integration period T252, when photoelectric charge generated from the photoelectric element PD2 exceeds the turn-off potential of the transfer transistor TX2, the photoelectric charge exceeding the turn-off potential of the transfer transistor TX2 passes through the overflow transistor OX2 and is stored in the storage gate transistor SGX2. Photocharges generated by the photoelectric element PD2 are transferred to the storage gate transistor SGX2 during a second integration interval T252, which is shorter than the first integration interval T251. The total amount of photocharge is estimated based on the amount of photocharge accumulated in the storage gate transistor SGX2. After the second integration period T252, the reset control signal RG2 and the overflow control signal OG2 transition from high level (H) to low level (L).

[0126] In the third integration period T253, the gain control signal DCG3 and the storage control signal SG2 have a high level (H), and the overflow control signal OG2, the reset control signal RG2, the transmission control signal TG2, and the selection signal SEL2 have a low level (L). The row driver (130 in FIG. 1) adjusts the ratio between the period during which the overflow control signal OG2 is at a high level (H) and the period during which the overflow control signal OG2 is at a low level (L), thereby controlling the transfer of a portion of the charge generated from the photoelectric element PD2 to the storage gate transistor SGX2. Therefore, the row driver (130 in FIG. 1) can achieve a similar effect to adjusting the sensitivity of pixel PX6. For example, the ratio of the period during which the overflow control signal OG2 is at high level (H) to the period during which the overflow control signal OG2 is at low level (L) is about 10%, but the present invention is not limited to this.

[0127] The readout section (READOUT) is a section in which the pixel signal VOUT generated from the pixel PX6 is transmitted to the readout circuit (150 in FIG. 1). One lead-out section (READOUT) includes a first lead-out section T401, a second lead-out section T403, a third lead-out section T405, a fourth lead-out section T407, a fifth lead-out section T409, a sixth lead-out section T411, a seventh lead-out section T413, an eighth lead-out section T415, a ninth lead-out section T417, and a tenth lead-out section T419. In the read-out period (READOUT), the selection control signal SEL2 transitions from a low level (L) to a high level (H). When the selection control signal SEL2 is maintained at a high level (H), the pixel PX6 reads out the pixel signal VOUT.

[0128] The pixel PX6 in the first read-out section T401 outputs a signal corresponding to the charge accumulated in the second floating diffusion node FN2 as a pixel signal VOUT. In the first lead-out section T401, the gain control signal DCG3 and the storage control signal SG2 have a high level (H), and the overflow control signal OG2, the reset control signal RG2, and the transmission control signal TG2 have a low level (L). A high level (H) of the gain control signal DCG3 causes the pixel PX6 to operate in the LCG mode. In the second lead-out section T403, the gain control signal DCG3 transitions from high level (H) to low level (L).

[0129] The third read-out section T405 is a section for resetting the charge accumulated in the second floating diffusion node FN2. In the third lead-out section T405, the reset control signal RG2 and the storage control signal SG2 have a high level (H), and the transmission control signal TG2, the overflow control signal OG2, and the gain control signal DCG3 have a low level (L). During the fourth read-out period T407, the pixel PX6 outputs a signal corresponding to the charge of the reset second floating diffusion node FN2 as the pixel signal VOUT. Here, the pixel PX6 operates in the HCG mode due to the gain control signal DCG3 being at a low level (L).

[0130] The fifth read-out section T409 is a section in which the charges accumulated in the photoelectric element PD2 are transferred to the second floating diffusion node FN2. For example, the transmission control signal TG2 transitions from a low level (L) to a high level (H). During the ninth lead-out section T417, the transmission control signal TG2 and the storage control signal SG2 have a high level (H), and the reset control signal RG2, the overflow control signal OG2, and the gain control signal DCG3 have a low level (L). During the sixth read-out period T411, the pixel PX6 outputs a signal corresponding to the charge of the second floating diffusion node FN2 as the pixel signal VOUT. Here, the second floating diffusion node FN2 accumulates the charges transferred from the photoelectric element PD2. A low level (L) gain control signal DCG3 causes the pixel PX6 to operate in the HCG mode.

[0131] The seventh read-out section T413 is a section for resetting the charges accumulated in the second floating diffusion node FN2 and the fourth node N24. In the seventh lead-out section T413, the reset control signal RG2, the gain control signal DCG3, and the storage control signal SG2 have a high level (H), and the transmission control signal TG2 and the overflow control signal OG2 have a low level (L). During the eighth read-out period T415, the pixel PX6 outputs a signal corresponding to the charge of the reset second floating diffusion node FN2 as the pixel signal VOUT. Here, the pixel PX6 operates in the LCG mode due to the high level (H) of the gain control signal DCG3.

[0132] The ninth read-out section T417 is a section in which the charge stored in the storage gate transistor SGX2 is transferred to the second floating diffusion node FN2 via the second node N22. For example, the transmission control signal TG2 and the overflow control signal OG2 transition from a low level (L) to a high level (H). While the transmission control signal TG2 and the overflow control signal OG2 maintain a high level (H), the storage control signal SG2 transitions from a high level (H) to a low level (L). Therefore, all the photo-induced charges stored in the storage gate transistor SGX2 are transferred to the second floating diffusion node FN2. Thereafter, the transmission control signal TG2 and the overflow control signal OG2 transition from high level (H) to low level (L), and the storage control signal SG2 transitions from low level (L) to high level (H).

[0133] During the tenth read-out period T419, the pixel PX6 outputs a signal corresponding to the charge of the second floating diffusion node FN2 as the pixel signal VOUT. Here, the second floating diffusion node FN2 accumulates the charges transferred from the storage gate transistor SGX2. A high level (H) of the gain control signal DCG2 causes the pixel PX6 to operate in the LCG mode. Meanwhile, in FIG. 26, the operation is described as including the ninth read-out section T417, but the present invention is not limited to this, and various methods for transferring the charge stored in the storage gate transistor SGX2 to the second floating diffusion node FN2 may be used. Also, in FIG. 26, it has been described that multiple transistors are enabled when a high level (H) signal is applied, but the present invention is not limited to this, and any transistor may be enabled when a low level (L) signal is applied.

[0134] The image sensor (100 in FIG. 1) including the pixel PX6 senses an image signal using photocharges generated by one photoelectric element PD2. For example, in a low-light environment where the amount of incident light is relatively small, photo-induced charges are stored in one floating diffusion node (the second floating diffusion node FN2 in FIG. 25). In a high-illuminance environment where the amount of incident light is relatively large, the photocharges are stored in the photoelectric element PD2, the storage gate transistor SGX2, and the sixth capacitor C6 in a certain proportion. Therefore, the image sensor 100 including the pixel PX6 can sense an image signal even in a relatively high-illumination environment, thereby ensuring a relatively wide dynamic range. On the other hand, in Figure 26, the magnitude of the high level (H) of all control signals (TG2, RG2, SEL2, OG2, SG2) is shown to be the same, but the present invention is not limited to this, and the strength of each signal may be set to be different depending on each of the multiple transistors.

[0135] FIG. 27 is a circuit diagram of a pixel according to an embodiment of the present invention. As shown in FIG. 27, pixel PX7 includes a plurality of photosensitive elements (PD3, PD4) and a pixel circuit that processes the charges generated by each of the plurality of photosensitive elements (PD3, PD4) and outputs an electrical signal. Control signals (TG3, TG4, RG3, SEL3, OG3, OG4, SG3, SG4) are applied to pixel PX6.

[0136] In one embodiment, the control signals are generated in the row driver ( 130 in FIG. 1) under the control of the timing controller 120 . The transistors (TX3, TX4, RX3, SX3, OX3, OX4, SGX3, SGX4) in the pixel circuit operate in response to control signals provided from the row driver 130, such as transmission control signals (TG3, TG4), reset control signal RG3, selection signal SEL3, overflow control signals (OG3, OG4), and storage control signals (SG3, SG4). The pixel circuit includes a first circuit for processing the photocharges generated from the photosensitive element PD3, a second circuit for processing the photocharges generated from the photosensitive element PD4, and a third circuit for outputting an electrical signal. On the other hand, unless otherwise specified, the contents described for the first circuit with reference to FIG. 25 may be applied identically or similarly to the sub-circuits of the photoelectric elements (PD3, PD4) in FIG. 27, and the contents described for the third circuit with reference to FIG. 25 may be applied identically or similarly to the third circuit.

[0137] On the other hand, in FIG. 27, pixel PX7 is shown as not including a dual conversion gain circuit, but the present invention is not limited to this, and pixel PX7 may further include a dual conversion gain circuit. In one embodiment, pixel PX7 may also include a dual conversion gain circuit connected in series or parallel with the third reset transistor RX3. In FIG. 27, one pixel PX7 is shown as including two photoelectric elements (PD3, PD4), however the present invention is not limited to this and one pixel PX7 may include a greater or lesser number of photoelectric elements.

[0138] FIG. 28 is a schematic cross-sectional view of a pixel according to FIG. Referring to FIG. 28, the pixel PXd includes a pixel isolation pattern 221 and a plurality of transistors. The plurality of transistors include, for example, a third transfer transistor TX3 (4009), a fourth transfer transistor TX4 (4019), a third overflow transistor OX3 (4007), a fourth overflow transistor OX4 (4017), a storage gate transistor SGX3 (4005), a storage gate transistor SGX4 (4015), a third selection transistor SX3 (4001), and a drive transistor DX3 (4003). The pixel PXd includes two photosensitive elements under one microlens ML4. Although in FIG. 28 pixel PXd is shown as including two photosensitive elements, the present invention is not limited to this, and pixel PXd may include three or more photosensitive elements. Therefore, in a high illumination environment where a large amount of light is incident on the pixel PXd, an image signal can be sensed using at least one photoelectric element.

[0139] FIG. 29 is a block diagram showing a schematic configuration of an electronic device according to an embodiment of the present invention, and FIG. 30 is a block diagram showing a detailed configuration of a camera module according to FIG. Referring to FIG. 29, an electronic device 2000 includes a camera module group 2100, an application processor 2200, a PMIC 2300, an external memory 2400, and a display 2500. In one embodiment, the electronic device 2000 is mounted on a mobile device, a surveillance camera, a vehicle, or the like.

[0140] The camera module group 2100 includes multiple camera modules (2100a, 2100b, 2100c). In FIG. 29, camera module group 2100 is shown as including three camera modules (2100a, 2100b, 2100c), however the present invention is not limited thereto and camera module group 2100 may include at least one camera module. In one embodiment, the three camera modules (2100a, 2100b, 2100c) may be camera modules including the image sensor 100 described with reference to FIGS.

[0141] The camera module 2100b will be described with reference to FIG. The following description may be applied identically or similarly to other camera modules (2100a, 2100c) according to the embodiments. As shown in FIG. 30, the camera module 2100b includes a prism 2105, an optical path folding element (hereinafter referred to as “OPFE”) 2110, an actuator 2130, an image sensing device 2140, and a storage unit 2150.

[0142] Prism 2105 includes a reflecting surface 2107 made of a light-reflecting material, and changes the path of light L incident from the outside. In one embodiment, the prism 2105 changes the path of light L incident in a first direction (X direction) to a second direction (Y direction) perpendicular to the first direction (X direction). In addition, the prism 2105 can change the path of light L incident in a first direction (X direction) to a perpendicular second direction (Y direction) by rotating the reflecting surface 2107 of the light-reflecting material in direction A around the central axis 2106 or by rotating the central axis 2106 in direction B. At this time, the OPFE 2110 also moves in a third direction (Z direction) perpendicular to the first direction (X direction) and the second direction (Y direction). In one embodiment, the prism 2105 can move the reflective surface 2106 of the light-reflecting material in a third direction (eg, Z direction) parallel to the extension direction of the central axis 2106.

[0143] The OPFE 2110 includes, for example, m groups of optical lenses (where m is a natural number). The m lenses move in a second direction (Y direction) to change the optical zoom ratio of the camera module 2100b. For example, if the basic optical zoom magnification of camera module 2100b is Z, when m optical lenses included in OPFE 2110 are moved, the optical zoom magnification of camera module 2100b can be changed to an optical zoom magnification of 3Z or 5Z or more. The actuator 2130 moves the OPFE 2110 or the optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 2130 adjusts the position of the optical lens so that the image sensor 2142 is located at the focal length of the optical lens for accurate sensing.

[0144] The image sensing device 2140 includes an image sensor 2142 , control logic 2144 and memory 2146 . The image sensor 2142 senses an image of a sensing target using light L provided through an optical lens. In one embodiment, image sensor 2142 includes image sensor 100 described with reference to Figures 1-28. For example, an image sensor may include a transfer transistor that includes a vertical transfer gate with different potentials on one side and the other side. For example, one side and the other side of the gate electrode of the transfer transistor may have different doping concentrations. For example, one side of the gate electrode of a transfer transistor has a different oxide thickness than the other side.

[0145] The image sensor includes a charge storage element for storing photocharges generated from the photosensitive element, and an overflow transistor between the charge storage element and the transfer transistor. Here, the overflow transistor has a potential level between a first level higher than the potential level of one side of the transfer transistor and a second level lower than the potential level of the other side of the transfer transistor. The image sensor controls the overflow transistor to transfer the photocharges to the floating diffusion node during a first interval of the integration interval and to transfer the photocharges to the charge storage element during a second interval of the integration interval. Therefore, the image sensor can sense an accurate image signal even in a high-illumination environment by controlling one transistor.

[0146] Control logic 2144 controls the overall operation of camera module 2100b. For example, control logic 2144 controls the operation of camera module 2100b via control signals provided over control signal line CSLb. Memory 2146 stores information necessary for the operation of camera module 2100b, such as calibration data 2147. The calibration data 2147 includes information necessary for the camera module 2100b to generate image data using light L provided from an external source. The calibration data 2147 may include, for example, information regarding the degree of rotation described above, information regarding the focal length, information regarding the optical axis, and the like. If the camera module 2100b is implemented in the form of a multi-state camera in which the focal length changes depending on the position of the optical lens, the calibration data 2147 includes the focal length value for each position (or state) of the optical lens and information regarding autofocusing. Here, the memory 2146 includes the variable resistance element VR1 described above. For example, the memory 2146 includes a memory cell MC that includes a variable resistance element VR1.

[0147] The storage unit 2150 stores image data sensed through the image sensor 2142 . The storage unit 2150 may be disposed outside the image sensing device 2140 or may be implemented in a stacked form with the sensor chip that constitutes the image sensing device 2140. In one embodiment, the storage unit 2150 may be implemented as an Electrically Erasable Programmable Read-Only Memory (EEPROM), although embodiments are not limited thereto. The storage unit 2150 can be realized by the lower chip 300 . The storage unit 2150 includes a memory cell MC including the variable resistance element VR1 described above.

[0148] 29 and 30 together, in one embodiment, each of the multiple camera modules (2100a, 2100b, 2100c) includes an actuator 2130. Thus, each of the multiple camera modules (2100a, 2100b, 2100c) includes calibration data 2147 that may be the same or different depending on the operation of the actuator 2130 contained therein. In one embodiment, one of the multiple camera modules (2100a, 2100b, 2100c) (e.g., 2100b) may be a folded lens-type camera module including the above-mentioned prism 2105 and OPFE 2110, and the remaining camera modules (e.g., 2100a, 2100c) may be vertical-type camera modules that do not include the prism 2105 and OPFE 2110, but the embodiment is not limited thereto.

[0149] In one embodiment, one of the camera modules (2100a, 2100b, 2100c) (e.g., 2100c) may be a vertical depth camera that extracts depth information using, for example, IR (Infrared Ray). In this case, the application processor 1200 can merge the image data provided from such a depth camera with the image data provided from a different camera module (e.g., 2100a or 2100b) to generate a 3D depth image. In one embodiment, at least two camera modules (eg, 2100a, 2100c) of the plurality of camera modules (2100a, 2100b, 2100c) may have different fields of view (field of view angles). In this case, for example, the optical lenses of at least two camera modules (for example, 2100a, 2100c) among the plurality of camera modules (2100a, 2100b, 2100c) may be different from each other, but this is not limitative. In addition, in one embodiment, the viewing angles of each of the multiple camera modules (2100a, 2100b, 2100c) may be different from each other. In one embodiment, each of the multiple camera modules (2100a, 2100b, 2100c) is located physically separate from one another. In other words, instead of the sensing area of ​​one image sensor 2142 being divided and used by multiple camera modules (2100a, 2100b, 2100c), an independent image sensor 2142 is arranged inside each of the multiple camera modules (2100a, 2100b, 2100c).

[0150] Referring again to FIG. 29, the application processor 2200 includes an image processing unit 2210, a memory controller 2220, and an internal memory 2230. The application processor 2200 may be implemented separately from the multiple camera modules (2100a, 2100b, 2100c). For example, the application processor 2200 and the multiple camera modules (2100a, 2100b, 2100c) may be implemented separately from each other on separate semiconductor chips. The image processing device 2210 includes a plurality of sub-image processors (2212a, 2212b, 2212c), an image generator 2214, and a camera module controller 2216. The image processing device 2210 includes a number of sub-image processors (2212a, 2212b, 2212c) corresponding to the number of camera modules (2100a, 2100b, 2100c).

[0151] Image data generated from each camera module (2100a, 2100b, 2100c) is provided to the corresponding sub-image processor (2212a, 2212b, 2212c) via separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module 2100a is provided to sub-image processor 2212a via image signal line ISLa, image data generated from camera module 2100b is provided to sub-image processor 2212b via image signal line ISLb, and image data generated from camera module 2100c is provided to sub-image processor 2212c via image signal line ISLc. Such image data transmission can be performed using, for example, a camera serial interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiment is not limited to this.

[0152] In one embodiment, one sub-image processor may be arranged to correspond to multiple camera modules. For example, sub-image processor 2212a and sub-image processor 2212c may be implemented as a single integrated sub-image processor, rather than being implemented separately from each other as shown in the figure, and the image data provided from camera module 2100a and camera module 2100c may be selected via a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor. The image data provided to each of the sub-image processors (2212a, 2212b, 2212c) is provided to an image generator 2214. The image generator 2214 generates an output image using image data provided from each of the sub-image processors 2212a, 2212b, and 2212c according to image generating information or a mode signal. In one embodiment, the image generator 2214 receives multiple image data with different exposure times from at least one of the multiple sub-image processors (2212a, 2212b, 2212c) and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with an increased dynamic range.

[0153] The camera module controller 2216 provides control signals to each of the camera modules (2100a, 2100b, 2100c). The control signals generated by the camera module controller 2216 are provided to the corresponding camera modules (2100a, 2100b, 2100c) via separate control signal lines (CSLa, CSLb, CSLc). The application processor 2200 stores the received image signal, i.e., the encoded image signal, in the internal memory 2230 or the external storage 2400 of the application processor 2200, and then reads and decodes the encoded image signal from the memory 2230 or the storage 2400, and displays image data generated based on the decoded image signal. For example, a corresponding sub-processor among the multiple sub-processors (2212a, 2212b, 2212c) of the image processing device 2210 performs decoding and image processing on the decoded image signal. For example, the display 2500 displays image data generated based on the decoded image signal.

[0154] The PMIC 2300 supplies power, for example, a power supply voltage, to each of the multiple camera modules (2100a, 2100b, 2100c). For example, under the control of application processor 2200, PMIC 2300 supplies a first power to camera module 2100a via power signal line PSLa, a second power to camera module 2100b via power signal line PSLb, and a third power to camera module 2100c via power signal line PSLc. In response to a power control signal PCON from the application processor 2200, the PMIC 2300 generates power corresponding to each of the multiple camera modules (2100a, 2100b, 2100c) and adjusts the power level. The power control signal PCON includes a power adjustment signal for each operation mode of the multiple camera modules (2100a, 2100b, 2100c). For example, the operating mode may include a low power mode, and the power control signal PCON may then include information about the camera module operating in the low power mode and the set power level. The level of power provided to each of the multiple camera modules (2100a, 2100b, 2100c) may be the same as or different from each other. Additionally, the power level can be changed dynamically.

[0155] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0156] 100 image sensors 110 Controller 120 Timing Generator 130 Low Driver 140 pixel array 150 Readout circuit 160 Ramp Signal Generator 170 data buffers 180 Image Signal Processor 200 pixel array 210 Surface insulating layer 220 Semiconductor substrate 221 pixel isolated pattern 222 Insulating spacer film 223 Conductive Filling Pattern 230 Insulating layer 241 Photoelectric Conversion Region 242, 252, 262 Gate insulating film 243, 253, 263 Gate electrodes 244, 254, 264 Gate Spacer 245, 265 impurity implantation region 270 Color Filter Grid 271 Metal Pattern 272 Low refractive index pattern 1001 First selection transistor 1003 First drive transistor 1005 Storage Gate Transistor 1007 First overflow transistor 1009 First transmission transistor 1011 Second gain control transistor 1013 First reset transistor 1015 Photocharge Floating Diffusion Region 1017 Switch Transistor CF color filter layer FD Floating diffusion area ML Micro Lens PB P-type barrier PD photoelectric conversion element

Claims

1. a pixel including: a photoelectric element that generates photocharges; a charge storage element connected to the photoelectric element and storing the photocharges; a drive transistor that generates a pixel signal based on a voltage of a first node connected to the photoelectric element; a transfer transistor including a vertical transfer gate connected between the first node and a second node; a first region doped with a first doping concentration disposed on one side of the transfer transistor; a second region doped with a second doping concentration different from the first doping concentration disposed on the other side of the transfer transistor; and an overflow transistor disposed between the second node and the charge storage element; and a row driver connected to the pixels and controlling the pixels.

2. 2. The image sensor of claim 1, wherein the first region is a p-type doped region, the second region is an n-type doped region, the first node is connected to the first region, and the second node is connected to the second region.

3. The photoelectric element generates the photocharges in an integration section including a first section and a second section; The row driver During the first period, the overflow transistor is turned on to transfer first photocharges generated in the photoelectric element to the first node; 3. The image sensor of claim 2, wherein the pixel is controlled to turn off the overflow transistor during the second period and transfer second photocharges generated in the photoelectric element to the second node.

4. The pixel further includes a power supply voltage line configured to supply a power supply voltage and a reset transistor connected to the second node; 4. The image sensor of claim 3, wherein the row driver controls the pixel to turn on the reset transistor during the first period and reset the first photocharges transferred to the second node beyond the capacity of the charge storage element to the power supply voltage.

5. 4. The image sensor of claim 3, wherein the row driver controls the pixel so that a first operation of turning on the overflow transistor and a second operation of turning off the overflow transistor are repeated during the first period.

6. The image sensor of claim 3 , wherein the row driver performs the second period before the first period.

7. The pixel further includes a reset transistor connected to a power supply voltage line configured to supply a power supply voltage and the second node; The photoelectric element is configured to generate the photocharges in an integration section including a first section, a second section, and a third section; The row driver During the first period, the overflow transistor is turned off and the reset transistor is turned on to transfer first photocharges generated in the photoelectric element to the second node and reset the first photocharges to the power supply voltage; During the second interval, the overflow transistor is turned on to transfer second photocharges generated in the photoelectric element to the first node; 3. The image sensor of claim 2, wherein during the third period, the pixel is controlled to turn off the overflow transistor, turn off the reset transistor, and transfer a third photocharge generated in the photoelectric element to the second node.

8. one side of the vertical transmission gate has a first oxide thickness; 2. The image sensor of claim 1, wherein the other side of the vertical transmission gate has a second oxide thickness different from the first oxide thickness.

9. 2. The image sensor of claim 1, wherein the charge storage element is at least one of a storage gate transistor, a storage diode, and a metal insulator metal (MIM) capacitor.

10. 2. The image sensor of claim 1, wherein the potential of the overflow transistor is variable between a first level higher than the potential level of the first region and a second level lower than the potential level of the second region.

11. a semiconductor substrate having a photoelectric conversion region and a first floating diffusion region; a first vertical transfer transistor extending along a thickness direction of the semiconductor substrate to penetrate at least a portion of the semiconductor substrate; a first region having a first conductivity type, the first region being disposed on one side of the first vertical transfer transistor between the first floating diffusion region and the photoelectric conversion region; a second region having a second conductivity type on the other side of the first vertical transfer transistor; a charge storage element disposed on the other side of the first vertical transfer transistor; an overflow transistor disposed between the first vertical transfer transistor and the charge storage element.

12. 12. The image sensor of claim 11, wherein the first region is a p-type doped region and the second region is an n-type doped region.

13. the overflow transistor is configured to transfer photocharges generated in the photoelectric conversion region to the charge storage element or the first floating diffusion region; 12. The image sensor of claim 11, wherein the potential of the overflow transistor is variable between a first level higher than the potential level of the first region and a second level lower than the potential level of the second region.

14. a charge storage region disposed in a region of the semiconductor substrate corresponding to the charge storage element along a thickness direction of the semiconductor substrate; 12. The image sensor of claim 11, further comprising p-type barriers spaced apart from the charge storage region and the photoelectric conversion region, and disposed on both sides of the charge storage region.

15. The photoelectric conversion device further includes pixel isolation patterns having a backside deep trench isolation (BDTI) structure disposed on both sides of the photoelectric conversion region, 15. The image sensor of claim 14, wherein the charge storage element is disposed in an area corresponding to the pixel separating pattern.

16. generating a first photocharge during a first interval at a photoelectric element coupled to a first node; transferring the first photocharges to a charge storage element connected to the first node through a first region having a first conductivity type disposed on one side of a vertical transfer gate; generating second photocharges at the photoelectric element during a second interval; transferring the second photocharges to a second node through a second region having a second conductivity type disposed on the other side of the vertical transfer gate; generating a pixel signal based on the charge accumulated at the second node.

17. 17. The method of claim 16, further comprising resetting the first photocharges transferred to the second node exceeding a capacitance of the charge storage element during the first period by a power supply voltage.

18. the image sensor further comprises an overflow transistor disposed between the first node and the charge storage element; the step of transferring to the charge storage element includes performing a first operation of turning on the overflow transistor; 17. The method of claim 16, wherein the transmitting to the second node comprises performing a second operation of turning off the overflow transistor.

19. 20. The method of claim 18, further comprising: repeatedly performing the first operation and the second operation during the first period.

20. 20. The method of claim 18, wherein the charge storage element is at least one of a storage gate transistor, a storage diode, and a metal insulator metal (MIM) capacitor.

Images