Semiconductor device

Abstract

To provide a semiconductor device comprising a switching regulator in which the offset of output voltage does not occur when in operation at lowest frequency by using a ripple injection technique.SOLUTION: A semiconductor device 100 sets a first supply voltage V1. A state control circuit 3 generates a MINF state signal SMINF. When the MINF state signal SMINF is negated, a ripple injection circuit 4 generates a ripple superimposed reference voltage INN by superimposing a ripple voltage, which is an integral of a switch voltage SW, over a reference voltage REF. A first control circuit 5 generates a high potential-side driving signal HG and a low potential-side driving signal LG in this order, when a first power supply detection voltage based on a negative feedback voltage FBN surpasses the ripple superimposed reference voltage INN. When the MINF state signal SMINF is asserted, the ripple injection circuit 4 stops the superimposition of the ripple voltage, the first control circuit 5 generates the low potential-side driving signal LG, and then the MINF state signal SMINF operates an operation in negation.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] TECHNICAL FIELD The present disclosure relates to a semiconductor device. [Background technology]

[0002] Switching regulators, which convert DC voltages into other DC voltages by controlling switching elements, have been used in a variety of applications. One type of switching regulator, classified by function, is the inverting switching regulator. An inverting switching regulator generates a desired negative voltage at a negative voltage output terminal using an input positive voltage, an inductor connected to a switch terminal, and a capacitor connected to a negative voltage output terminal.

[0003] Furthermore, when classifying switching regulators by feedback control method, one type is the hysteresis control method. In the hysteresis control method, a comparator monitors the output voltage and controls the on / off of the switch element when it detects whether the output voltage exceeds or falls below a set threshold. Some hysteresis control methods use ripple injection technology, which injects ripple components into the reference voltage or feedback voltage input to the comparator, to ensure stable operation of the comparator even when the amplitude of the ripple component of the output voltage is not large.

[0004] When the load current of a switching regulator is light, the switching regulator performs intermittent operation, intermittently repeating the operation of turning the switch element on and off and then returning to the Hi-Z state. During intermittent operation under light load, the change in output voltage over time is small, so the time from when the switch element is turned on and off until the next time the output voltage rises above or falls below the set threshold and the switch element is turned on and off can be very long and the range can be wide. Depending on the application in which a switching regulator is used, it is not desirable for the operating frequency of the switching regulator to be very low and uncontrollable, so a minimum frequency operation is provided that operates the switching regulator at the set minimum frequency. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP2012-115047 Public Relations

[0006] [overview] Inverting switching regulators operate at the lowest frequency by turning on the switch element connecting the negative voltage output terminal and the switch terminal to raise the voltage at the negative voltage output terminal, and then by turning the switch element on and off as usual to charge the voltage at the negative voltage output terminal to a specified voltage. Inverting switching regulators that use a hysteresis control method with ripple injection technology have a problem in that, when operating at the lowest frequency, the output voltage is slightly lower than when operating intermittently; in other words, an offset occurs in the output voltage. To correct the output voltage offset during minimum frequency operation, switching regulators must switch the feedback resistor used to convert the output voltage before inputting it to the comparator to a resistor adjusted for minimum frequency operation.

[0007] Generally, to enable changes according to user requirements, it becomes necessary to switch the resistor that corrects the output voltage offset of the switching regulator to a resistor that is adjusted for each output voltage setting. In other words, in an inverting switching regulator that uses ripple injection technology, a resistance changing circuit that switches the resistance value for each output voltage setting is required to correct the output voltage offset at the lowest frequency operation, which poses the problem of increasing the circuit area.

[0008] In view of the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device including a switching regulator that uses ripple injection technology and does not generate an offset in the output voltage when operating at the lowest frequency.

[0009] A semiconductor device according to the present disclosure sets the voltage of a first power supply connected to a first main electrode of the first switch transistor by complementary on-state operations of a first switch transistor and a second switch transistor connected in series between a first power supply of a low potential and a second power supply of a high potential. The semiconductor device includes a state control circuit, a ripple injection circuit, and a first control circuit.

[0010] The state control circuit generates a first state signal at regular time intervals. When the first state signal is negated, the ripple injection circuit integrates the voltage at the output terminal, which is the connection point between the first and second switch transistors, to generate a ripple voltage similar to the ripple current flowing through the inductor connected to the output terminal. The ripple injection circuit generates a ripple-superimposed reference voltage by superimposing the ripple voltage on a reference voltage. The first control circuit generates a first power supply detection voltage based on a feedback voltage that is higher than the voltage of the first power supply and is generated so as to become equal to the reference voltage when the voltage of the first power supply reaches a reference value. The first control circuit sequentially generates a high-side drive signal and a low-side drive signal when the first power supply detection voltage becomes higher than the ripple-superimposed reference voltage.

[0011] When the first state signal is asserted, the ripple injection circuit stops superimposing the ripple voltage, and the first control circuit generates the low side drive signal. After the first control circuit generates the low side drive signal LG, the first control circuit sequentially generates the high side drive signal HG and the low side drive signal LG while the ripple injection circuit continues superimposing the ripple voltage. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a configuration diagram of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a configuration diagram of the MINF state control circuit of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a configuration diagram of a ripple injection circuit of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a configuration diagram of the first control circuit of the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a configuration diagram of the sense voltage generating circuit of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a state transition diagram of the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is an operational waveform diagram of the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is an enlarged operational waveform diagram of the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a configuration diagram of a ripple injection circuit of a semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a configuration diagram of a semiconductor device according to a comparative example. [Figure 11] FIG. 11 is a configuration diagram of a ripple injection circuit of a semiconductor device according to a comparative example. [Figure 12] FIG. 12 is a configuration diagram of a first control circuit of a semiconductor device according to a comparative example. [Figure 13] FIG. 13 is a configuration diagram of a detection voltage generating circuit of a semiconductor device according to a comparative example. [Figure 14] FIG. 14 is an operational waveform diagram of the semiconductor device according to the comparative example.

[0013] [Detailed explanation] The embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts will be denoted by the same or similar reference numerals, and the description thereof will be omitted. The drawings are schematic.

[0014] Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical ideas, and do not specify the materials, shapes, structures, arrangements, etc. of each component part. Various modifications can be made to these embodiments within the scope of the claims.

[0015] [First embodiment] (Configuration of semiconductor device) 1 is a configuration diagram of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 in FIG. 1 is a switching regulator.

[0016] The switching regulator 100 includes a low-side switch transistor 1, which is a first switch transistor, and a high-side switch transistor 2, which is a second switch transistor. The switching regulator 100 also includes a MINF state control circuit 3, a ripple injection circuit 4, a first control circuit 5, and a reference voltage generation circuit 6. Here, MINF stands for minimum frequency, and the MINF state refers to the initial state when the switching regulator 100 starts operating at the minimum frequency. The switching regulator 100 includes a second power supply terminal TV2, which is an external power supply terminal, a switch terminal T1, a first power supply terminal TV1, which is a negative voltage output terminal, and a feedback terminal T2. The switch terminal T1 is a connection point between the low-side switch transistor 1 and the high-side switch transistor 2. The first power supply voltage V1 output to the first power supply terminal TV1 is, for example, −3 V, and the second power supply voltage V2 supplied to the second power supply terminal TV2 is, for example, 5 V.

[0017] The low-side switch transistor 1 is an n-channel MOS transistor with its source, which is a first main electrode, connected to the first power supply terminal TV1, its drain connected to the switch terminal T1, its gate connected to the first control circuit 5, and a low-side drive signal LG input to its gate. The high-side switch transistor 2 is an n-channel MOS transistor with its source connected to the switch terminal T1, its drain connected to the second power supply terminal TV2, and its gate connected to the first control circuit 5, and a high-side drive signal HG input to its gate. The low-side switch transistor 1 and the high-side switch transistor 2 are connected in series between the first power supply terminal TV1 and the second power supply terminal TV2, and are turned on complementarily.

[0018] The MINF state control circuit 3 is connected to the first control circuit 5, receives the high-side drive signal HG, and outputs a MINF state signal SMINF, which is a first state signal. The MINF state control circuit 3 also receives an enable signal EN. The enable signal EN is asserted, for example, when a circuit (not shown) detects that the second power supply voltage V2 has risen above a predetermined voltage. Alternatively, the enable signal EN is asserted in accordance with an operating mode set externally to the switching regulator. The MINF state control circuit 3 outputs the MINF state signal SMINF to the ripple injection circuit 4.

[0019] The ripple injection circuit 4 receives the MINF state signal SMINF from the MINF state control circuit 3. The ripple injection circuit 4 is connected to the first control circuit 5, receives the HiZ state signal SHIZ and the HON state signal SHON, and outputs a ripple-superimposed reference voltage INN. The ripple injection circuit 4 receives the reference voltage REF from the reference voltage generation circuit 6. The ripple injection circuit 4 receives the switch voltage SW from the switch terminal T1.

[0020] The first control circuit 5 outputs a low-side drive signal LG to the gate of the low-side switch transistor 1 and a high-side drive signal HG to the gate of the high-side switch transistor 2. The first control circuit 5 is connected to the MINF state control circuit 3, receives the MINF state signal SMINF, and outputs the high-side drive signal HG. The first control circuit 5 is connected to the ripple injection circuit 4, receives the ripple superimposed reference voltage INN, and outputs the HiZ state signal SHIZ and the HON state signal SHON. The first control circuit 5 is connected to the switch terminal T1, the first power supply terminal TV1, and the feedback terminal T2, and receives the switch voltage SW, the first power supply voltage V1, and the feedback negative voltage FBN.

[0021] When the enable signal EN is input and asserted, the reference voltage generation circuit 6 generates a reference voltage REF and outputs it to the ripple injection circuit 4. The reference voltage REF is set to a voltage with 0 V as its center value, for example.

[0022] An inductor L0 is connected to the switch terminal T1 via a resistor R0 outside the switching regulator 100. A first terminal of the resistor R0 is connected to the switch terminal T1, a first terminal of the inductor L0 is connected to a second terminal of the resistor R0, and the second terminal of the inductor L0 is connected to the ground power supply GND. The current flowing through the inductor L0 is referred to as an inductor current IL0, and the current flowing from the first terminal to the second terminal of the inductor L0 is defined as a positive current.

[0023] A capacitor C0 is connected to the first power supply terminal TV1 outside the switching regulator 100. A first electrode of the capacitor C0 is connected to the first power supply terminal TV1 and the feedback terminal T2, and a second electrode is connected to the ground power supply GND.

[0024] The feedback terminal T2 is connected to the first power supply terminal TV1 outside the switching regulator 100. The voltage of the feedback terminal T2 is a feedback negative voltage FBN, and when the first power supply voltage V1 is, for example, −3V, the feedback negative voltage FBN is also −3V.

[0025] 2 is a configuration diagram of the MINF state control circuit 3 of the switching regulator 100. The MINF state control circuit 3 has an oscillator circuit 31, a counter circuit 32, and a determination circuit 33.

[0026] When the enable signal EN is at a high level, the oscillator circuit 31 generates an oscillation signal OSC that transitions from a low level to a high level and back to a low level at a fixed period TOSC, and outputs the oscillation signal OSC to the counter circuit 32. The counter circuit 32 counts the number of transitions of the oscillation signal OSC that occur when the high-side drive signal HG is at a low level, and outputs the counted number as a count signal CNT[n:1] to the decision circuit 33. The count signal CNT[n:1] is a digital signal having a number of lines equal to the natural number n and indicating a number of times from 0 to 2(n)-1, but it may also be an analog signal whose value changes continuously with a single signal. When the number of times indicated by the count signal CNT[n:1] exceeds the threshold number for transitioning to the MINF state, the decision circuit 33 asserts the MINF state signal SMINF at a high level.

[0027] The threshold number of transitions to the MINF state is the number of times equivalent to the period calculated as the reciprocal of the minimum frequency. For example, if the minimum frequency is 200 kHz and the period TOSC of the oscillation signal OSC is 100 ns, the period TPMINF at which the MINF state signal SMINF becomes high level is 5 us, and the threshold number of transitions of the oscillation signal OSC at which the state transitions to the MINF state is 50.

[0028] As will be described in detail later, when the MINF state signal SMINF goes high, the switching regulator 100 starts minimum frequency operation, and during minimum frequency operation the high potential side drive signal HG goes high. When the high potential side drive signal HG goes high, the counter circuit 32 resets the count signal CNT[n:1] and restarts counting the number of transitions of the oscillation signal OSC. When the count signal CNT[n:1] is reset and becomes smaller than the threshold number, the determination circuit 33 negates the MINF state signal SMINF by going low.

[0029] When the load current of the switching regulator 100 is small and light, the high-side drive signal HG remains at a low level after the switching regulator 100 operates once. When the high-side drive signal HG remains at a low level, the MINF state control circuit 3 asserts the MINF state signal SMINF at a fixed cycle TPMINF measured by the oscillator circuit 31 and the counter circuit 32. Asserting the MINF state signal SMINF triggers the start of minimum frequency operation.

[0030] 3 is a configuration diagram of the ripple injection circuit 4 of the switching regulator 100. The ripple injection circuit 4 includes a p-channel MOS transistor 41, voltage-to-current (VI conversion) circuits 42 and 43, a current mixing circuit 44, and a current-to-voltage (IV conversion) circuit 45. The ripple injection circuit 4 further includes an inverter 46, an OR circuit 47, a p-channel MOS transistor 48, resistors R41, R42, R43, and R44, and a capacitor C41.

[0031] The resistor R41 has a first terminal to which the switch voltage SW is input, and a second terminal to which the first terminal of the resistor R42 is connected. The second terminal of the resistor R42 is connected to the ground power supply GND. The resistors R41 and R42 divide the switch voltage SW and the voltage of the ground power supply GND to generate a divided switch voltage SSW.

[0032] The resistor R43 has a first terminal connected to the voltage-divider switch voltage SSW, and a second terminal connected to the first terminal of the resistor R44 and the source of the p-channel MOS transistor 41. The second terminal of the resistor R44 is connected to the first electrode of the capacitor C41 and the drain of the p-channel MOS transistor 41. The second electrode of the capacitor C41 is connected to the ground power supply GND. The HON state signal SHON is input to the gate of the p-channel MOS transistor 41. A ripple voltage CSP is output from the second terminal of the resistor R44 and the drain of the p-channel MOS transistor 41. The resistors R43, R44, and capacitor C41 form an RC integrator circuit that delays the transition of the voltage-divider switch voltage SSW and generates the ripple voltage CSP. When the HON state signal SHON is low, the p-channel MOS transistor 41 turns on and shorts out the first and second terminals of the resistor R44, thereby reducing the resistance of the RC integrator circuit and reducing the delay of the ripple voltage CSP. The ripple voltage CSP is substantially similar to the ripple current flowing through the inductor L0 connected to the switch terminal T1.

[0033] The OR circuit 47 receives the HiZ state signal SHIZ and the MINF state signal SMINF at its input terminals and outputs the HiZ_MINF state signal SHIZ_MINF to the inverter 46. The inverter 46 inverts the HiZ_MINF state signal SHIZ_MINF to generate the ripple injection enable signal ENRIP and outputs it to the VI conversion circuit 42. When both the HiZ state signal SHIZ and the MINF state signal SMINF are at a low level, the OR circuit 47 and the inverter 46 set the ripple injection enable signal ENRIP to a high level. When either the HiZ state signal SHIZ or the MINF state signal SMINF is at a high level, the OR circuit 47 and the inverter 46 set the ripple injection enable signal ENRIP to a low level.

[0034] The p-channel MOS transistor 48 has a gate to which a ripple injection enable signal ENRIP is input, a source to which the ripple voltage CSP is set, and a drain to which the reset voltage VRST is set. The p-channel MOS transistor 48 is turned off when the ripple injection enable signal ENRIP is at a high level, and turned on when the ripple injection enable signal ENRIP is at a low level, thereby resetting the ripple voltage CSP to the reset voltage VRST. As will be described later, the reset voltage VRST is a voltage that, when input to the VI conversion circuit 42, causes the ripple conversion current ICSP output from the VI conversion circuit 42 to become substantially 0 amperes. The reset voltage VRST may be generated, for example, by delaying the voltage-divider switch voltage SSW with respect to the ripple voltage CSP using an RC integrator circuit.

[0035] The VI conversion circuit 42 performs voltage-to-current conversion on the ripple voltage CSP to generate a ripple conversion current ICSP and outputs it to the current mixing circuit 44. When the ripple injection enable signal ENRIP is at a low level and the ripple voltage CSP is reset to the reset voltage VRST, the VI conversion circuit 42 sets the ripple conversion current ICSP to substantially 0 amperes. The VI conversion circuit 43 performs voltage-to-current conversion on the reference voltage REF to generate a reference current IREF and outputs it to the current mixing circuit 44. The VI conversion circuit 43 performs substantially the same voltage-to-current conversion as the VI conversion circuit 42. The VI conversion circuits 42 and 43 may perform voltage-to-current conversion, for example, by having a transistor to which a voltage is input flow a drain current corresponding to the gate voltage.

[0036] The current mixing circuit 44 mixes the ripple converted current ICSP and the reference current IREF to generate a total current ISUM, which is a ripple superimposed reference current, and outputs it to the IV conversion circuit 45. The current mixing circuit 44 may generate the total current ISUM, for example, by outputting a current flowing through a single wiring that connects the wiring for the ripple converted current ICSP and the wiring for the reference current IREF.

[0037] The IV conversion circuit 45 performs current-to-voltage conversion on the total current ISUM to generate the ripple superimposed reference voltage INN. The IV conversion circuit 45 may convert the current into a voltage, for example, by using a resistor to which a current is input and generating a voltage corresponding to the amount of current between both ends of the resistor.

[0038] The ripple injection circuit 4 in Figure 3 operates as follows overall. The ripple injection circuit 4 generates a ripple voltage CSP by delaying the divided switch voltage SSW, which is obtained by dividing the switch voltage SW and the ground power supply GND, using an RC integrator circuit. When both the HiZ state signal SHIZ and the MINF state signal SMINF are low, the ripple injection circuit 4 performs voltage-to-current conversion on the ripple voltage CSP and the reference voltage REF, and mixes the resulting currents. By performing current-to-voltage conversion on the mixed current, the ripple injection circuit 4 generates a ripple-superimposed reference voltage INN on which the ripple voltage CSP is superimposed. When either the HiZ state signal SHIZ or the MINF state signal SMINF is high, the ripple injection circuit 4 sets the ripple conversion current ICSP to essentially 0 amperes, and generates the ripple-superimposed reference voltage INN without superimposing the ripple voltage CSP.

[0039] 4 is a configuration diagram of the first control circuit 5 of the switching regulator 100. The first control circuit 5 includes a detection voltage generating circuit 51, comparators 52 and 53, a timer circuit 54, and an output control circuit 55.

[0040] The detection voltage generating circuit 51 receives the feedback negative voltage FBN from a feedback terminal T2 (not shown in FIG. 4), receives the third power supply voltage V3, and outputs a first power supply detection voltage INP to the comparator 52.

[0041] 5 is a configuration diagram of the sense voltage generation circuit 51 of the switching regulator 100. The sense voltage generation circuit 51 includes a soft start circuit 511, a resistor R511 which is a first resistor, a resistor R512 which is a second resistor, a VI conversion circuit 512, and an IV conversion circuit 513. The sense voltage generation circuit 51 receives the third power supply voltage V3 and the negative feedback voltage FBN as input to generate a feedback voltage FB, and generates a first power supply sense voltage INP based on the feedback voltage FB.

[0042] The soft start circuit 511 receives the third power supply voltage V3 and the voltage of the ground power supply GND and outputs an internal third power supply voltage V3_INT. Generally, a soft start function is a function that controls the output voltage to rise slowly from 0V to a set voltage by setting a soft start time in order to suppress inrush current at the start of a power supply IC and prevent overshoot. The soft start circuit 511 controls the internal third power supply voltage V3_INT to rise slowly even when the third power supply voltage V3 rises sharply. The third power supply voltage V3 is, for example, 1.5V, and the internal third power supply voltage V3_INT also becomes, for example, 1.5V when start-up is complete.

[0043] Resistors R511 and R512 divide the high-side internal third power supply voltage V3_INT and the low-side negative feedback voltage FBN to generate a feedback voltage FB. The feedback voltage FB is set to be substantially equal to the reference voltage REF when the first power supply voltage V1 and the negative feedback voltage FBN reach their reference values. For example, consider a case where the internal third power supply voltage V3_INT is 1.5 V, the reference value of the negative feedback voltage FBN is −3 V, and the reference voltage REF is 0 V. If the resistance ratio of resistors R511 and R512 is set to 1:2, when the negative feedback voltage FBN reaches the reference value of −3 V, the feedback voltage FB will be substantially equal to the reference voltage REF, which is 0 V.

[0044] The VI conversion circuit 512 performs voltage-to-current conversion on the feedback voltage FB to generate a feedback current IFB. The VI conversion circuit 512 performs substantially the same voltage-to-current conversion as the VI conversion circuits 42 and 43 of the ripple injection circuit 4 shown in FIG. 3. The IV conversion circuit 513 performs current-to-voltage conversion on the feedback current IFB to generate a first power supply detection voltage INP. The IV conversion circuit 513 performs substantially the same current-to-voltage conversion as the IV conversion circuit 45 of the ripple injection circuit 4. The first power supply detection voltage INP is output to the comparator 52.

[0045] Returning to the explanation of FIG. 4, the comparator 52 receives the first power supply detection voltage INP from the detection voltage generation circuit 51, the ripple-superimposed reference voltage INN from the ripple injection circuit 4 of FIG. 3, and the enable signal EN. The comparator 52 outputs a feedback determination signal FBOUT to the output control circuit 55. When the enable signal EN is at a high level, the comparator 52 compares the first power supply detection voltage INP with the ripple-superimposed reference voltage INN, and when the first power supply detection voltage INP is high, the comparator 52 sets the feedback determination signal FBOUT to a high level. When the enable signal EN is at a low level, the comparator 52 sets the feedback determination signal FBOUT to a low level.

[0046] The comparator 53 receives the switch voltage SW from the switch terminal T1, the first power supply voltage V1 from the first power supply terminal TV1, and the enable signal EN, and outputs a determination signal COMP to the output control circuit 55. When the enable signal EN is at a high level, the comparator 53 compares the switch voltage SW with the first power supply voltage V1, and when the switch voltage SW and the first power supply voltage V1 are substantially equal, the comparator 53 determines that the inductor current IL0 flowing through the inductor L0 is 0 amperes, and sets the determination signal COMP to a high level. When the enable signal EN is at a low level, the comparator 53 sets the determination signal COMP to a low level.

[0047] The timer circuit 54 receives the high potential side drive signal HG from the output control circuit 55, measures a fixed time THON after the high potential side drive signal HG goes high, and outputs a high-level timer signal TIMER to the output control circuit 55. The timer circuit 54 may measure the fixed time THON, for example, by counting the number of transitions of the oscillation signal output from the oscillator circuit with a counter, or may measure it by charging a capacitor with a constant current and determining the voltage of the capacitor electrodes.

[0048] The output control circuit 55 receives the timer signal TIMER from the timer circuit 54 and the MINF state signal SMINF from the MINF state control circuit 3. The output control circuit 55 also receives the feedback determination signal FBOUT from the comparator 52, the determination signal COMP from the comparator 53, and the enable signal EN. The output control circuit 55 outputs a high-side drive signal HG to the gate of the high-side switch transistor 2 and to the timer circuit 54, and outputs a low-side drive signal LG to the gate of the low-side switch transistor 1. The output control circuit 55 outputs a HiZ state signal SHIZ and a HON state signal SHON to the ripple injection circuit 4.

[0049] FIG. 6 is a state transition diagram of the semiconductor device 100 according to the first embodiment. Using the state transition diagram of FIG. 6, the operation of the switching regulator 100 under the control of the MINF state control circuit 3 and the output control circuit 55 will be described. The state transition diagram shows the parts related to the minimum frequency operation and intermittent operation performed under a light load. In FIG. 6, the low potential side switch transistor 1 is referred to as "L SW Tr." and the high potential side switch transistor 2 is referred to as "H SW Tr."

[0050] When a drop in the second power supply voltage V2 is detected or a stop command is input from an external device, the enable signal EN changes to low level from the All State, which indicates all states. When the enable signal EN changes to low level, the switching regulator 100 transitions to the Disable State, which is a stopped state. In the Disable State, the reference voltage generation circuit 6 in FIG. 1, the MINF state control circuit 3 in FIG. 2, the comparators 52 and 53, and the output control circuit 55 in FIG. 4 stop operating, and the low-side drive signal LG and the high-side drive signal HG are fixed to low level. Then, both the low-side switch transistor 1 and the high-side switch transistor 2 are turned off, and the switch terminal T1 becomes Hi-Z.

[0051] When the enable signal EN is set to high level in the Disable state, the switching regulator 100 detects that the second power supply voltage V2 has risen or receives an external operation command. When the enable signal EN is set to high level, the switching regulator 100 transitions to the HiZ state, in which the reference voltage generating circuit 6 in FIG. 1, the comparators 52 and 53 in FIG. 4, and the output control circuit 55 are operating and the switch terminal T1 is set to Hi-Z. The output control circuit 55 sets the HiZ state signal SHIZ to high level.

[0052] Both intermittent operation and lowest frequency operation start from this HiZ state and end by returning to the HiZ state. First, the state transitions in intermittent operation will be explained.

[0053] In the HiZ state, the load current increases the first power supply voltage V1, causing the negative feedback voltage FBN at the feedback terminal T2 to increase. If the first power supply detection voltage INP in FIG. 4 becomes higher than the ripple reference voltage INN before the count indicated by the count signal CNT[n:1] in FIG. 2 exceeds the threshold count for transitioning to the MINF state, the comparator 52 sets the feedback determination signal FBOUT to a high level. When the feedback determination signal FBOUT becomes a high level, the switching regulator 100 transitions to the HON state.

[0054] In the HON state, in the output control circuit 55 in Fig. 4, the HiZ state signal SHIZ goes low and the HON state signal SHON goes high. The high-side drive signal HG goes high, and the count signal CNT[n:1] is reset in the MINF state control circuit 3 in Fig. 2. When the high-side drive signal HG goes high, the high-side switch transistor 2 turns on, and the switch voltage SW, which is the voltage at the switch terminal T1, rises to the second power supply voltage V2. When the high-side switch transistor 2 turns on, current flows from the second power supply terminal TV2 through the high-side switch transistor 2, resistor R0, and inductor L0 to the ground power supply GND.

[0055] 4 measures a certain period of time THON after the high-side drive signal HG goes high, and then sets the timer signal TIMER to high. When the timer signal TIMER goes high, the switching regulator 100 transitions to the LON state.

[0056] In the LON state, the HON state signal SHON goes low in the output control circuit 55 in Fig. 4, and the LON state signal SLON goes high inside the output control circuit 55. In the LON state, the high-side drive signal HG in Fig. 1 goes low, turning off the high-side switch transistor 2, and the low-side drive signal LG goes high, turning on the low-side switch transistor 1. When the low-side switch transistor 1 turns on, current flows from the ground power supply GND through inductor L0, resistor R0, and low-side switch transistor 1 to the first power supply terminal TV1. The current charges capacitor C0, and a negative first power supply voltage V1 is output to the first power supply terminal TV1.

[0057] 4 determines that the current flowing from the inductor L0 via the low-side switch transistor 1 has reached 0 amperes when the switch voltage SW becomes substantially equal to the first power supply voltage V1, and sets the determination signal COMP to high level. When the determination signal COMP becomes high level, the switching regulator 100 returns to the HiZ state. In the LON state, the LON state signal SLON becomes low level, and the HiZ state signal SHIZ becomes high level.

[0058] When the load on the switching regulator 100 is light, the switching regulator 100 repeats the above-described operation of transitioning from the HiZ state to the HON state and the LON state in that order and then returning to the HiZ state. This type of transition operation is called intermittent operation.

[0059] Next, a state transition in the lowest frequency operation will be described. The lowest frequency operation is performed when the load current of the switching regulator 100 is even smaller.

[0060] Because the load current of the switching regulator 100 becomes even smaller and the change in the first power supply voltage V1 is small, the first power supply detection voltage INP in Figure 4 becomes lower than the ripple superimposed reference voltage INN, and the state in which the switching regulator 100 does not transition to the HON state continues. The switching regulator 100 remains in the HiZ state without transitioning to the HON state. When the number of times indicated by the count signal CNT[n:1] in the MINF state control circuit 3 exceeds the threshold number of times for transitioning to the MINF state, the MINF state signal SMINF goes high. When the MINF state signal SMINF goes high, the switching regulator 100 transitions to the MINF state.

[0061] In the MINF state, the low-side drive signal LG first goes high, turning on the low-side switch transistor 1. When the low-side switch transistor 1 turns on after the HiZ state, the first power supply terminal TV1 is connected to the switch terminal T1, current flows from the first power supply terminal TV1 to the ground power supply GND via the inductor L0, and the first power supply voltage V1 is raised. When the first power supply detection voltage INP in Figure 4 becomes higher than the ripple superimposed reference voltage INN, the comparator 52 sets the feedback determination signal FBOUT to a high level, and the switching regulator 100 transitions to the HON state.

[0062] After the HON state, which operates at the lowest frequency, the operation is similar to intermittent operation, except that in the HON state, the MINF state signal SMINF goes low instead of the HiZ state signal SHIZ. That is, when the high-side drive signal HG goes high, the high-side switch transistor 2 turns on, causing current to flow from the second power supply terminal TV2 through inductor L0 to the ground power supply GND. When the timer signal TIMER goes high, the operation transitions to the LON state. In the LON state, the low-side drive signal LG goes high, causing the low-side switch transistor 1 to turn on, causing current to flow from the ground power supply GND through inductor L0 to the first power supply terminal TV1, and a negative first power supply voltage V1 is output to the first power supply terminal TV1. When the switch voltage SW in the comparator 53 in FIG. 4 becomes substantially equal to the first power supply voltage V1, the decision signal COMP goes high, and the operation returns to the HiZ state.

[0063] When the load current of the switching regulator 100 becomes even smaller, the above-described operation of transitioning from the HiZ state to the MINF state, the HON state, and the LON state in that order, and then returning to the HiZ state, is repeated. This transition operation is called the minimum frequency operation.

[0064] FIG. 7 is an operational waveform diagram of the semiconductor device 100 according to the first embodiment. The horizontal axis in FIG. 7 represents time. The vertical axis in FIG. 7 varies depending on the signal, as explained below. The vertical axes of the switch voltage SW, first power supply voltage V1, ripple voltage CSP, ripple superimposed reference voltage INN, first power supply sense voltage INP, HiZ_MINF state signal SHIZ_MINF, and feedback determination signal FBOUT represent voltage. The vertical axis of the inductor current IL0 represents current. The state notation "state" indicates the state in the state transition diagram of FIG. 6. The waveform of the first power supply sense voltage INP is indicated by a dashed line, and waveforms other than the first power supply sense voltage INP are indicated by solid lines. The operational waveform diagram in FIG. 7 shows the operational waveform diagram of the lowest frequency operation performed twice from the HiZ state.

[0065] At time t0, the switching regulator 100 is in the HiZ state. In the HiZ state, the HiZ state signal SHIZ is at a high level, and the switch terminal T1 is in the Hi-Z state.

[0066] At time t1, when the count indicated by the count signal CNT[n:1] (not shown in FIG. 7) exceeds the threshold count for transitioning to the MINF state, the switching regulator 100 transitions to the MINF state. In the MINF state, the low-side switch transistor 1 turns on, and the switch voltage SW goes low. Because the HiZ_MINF state signal SHIZ_MINF (not shown in FIG. 7) is high, the ripple injection circuit 4 in FIG. 3 stops injecting the ripple voltage CSP. The ripple voltage CSP is reset and remains almost unchanged from the voltage in the HiZ state. Meanwhile, an inductor current IL0 flows from the first power supply terminal TV1 to the ground power supply GND via the low-side switch transistor 1 through the inductor L0, and the current value becomes increasingly negative over time. The low-side switch transistor 1 turns on, connecting the first power supply terminal TV1 and the switch terminal T1, causing the first power supply voltage V1 to rise.

[0067] Figure 8 is an operational waveform diagram showing enlarged operational waveforms of the first power supply voltage V1, ripple reference voltage INN, first power supply sensing voltage INP, and feedback determination signal FBOUT around time t2 in Figure 7. The horizontal axis of Figure 8 represents time, and the vertical axis represents voltage. The waveform of the first power supply sensing voltage INP is shown by a dashed line, and the waveforms other than the first power supply sensing voltage INP are shown by solid lines.

[0068] At time t1, the low-side switch transistor 1 is turned on, and the first power supply voltage V1 rises, causing the first power supply detection voltage INP to rise. When the first power supply detection voltage INP becomes higher than the ripple-superimposed reference voltage INN, the feedback determination signal FBOUT goes high, and at time t2, the switching regulator 100 transitions to the HON state. As will be described in detail later, when a ripple voltage is superimposed on the ripple-superimposed reference voltage INN in the HON state, the ripple-superimposed reference voltage INN rises, the first power supply detection voltage INP again becomes lower than the ripple-superimposed reference voltage INN, and the feedback determination signal FBOUT goes low.

[0069] 7, at time t2, the switching regulator 100 transitions to the HON state. In the HON state, the high-side drive signal HG goes high, turning on the high-side switch transistor 2 and causing the switch voltage SW to go high. When the high-side switch transistor 2 turns on, an inductor current IL0 flows through the inductor L0 from the second power supply terminal TV2 to the ground power supply GND via the high-side switch transistor 2, and the current value becomes increasingly positive over time.

[0070] In the HON state, the HiZ_MINF state signal SHIZ_MINF (not shown in FIG. 7) goes low. In the ripple injection circuit 4 in FIG. 3, the ripple voltage CSP is generated by dividing and integrating the switch voltage SW. This voltage is then injected into the reference voltage REF to generate the ripple-superimposed reference voltage INN. The ripple-superimposed reference voltage INN increases as the ripple voltage CSP increases. Because the HON state signal SHON is high, the p-channel MOS transistor 41 in FIG. 3 releases the short circuit between the first and second terminals of the resistor R44, increasing the delay of the ripple voltage CSP from the switch voltage SW. The first power supply sense voltage INP decreases due to voltage-to-current conversion and current-to-voltage conversion. In parallel, the timer circuit 54 in FIG. 4 measures the time since the high-side drive signal HG went high.

[0071] At time t3, the timer circuit 54 measures a certain time THON after the high-side drive signal HG goes high, and the switching regulator 100 transitions to the LON state. In the LON state, the high-side drive signal HG goes low, turning off the high-side switch transistor 2, the low-side drive signal LG goes high, turning on the low-side switch transistor 1, and the switch voltage SW goes low. When the low-side switch transistor 1 turns on, an inductor current IL0 flows from the ground power supply GND through the low-side switch transistor 1 to the first power supply terminal TV1, and the first power supply voltage V1 is set to a predetermined negative voltage. The current value of the inductor current IL0 approaches 0 amperes over time.

[0072] Because the HiZ_MINF state signal SHIZ_MINF is low, the ripple-superimposed reference voltage INN, generated by injecting the ripple voltage CSP into the reference voltage REF in the ripple injection circuit 4 in Figure 3, operates with a waveform superimposed with the ripple voltage CSP. Because the HON state signal SHON is low, the first and second ends of resistor R44 are shorted by the p-channel MOS transistor 41, so the delay of the ripple voltage CSP from the switch voltage SW is shorter than the delay in the HON state. In parallel, the comparator 53 in Figure 4 compares the switch voltage SW with the first power supply voltage V1.

[0073] 4 detects that the switch voltage SW and the first power supply voltage V1 are substantially equal and determines that the inductor current IL0 has reached 0 amperes, and sets the determination signal COMP to high level. When the determination signal COMP goes high, the switching regulator 100 transitions to the HiZ state. In the HiZ state, the high-side drive signal HG and the low-side drive signal LG go low, turning off the high-side switch transistor 2 and the low-side switch transistor 1, causing the switch terminal T1 to go into Hi-Z, and the switch voltage SW to go to the Hi-Z state voltage.

[0074] In the HiZ state, the HiZ_MINF state signal SHIZ_MINF goes high, the ripple voltage CSP is reset by the p-channel MOS transistor 48 in Fig. 3, and injection into the ripple superimposed reference voltage INN is stopped. In the HiZ state, the comparator 52 in Fig. 4 compares the first power supply detection voltage INP with the ripple superimposed reference voltage INN, and the MINF state control circuit 3 in Fig. 2 measures the time since the high potential side drive signal HG went low.

[0075] 7 exceeds the threshold number of times for transitioning to the MINF state, the MINF state signal SMINF becomes high level, and the switching regulator 100 transitions to the MINF state. The operation from time t5 to time t8 is the same as the operation from time t1 to time t4, and therefore a description thereof will be omitted.

[0076] By performing the above-described operation from time t0 to time t8, the switching regulator 100 can maintain the first power supply voltage V1 at a predetermined negative voltage during the lowest frequency operation.

[0077] Here, to facilitate understanding of the features of the present invention, a semiconductor device of a comparative example will be described.

[0078] 10 is a configuration diagram of a semiconductor device 200 according to a comparative example. The semiconductor device 200 of FIG. 10 is a switching regulator. The switching regulator 200 differs from the switching regulator 100 according to the first embodiment shown in FIG. 1 in the following respects. The switching regulator 200 of FIG. 10 uses a ripple injection circuit 7 having a different configuration from the ripple injection circuit 4, uses a first control circuit 8 having a different configuration from the first control circuit 5, and does not input a MINF state signal SMINF to the ripple injection circuit 7.

[0079] 11 is a configuration diagram of the ripple injection circuit 7 of the switching regulator 200. The ripple injection circuit 7 differs from the ripple injection circuit 4 of the switching regulator 100 according to the first embodiment shown in FIG. 3 in that the ripple injection enable signal ENRIP is generated by inverting the HiZ state signal SHIZ by an inverter 76.

[0080] 12 is a configuration diagram of the first control circuit 8 of the switching regulator 200. The first control circuit 8 differs from the first control circuit 5 of the switching regulator 100 according to the first embodiment shown in FIG. 4 in that a detection voltage generation circuit 81 having a configuration different from that of the detection voltage generation circuit 51 is used.

[0081] 13 is a configuration diagram of the detection voltage generation circuit 81 of the switching regulator 200. The detection voltage generation circuit 81 differs from the detection voltage generation circuit 51 of the switching regulator 100 according to the first embodiment shown in FIG. 5 in the following respects: When generating the feedback voltage FB by dividing the internal third power supply voltage V3_INT and the negative feedback voltage FBN, the detection voltage generation circuit 81 uses a resistor R812 and a resistor R811 whose resistance value is switched by the MINF state signal SMINF.

[0082] In order to explain the purpose of switching the resistance value of the resistor R811 by the MINF state signal SMINF in the switching regulator 200 according to the comparative example, an operation waveform diagram when the resistance value is not switched by the MINF state signal SMINF will be described below.

[0083] FIG. 14 is an operational waveform diagram of the semiconductor device 200 according to the comparative example. FIG. 14 illustrates a case where the resistance value of the resistor R811 in FIG. 13 is not switched by the MINF state signal SMINF. The horizontal axis in FIG. 14 represents time. The vertical axis in FIG. 14 varies depending on the signal, as explained below. The vertical axes of the switch voltage SW, first power supply voltage V1, ripple voltage CSP, ripple superimposed reference voltage INN, first power supply sense voltage INP, HiZ state signal SHIZ, and feedback determination signal FBOUT represent voltage. The vertical axis of the inductor current IL0 represents current. The state notation "state" indicates the state in the state transition diagram of FIG. 6. The waveform of the first power supply sense voltage INP is indicated by a dashed line, and waveforms other than the first power supply sense voltage INP are indicated by solid lines. The operational waveform diagram in FIG. 14 illustrates the operational waveform diagram of the lowest frequency operation performed twice from the HiZ state.

[0084] At time t0, the switching regulator 200 is in the HiZ state. At time t1, when the count indicated by the count signal CNT[n:1] (not shown in FIG. 13) exceeds the threshold count for transitioning to the MINF state, the switching regulator 200 transitions to the MINF state. In the MINF state, the low-side switch transistor 1 turns on, and the switch voltage SW goes low. The HiZ state signal SHIZ goes low, and the ripple injection circuit 7 in FIG. 11 generates a ripple voltage CSP by dividing and integrating the low-level switch voltage SW, which decreases over time. The ripple superimposed reference voltage INN, on which this ripple voltage CSP is superimposed, also decreases over time. Meanwhile, when the low-side switch transistor 1 turns on and connects the first power supply terminal TV1 and the switch terminal T1, the first power supply voltage V1 increases, and the first power supply detection voltage INP increases.

[0085] At time t2, when the first power supply detection voltage INP becomes higher than the ripple-superimposed reference voltage INN due to a decrease in the ripple-superimposed reference voltage INN and an increase in the first power supply voltage V1, the feedback determination signal FBOUT goes high, and the switching regulator 200 transitions to the HON state. FIG. 14 differs from the operational waveform diagram of the switching regulator 100 according to the first embodiment shown in FIG. 7 in the following respects. The first power supply detection voltage INP becomes higher than the ripple-superimposed reference voltage INN earlier than the decrease in the ripple-superimposed reference voltage INN. At time t2, the switching regulator 200 transitions to the HON state before the first power supply voltage V1 has risen to a predetermined voltage. Concurrently, the timer circuit 54 shown in FIG. 12 measures the time since the high-side drive signal HG went high.

[0086] At time t3, the timer circuit 54 measures a certain time THON after the high-side drive signal HG goes high, and the switching regulator 200 transitions to the LON state. When the low-side switch transistor 1 turns on, an inductor current IL0 flows through the inductor L0 from the ground power supply GND to the first power supply terminal TV1, and the first power supply voltage V1 is pulled down. At time t2, the first power supply voltage V1 has not yet risen to a predetermined voltage, but at time t3 it is pulled down, becoming a voltage lower than the predetermined negative voltage.

[0087] At time t4, when the comparator 53 in FIG. 12 determines that the switch voltage SW and the first power supply voltage V1 are substantially equal and the inductor current IL0 becomes 0 amperes, the determination signal COMP becomes high level and the switching regulator 200 transitions to the HiZ state.

[0088] At time t5, when the number of times indicated by the count signal CNT[n:1] (not shown in FIG. 14) exceeds the threshold number of times for transitioning to the MINF state, the MINF state signal SMINF goes high, and the switching regulator 200 transitions to the MINF state. The operation from time t5 to time t8 is the same as the operation from time t1 to time t4. The first power supply voltage V1, which has not yet risen to a predetermined voltage at time t6, is reduced at time t7, and therefore becomes a voltage lower than the predetermined negative voltage.

[0089] By performing the above-described operations from time t0 to time t8, the first power supply voltage V1 output by switching regulator 200 during the minimum frequency operation becomes a voltage lower than the predetermined negative voltage output during operations other than the minimum frequency operation. In other words, during the minimum frequency operation of switching regulator 200, an offset occurs in first power supply voltage V1, which is the output voltage.

[0090] 14, the reason why the first power supply voltage V1 becomes lower than the predetermined negative voltage can be explained as follows: In the MINF state, the first power supply detection voltage INP becomes higher than the ripple reference voltage INN earlier than the ripple reference voltage INN, and the state transitions to the HON state before the first power supply voltage V1 has risen to the predetermined voltage.

[0091] In the switching regulator 200 according to the comparative example, in order to correct the offset occurring in the first power supply voltage V1 during minimum frequency operation, for example, a measure is taken to make the first power supply sense voltage INP in the MINF state lower than the voltage in states other than the MINF state. Returning to the configuration diagram of the sense voltage generation circuit 81 in FIG. 13, when the MINF state signal SMINF is at a high level, the resistance value of the resistor R811 is switched to a relatively large resistance to lower the first power supply sense voltage INP, thereby lowering the feedback voltage FB. When the MINF state signal SMINF is at a low level, the resistance value of the resistor R811 is switched to a relatively small resistance to maintain the feedback voltage FB and the first power supply sense voltage INP at normal voltages.

[0092] Switching the resistance value of resistor R811 can be achieved, for example, as follows: R811 is divided into two resistors R811_1 and R811_2, the first and second terminals of resistor R811_1 are connected to the source and drain of a p-channel MOS transistor, and the MINF state signal SMINF is input to the gate of the p-channel MOS transistor. When the MINF state signal SMINF is at a low level, the first and second terminals of resistor R811_1 are shorted by the p-channel MOS transistor, and the resistance value of resistor R811 decreases. When the MINF state signal SMINF is at a high level, the first and second terminals of resistor R811_1 are not shorted, and the resistance value of resistor R811 increases.

[0093] The switching regulator 200 according to the comparative example requires an additional resistor and a MOS transistor to increase the resistance R811 of the sense voltage generation circuit 81 in the MINF state. Furthermore, since the setting of the first power supply voltage V1 can be changed according to user requirements, the resistance value of the resistor R811 must be changed to a resistance value suitable for correcting the offset of the first power supply voltage V1 for each setting of the first power supply voltage V1. To change the resistance value of the resistor R811 for each setting of the first power supply voltage V1, the resistor must be further divided and a MOS transistor must be added to short both ends of some of the divided resistors, increasing the circuit area. In contrast, the semiconductor device 100 according to the first embodiment does not generate an offset of the first power supply voltage V1 during minimum frequency operation, eliminating the need to change the resistance value of the resistor R511 of the sense voltage generation circuit 51 in the MINF state, thereby reducing the circuit area.

[0094] (Effects of the first embodiment) According to the first embodiment, the switching regulator 100 generates a ripple-superimposed reference voltage INN without the ripple voltage CSP superimposed thereon in either the HiZ state or the MINF state and compares the generated voltage with the first power supply sense voltage INP. By stopping the injection of the ripple voltage CSP in the MINF state, the switching regulator 100 transitions to the HON state after the first power supply voltage V1 exceeds a predetermined voltage in the MINF state, which is the lowest frequency operation. By transitioning to the HON state after the first power supply voltage V1 exceeds a predetermined voltage, the switching regulator 100 can set the first power supply voltage V1 to a predetermined negative voltage in the LON state. In other words, when the switching regulator 100 operates at the lowest frequency, no offset occurs in the first power supply voltage V1, which is the output voltage. This eliminates the need to switch the resistance value of the sense voltage generation circuit 51 to correct the offset of the first power supply voltage V1 in the MINF state, thereby minimizing the circuit area of ​​the switching regulator 100.

[0095] When the switching regulator 100 is not in the HiZ state or the MINF state, it generates a ripple-superimposed reference voltage INN by superimposing a ripple voltage CSP, which is obtained by dividing and integrating the switch voltage SW and the voltage of the ground power supply GND, and compares this with the first power supply detection voltage INP. By superimposing the ripple voltage CSP on the ripple-superimposed reference voltage INN, the comparator can operate stably even if the amplitude of the ripple component of the output voltage is not large, allowing the switching regulator 100 to operate stably.

[0096] [Second embodiment] (Configuration of semiconductor device) 9 is a configuration diagram of the ripple injection circuit 4 of the semiconductor device 100 according to the second embodiment. The ripple injection circuit 4 of FIG. 9 differs from the configuration diagram of the ripple injection circuit 4 of the semiconductor device 100 according to the first embodiment shown in FIG. 3 in the following respects. Instead of the p-channel MOS transistor 48 connecting the ripple voltage CSP and the reset voltage VRST, the ripple injection circuit 4 has p-channel MOS transistors 48a and 48b and an inverter 48c. The ripple source voltage PCSP, rather than the ripple voltage CSP, is output from the second end of the resistor R44 and the drain of the p-channel MOS transistor 41.

[0097] The inverter 48c inverts the ripple injection enable signal ENRIP input to its gate and outputs the ripple injection enable inverted signal ENRIPB. The p-channel MOS transistor 48a receives the ripple source voltage PCSP at its source and the ripple voltage enable inverted signal ENRIPB at its gate. When the ripple injection enable signal ENRIP is at a high level, the p-channel MOS transistor 48a turns on and outputs the ripple source voltage PCSP input to its source as a ripple voltage CSP from its drain. The p-channel MOS transistor 48b receives the ripple voltage CSP at its source, a reset voltage VRST at its drain, and the ripple injection enable signal ENRIP at its gate. When the ripple injection enable signal ENRIP is at a low level, the p-channel MOS transistor 48b turns on and resets the ripple voltage CSP input to its source to the same potential as the reset voltage VRST input to its drain.

[0098] That is, when the ripple injection enable signal ENRIP is at a high level, the p-channel MOS transistors 48a, 48b and the inverter 48c make the ripple voltage CSP have the same potential as the ripple source voltage PCSP. When the ripple injection enable signal ENRIP is at a low level, the p-channel MOS transistors 48a, 48b and the inverter 48c separate the ripple voltage CSP from the ripple source voltage PCSP and reset it to the reset voltage VRST.

[0099] (Effects of the second embodiment) According to the second embodiment, when the ripple injection circuit 4 resets the ripple voltage CSP to the reset voltage VRST, it disconnects the ripple voltage CSP from the second end of the resistor R44 and the drain of the p-channel MOS transistor 41. By disconnecting the second end of the resistor R44 and the drain of the p-channel MOS transistor 41 from the reset voltage VRST, it is possible to eliminate the current flowing from the second end of the resistor R44 and the drain of the p-channel MOS transistor 41 to the reset voltage VRST.

[0100] In the switching regulator 100 according to the second embodiment, by stopping injection of the ripple voltage CSP in the MINF state, the first power supply voltage V1 can be set to a predetermined negative voltage during minimum frequency operation, and no offset occurs in the first power supply voltage V1. In the MINF state, there is no need to switch the resistance value of the detection voltage generation circuit 51 to correct the offset of the first power supply voltage V1, and the circuit area of ​​the switching regulator 100 can be kept small.

[0101] [Other embodiments] Although several embodiments of the present disclosure have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. One or more elements of one embodiment can be combined with one or more elements of another embodiment. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0102] For example, although the semiconductor device 100 according to some embodiments of the present disclosure has been described as an inverting switching regulator, it may also be a step-down switching regulator with external connections modified to generate a negative voltage.

[0103] Also, for example, the ripple injection circuit 4 of the semiconductor device according to some embodiments of the present disclosure sets the ripple conversion current ICSP to 0 amperes in the MINF state so that the ripple voltage CSP is not superimposed on the reference voltage REF. However, the semiconductor device 100 may be configured to substantially not superimpose the ripple voltage on the reference voltage in the MINF state as follows. In the MINF state, the ripple injection circuit 4 generates a second ripple voltage CSP2 that has a longer delay from the switch voltage SW than the ripple voltage CSP. In the MINF state, the semiconductor device 100 superimposes the second ripple voltage CSP2 on the reference voltage REF in the ripple injection circuit 4 to generate a ripple-superimposed reference voltage INN, and superimposes it on the feedback voltage FB in the sense voltage generation circuit 51 to generate a first power supply sense voltage INP. Since the second ripple voltage CSP2 is superimposed on both the ripple superimposed reference voltage INN and the first power supply detection voltage INP, the second ripple voltage CSP2 is not superimposed on the difference obtained by comparing the ripple superimposed reference voltage INN and the first power supply detection voltage INP by the comparator 52.

[0104] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0105] (Appendix 1) The semiconductor device 100 sets the voltage of the first power supply TV1 connected to the source, which is the first main electrode of the first switch transistor 1, by complementary on-operation of first and second switch transistors 1 and 2 connected in series between a first power supply TV1 of low potential and a second power supply TV2 of high potential. The semiconductor device 100 includes a state control circuit 3, a ripple injection circuit 4, and a first control circuit 5.

[0106] The state control circuit 3 periodically generates a first state signal, the MINF state signal SMINF. When the MINF state signal SMINF is negated, the ripple injection circuit 4 integrates the voltage at the switch terminal T1 (the output terminal) to generate a ripple voltage CSP similar to the ripple current flowing through the inductor L0 connected to the switch terminal T1. The switch terminal T1 (the output terminal) is the connection point between the first and second switch transistors 1 and 2. The ripple injection circuit 4 generates a ripple-superimposed reference voltage INN by superimposing the ripple voltage CSP on a reference voltage REF. The first control circuit 5 generates a first power supply detection voltage INP based on a feedback voltage FB that is higher than the voltage of the first power supply TV1 and is equal to the reference voltage REF when the voltage of the first power supply TV1 reaches a reference value. The first control circuit 5 sequentially generates a high-side drive signal HG and a low-side drive signal LG when the first power supply detection voltage INP becomes higher than the ripple-superimposed reference voltage INN.

[0107] When the MINF state signal SMINF is asserted, the ripple injection circuit 4 stops superimposing the ripple voltage CSP, and the first control circuit 5 generates the low side drive signal LG. When the first power supply detection voltage INP becomes higher than the ripple superposition reference voltage INN, the first control circuit 5 generates the high side drive signal HG and the low side drive signal LG in sequence while the ripple injection circuit 4 continues to superimpose the ripple voltage CSP.

[0108] (Appendix 2) In the semiconductor device 100 described in Supplementary Note 1, when the MINF state signal SMINF, which is a first state signal, is negated, the ripple injection circuit 4 performs voltage-to-current conversion on the ripple voltage CSP to generate the ripple-converted current ICSP. The ripple injection circuit 4 also performs voltage-to-current conversion on the reference voltage REF to generate the reference current IREF, and superimposes the ripple-converted current ICSP on the reference current IREF to generate the ripple-superimposed reference current ISUM, which is then subjected to current-to-voltage conversion to generate the ripple-superimposed reference voltage INN. When the first state signal SMINF is asserted, the ripple injection circuit 4 generates the ripple-superimposed reference voltage INN without superimposing the ripple-converted current ICSP on the reference current IREF.

[0109] (Appendix 3) In the semiconductor device 100 described in Supplementary Note 1 or 2, the first control circuit 5 includes a sense voltage generation circuit 51. The sense voltage generation circuit 51 generates a feedback voltage FB by dividing the voltage V1 of the first power supply TV1 and a third power supply voltage V3, which is higher than the voltage of the first power supply TV1, using a first resistor R511 and a second resistor R512. The sense voltage generation circuit 51 performs voltage-to-current conversion of the feedback voltage FB to generate a feedback current IFB, and performs current-to-voltage conversion of the feedback current IFB to generate a first power supply sense voltage INP.

[0110] (Appendix 4) In the semiconductor device 100 described in Appendix 3, the resistance values ​​of the first and second resistors R511 and R512 when the MINF state signal SMINF, which is the first state signal, is asserted are the same as the resistance values ​​when the MINF state signal SMINF is negated.

[0111] (Appendix 5) The semiconductor device 100 described in any one of Supplementary Notes 1 to 4 may be configured to substantially prevent a ripple voltage from being superimposed on the reference voltage in the MINF state as follows. In the MINF state, the ripple injection circuit 4 generates a second ripple voltage CSP2 having a longer delay from the switch voltage SW than the ripple voltage CSP. In the MINF state, the semiconductor device 100 superimposes the second ripple voltage CSP2 on the reference voltage REF in the ripple injection circuit 4 to generate a ripple-superimposed reference voltage INN, and superimposes it on the feedback voltage FB in the detection voltage generation circuit 51 to generate a first power supply detection voltage INP. By superimposing the second ripple voltage CSP2 on both the ripple-superimposed reference voltage INN and the first power supply detection voltage INP by the comparator 52 comparing the ripple-superimposed reference voltage INN and the first power supply detection voltage INP, the second ripple voltage CSP2 is not superimposed on the difference between the ripple-superimposed reference voltage INN and the first power supply detection voltage INP. [Explanation of symbols]

[0112] 1 Low-side switch transistor 2 High-side switch transistor 3 MINF state control circuit 4 Ripple injection circuit 5. First control circuit 6 Reference voltage generation circuit 31 Oscillator Circuit 32 Counter Circuit 33 Judgment circuit 41 p-channel MOS transistor 42, 43 Voltage-to-current conversion (VI conversion) circuit 44 Current mixing circuit 45 Current-to-voltage conversion (IV conversion) circuit 46 inverter 47 OR Circuit 51 Detection voltage generation circuit 52, 53 Comparator 54 Timer Circuit 55 Output control circuit 100 Semiconductor device, particularly switching regulator 511 Soft start circuit 512 VI conversion circuit 513 IV conversion circuit C0, C1, C41 capacitors CNT[n:1] Count signal COMP judgment signal CSP ripple voltage EN Enable signal ENRIP Ripple injection enable signal FB Feedback voltage FBN Negative feedback voltage FBOUT Feedback judgment signal GND Ground power supply HG High potential side drive signal ICSP ripple conversion current IFB Feedback current IL0 Inductor current INN Ripple Reference Voltage INP First power supply detection voltage IREF Reference Current ISUM Total current L0 inductor LG Low potential side drive signal n natural number OSC Oscillator signal R0, R41, R42, R43, R44 resistors R511, R512 resistor REF Reference voltage SHIZ HiZ state signal SHIZ_MINF HiZ_MINF state signal SHON HON state signal SLON LON state signal SMINF MINF state signal SSW Voltage divider switch voltage SW Switch voltage t0, t1, t2, t3, t4, t5, t6, t7, t8 time T1 switch terminal T2 feedback terminal TIMER Timer signal TV1 1st power terminal TV2 2nd power terminal V1 First power supply voltage V2 Second power supply voltage V3 Third power supply voltage V3_INT Internal third power supply voltage VRST Reset voltage

Claims

1. A semiconductor device in which a first switch transistor and a second switch transistor connected in series between a first power supply of a low potential and a second power supply of a high potential are turned on in a complementary manner, thereby setting a voltage of a first power supply connected to a first main electrode of the first switch transistor, a state control circuit that generates a first state signal at regular intervals; a ripple injection circuit that, when the first state signal is negated, integrates a voltage at an output terminal that is a connection point between the first switch transistor and the second switch transistor to generate a ripple voltage similar to a ripple current flowing through an inductor connected to the output terminal, and superimposes the ripple voltage on a reference voltage to generate a ripple-superimposed reference voltage; a first control circuit that generates a first power supply detection voltage based on a feedback voltage that is higher than the voltage of the first power supply and that is equal to the reference voltage when the voltage of the first power supply reaches a reference value, and that sequentially generates a high potential side drive signal and a low potential side drive signal when the first power supply detection voltage becomes higher than the ripple superimposed reference voltage; Equipped with When the first state signal is asserted, the ripple injection circuit stops superimposing the ripple voltage, and the first control circuit generates the low-potential side drive signal; when the first power supply detection voltage becomes higher than the ripple superimposed reference voltage, the first control circuit generates the high potential side drive signal and the low potential side drive signal in sequence while the ripple injection circuit superimposes the ripple voltage.

2. the ripple injection circuit When the first state signal is negated, converting the ripple voltage into a current to generate a ripple converted current; converting the reference voltage into a current to generate a reference current; generating a ripple-superimposed reference current by superimposing the ripple-converted current on the reference current; generating the ripple-superimposed reference voltage by performing current-to-voltage conversion on the ripple-superimposed reference current; When the first state signal is asserted, generating a ripple-superimposed reference current without superimposing the ripple converted current on the reference current; The semiconductor device according to claim 1 .

3. the first control circuit includes a detection voltage generating circuit; The detection voltage generating circuit generating the feedback voltage by dividing a voltage of the first power supply and a voltage of a third power supply that supplies a voltage higher than the voltage of the first power supply using a first resistor and a second resistor; generating a feedback current by performing voltage-to-current conversion on the feedback voltage, and generating the first power supply detection voltage by performing current-to-voltage conversion on the feedback current; 3. The semiconductor device according to claim 1.

4. the resistance values ​​of the first resistor and the second resistor when the first state signal is asserted are the same as the resistance values ​​when the first state signal is negated; The semiconductor device according to claim 3 .

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