Controller, target, and communication system

Abstract

To provide a controller capable of improving communication quality while suppressing a decrease in communication efficiency.SOLUTION: A controller (CNT1) is a controller configured to perform serial communication with a target (TG1, TG2), and includes: an arithmetic circuit (101) configured to calculate a CRC value of a signal string including an address of the target, an address of the storage circuit, and write data when the controller writes data to a storage circuit (201) of the target; and a communication circuit (102) configured to transmit the address of the target, the address of the storage circuit, the write data, and the CRC value to the target. The arithmetic circuit is configured to hold a calculation value in the middle of calculation when an acknowledgment is returned from the target.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a controller, a target, and a communication system. [Background technology]

[0002] A CRC (Cyclic Redundancy Check) value is used to verify whether data transmitted from a transmitting side to a receiving side is sent correctly (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-16751

[0004] [overview] However, if only data is subject to CRC calculation, it is not possible to verify whether there are any errors in the address information sent from the sender to the receiver along with the data when the data is sent from the sender to the receiver, which leaves issues in terms of communication quality.

[0005] The controller according to the present disclosure is a controller configured to perform serial communication with a target, and includes: an arithmetic circuit configured to calculate a CRC value of a signal sequence including an address of the target, an address of the memory circuit, and write data when the controller writes data to a memory circuit of the target; and a communication circuit configured to transmit the address of the target, the address of the memory circuit, the write data, and the CRC value to the target, and the arithmetic circuit is configured to hold a calculated value in the middle of calculation when a positive response is returned from the target.

[0006] A target according to the present disclosure is a target configured to perform serial communication with a controller, and includes: calculation circuits configured to calculate a CRC value of a signal sequence including an address of the target, an address of the memory circuit, and read data when the controller reads data from the memory circuit of the target; and a communication circuit configured to transmit the read data and the CRC value to the controller, wherein the calculation circuits include a first calculation circuit and a second calculation circuit, each configured to perform a CRC calculation on the received signal sequence; the first calculation circuit is configured to perform a reset operation in response to a start condition of the serial communication; and the second calculation circuit is configured to receive a value calculated by the first calculation circuit in the middle of a calculation when the target returns an affirmative response to the address of the target that it first received, and to avoid a reset operation in response to the start condition of the serial communication. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a communication protocol for writing data according to a comparative example. [Figure 2] FIG. 2 is a diagram showing a communication protocol for reading data according to a comparative example. [Figure 3] FIG. 3 is a diagram illustrating a communication protocol for writing data according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating a communication protocol for reading data according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram illustrating a configuration example of a communication system according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of an arithmetic circuit. [Figure 7] FIG. 7 is a diagram for explaining the operation of the arithmetic circuit. [Figure 8] FIG. 8 is a diagram for explaining the operations of the first arithmetic circuit and the second arithmetic circuit. [Figure 9] FIG. 9 is a diagram illustrating a communication protocol in multiple modes of data writing according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating a communication protocol in multiple modes of data reading according to an embodiment of the present disclosure.

[0008] [Detailed explanation] <Comparative Example> 1 is a diagram showing a communication protocol for writing data according to a comparative example. Note that the communication protocol of the comparative example and the embodiments described below conforms to the I2C communication standard. In each diagram showing the communication protocol, each block represents a 1-bit signal, with white blocks representing signals transmitted from the controller to the target and gray blocks representing signals transmitted from the target to the controller.

[0009] In the communication protocol shown in FIG. 1, signals are transmitted in the following order: start condition 1, target address 2, signal indicating data write 3, acknowledgement 4, CRC code (CRC value) 5, acknowledgement 6, register address 7, acknowledgement 8, CRC code 9, acknowledgement 10, write data 11, acknowledgement 12, CRC code 13, acknowledgement 14, and stop condition 15.

[0010] CRC code 5 is the result of a CRC calculation for target address 2 and signal 3 indicating data write. CRC code 9 is the result of a CRC calculation for register address 7. CRC code 13 is the result of a CRC calculation for write data 11.

[0011] FIG. 2 is a diagram showing a communication protocol for reading data according to a comparative example.

[0012] In the communication protocol shown in FIG. 2, signals are transmitted in the following order: start condition 21, target address 22, signal 23 indicating data write, acknowledgement 24, CRC code 25, acknowledgement 26, register address 27, acknowledgement 28, CRC code 29, acknowledgement 30, start condition 31, target address 32, signal 33 indicating data read, acknowledgement 34, CRC code 35, acknowledgement 36, read data 37, acknowledgement 38, CRC code 39, negative acknowledgement 40, and stop condition 41.

[0013] CRC code 25 is the result of a CRC calculation on target address 22 and signal 23 indicating data write. CRC code 29 is the result of a CRC calculation on register address 27. CRC code 35 is the result of a CRC calculation on target address 32 and signal 33 indicating data read. CRC code 39 is the result of a CRC calculation on read data 37.

[0014] In the comparative example, not only data errors but also address errors can be detected, thereby improving communication quality. However, in the comparative example, when writing data, the CRC value of the signal sequence including the target address, the CRC value of the register address, and the CRC value of the write data are calculated separately. Also, in the comparative example, when reading data, the CRC value of the signal sequence including the target address, the CRC value of the register address, and the CRC value of the read data are calculated separately. As a result, in the comparative example, the number of CRC values ​​transmitted increases, significantly reducing communication efficiency. In the embodiment described below, this problem can be solved.

[0015] <Embodiment> FIG. 3 is a diagram illustrating a communication protocol for writing data according to an embodiment of the present disclosure.

[0016] In the communication protocol shown in FIG. 3, signals are transmitted in the following order: start condition 51, target address 52, signal indicating data write 53, acknowledgement 54, register address 55, acknowledgement 56, write data 57, acknowledgement 58, CRC code 59, acknowledgement 60, and stop condition 61.

[0017] The CRC code 59 is the result of a CRC calculation performed on the target address 52 , the signal 53 indicating data writing, the register address 55 , and the write data 57 .

[0018] FIG. 4 is a diagram illustrating a communication protocol for reading data according to an embodiment of the present disclosure.

[0019] In the communication protocol shown in FIG. 4, signals are transmitted in the following order: start condition 71, target address 72, signal 73 indicating data write, acknowledgement 74, register address 75, acknowledgement 76, start condition 77, target address 78, signal 79 indicating data read, acknowledgement 80, read data 81, acknowledgement 82, CRC code 83, negative acknowledgement 84, and stop condition 85.

[0020] The CRC code 83 is the result of a CRC calculation performed on the target address 72 , the signal 73 indicating data writing, the register address 75 , the target address 78 , the signal 79 indicating data reading, and the read data 81 .

[0021] In an embodiment of the present disclosure, not only data errors but also address errors can be detected, thereby improving communication quality. Furthermore, in an embodiment of the present disclosure, when writing data, a CRC value of a signal sequence including a target address, a register address, and write data is calculated. Furthermore, in an embodiment of the present disclosure, when reading data, a CRC value of a signal sequence including a target address, a register address, and read data is calculated. Therefore, in an embodiment of the present disclosure, an increase in the CRC value transmitted can be suppressed, thereby suppressing a decrease in communication efficiency.

[0022] FIG. 5 is a diagram illustrating an example configuration of a communication system according to an embodiment of the present disclosure. The communication system SYS1 illustrated in FIG. 5 includes a controller CNT1 and targets TG1 and TG2. Each of the targets TG1 and TG2 is assigned a unique address. In the communication system SYS1 illustrated in FIG. 5, the number of targets is two, but the number of targets is not limited to two and may be one, or three or more. In the following description, when there is no need to distinguish between the target TG1 and the target TG2, each of the targets TG1 and TG2 may be referred to as the target TG.

[0023] The controller CNT1 is configured by, for example, a CPU (Central Processing Unit). The controller CNT1 includes an arithmetic circuit 101 and a communication circuit .

[0024] The arithmetic circuit 101 calculates the CRC value of a signal sequence including the address of the target TG, which is the communication partner, the address of the register 2101 built in the target TG, which is the communication partner, and the write data. In other words, the arithmetic circuit 101 calculates the CRC code 59 in FIG.

[0025] The communication circuit 102 generates a clock signal and transmits and receives the signal sequence (serial data signal) shown in Fig. 3 and the signal sequence (serial data signal) shown in Fig. 4 transmitted by the second signal line SL2 in synchronization with the clock signal. The communication circuit 102 also outputs the generated clock signal to the first signal line SL1.

[0026] The controller CNT1 verifies whether there are any errors in the target address 72, signal 73 indicating data write, register address 75, target address 78, and signal 79 indicating data write received by the target TG, and the read data 81 received by the controller CNT1, using a CRC code 83. Specifically, the controller CNT1 calculates a CRC code from the target address 72, signal 73 indicating data write, register address 75, target address 78, and signal 79 indicating data write sent to the target TG, and the read data 81 received by the controller CNT1, and determines that there is an error if this calculated CRC code does not match the CRC code 83.

[0027] The target TG is configured by, for example, an LSI (Large Scale Integration) and includes a register 201, an arithmetic circuit 202, and a communication circuit 203.

[0028] The register 201 is a storage circuit that can write data and read data. Note that the target TG may include a storage circuit other than the register 201 instead of the register 201.

[0029] The arithmetic circuit 202 calculates the CRC value of a signal string including the address of the target TG in which it is mounted, the address of the register 201 built in the target TG in which it is mounted, and the read data. That is, the arithmetic circuit 101 calculates the CRC code 83 in FIG. 4. The arithmetic circuit 202 includes a first arithmetic circuit 202A and a second arithmetic circuit 202B. The first arithmetic circuit 202A and the second arithmetic circuit 202B will be described in detail later.

[0030] The communication circuit 203 receives a clock signal output from the controller CNT1, and transmits and receives the signal sequence (serial data signal) shown in FIG. 3 and the signal sequence (serial data signal) shown in FIG. 4 transmitted by the second signal line SL2 in synchronization with the clock signal.

[0031] The target TG verifies whether there are any errors in the target address 52, signal 53 indicating data writing, register address 55, and write data 57 received by the target TG using the CRC code 59. Specifically, the target TG calculates a CRC code from the target address 52, signal 53 indicating data writing, register address 55, and write data 57 received by the target TG, and determines that there is an error if the calculated CRC code does not match the CRC code 59.

[0032] Fig. 6 is a diagram showing an example configuration of the arithmetic circuit 101. The arithmetic circuit 101 of the example configuration shown in Fig. 6 includes flip-flops FF0 to FF7 and exclusive OR circuits XOR1 to XOR3, and performs serial data processing. The example configuration of the first arithmetic circuit 202A is also the example configuration shown in Fig. 6, and the example configuration of the second arithmetic circuit 202B is also the example configuration shown in Fig. 6. A clock signal generated in the communication circuit 102 is supplied to the clock input terminals of the flip-flops FF0 to FF7.

[0033] In the arithmetic circuit of the configuration example shown in Fig. 6, the initial values ​​of the signals output from the output terminals of the flip-flops FF0 to FF7 are all 0. Therefore, the initial value of the CRC code calculated by the arithmetic circuit of the configuration example shown in Fig. 6 is 00000000. When the arithmetic circuit of the configuration example shown in Fig. 6 performs a reset operation, the CRC code calculated by the arithmetic circuit of the configuration example shown in Fig. 6 is reset to the initial value.

[0034] Fig. 7 is a diagram for explaining the operation of the arithmetic circuit 101. The arithmetic circuit 101 performs the operation shown in Fig. 7 when the controller CNT1 writes data to the register 201 of the target TG.

[0035] The arithmetic circuit 101 performs a reset operation OP1 in a cycle in which the flip-flops FF0 to FF7 store data supplied to their input terminals while a start condition 51 is being input to the arithmetic circuit 101. After the reset operation OP1, the arithmetic circuit 101 performs a normal arithmetic operation OP2.

[0036] After the arithmetic operation OP2, the arithmetic circuit 101 performs a hold operation OP3 in which it holds a calculation value during calculation in a cycle in which the flip-flops FF0 to FF7 store data supplied to their input terminals while the affirmative response 54 is being input to the arithmetic circuit 101. In the hold operation OP3, the flip-flops FF0 to FF7 supply data output from their output terminals to their input terminals. After the hold operation OP3, the arithmetic circuit 101 performs a normal arithmetic operation OP4.

[0037] After the arithmetic operation OP4, the arithmetic circuit 101 performs a hold operation OP5 in which the calculation result is held in a cycle in which the flip-flops FF0 to FF7 store data supplied to their input terminals while the affirmative response 56 is being input to the arithmetic circuit 101. In the hold operation OP5, the flip-flops FF0 to FF7 supply data output from their output terminals to their input terminals. After the hold operation OP5, the arithmetic circuit 101 performs a normal arithmetic operation OP6.

[0038] After the operation OP6, the arithmetic circuit 101 starts a holding operation OP7 for holding the calculation result (CRC code 59) in a cycle in which the flip-flops FF0 to FF7 store the data supplied to their input terminals while the acknowledgment 56 is being input to the arithmetic circuit 101. The holding operation OP7 continues until the output of the CRC code 59 from the arithmetic circuit 101 is completed.

[0039] The arithmetic circuit 101 may perform any operation during periods other than the periods during which the operations OP1 to OP7 are performed.

[0040] Fig. 8 is a diagram for explaining the operations of the first arithmetic circuit 202A and the second arithmetic circuit 202B. The first arithmetic circuit 202A and the second arithmetic circuit 202B perform the operations shown in Fig. 8 when the controller CNT1 reads data from the register 201 of the target TG.

[0041] The arithmetic circuit 202A performs a reset operation OP11 in a cycle in which the flip-flops FF0 to FF7 store data supplied to their input terminals while a start condition 71 is being input to the arithmetic circuit 202A. After the reset operation OP11, the arithmetic circuit 202A starts a normal arithmetic operation OP12. The arithmetic operation OP12 continues until the cycle immediately before the cycle in which the flip-flops FF0 to FF7 store data supplied to their input terminals while an affirmative response 74 is being input to the arithmetic circuit 202A.

[0042] The arithmetic circuit 202A performs a reset operation OP13 in a cycle in which the flip-flops FF0 to FF7 store data supplied to their input terminals while a start condition 77 is being input to the arithmetic circuit 202A. After the reset operation OP13, the arithmetic circuit 202A starts a normal arithmetic operation OP14. The arithmetic operation OP14 continues until the cycle immediately before the cycle in which the flip-flops FF0 to FF7 store data supplied to their input terminals while an acknowledgment 80 is being input to the arithmetic circuit 202A.

[0043] The arithmetic circuit 202A may perform any operation during periods other than the periods during which the operations OP11 to OP14 are performed.

[0044] The arithmetic circuit 202B performs a load operation OP21 in a cycle in which the flip-flops FF0 to FF7 store data supplied to their input terminals while the acknowledgment 74 is being input to the arithmetic circuit 202B. In the load operation OP21, the arithmetic circuit 202B receives a calculation value that is being calculated midway through the calculation being performed by the arithmetic circuit 202A. Therefore, immediately after the arithmetic circuit 202B completes the load operation OP21, the data stored in the flip-flops FF0 to FF7 of the arithmetic circuit 202A and the data stored in the flip-flops FF0 to FF7 of the arithmetic circuit 202B completely match. After the load operation OP21, the arithmetic circuit 202B performs a normal arithmetic operation OP22.

[0045] After the arithmetic operation OP22, the arithmetic circuit 202B performs a holding operation OP23 in which it holds a calculation value during the calculation, in a cycle in which the flip-flops FF0 to FF7 store data supplied to their input terminals while the acknowledgment 76 is being input to the arithmetic circuit 202B, and in a cycle in which the flip-flops FF0 to FF7 store data supplied to their input terminals while the start condition 77 is being input to the arithmetic circuit 202B. In the holding operation OP23, the flip-flops FF0 to FF7 supply data output from their output terminals to their input terminals. After the holding operation OP23, the arithmetic circuit 202B performs a normal arithmetic operation OP24.

[0046] After the arithmetic operation OP24, the arithmetic circuit 202B performs a hold operation OP25 in which it holds the calculation result in a cycle in which the flip-flops FF0 to FF7 store the data supplied to their input terminals while the affirmative response 80 is being input to the arithmetic circuit 202B. In the hold operation OP25, the flip-flops FF0 to FF7 supply the data output from their output terminals to their input terminals. After the hold operation OP25, the arithmetic circuit 202B performs a normal arithmetic operation OP26.

[0047] After the arithmetic operation OP26, the arithmetic circuit 202B starts a holding operation OP27 in which the calculation result (CRC code 83) is held in a cycle in which the flip-flops FF0 to FF7 store the data supplied to their input terminals while the acknowledgment 82 is being input to the arithmetic circuit 202B. The holding operation OP27 continues until the output of the CRC code 83 from the arithmetic circuit 202B is completed.

[0048] The arithmetic circuit 202B may perform any operation during periods other than the periods during which the operations OP21 to OP27 are performed.

[0049] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0050] For example, although a single-mode communication protocol is employed in the above embodiment, a multiple-mode communication protocol may also be employed.

[0051] 9 is a diagram illustrating a communication protocol for data writing in multiple mode according to an embodiment of the present disclosure. The communication protocol illustrated in FIG. 9 differs from the communication protocol illustrated in FIG. 3 in that after acknowledgment 60, write data 62, acknowledgment 63, CRC code 64, acknowledgment 65, and stop condition 66 are sent. However, the communication system SYS1 may have the same circuit configuration as in single mode. CRC code 64 is the result of a CRC calculation on write data 62. Note that, although there are two pieces of write data in the communication protocol illustrated in FIG. 9, there may be three or more pieces of write data in multiple mode.

[0052] FIG. 10 is a diagram illustrating a communication protocol for data read in multiple mode according to an embodiment of the present disclosure. The communication protocol illustrated in FIG. 10 differs from the communication protocol illustrated in FIG. 4 in that after the CRC code 83, there is an acknowledgment 86, read data 87, an acknowledgment 88, a CRC code 89, a negative acknowledgment 90, and a stop condition 91. However, the communication system SYS1 may have the same circuit configuration as in single mode. The CRC code 89 is the result of a CRC calculation on the read data 87. Note that, although the communication protocol illustrated in FIG. 10 includes two pieces of read data, there may be three or more pieces of read data in multiple mode.

[0053] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0054] The controller (CNT1) of the present disclosure is a controller configured to perform serial communication with targets (TG1, TG2), and includes an arithmetic circuit (101) configured to calculate a CRC value of a signal sequence including the address of the target, the address of the memory circuit, and write data when the controller writes data to the memory circuit (201) of the target, and a communication circuit (102) configured to transmit the address of the target, the address of the memory circuit, the write data, and the CRC value to the target, and the arithmetic circuit is configured to hold the calculated value in the middle of the calculation when a positive response is returned from the target (first configuration).

[0055] According to the controller of the first configuration, the CRC value of the signal sequence including the target address, the memory circuit address, and the write data is calculated, so that not only data errors but also address errors can be detected, improving communication quality.Furthermore, according to the controller of the first configuration, the CRC value of the signal sequence including the target address, the memory circuit address, and the write data is calculated, so that a decrease in communication efficiency can be suppressed compared to when the CRC value of the signal sequence including the target address, the CRC value of the memory circuit address, and the CRC value of the write data are calculated separately.

[0056] In the controller of the first configuration described above, the target and the controller may be connected via a first signal line (SL1) configured to transmit a clock signal output from the controller and a second signal line (SL2) configured to transmit a serial data signal synchronized with the clock signal, and the arithmetic circuit may be configured to receive the serial data signal (second configuration).

[0057] The targets (TG1, TG2) of the present disclosure are targets configured to perform serial communication with a controller (CNT1), and include: arithmetic circuits (202) configured to calculate a CRC value of a signal sequence including an address of the target, an address of the memory circuit, and read data when the controller reads data from the memory circuit (201) of the target; and a communication circuit (203) configured to transmit the read data and the CRC value to the controller, wherein the arithmetic circuits include a first arithmetic circuit (202A) and a second arithmetic circuit (202B), each configured to perform a CRC calculation on the received signal sequence; the first arithmetic circuit is configured to perform a reset operation in response to a start condition of the serial communication; and the second arithmetic circuit is configured to receive a value calculated by the first arithmetic circuit at the timing when the target returns an affirmative response to the address of the target that it first received, and to avoid a reset operation in response to the start condition of the serial communication (third configuration).

[0058] According to the target of the third configuration, the CRC value of the signal sequence including the target address, the memory circuit address, and the read data is calculated, so that not only data errors but also address errors can be detected, improving communication quality. Furthermore, according to the target of the third configuration, the CRC value of the signal sequence including the target address, the memory circuit address, and the read data is calculated, so that a decrease in communication efficiency can be suppressed compared to when the CRC value of the signal sequence including the target address, the CRC value of the memory circuit address, and the CRC value of the read data are calculated separately.

[0059] In the target of the third configuration, the second arithmetic circuit may be configured to hold a calculation value during calculation when an affirmative response is returned to the controller and when the controller outputs a start condition for the serial communication (fourth configuration).

[0060] In the target of the third or fourth configuration, the target and the controller may be connected via a first signal line configured to transmit a clock signal output from the controller and a second signal line configured to transmit a serial data signal synchronized with the clock signal, and the first arithmetic circuit may be configured to receive the serial data signal (fifth configuration).

[0061] A communication system (SYS1) according to one aspect of the present disclosure comprises a controller of the first or second configuration described above and the target, wherein the target is configured to use the CRC value to verify whether there are any errors in the address of the target and the address of the memory circuit received by the target and the read data received by the controller (fifth configuration).

[0062] A communication system (SYS1) according to another aspect of the present disclosure is a configuration (sixth configuration) comprising a target of any of the third to fifth configurations described above and the controller, wherein the controller is configured to use the CRC value to verify whether there are any errors in the received address of the target, the address of the memory circuit, and the read data. [Explanation of symbols]

[0063] 1, 21, 31, 51, 71, 77 Start condition 2, 22, 32, 52, 72, 78 target addresses 3, 23, 53, 73, 76 Signals indicating data write 4, 6, 8, 10, 12, 14, 24, 26, 28, 30, 34, 36, 38, 54, 56, 58, 60, 63, 65, 74, 80, 82, 86, 88 Acknowledgement 5, 9, 13, 25, 29, 35, 39, 59, 64, 83, 89 CRC codes 7, 27, 55, 75 register addresses 11, 57, 62 Write data 15, 41, 61, 66, 85, 91 Stop conditions 33, 79 Signal indicating data read 37, 81, 87 Read data 40, 84, 90 negative response 101, 202 Arithmetic circuit 102, 203 Communication circuits 201 Register 202A 1st calculation circuit 202B 2nd calculation circuit CNT1 controller FF0~FF7 flip-flops OP1, OP11, OP13 reset operation OP2, OP4, OP6, OP12, OP14, OP22, OP24, OP26 arithmetic operations OP3, OP5, OP7, OP23, OP25, OP27 holding operation OP21 Load operation TG1, TG2 targets SL1 First signal line SL2 Second signal line SYS1 Communication System XOR1~XOR3 Exclusive OR circuit

Claims

1. A controller configured for serial communication with a target, an arithmetic circuit configured to calculate a CRC value of a signal sequence including an address of the target, an address of the storage circuit, and write data when the controller writes data to the target storage circuit; a communication circuit configured to transmit the address of the target, the address of the storage circuit, the write data, and the CRC value to the target; Equipped with The controller, wherein the calculation circuit is configured to hold a calculation value in progress when an acknowledgement is returned from the target.

2. the target and the controller are connected via a first signal line configured to transmit a clock signal output from the controller and a second signal line configured to transmit a serial data signal synchronized with the clock signal; The controller of claim 1 , wherein the operational circuitry is configured to receive the serial data signal.

3. a target configured for serial communication with a controller, an arithmetic circuit configured to calculate a CRC value of a signal string including an address of the target, an address of the storage circuit, and read data when the controller reads data from the storage circuit of the target; a communication circuit configured to transmit the read data and the CRC value to the controller; Equipped with the arithmetic circuit includes a first arithmetic circuit and a second arithmetic circuit, the first arithmetic circuit and the second arithmetic circuit are each configured to perform a CRC operation on a received signal sequence; the first arithmetic circuit is configured to perform a reset operation in response to a start condition of the serial communication; The second arithmetic circuit is configured to receive a calculation value in the middle of a calculation being performed by the first arithmetic circuit at the timing when the target returns an affirmative response to the address of the target that it first received, and to avoid a reset operation at the start condition of the serial communication.

4. 4. The target according to claim 3, wherein the second calculation circuit is configured to hold a calculation value in progress when an affirmative response is returned to the controller and when the controller outputs a start condition for the serial communication.

5. the target and the controller are connected via a first signal line configured to transmit a clock signal output from the controller and a second signal line configured to transmit a serial data signal synchronized with the clock signal; The target of claim 3 , wherein the first operational circuit is configured to receive the serial data signal.

6. A control system comprising: the controller according to claim 1 or claim 2; and the target; The target is configured to verify, using the CRC value, whether there are any errors in the target address, the memory circuit address, and the write data received by the target.

7. A target according to any one of claims 3 to 5 and the controller, The controller is configured to use the CRC value to verify whether there are any errors in the address of the target and the address of the memory circuit received by the target and the read data received by the controller.

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