Semiconductor device

Abstract

To provide a semiconductor device that forms a gate dielectric layer with higher reliability as a buffer layer by using a heteroepitaxial layer of a semiconductor, to prevent formation of carbon clusters in the gate dielectric layer.SOLUTION: A semiconductor device includes a semiconductor layer 100, a trench gate structure 150, and a buffer layer 190. The semiconductor layer has a first surface and a second surface facing each other. At least part of the trench gate structure is located in a trench 102 of the first surface of the semiconductor layer, and includes a source region 130, a drift region 101, and a body region 110. The buffer layer is a heteroepitaxial layer of the semiconductor layer, covers an inner surface of the trench and the first surface of the semiconductor layer, and is located between a gate dielectric layer 151 and the semiconductor layer. A gate dielectric layer with higher reliability is formed as the buffer layer by using the heteroepitaxial layer of the semiconductor, to prevent formation of carbon clusters in the gate dielectric layer and improve the reliability of the device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to the field of semiconductor device technology, and more particularly to semiconductor devices having trench gate structures. [Background technology]

[0002] Silicon carbide (SiC) semiconductor devices have advantages such as fast switching speeds and high power densities. Compared with planar transistor structures, vertical transistor structures facilitate a tradeoff between blocking voltage and on-resistance within the same area. The reliability of the gate dielectric layer is one of the key indicators of vertical transistor structures. However, when the gate dielectric layer is formed on the semiconductor layer by an oxidation process, preferential oxidation of Si in SiC leads to the formation of carbon clusters (C clusters) in the gate dielectric layer, which degrades the uniformity and film quality of the gate dielectric layer and reduces the stability and reliability of the device. Summary of the Invention [Problem to be solved by the invention]

[0003] In view of the above problems, the present disclosure aims to provide a semiconductor device in which a heteroepitaxial layer of a semiconductor layer is used as a buffer layer to form a more reliable gate dielectric layer, thereby suppressing the formation of carbon clusters in the gate dielectric layer. [Means for solving the problem]

[0004] An embodiment of the present disclosure provides a semiconductor device including a semiconductor layer having opposing first and second surfaces, a trench gate structure, and a buffer layer, wherein at least a portion of the trench gate structure is located within a trench in the first surface of the semiconductor layer; Here, the semiconductor layer is a source region extending in a direction from the first surface toward the second surface; a drift region and a body region, at least a portion of which is located between the body region and the second surface of the semiconductor layer; a first portion of the body region is located between the source region and the drift region along a direction from the first surface toward the second surface, and both the first portion of the body region and the source region are adjacent to a first sidewall of the trench; wherein the buffer layer is a heteroepitaxial layer of the semiconductor layer, the buffer layer covers an inner surface of the trench and a first surface of the semiconductor layer, and the buffer layer is located between a gate dielectric layer of the trench gate structure and the semiconductor layer; Here, the source region and the drift region are of a first conductivity type, the body region is of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

[0005] Optionally, the semiconductor layer comprises a silicon carbide semiconductor layer, and the buffer layer comprises one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer.

[0006] Optionally, the buffer layer thickness comprises one or more atomic layers thick.

[0007] Optionally, the first portion, the second portion, and the third portion of the body region are adjacent to each other in a width direction of the trench gate structure; the first and second portions of the body region are located between two of the trench gate structures, the first portion is adjacent to a first sidewall of the trench, the second portion is adjacent to a second sidewall of the trench, and the first sidewall and the second sidewall face each other; the third portion and the second portion are adjacent to the same trench, and the third portion is located between a bottom surface of the trench and the second surface, and the third portion and the first portion are separated by the drift region; Here, the second portion is adjacent to the second sidewall, or the second portion and the second sidewall are separated by the drift region.

[0008] Optionally, a third portion of the body region extends from a bottom surface of the trench toward the second surface; or At least a portion of the bottom surface of the trench and a third portion of the body region are separated by the drift region along a direction from the first surface toward the second surface.

[0009] Optionally, the second portion of the body region includes a first sub-region and a second sub-region that are connected; Along a width direction of the trench gate structure, the first sub-region is adjacent to a first portion of the body region, and the second sub-region is adjacent to a third portion of the body region; wherein a distance from an edge of the first portion of the body region in the direction of the second surface to the first surface is a first distance, a distance from an edge of the first sub-region in the direction of the second surface to the first surface is a second distance, and a distance from an edge of the second sub-region in the direction of the second surface to the first surface is a third distance; The third distance is greater than the second distance, and the second distance is greater than the first distance.

[0010] Optionally, the distance from the bottom of the trench to the first surface is a fourth distance, and the second distance is greater than or equal to the fourth distance.

[0011] Optionally, a distance that the drift region separates a third portion of the body region from a bottom surface of the trench along a direction from the second surface toward the first surface is a fifth distance; The sum of the fourth distance and the fifth distance is equal to the second distance.

[0012] Optionally, the edges of the second and third portions of the body region facing the second surface are connected; or The edge of the third portion facing the second surface is closer to the second surface than the edge of the second portion facing the second surface.

[0013] Optionally, the semiconductor layer further includes a channel drain region located between a first portion of the body region and the drift region, whereby the source region, the first portion of the body region, and the channel drain region are adjacent to each other in a direction from the first surface to the second surface, and are all adjacent to the first sidewall of the trench; the channel drain region is further adjacent to the drift region and the second portion of the body region, and the channel drain region and the third portion of the body region are separated by the drift region; Here, the channel drain region is of a first conductivity type.

[0014] Optionally, the doping concentration of the channel drain region is greater than the doping concentration of the drift region.

[0015] Optionally, a distance from an edge of the channel drain region toward the second surface to the first surface is not greater than a distance from a bottom surface of the trench to the first surface; or The distance from the edge of the channel drain region toward the second surface to the first surface is greater than the distance from the bottom surface of the trench to the first surface, and the channel drain region is adjacent to a portion of the bottom surface of the trench.

[0016] Optionally, the semiconductor layer further includes a channel drain region located between the first portion of the body region and the drift region, whereby the source region, the first portion of the body region, and the channel drain region are adjacent to each other in a direction from the first surface to the second surface, and are all adjacent to a first sidewall of the trench; the channel drain region is further adjacent to the drift region and the second portion of the body region, and the channel drain region and the third portion of the body region are separated by the drift region; wherein the channel drain region is of a first conductivity type; a distance from an edge of the channel drain region toward the second surface to the first surface is a sixth distance; The sixth distance is greater than the second distance, and the third distance is greater than the sixth distance, such that the channel drain region and the second sub-region are separated by the drift region along a width direction of the trench gate structure.

[0017] Optionally, the semiconductor layer further includes a body contact region extending in a direction from the first surface toward the second surface, the body contact region being adjacent to the body region; the body contact region is adjacent to the source region or separated by the body region; Here, the body contact region is of the second conductivity type.

[0018] Optionally, a portion of the body contact region is adjacent to the second sidewall along an extension direction of the trench gate structure, and a gap is formed between another portion of the body contact region and the second sidewall, and the adjacent portion of the body contact region and the second sidewall and the portion having the gap are alternately provided along an extension direction of the trench gate structure; Alternatively, the body contact region and the second sidewall are both separated by the body region.

[0019] Optionally, the trench gate structure includes the gate dielectric layer and a gate conductor; the gate dielectric layer covers the buffer layer located on the inner surface of the trench and a portion of the buffer layer located on the first surface adjacent to the trench, the trench extending in a direction from the first surface toward the second surface; a portion of the gate conductor located within the trench and another portion extending outside the trench and covering the gate dielectric layer; Here, the gate dielectric layer is located between the gate conductor and the buffer layer to separate the gate conductor and the buffer layer.

[0020] Optionally, the semiconductor device is a metal-oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

[0021] Optionally, between the two trench gate structures, the source region extends in a direction from a first sidewall of one of the trenches to a second sidewall of the other of the trenches and is adjacent to a second portion of the body region.

[0022] One of the above technical solutions has the following beneficial effects.

[0023] By forming a heteroepitaxial layer between the inner surface of the trench in the semiconductor layer and the first surface of the semiconductor layer, a more reliable gate dielectric layer is formed using the heteroepitaxial layer of the semiconductor layer as a buffer layer, thereby suppressing the formation of carbon clusters in the gate dielectric layer.

[0024] In some embodiments, by placing a portion of the body region below the bottom of the trench and separating the bottom of the trench from the portion of the body region by the drift region, the electric field distribution near the bottom and corners of the trench is adjusted, and the problem of damage to the gate dielectric layer due to excessive electric field concentration at the bottom and corners of the trench is alleviated.

[0025] In some embodiments, the channel drain region, the first portion of the body region, and the source region are sequentially disposed adjacent to the first sidewall of the same trench in the vertical direction, thereby controlling the channel length through the position of the channel drain region, improving the uniformity of the channel length, the uniformity of the overlap between the channel and the drain region, and the uniformity of the concentration of the drain region, thereby improving the overall performance of the device.

[0026] In some embodiments, the second portion of the body region is divided into a first sub-region and a second sub-region in the horizontal direction, and the first portion of the body region, the first sub-region, and the second sub-region are adjacent to each other in sequence. The distance from the bottom edge of the first sub-region to the first surface is adjusted so that the distance from the first sidewall of the trench to the body region gradually increases in the direction from the first surface to the second surface. In the on-state of the device, after current flows through the source region and the channel, the current path to the second surface gradually becomes wider, thereby reducing the on-resistance and further improving the performance of the device.

[0027] In some embodiments, the gate dielectric layer extends from the interior surface of the trench to the first surface of the semiconductor layer, protecting a portion of the buffer layer located on the first surface of the semiconductor layer adjacent to the trench.

[0028] It is to be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. [Brief explanation of the drawings]

[0029] In the following, in order to more clearly explain the technical solutions of the embodiments of the present disclosure, drawings of the embodiments will be briefly described. It should be obvious that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0030] [Figure 1] 1 is a schematic perspective view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line AA in FIG. [Figure 3] 1A to 1C are schematic cross-sectional views of some stages in a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. [Figure 4] 1A to 1C are schematic cross-sectional views of some stages in a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. [Figure 5] 1A to 1C are schematic cross-sectional views of some stages in a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. [Figure 6] 1A to 1C are schematic cross-sectional views of some stages in a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. [Figure 7] 1A to 1C are schematic cross-sectional views of some stages in a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. [Figure 8] 1A to 1C are schematic cross-sectional views of some stages in a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. [Figure 9] FIG. 10 is a schematic configuration diagram of a semiconductor device according to a second embodiment of the present disclosure. [Figure 10] FIG. 10 is a schematic configuration diagram of a semiconductor device according to a third embodiment of the present disclosure. [Figure 11] FIG. 10 is a schematic configuration diagram of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 12] FIG. 10 is a schematic configuration diagram of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 13] FIG. 10 is a schematic configuration diagram of a semiconductor device according to a sixth embodiment of the present disclosure. [Figure 14] FIG. 12 is a schematic configuration diagram of a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 15] FIG. 13 is a schematic configuration diagram of a semiconductor device according to an eighth embodiment of the present disclosure. [Figure 16] FIG. 13 is a schematic configuration diagram of a semiconductor device according to a ninth embodiment of the present disclosure. [Figure 17] 13A to 13C are schematic cross-sectional views of some stages of a method for manufacturing a semiconductor device according to a ninth embodiment of the present disclosure. [Figure 18] 13A to 13C are schematic cross-sectional views of some stages of a method for manufacturing a semiconductor device according to a ninth embodiment of the present disclosure. [Figure 19] 13A to 13C are schematic cross-sectional views of some stages of a method for manufacturing a semiconductor device according to a ninth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0031] The present disclosure will now be described in more detail with reference to the drawings. In each drawing, like elements are given like reference numerals. For clarity, parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained through several steps may be shown in one drawing.

[0032] When describing the structure of a device, a reference to a layer or region being "on" or "above" another layer or region can refer to a layer or region that is directly on top of the other layer or region, or to a layer or region that is between the other layer or region and the layer or region. Also, when the device is inverted, the layer or region would be "below" or "underneath" the other layer or region.

[0033] To describe cases where a layer or region is directly located on another layer or region, this specification uses phrases such as "directly located on" and "on and adjacent to."

[0034] A power device typically includes an active device region, an edge termination region, and a crackstop or shield region. The active device region includes an array of active devices. The present disclosure relates to active device structures. The dimensions of the active devices vary depending on product requirements, and body regions may exist between the active devices in the active device region.

[0035] In order to provide a clearer understanding of the present disclosure, numerous specific details of the present disclosure are set forth below, such as device structures, materials, dimensions, processing processes, and techniques, etc. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

[0036] Fig. 1 shows a schematic perspective configuration diagram of a semiconductor device according to a first embodiment of the present disclosure, and Fig. 2 shows a schematic cross-sectional view taken along line AA in Fig. 1. Note that Fig. 1 omits a portion of the structure above the buffer layer and the trench gate structure in order to more clearly show the positional relationship between the structures.

[0037] 1 and 2, a semiconductor device according to a first embodiment of the present disclosure includes a semiconductor layer 100, a buffer layer 190, a plurality of trench gate structures 150, an interlayer dielectric layer 160, and a source metal layer 170. The semiconductor layer 100 includes opposing first and second surfaces 10 and 20 and a plurality of trenches 102 extending into the semiconductor layer 100 from the first surface 10 to the second surface 20. The trenches 102 have a first sidewall 102a, a second sidewall 102b, and a bottom surface 102c, where the first sidewall 102a faces the second sidewall 102b. The plurality of trenches 102 extend in the Y-axis direction and are distributed at intervals in the X-axis direction (also considered as the width direction of the trenches 102). Optionally, two of the X-axis, Y-axis, and Z-axis directions (directions from the second surface 20 toward the first surface 10) are perpendicular to each other. Optionally, the X-axis direction is the <11-20> direction or the <1-100> direction, and the planes of the first sidewall 102a and the second sidewall 102b are the (11-20) plane or the (1-100) plane. Multiple trench gate structures 150 are located within corresponding trenches 102, and the extension direction of the trench gate structures 150 is the same as the extension direction of the trenches 102. Here, the semiconductor layer 100 is, for example, a SiC substrate or a stacked structure including a SiC substrate and an epitaxial layer. However, embodiments of the present disclosure are not limited thereto, and a person skilled in the art can set other materials, number of layers, and the like of the semiconductor layer 100 as needed.

[0038] The semiconductor layer 100 includes a drift region 101, a body region 110, a source region 130, a body contact region 140, and a drain contact region 180. Here, the source region 130 and the drift region 101 are of a first conductivity type, the body region 110 and the body contact region 140 are of a second conductivity type, and the doping concentration of the body contact region 140 is greater than the doping concentration of the body region 110. The first conductivity type is opposite to the second conductivity type. The first conductivity type is one of P-type and N-type, and the second conductivity type is the other of P-type and N-type.

[0039] The semiconductor device of this embodiment may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT), and the conductivity type of the drain contact region 180 may be set to correspond to a first conductivity type or a second conductivity type. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may set the conductivity type of each region in the semiconductor layer 100 to other values ​​as needed to operate the semiconductor device as a MOSFET or an IGBT.

[0040] The buffer layer 190 covers the inner surface of the trench 102 and the first surface 100 of the semiconductor layer 100. The buffer layer 190 is a heteroepitaxial layer that is the crystal form of the semiconductor layer 100. Optionally, the semiconductor layer 100 may be a semiconductor layer containing C or Si elements, such as a SiC semiconductor layer, or the semiconductor layer 100 may be a semiconductor layer containing other elements, and the buffer layer 190 may include one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. The heteroepitaxial layer may be another semiconductor crystalline material or a crystalline material with little in-situ doping. The thickness of the buffer layer 190 is at the atomic layer level, for example, the thickness of one atomic layer or two to three atomic layers, thereby preventing a significant barrier to carrier flow.

[0041] The trench gate structure 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 covers a buffer layer 190 located on the inner surface of the trench 102, and the gate conductor 152 is located within the trench 102. The gate dielectric layer 151 is located between the buffer layer 190 and the gate conductor 152 and is used to separate the buffer layer 190 from the gate conductor 152.

[0042] In this embodiment, a buffer layer 190, which is a heteroepitaxial layer of the semiconductor layer 100, is formed on the inner surface of the trench 102 of the semiconductor layer 100 and on the first surface 10 of the semiconductor layer 100. The buffer layer 190 separates the gate dielectric layer 151 from the semiconductor layer 100, and suppresses the formation of carbon clusters in the gate dielectric layer 151.

[0043] The body region 110 includes a first portion 111, a second portion 112, and a third portion 113, which are sequentially connected in the X-axis direction. The first portion 111 is adjacent to a first sidewall 102a of the trench 102, the second portion 112 is adjacent to a second sidewall 102b of the trench 102, and the third portion 113 is located between a bottom surface 102c of the trench 102 and the second surface 20 and is adjacent to the bottom surface 102c. The second portion 112 is substantially flush with an edge of the third portion 113 that extends toward the second surface 20. Optionally, the first portion 111, the second portion 112, and the third portion 113 have different doping concentrations.

[0044] The source region 130 extends from the first surface 10 to the second surface 20 of the semiconductor layer 100. The source region 130 and the drift region 101 are separated along the Z-axis direction by a first portion 111 of the body region 110. Between the two trench gate structures 150, the source region 130 and the first portion 111 are adjacent to the first sidewall 102a of the same trench 102.

[0045] Optionally, between the two trench gate structures 150, the source region 130 extends from the first sidewall 102 a of one trench 102 to the second sidewall 102 b of the other trench 102, so that the source region 130 is adjacent to the second portion 112 of the body region 110. When the junction depth of the source region 130 is deep, increasing the width of the source region 130 helps to reduce the contact diffusion resistance of the source region 130.

[0046] The body contact region 140 extends from the first surface 10 to the second surface 20 of the semiconductor layer 100 and is adjacent to the body region 110. Along the X-axis direction, between two adjacent trench gate structures 150, one end of the body contact region 140 is adjacent to the source region 130 and the other end is adjacent to the second sidewall 102b of the trench 102, but is not connected to the second sidewall 102b, where the body contact region 140 and the second sidewall 102b are separated by the body region 110. Optionally, the body contact region 140 and the source region 130 are separated by the body region 110.

[0047] Optionally, along the Y-axis direction, a portion of the body contact region 140 is adjacent to the second sidewall 102b, and another portion of the body contact region 140 is separated from the second sidewall 102b by the body region 110, leaving a gap therebetween, and along the Y-axis direction, the body contact region 140 and the adjacent and gapped portions of the second sidewall 102b are alternately arranged.

[0048] The gate-to-source capacitance is composed of three components: the capacitance from the gate conductor 152 to the body region 110, the capacitance from the gate conductor 152 to the body contact region 140, and the capacitance from the gate conductor 152 to the source region 130. The source region 130 is electrically connected to the body region 110. The body contact region 140 has a higher doping concentration than the body region 110, resulting in a higher capacitance per unit area. Therefore, the total gate-to-source capacitance can be adjusted by adjusting the area of ​​direct contact of the second sidewall 102b with the body contact region 140. Different applications and system requirements require different ratios of gate charge or gate-to-drain capacitance / (gate-to-drain capacitance + gate-to-source capacitance). For example, during the turn-off process of a hard-switch transistor, the drain voltage suddenly rises, causing gate self-turn-on due to capacitive coupling. If there is insufficient margin for gate self-turn-on, increasing the gate-to-source capacitance can improve it.

[0049] The source metal layer 170 is located on the first surface 100 of the semiconductor layer 100 and adjacent to the buffer layer 190, where the source metal layer 170 is electrically connected to the source region 130, the body region 110, and the body contact region 140 via the buffer layer 190. The interlayer dielectric layer 160 is located between the buffer layer 190 and the source metal layer 170 and is disposed corresponding to the gate structure 150 to separate the source metal layer 170 from the trench gate structure 150. The source metal layer 170 and the interlayer dielectric layer 160 may be a multilayer structure made of different materials. As an example of the multilayer source metal layer 170, the source metal layer 170 includes a tungsten (W) layer coated directly on the buffer layer 190 and an aluminum copper (AlCu) layer coated directly on the tungsten layer. The embodiment also optionally includes portions not shown, such as opening a gate contact region directly above the gate conductor 152 so that the gate conductor 152 is connected to a gate metal layer, the gate contact region being located directly on the gate conductor 152, and the gate conductor 152 being separated from the source metal layer 170 by an interlayer dielectric layer 160.

[0050] At least a portion of the drift region 101 is located between the body region 110 and the second surface 20 and is adjacent to the second portion 112, the third portion 113 of the body region 110, the bottom surface 102c of the trench 102, and the drain contact region 180, respectively, where the drain contact region 180 extends in a direction from the second surface 20 toward the first surface 10 of the semiconductor layer 100.

[0051] The semiconductor device of this embodiment also includes a drain metal layer (not shown) located on the second surface 20 of the semiconductor layer 100 and connected to the drain contact region 180 .

[0052] 3 to 8 are schematic cross-sectional views of some stages in a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure.

[0053] As shown in FIG. 3, a buffer layer 201 is formed on the first surface 10 of the semiconductor layer 100, and after the first doping region 110-1 is formed by an ion implantation process, the buffer layer 201 is removed.

[0054] Furthermore, a buffer layer 202 is formed on the first surface 10 of the semiconductor layer 100, a mask layer 203 is formed on the buffer layer 202, and a plurality of second doped regions 110-2 are formed by an ion implantation process, as shown in Figure 4. Here, the plurality of second doped regions 110-2 are adjacent to the first doped region 110-1, located between the first doped region 110-1 and the second surface 20, and are distributed at intervals in the X-axis direction.

[0055] Furthermore, the buffer layer 202 and the mask layer 203 are removed, and the body region 110 is formed of the first doping region 110-1 and the second doping region 110-2, as shown in FIG.

[0056] 6, a mask layer 204 is formed on the first surface 10 of the semiconductor layer 100, and a plurality of trenches 102 are formed by an etching process. Here, the body region 110 includes a first portion 111, a second portion 112, and a third portion 113 that are adjacent to each other in the X-axis direction. The first portion 111 is adjacent to a first sidewall 102a of the trench 102, the second portion 112 is adjacent to a second sidewall 102b of the trench 102, and the third portion 113 is adjacent to a bottom surface 102c of the trench 102.

[0057] The mask layer 204 is then removed, and a buffer layer 190 is formed on the inner surface of the trench 102 and the first surface 10 of the semiconductor layer 100 by an epitaxial process, as shown in FIG. 7 . The buffer layer 190 is a heteroepitaxial layer of the semiconductor layer 100, and includes one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. The heteroepitaxial layer may be made of other semiconductor crystal materials or a material that is not doped with in situ impurities. In this embodiment, the body region 110 is formed before the buffer layer 190 is formed, so that impurities implanted during the formation of the body region 110 do not remain on the surface of the buffer layer 190, which helps to improve device reliability.

[0058] 8, a gate dielectric layer 151 is formed on the buffer layer 190. Here, the gate dielectric layer 151 is formed, for example, by a thermal oxidation process, during which part of the buffer layer 190 is consumed. After the gate dielectric layer 151 is formed, the buffer layer 190 has a thickness at the atomic level, which can continue to suppress the formation of carbon cluster defects at the interface between the gate dielectric layer and the semiconductor layer, and the thin thickness of the buffer layer 190 does not create a significant barrier to carrier flow. In a subsequent process, the gate dielectric layer 151 located on the first surface 10 is removed.

[0059] FIG. 9 is a schematic diagram of a semiconductor device according to a second embodiment of the present disclosure.

[0060] As shown in FIG. 9 , the same description of the semiconductor device according to the second embodiment of the present disclosure as that of the first embodiment will be omitted here, and reference may be made to the descriptions of FIGS. 1 to 8 . The difference is that in this embodiment, at least a portion of the bottom surface 102c of the trench 102 is separated from the third portion 113 of the body region 110 by the drift region 101 in the Z-axis direction. Optionally, the third portion 113 is adjacent to the bottom surface 102c near the corner between the second sidewall 102b and the bottom surface 102c. Optionally, the third portion 113 and the bottom surface 102c are completely separated by the drift region 101. Optionally, the second portion 112 of the body region 110 and the second sidewall 102b of the trench 102 are separated by the drift region 101.

[0061] In this embodiment, the drift region 101 separates the bottom surface 102c of the trench 102 from the third portion 113 of the body region 110, thereby adjusting the electric field distribution near the bottom and corners of the trench 102 and reducing the problem of damage to the gate dielectric layer 151 due to excessive electric field concentration at the bottom and corners of the trench 102.

[0062] FIG. 10 is a schematic configuration diagram of a semiconductor device according to a third embodiment of the present disclosure.

[0063] 10, the same points as those in the first embodiment of the semiconductor device according to the third embodiment of the present disclosure will not be described here, but the descriptions of FIGS. 1 to 8 may be referred to. The difference is that the semiconductor layer 100 of this embodiment further includes a channel drain region 120 of the first conductivity type, and the doping concentration of the channel drain region 120 is higher than the doping concentration of the drift region 101.

[0064] The channel drain region 120 is located between the first portion 111 of the body region 110 and the drift region 101 such that the source region 130, the first portion 111 of the body region 110, and the channel drain region 120 are adjacent to each other in a direction from the first surface 10 to the second surface 20. Between the two trench gate structures 150, the first portion 111, the channel drain region 120, and the source region 130 are all adjacent to the first sidewall 102a of the same trench 102. The channel drain region 120 is adjacent to the bottom surface 102c of the trench 102 and adjacent to the second portion 112. The channel drain region 120 and the third portion 113 of the body region 110 are separated by the drift region 101. Optionally, the distance from the edge of the channel drain region 120 in a direction toward the second surface 20 to the first surface 10 is equal to or less than the distance from the bottom surface 102c of the trench 102 to the first surface 10. Optionally, the distance from the edge of the channel drain region 120 toward the second surface 20 to the first surface 10 is greater than the distance from the bottom surface 102c of the trench 102 to the first surface 10, and the channel drain region 120 is adjacent to a portion of the bottom surface 102c of the trench 102.

[0065] In this embodiment, when the semiconductor device is in an on-state, the first portion 111 of the body region 110 adjacent to the first sidewall 102a of the trench 102 has an inverted conductivity type, thereby forming a channel. By providing the channel drain region 120 adjacent to the bottom surface 102c of the trench 102, the channel length can be controlled relatively precisely, thereby improving the uniformity of the channel lengths in the semiconductor device. The provision of the channel drain region 120 also improves the uniformity of the overlap between the channel and the drain region and the concentration uniformity in the drain region, thereby improving the overall performance of the device.

[0066] In some specific embodiments, the channel drain region 120 is formed in the same process step as the source region 130 to more precisely control the channel length, further improving the uniformity of the channel length.

[0067] FIG. 11 is a schematic configuration diagram of a semiconductor device according to a fourth embodiment of the present disclosure.

[0068] As shown in FIG. 11 , the description of the same points between the semiconductor device according to the fourth embodiment of the present disclosure and the third embodiment will be omitted here, and reference can be made to the description of FIG. 10 . The difference is that in this embodiment, at least a portion of the bottom surface 102c of the trench 102 is separated from the third portion 113 of the body region 110 by the drift region 101 in the Z-axis direction. Optionally, the third portion 113 is adjacent to the bottom surface 102c near the corner between the second sidewall 102b and the bottom surface 102c. Optionally, the third portion 113 and the bottom surface 102c are completely separated by the drift region 101. Optionally, the second portion 112 of the body region 110 and the second sidewall 102b of the trench 102 are separated by the drift region 101.

[0069] In this embodiment, the drift region 101 separates the bottom surface 102c of the trench 102 from the third portion 113, thereby adjusting the electric field distribution near the bottom and corners of the trench 102 and reducing the problem of damage to the gate dielectric layer 151 due to excessive electric field concentration at the bottom and corners of the trench 102.

[0070] FIG. 12 is a schematic configuration diagram of a semiconductor device according to a fifth embodiment of the present disclosure.

[0071] 12, the same points as those in the semiconductor device according to the fifth embodiment of the present disclosure and the second embodiment will not be described here, but the description of FIG. 9 may be referred to. The difference is that in this embodiment, the second portion 112 of the body region 110 includes a first sub-region 112a and a second sub-region 112b that are connected. Along the X-axis, the first sub-region 112a is adjacent to the first portion 111 of the body region 110, and the second sub-region 112b is adjacent to the third portion 113 of the body region 110.

[0072] The distance from the edge of the first portion 111 in the direction toward the second surface 20 to the first surface 10 is a first distance d1, the distance from the edge of the first sub-region 112a in the direction toward the second surface 20 to the first surface 10 is a second distance d2, and the distance from the edge of the second sub-region 112b in the direction toward the second surface 20 to the first surface 10 is a third distance d3, where the third distance d3 is greater than the second distance d2, and the second distance d2 is greater than the first distance d1.

[0073] In this embodiment, the distance d2 from the bottom edge of the first sub-region 112a to the first surface is adjusted so that the edge of the body region 110 adjacent to the first sidewall 102a is stepped, so that the distance from the first sidewall 102a to the second portion 112 of the body region 110 gradually increases in the direction from the first surface 10 to the second surface 20. In the on-state of the device, after the current flows through the source region 130 and the channel, the path of the current to the second surface 20 gradually becomes wider, thereby reducing the on-resistance and further improving the performance of the device.

[0074] Optionally, the distance from the bottom surface 102c of the trench 102 to the first surface 10 is a fourth distance d4, where the second distance d2 is greater than or equal to the fourth distance d4, thereby reducing the influence of high electric fields on the bottom of the trench 102.

[0075] Optionally, in the Z-axis direction, the distance by which the third portion 111 of the body region 110 and the bottom surface 102c of the trench 102 are separated by the drift region 101 is a fifth distance d5, and the sum of the fourth distance d4 and the fifth distance d5 is equal to the second distance d2, so that the bottom surface 112-1 of the second sub-region 112b is substantially flush with the separation surface 113-1 of the third portion 113 of the body region 110. Therefore, the depth of the second sub-region 112b is controlled to an appropriate extent to avoid limiting the contribution of charge compensation to reducing the turn-on resistance due to the second distance d2 being too large.

[0076] FIG. 13 is a schematic diagram of a semiconductor device according to a sixth embodiment of the present disclosure.

[0077] 13, the semiconductor device according to the sixth embodiment of the present disclosure has the same features as the third embodiment, and therefore the description of FIG. 10 is not repeated here. The difference is that in this embodiment, the second portion 112 of the body region 110 includes a first sub-region 112a and a second sub-region 112b that are connected. Along the X-axis, the first sub-region 112a is adjacent to the first portion 111 of the body region 110, and the second sub-region 112b is adjacent to the third portion 113 of the body region 110.

[0078] The distance from the edge of the first portion 111 in the direction toward the second surface 20 to the first surface 10 is a first distance d1, the distance from the edge of the first sub-region 112a in the direction toward the second surface 20 to the first surface 10 is a second distance d2, and the distance from the edge of the second sub-region 112b in the direction toward the second surface 20 to the first surface 10 is a third distance d3, where the third distance d3 is greater than the second distance d2, and the second distance d2 is greater than the first distance d1.

[0079] In this embodiment, the distance d2 from the bottom edge of the first sub-region 112a to the first surface is adjusted so that the edge of the body region 110 adjacent to the first sidewall 102a is stepped, so that the distance from the first sidewall 102a to the second portion 112 of the body region 110 gradually increases in the direction from the first surface 10 to the second surface 20. In the on-state of the device, after the current flows through the source region 130 and the channel, the path of the current to the second surface 20 gradually becomes wider, thereby reducing the on-resistance and further improving the performance of the device.

[0080] Optionally, the distance from the edge of the channel drain region 120 toward the second surface 20 to the first surface 10 is a sixth distance d6, the sixth distance d6 being greater than the second distance d2, and the third distance d3 being greater than the sixth distance d6, thereby separating some of the channel drain regions 120 and the second sub-regions 112b in the X-axis direction by the drift region 101.

[0081] FIG. 14 is a schematic configuration diagram of a semiconductor device according to a seventh embodiment of the present disclosure.

[0082] As shown in FIG. 14 , the same points as those in the semiconductor device according to the seventh embodiment of the present disclosure and the sixth embodiment will not be described here, but the description of FIG. 13 may be referred to. The difference is that in this embodiment, at least a portion of the bottom surface 102c of the trench 102 is separated from the third portion 113 of the body region 110 by the drift region 101 in the Z-axis direction. Optionally, the third portion 113 is adjacent to the bottom surface 102c near the corner between the second sidewall 102b and the bottom surface 102c. Optionally, the third portion 113 and the bottom surface 102c are completely separated by the drift region 101. Optionally, the second portion 112 of the body region 110 and the second sidewall 102b of the trench 102 are separated by the drift region 101.

[0083] In this embodiment, the drift region 101 separates the bottom surface 102c of the trench 102 from the third portion 113, thereby adjusting the electric field distribution near the bottom and corners of the trench 102 and reducing the problem of damage to the gate dielectric layer 151 due to excessive electric field concentration at the bottom and corners of the trench 102.

[0084] FIG. 15 is a schematic configuration diagram of a semiconductor device according to an eighth embodiment of the present disclosure.

[0085] 15 , the same points as those in the first embodiment of the semiconductor device according to the eighth embodiment of the present disclosure will not be described here, but the descriptions of FIGS. 1 to 8 may be referred to. The difference is that in this embodiment, a portion of the trench gate structure 150 is located within the trench 102, and another portion is located on the first surface 10. Specifically, the gate dielectric layer 151 covers the buffer layer 190 located on the inner surface of the trench 102 and also covers a portion of the buffer layer 190 on the first surface 10 adjacent to the trench 102, and a portion of the gate conductor 152 is located within the trench 102, and another portion extends into the trench 102 to cover the gate dielectric layer 151 located on the first surface 10.

[0086] The trench gate structure 150 of this embodiment extends from inside the trench 102 to above the first surface 10, protecting the first surface 10 and the portion of the buffer layer 190 adjacent to the trench 102 and reducing damage to the first surface 10 and the portion of the buffer layer 190 adjacent to the trench 102 during the manufacturing process.

[0087] Optionally, the semiconductor device according to the eighth embodiment of the present disclosure may be configured such that at least a portion of the bottom surface 102c of the trench 102 is separated in the Z-axis direction from the third portion 113 by the drift region 101, as in the second, fourth, fifth, and seventh embodiments of the present disclosure.

[0088] Optionally, the semiconductor device according to the eighth embodiment of the present disclosure may be provided with a channel drain region 120, as in the third, fourth, sixth and seventh embodiments of the present disclosure.

[0089] Optionally, the semiconductor device according to the eighth embodiment of the present disclosure may be provided with a first sub-region 112a and a second sub-region 112b, as in the fifth, sixth, and seventh embodiments of the present disclosure.

[0090] FIG. 16 is a schematic configuration diagram of a semiconductor device according to a ninth embodiment of the present disclosure.

[0091] 16 , the same points as those in the first embodiment of the semiconductor device according to the ninth embodiment of the present disclosure will not be described here, but reference can be made to the descriptions of FIGS. 1 to 8. The differences are that in this embodiment, the distance from the edge of the first portion 111 of the body region 110 toward the second surface 20 to the first surface 10 is d1, the distance from the edge of the second portion 112 of the body region 110 toward the second surface 20 to the first surface 10 is d7, the distance from the edge of the third portion 113 of the body region 110 toward the second surface 20 to the first surface 10 is d8, and the distance from the bottom surface 102c of the trench 102 to the first surface 10 is d4, where d8>d7>d4>d1.

[0092] In this embodiment, the third portion 113 plays a role in charge compensation, and increasing the depth of the third portion 113 (increasing the distance d8) can improve the breakdown voltage of the device.

[0093] Optionally, the semiconductor device according to the ninth embodiment of the present disclosure may have at least a portion of the bottom surface 102c of the trench 102 separated in the Z-axis direction from the third portion 113 by the drift region 101, as in the second, fourth, fifth, and seventh embodiments of the present disclosure.

[0094] Optionally, the semiconductor device according to the ninth embodiment of the present disclosure may be provided with a channel drain region 120 as in the third, fourth, sixth, and seventh embodiments of the present disclosure.

[0095] Optionally, the semiconductor device according to the ninth embodiment of the present disclosure may be provided with a trench gate structure 150 as in the eighth embodiment of the present disclosure.

[0096] 17 to 19 are schematic cross-sectional views of some stages in a method for manufacturing a semiconductor device according to a ninth embodiment of the present disclosure.

[0097] 3 and the text description, first doping region 110-1 is formed by an implantation process, then a mask layer 301 is formed on first surface 10 of semiconductor layer 100, and a plurality of trenches 102 are formed by an etching process, as shown in FIG. 17. Then, mask layer 301 is removed.

[0098] Furthermore, a mask layer 302 is formed on the first surface 100 of the semiconductor layer 100 and in the trench 102, and a second doping region 110-2 is formed by an implantation process, as shown in Figure 18. Then, the mask layer 302 is removed.

[0099] 19, a buffer layer 190 is formed on the inner surface of the trench 102 and on the first surface 10 of the semiconductor layer 100 by an epitaxial process. Here, the buffer layer 190 is a heteroepitaxial layer of the semiconductor layer 100, and includes one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. The heteroepitaxial layer may be other semiconductor crystalline materials or materials that are hardly doped with in situ impurities.

[0100] In this embodiment, the second doping region 110-2 is formed after the trench 102 is formed, so the depth of the third portion 113 of the body region 110 can be more easily increased due to the structure of the trench 102. The body region 110 is formed before the buffer layer 190 is formed, so impurities implanted when forming the body region 110 do not remain on the surface of the buffer layer 190, which helps to improve the reliability of the device.

[0101] The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. 1. A semiconductor device comprising: a semiconductor layer having opposing first and second surfaces; a trench gate structure; and a buffer layer, wherein at least a portion of the trench gate structure is located in a trench in the first surface of the semiconductor layer; Here, the semiconductor layer is a source region extending in a direction from the first surface toward the second surface; a drift region and a body region, at least a portion of the drift region being located between the body region and the second surface of the semiconductor layer; a first portion of the body region is located between the source region and the drift region along a direction from the first surface toward the second surface, and both the first portion of the body region and the source region are adjacent to a first sidewall of the trench; wherein the buffer layer is a heteroepitaxial layer of the semiconductor layer, the buffer layer covers an inner surface of the trench and a first surface of the semiconductor layer, and the buffer layer is located between a gate dielectric layer of the trench gate structure and the semiconductor layer; A semiconductor device, wherein the source region and the drift region are of a first conductivity type, and the body region is of a second conductivity type, the first conductivity type being opposite to the second conductivity type.

2. The semiconductor device of claim 1 , wherein the semiconductor layer comprises a SiC semiconductor layer, and the buffer layer comprises one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer.

3. The semiconductor device of claim 1 , wherein the buffer layer has a thickness of one or more atomic layers.

4. the first portion, the second portion, and the third portion of the body region are adjacent to each other in sequence along a width direction of the trench gate structure; the first and second portions of the body region are located between two of the trench gate structures, the first portion is adjacent to a first sidewall of the trench, the second portion is adjacent to a second sidewall of the trench, and the first sidewall and the second sidewall face each other; the third portion and the second portion are adjacent to the same trench, and the third portion is located between a bottom surface of the trench and the second surface, and the third portion and the first portion are separated by the drift region; The semiconductor device of claim 1 , wherein the second portion is adjacent to the second sidewall, or the second portion and the second sidewall are separated by the drift region.

5. a third portion of the body region extending from a bottom surface of the trench toward the second surface; or The semiconductor device of claim 4 , wherein at least a portion of a bottom surface of the trench and a third portion of the body region are separated from each other by the drift region along a direction from the first surface toward the second surface.

6. the second portion of the body region includes a first sub-region and a second sub-region that are connected; Along a width direction of the trench gate structure, the first sub-region is adjacent to a first portion of the body region, and the second sub-region is adjacent to a third portion of the body region; wherein a distance from an edge of the first portion of the body region in a direction toward the second surface to the first surface is a first distance, a distance from an edge of the first sub-region in a direction toward the second surface to the first surface is a second distance, and a distance from an edge of the second sub-region in a direction toward the second surface to the first surface is a third distance; The semiconductor device of claim 5 , wherein the third distance is greater than the second distance, and the second distance is greater than the first distance.

7. The semiconductor device of claim 6 , wherein a distance from a bottom surface of the trench to the first surface is a fourth distance, and the second distance is greater than or equal to the fourth distance.

8. a fourth distance from a bottom surface of the trench to the first surface along a direction from the second surface to the first surface, and a fifth distance between the third portion of the body region and the bottom surface of the trench by the drift region; The semiconductor device of claim 6 , wherein the sum of the fourth distance and the fifth distance is equal to the second distance.

9. The edges of the second and third portions of the body region facing the second surface are connected, or The semiconductor device according to any one of claims 4 to 8, wherein an edge of the third portion facing the second surface is closer to the second surface than an edge of the second portion facing the second surface.

10. the semiconductor layer further includes a channel drain region located between the first portion of the body region and the drift region, whereby the source region, the first portion of the body region, and the channel drain region are adjacent to each other in a direction from the first surface to the second surface, and are all adjacent to a first sidewall of the trench; the channel drain region is further adjacent to the drift region and the second portion of the body region, and the channel drain region and the third portion of the body region are separated by the drift region; A semiconductor device according to any one of claims 1 to 8, wherein the channel drain region is of the first conductivity type.

11. The semiconductor device of claim 10 , wherein a doping concentration of the channel drain region is greater than a doping concentration of the drift region.

12. The distance from the edge of the channel drain region toward the second surface to the first surface is not greater than the distance from the bottom of the trench to the first surface, or 11. The semiconductor device of claim 10, wherein a distance from an edge of the channel drain region toward the second surface to the first surface is greater than a distance from a bottom surface of the trench to the first surface, and the channel drain region is adjacent to a portion of the bottom surface of the trench.

13. the semiconductor layer further includes a channel drain region located between the first portion of the body region and the drift region, whereby the source region, the first portion of the body region, and the channel drain region are adjacent to each other in sequence along a direction from the first surface to the second surface, and are all adjacent to a first sidewall of the trench; the channel drain region is further adjacent to the drift region and the second portion of the body region, and the channel drain region and the third portion of the body region are separated by the drift region; wherein the channel drain region is of a first conductivity type; a distance from an edge of the channel drain region toward the second surface to the first surface is a sixth distance; 7. The semiconductor device of claim 6, wherein the sixth distance is greater than the second distance and the third distance is greater than the sixth distance, such that the channel drain region and the second sub-region are separated by the drift region along a width direction of the trench gate structure.

14. the semiconductor layer further includes a body contact region extending in a direction from the first surface toward the second surface, the body contact region being adjacent to the body region; the body contact region is adjacent to the source region or separated by the body region; The semiconductor device of any one of claims 1 to 8, wherein the body contact region is of the second conductivity type.

15. a portion of the body contact region is adjacent to a second sidewall of the trench along an extension direction of the trench gate structure, and a gap is formed between another portion of the body contact region and the second sidewall, and the adjacent portion of the body contact region and the second sidewall and the portion having the gap are alternately provided along an extension direction of the trench gate structure; Alternatively, the body contact region and the second sidewall are both separated by the body region.

16. the trench gate structure includes the gate dielectric layer and a gate conductor; the gate dielectric layer covers the buffer layer located on the inner surface of the trench and a portion of the buffer layer located on the first surface adjacent to the trench, the trench extending in a direction from the first surface toward the second surface; a portion of the gate conductor located in the trench and another portion extending out of the trench and covering the gate dielectric layer; 9. The semiconductor device of claim 1, wherein the gate dielectric layer is located between the gate conductor and the buffer layer to separate the gate conductor and the buffer layer.

17. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is a metal-oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

18. 9. The semiconductor device of claim 4, wherein the source region extends between the two trench gate structures in a direction from a first sidewall of one of the trenches to a second sidewall of the other of the trenches and is adjacent to a second portion of the body region.

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