Class-d amplifier circuit

Abstract

To reduce distortion contained in an output signal while reducing application cost by incorporating an externally arranged current limiting resistor.SOLUTION: A class-D amplifier circuit includes: a first input terminal and a second input terminal to which a 3-value PWM signal can be inputted; and a first output terminal and a second output terminal to which a capacitive load is connected. The class-D amplifier circuit further includes: a first class-D driver circuit having a first driver output terminal capable of changeover based on a signal level at the first input terminal; and a second class-D driver circuit having a second driver output terminal capable of changeover based on a signal level at the second input terminal. A first current limiting resistor is connected between the first driver output terminal and the first output terminal, and a second current limiting resistor is connected between the second driver output terminal and the second output terminal. Changeover state of a first switch connected to the first current limiting resistor in parallel and the second switch connected to the second current limiting resistor in parallel are controlled so that an applied voltage to the capacitive load becomes the power supply voltage or less, based on the first signal level and the second signal level.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a class D amplifier circuit. [Background technology]

[0002] In recent years, in order to achieve both low cost and low power consumption in audio applications, development of audio applications using class D amplifier circuits that drive capacitive loads for audio applications such as piezo buzzers has been progressing (see, for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 6,262,632 [Patent Document 2] U.S. Patent No. 6,087,863 Summary of the Invention [Problem to be solved by the invention]

[0004] Here, a reference technique related to a class D amplifier circuit for driving a capacitive load will be described with reference to Fig. 10 and Fig. 11. Fig. 10 is a circuit configuration diagram of a class D amplifier circuit 1' according to a first reference technique, and Fig. 11 is an example showing temporal changes in signal levels at the first input terminal IN1 and the second input terminal IN2 of Fig. 10.

[0005] The class D amplifier circuit 1' includes a first input terminal IN1, a second input terminal IN2, a first output terminal OUT1, a second output terminal OUT2, and a power supply terminal VDD. A ternary PWM signal is input to the first input terminal IN1 and the second input terminal IN2 from an external signal source (not shown). The signal levels of the first input terminal IN1 and the second input terminal IN2 transition as shown in FIG. 11, for example. The first output terminal OUT1 and the second output terminal OUT2 are connected to both ends of a capacitive load CLOAD via a first current limiting resistor R1 and a second current limiting resistor R2, which are external resistors, respectively. A predetermined power supply voltage Vs is connected to the power supply terminal VDD.

[0006] The class D amplifier circuit 1' has a first class D driver circuit DD1 and a second class D driver circuit DD2, each having a sufficiently small output resistance. The first class-D driver circuit DD1 includes a first driver input terminal connected to the first input terminal IN1, a first driver output terminal connected to the first output terminal OUT1, a first pre-driver circuit PD1 operable in accordance with the signal level of the first driver input terminal, and a first driver switching circuit DSW1 whose connection state can be switched by the first pre-driver circuit PD1. The first pre-driver circuit PD1 switches the first driver switching circuit DSW1 so that when the signal level input to the first driver input terminal is H level, the first output terminal OUT1 is connected to the power supply terminal VDD, and when the signal level input to the first driver input terminal is L level, the first output terminal OUT1 is connected to the ground potential Vg. The second class-D driver circuit DD2 includes a second driver input terminal connected to the second input terminal IN2, a second driver output terminal connected to the second output terminal OUT2, a second pre-driver circuit PD2 operable in accordance with the signal level of the second driver input terminal, and a second driver switching circuit DSW2 whose connection state can be switched by the second pre-driver circuit PD2. The second pre-driver circuit PD2 switches the second driver switching circuit DSW2 so that when the signal level input to the second driver input terminal is H level, the second output terminal OUT2 is connected to the power supply terminal VDD, and when the signal level input to the second driver input terminal is L level, the second output terminal OUT2 is connected to the ground potential Vg.

[0007] An ESD protection element ESD1 made of a diode is provided at a first node N1 provided between the first driver output terminal and the first output terminal OUT1, between the power supply terminal VDD and the ground potential Vg. Also, an ESD protection element ESD2 made of a diode is provided at a second node N2 provided between the second driver output terminal and the second output terminal OUT2, between the power supply terminal VDD and the ground potential Vg.

[0008] Here, let us assume that the capacitive load CLOAD is set to the carrier frequency f PWM When directly driven by a PWM signal with capacitance C LOAD A capacitive load CLOAD with a large current consumption I SUP is playing. I SUP =2C LOAD ×V S ×f PWM (1) 10, a first current limiting resistor R1 and a second current limiting resistor R2 are provided between the first output terminal OUT1 and the second output terminal OUT2 and both ends of the capacitive load CLOAD, respectively. The first current limiting resistor R1 and the second current limiting resistor R2, together with the capacitive load CLOAD, form a low-pass filter, and the cutoff frequency of this low-pass filter is calculated by the following equation: PWM It is designed to be a value that is sufficiently smaller than f PWM ≫1 / (2πC LOAD (R1+R2)) (2)

[0009] In this way, the class D amplifier circuit 1' generates an excessive current consumption I SUP To prevent this, a first current-limiting resistor R1 and a second current-limiting resistor R2 are provided. However, these first current-limiting resistor R1 and second current-limiting resistor R2 are external resistors disposed outside the terminals of the class-D amplifier circuit 1', which increases the number of peripheral components, i.e., increases application costs. Therefore, a class-D amplifier circuit incorporating these external resistors, the first current-limiting resistor R1 and the second current-limiting resistor R2, is desired.

[0010] In response to such demands, a class D amplifier circuit 1" according to a second reference technology has been devised, which has been improved so that the first current limiting resistor R1 and the second current limiting resistor R2 configured as external elements in Fig. 10 are built-in. Fig. 12 is a circuit configuration diagram of the class D amplifier circuit 1" according to the second reference technology, and Fig. 13 shows an example of the first output terminal OUT1, the second output terminal OUT2, and the temporal change in the potential difference between these terminals in the circuit configuration example of Fig. 12.

[0011] Generally, ESD rules in semiconductor processes require that the ESD protection elements ESD1 and ESD2 be placed as close as possible to the first output terminal OUT1 and the second output terminal OUT2. Therefore, in the circuit configuration example of Fig. 12, the first current limiting resistor R1 and the second current limiting resistor R2 are built in so as to be placed between the first driver output terminal of the first class D driver circuit DD1 and the first node N1, and between the second driver output terminal of the second class D driver circuit DD2 and the second node N2, respectively.

[0012] In this circuit configuration example in which the first current limiting resistor R1 and the second current limiting resistor R2 are built in taking ESD rules into consideration, the charge of the capacitive load CLOAD is unintentionally discharged by the diodes that make up the ESD protection elements ESD1 and ESD2. As a result, the output signal (the potential difference between the first output terminal OUT1 and the second output terminal OUT2) applied to the capacitive load CLOAD has a triangular waveform as shown in Figure 13, causing distortion and degrading sound quality.

[0013] At least one embodiment of the present disclosure has been made in consideration of the above circumstances, and aims to provide a class D amplifier circuit that can reduce distortion contained in an output signal while reducing application costs by incorporating an external current limiting resistor. [Means for solving the problem]

[0014] In order to solve the above problem, a class D amplifier circuit according to at least one embodiment of the present disclosure comprises: a first input terminal and a second input terminal to which a ternary PWM signal can be input; a first output terminal and a second output terminal to which both ends of a capacitive load are respectively connected; a first class D driver circuit having a first driver output terminal switchable to a power supply voltage or a ground voltage based on a first signal level of the first input terminal; a second class D driver circuit having a second driver output terminal switchable to the power supply voltage or the ground voltage based on a second signal level of the second input terminal; a first current limiting resistor connected between the first driver output terminal and the first output terminal; a second current limiting resistor connected between the second driver output terminal and the second output terminal; a first switch connected in parallel to the first current limiting resistor; a second switch connected in parallel to the second current limiting resistor; a control unit that controls the switching states of the first switch and the second switch based on the first signal level and the second signal level so that the voltage applied to the capacitive load is equal to or lower than the power supply voltage; Equipped with. [Effects of the Invention]

[0015] According to at least one embodiment of the present disclosure, it is possible to provide a class D amplifier circuit that can reduce distortion contained in an output signal while reducing application costs by incorporating an external current limiting resistor. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a circuit configuration diagram of a class D amplifier circuit according to an embodiment. [Figure 2] 2 is an example of temporal changes in the signal level of the first input terminal, the signal level of the second input terminal, and the potential difference between the first output terminal and the second output terminal when pulse waveforms are input to the first input terminal and the second input terminal of FIG. [Figure 3] 1. This is an example of the change over time in the output voltage levels of the first and second output terminals and the potential difference between the first and second output terminals when a ternary PWM modulated sinusoidal waveform is input to the first and second input terminals of FIG. [Figure 4] FIG. 2 is a circuit diagram showing the switching state of each component in the class D amplifier circuit of FIG. 1 when the first signal level and the second signal level are both L level and the electric potential of the second output terminal is higher than the electric potential of the first output terminal due to the electric charge accumulated in the capacitive load. [Figure 5] FIG. 10 is a circuit configuration diagram of a class-D amplifier circuit 1B according to another embodiment. [Figure 6] 6 is an example showing the signal levels at the first input terminal IN1 and the second input terminal IN2 of FIG. 5 and the change over time of the second control signal. [Figure 7]6 is a circuit diagram showing the switching state of each component in the class D amplifier circuit of FIG. 5 when the first signal level and the second signal level are both L level and the electric potential of the second output terminal is higher than the electric potential of the first output terminal due to the electric charge accumulated in the capacitive load. [Figure 8] FIG. 10 is a circuit configuration diagram of a class D amplifier circuit according to another embodiment. [Figure 9] 9 is an example showing temporal changes in the signal levels at the first input terminal and the second input terminal, the second control signal, and the third control signal in FIG. 8. [Figure 10] FIG. 1 is a circuit configuration diagram of a class-D amplifier circuit according to a first reference technique. [Figure 11] 11 is an example showing temporal changes in signal levels at the first input terminal and the second input terminal of FIG. 10. [Figure 12] FIG. 10 is a circuit configuration diagram of a class-D amplifier circuit according to a second reference technique. [Figure 13] 13 is a diagram illustrating an example of temporal changes in a first output terminal, a second output terminal, and a potential difference between these terminals in the circuit configuration example of FIG. 12. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, several embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the dimensions, materials, shapes, relative arrangements, etc. of the configurations described as embodiments or shown in the drawings are merely illustrative examples and are not intended to limit the scope of the present disclosure.

[0018] FIG. 1 is a circuit diagram of a class D amplifier circuit 1A according to one embodiment, FIG. 2 is an example of the change over time in the signal level of the first input terminal IN1, the signal level of the second input terminal IN2, and the potential difference between the first output terminal OUT1 and the second output terminal OUT2 when pulse waveforms are input to the first input terminal IN1 and the second input terminal IN2 of FIG. 1, and FIG. 3 is an example of the change over time in the output voltage level of the first output terminal OUT1 and the second output terminal OUT2, and the potential difference between the first output terminal OUT1 and the second output terminal OUT2 when PWM signals that output sine waveforms are input to the first input terminal IN1 and the second input terminal IN2 of FIG. 1.

[0019] In the following description, the same reference numerals will be used to designate components corresponding to those in the respective reference technologies described above with reference to FIGS. 10 to 13, and overlapping descriptions will be omitted as appropriate.

[0020] The first current-limiting resistor R1 is connected between the first driver output terminal and the first output terminal OUT1 of the first class-D driver circuit DD1. The second current-limiting resistor R2 is connected between the second driver output terminal and the second output terminal OUT2 of the second class-D driver circuit DD2. That is, the first current-limiting resistor R1 and the second current-limiting resistor R2, which are configured as external resistors in the first reference technology shown in Fig. 10, are configured as internal resistors built into the circuit in the class-D amplifier circuit 1A.

[0021] The ESD protection element ESD1 is provided between the power supply terminal VDD and the ground potential Vg at a first node N1 provided between the first current limiting resistor R1 and the first output terminal OUT1. The ESD protection element ESD2 is provided between the power supply terminal VDD and the ground potential Vg at a second node N2 provided between the second current limiting resistor R2 and the second output terminal OUT2. In this way, the ESD protection elements ESD1 and ESD2 have a configuration in which the first current limiting resistor R1 and the second current limiting resistor R2 are built in while satisfying the ESD rule in semiconductor processes that requires them to be located as close as possible to the first output terminal OUT1 and the second output terminal OUT2, respectively.

[0022] The class D amplifier circuit 1A includes a first switch SW1 connected in parallel to a first current-limiting resistor R1, a second switch SW2 connected in parallel to a second current-limiting resistor R2, and a control unit 10 that controls the switching states of the first switch SW1 and the second switch SW2. The first switch SW1 is switchable between an ON state and an OFF state based on a first control signal S1a from the control unit 10. When the first switch SW1 is in an ON state, the first driver output terminal of the first class D driver circuit DD1 is shorted to the first output terminal OUT1. On the other hand, when the first switch SW1 is in an OFF state, the first driver output terminal of the first class D driver circuit DD1 is connected to the first output terminal OUT1 via the first current-limiting resistor R1. The second switch SW2 is switchable between an ON state and an OFF state based on a first control signal S1b from the control unit 10. When the second switch SW2 is in an ON state, the second driver output terminal of the second class D driver circuit DD2 is shorted to the second output terminal OUT2. On the other hand, when the second switch SW2 is in the off state, the second driver output terminal of the second class-D driver circuit DD2 is connected to the second output terminal OUT2 via the second current limiting resistor R2.

[0023] The control unit 10 is a control unit of the class-D amplifier circuit 1A, and is configured as an electronic calculation device. The control unit 10 includes a polarity determination unit 12 and a first control signal generation unit 14.

[0024] The polarity determination unit 12 is configured to determine the polarity of the charge accumulated in the capacitive load CLOAD based on a first signal level at the first input terminal IN1 and a second signal level at the second input terminal IN2. Specifically, the polarity determination unit 12 determines whether the polarity of the charge accumulated on the first output terminal OUT1 side and the second output terminal OUT2 side of the capacitive load CLOAD is positive or negative, respectively, based on whether the first signal level and the second signal level are H level or L level, respectively. The relationship between the first signal level and the second signal level and the polarity of the charge accumulated in the capacitive load CLOAD is specified in advance, for example, by design or testing. The polarity determination unit 12 can determine the polarity of the charge accumulated in the capacitive load CLOAD by applying the first signal level actually applied to the first input terminal IN1 and the second signal level actually applied to the second input terminal IN2 to this relationship.

[0025] The first control signal generating unit 14 is configured to generate first control signals S1a and S1b for switching the first switch SW1 and the second switch SW2, respectively, based on the polarity of the charge accumulated in the capacitive load CLOAD determined by the polarity determining unit 12. The first control signals S1a and S1b are generated based on a first signal level and a second signal level so that the voltage applied to the capacitive load CLOAD is equal to or lower than the power supply voltage Vs.

[0026] When the first signal level and the second signal level are both H level, the first control signals S1a and S1b are generated to switch on the first switch SW1 or the second switch SW2 whose polarity is determined to be positive by the polarity determination unit 12, and to switch off the switch whose polarity is determined to be negative by the polarity determination unit 12. In the example shown in FIG. 1 , when the first signal level and the second signal level are both H level, the polarity of the capacitive load CLOAD on the first output terminal OUT1 side is determined to be negative, and the first control signal S1a switches the first switch SW1 to the OFF state. At this time, in the first class D driver circuit DD1, the first pre-driver circuit PD1, whose input level is H level, switches the first driver switching circuit DSW1 so that the first driver output terminal is connected to the power supply terminal VDD. Therefore, an output voltage obtained by dropping the power supply voltage Vs applied to the power supply terminal VDD by the first current limiting resistor R1 is output from the first output terminal OUT1. In the example shown in FIG. 1, the polarity of the capacitive load CLOAD on the second output terminal OUT2 side is determined to be positive, and the second switch SW2 is switched on by the first control signal S1b. At this time, in the second Class D driver circuit DD2, the second pre-driver circuit PD2, whose input level is H, switches the second switch SW2 so that the second driver output terminal is connected to the power supply terminal VDD. Therefore, at the second output terminal OUT2, the power supply voltage Vs applied to the power supply terminal VDD is output directly to the second output terminal OUT2 without passing through the second current-limiting resistor R2. At this time, as shown in FIG. 2, the potential difference between the voltage applied to the first output terminal OUT1 and the voltage applied to the second output terminal OUT2 is applied to the capacitive load CLOAD, but this value is less than the power supply voltage Vs.

[0027] FIG. 1 shows the switching states of each configuration when the first signal level and the second signal level are both H level, while FIG. 4 shows the switching states of each configuration when the first signal level and the second signal level are both L level.

[0028] When the first signal level and the second signal level are both L, the first control signals S1a and S1b are generated to switch off the first switch SW1 or the second switch SW2 whose polarity is determined to be positive by the polarity determination unit 12, and to switch on the switch whose polarity is determined to be negative by the polarity determination unit 12. In the example shown in FIG. 4, when the first signal level and the second signal level are both L, the polarity of the capacitive load CLOAD on the first output terminal OUT1 side is determined to be negative, and the first control signal S1a switches the first switch SW1 to the ON state. At this time, in the first class D driver circuit DD1, the first pre-driver circuit PD1, whose input level is L, switches the first driver switching circuit DSW1 so that the first driver output terminal is connected to ground potential Vg. Therefore, the first output terminal OUT1 is set to ground potential Vg without passing through the first current limiting resistor R1. In the example shown in FIG. 4, the polarity of the capacitive load CLOAD on the second output terminal OUT2 side is determined to be positive, and the second switch SW2 is switched to the off state by the first control signal S1b. At this time, in the second Class D driver circuit DD2, the second pre-driver circuit PD2, whose input level is low, switches the second switch SW2 so that the second driver output terminal is connected to the ground potential Vg. Therefore, an output voltage obtained at the second output terminal OUT2 is obtained by increasing the ground potential Vg by the second current-limiting resistor R2. At this time, as shown in FIG. 2, the potential difference between the applied voltage at the first output terminal OUT1 and the applied voltage at the second output terminal OUT2 is applied to the capacitive load CLOAD, but this value is less than the power supply voltage Vs.

[0029] When the first signal level and the second signal level are different from each other, the first control signals S1a and S2b are generated to switch one of the first switch SW1 and the second switch SW2 to the on state and to switch the other to the off state.

[0030] In this way, in the class-D amplifier circuit 1A, the charge of the capacitive load CLOAD does not unintentionally discharge due to the diodes that make up the ESD protection elements ESD1 and ESD2, and an output waveform having an undistorted sine wave is obtained, as shown in Figure 3. Therefore, by incorporating the first current limiting resistor R1 and the second current limiting resistor R2, it is possible to reduce application costs and realize a class-D amplifier circuit that is capable of producing high-quality audio output by reducing distortion contained in the output signal.

[0031] The control unit 10 may control the switching of the first switch SW1 and the second switch SW2 so that the resistance value connected to the capacitive load CLOAD is constant. In this case, the first current limiting resistor R1 and the second current limiting resistor R2 have the same resistance value, and the control unit 10 can control the switching states so that the first switch SW1 and the second switch SW2 are not simultaneously in the on state or the off state. As a result, the resistance value connected to the capacitive load CLOAD is constant, and the cutoff frequency fc of the low-pass filter formed by the first current limiting resistor R1, the second current limiting resistor R2, and the capacitive load CLOAD is always constant as shown in the following equation, thereby minimizing distortion during demodulation of the PWM signal. fc=1 / (2πCLOAD·R) (3)

[0032] Next, a class-D amplifier circuit 1B according to another embodiment will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a circuit configuration diagram of the class-D amplifier circuit 1B according to another embodiment, and Fig. 6 is an example showing the signal levels at the first input terminal IN1 and the second input terminal IN2 of Fig. 5 and the temporal changes of the second control signals S2a and S2b.

[0033] The class D amplifier circuit 1B includes a third class D driver circuit DD3 as the first switch SW1 included in the above-described class D amplifier circuit 1A, and a fourth class D driver circuit DD4 as the second switch SW2 included in the above-described class D amplifier circuit 1A. That is, the class D amplifier circuit 1B has a configuration in which the first switch SW1 and the second switch SW2 in the class D amplifier circuit 1A are realized by other class D amplifier circuits.

[0034] The third-class-D driver circuit DD3 is configured to be switchable between a high-impedance state in which the impedance with respect to the first node N1 is high and a low-impedance state, based on a second control signal S2a from the control unit 10. Specifically, the third-class-D driver circuit DD3 includes a third driver input terminal connected to the first input terminal IN1, a third driver output terminal connected to the first node N1, a third pre-driver circuit PD3 operable in accordance with the signal level of the third driver input terminal, and a third driver switching circuit DSW3 whose connection state can be switched by the third pre-driver circuit PD3.

[0035] The fourth class D driver circuit DD4 is configured to be able to switch between a high impedance state in which the impedance with respect to the second node N2 is high and a low impedance state, based on a second control signal S2b from the control unit 10. Specifically, the fourth class D driver circuit DD4 includes a fourth driver input terminal connected to the second input terminal IN2, a fourth driver output terminal connected to the second node N2, a fourth pre-driver circuit PD4 operable in accordance with the signal level of the fourth driver input terminal, and a fourth driver switching circuit DSW4 whose connection state can be switched by the fourth pre-driver circuit PD4.

[0036] In this embodiment, the control unit 10 further includes a second control signal generation unit 16. The second control signal generation unit 16 is configured to generate second control signals S2a and S2b based on the polarity determined by the polarity determination unit 12.

[0037] 5, when the first signal level and the second signal level are both H level, the polarity of the capacitive load CLOAD on the first output terminal OUT1 side is determined to be negative, and the third-class D driver circuit DD3 is switched to a high-impedance state by the second control signal S2a. On the other hand, the polarity of the capacitive load CLOAD on the second output terminal OUT2 side is determined to be positive, and the fourth-class D driver circuit DD4 is switched to a low-impedance state by the second control signal S2b.

[0038] FIG. 5 shows the switching states of each configuration when the first signal level and the second signal level are both H level, while FIG. 7 shows the switching states of each configuration when the first signal level and the second signal level are both L level.

[0039] When the first signal level and the second signal level are both L level, the polarity of the capacitive load CLOAD on the second output terminal OUT2 side is determined to be positive, and the third class-D driver circuit DD3 is switched to a low-impedance state by the second control signal S2a. On the other hand, the polarity of the capacitive load CLOAD on the first output terminal OUT1 side is determined to be negative, and the fourth class-D driver circuit DD4 is switched to a high-impedance state by the second control signal S2b.

[0040] When the first signal level and the second signal level are different from each other, the second control signals S2a and S2b are generated to switch one of the third class D driver circuit DD3 and the fourth class D driver circuit DD4 to the high impedance state.

[0041] In this way, in the class D amplifier circuit 1B, the first switch SW1 and the second switch SW2 in the class D amplifier circuit 1A can be replaced by the third class D driver circuit DD3 and the fourth class D driver circuit DD4, respectively, to achieve an equivalent configuration with an efficient layout.

[0042] In this type of class-D amplifier circuit, capacitance elements C1 and C2 may be provided between the first output terminal OUT1 and the second output terminal OUT2 and ground potential, respectively, to counter axial radiation noise. In this case, a first time constant τ1 is generated by the output resistance of the first output terminal OUT1 and the capacitance element C1, and a second time constant τ2 is generated by the output resistance of the second output terminal OUT2 and the capacitance element C2. If the signal levels of the first input terminal IN1 and the second input terminal IN2 are different from each other, a mismatch between the first time constant τ1 and the second time constant τ2 may occur when either input terminal transitions logic, resulting in distortion of the output signal and a deterioration in the quality of the reproduced audio. The class-D amplifier circuit 1C described below can effectively solve this problem.

[0043] FIG. 8 is a circuit diagram of a class D amplifier circuit 1C according to another embodiment, and FIG. 9 is an example showing the signal levels at the first input terminal IN1 and the second input terminal IN2 of FIG. 8, the second control signals S2a and S2b, and the third control signal S3 over time.

[0044] Compared to the above-described class D amplifier circuit 1B, the class D amplifier circuit 1C further includes a first capacitance element C1, a second capacitance element C2, a third current limiting resistor R3, a fourth current limiting resistor R4, a fifth class D driver circuit DD5, and a sixth class D driver circuit DD6.

[0045] The first capacitance element C1 is connected between the first output terminal OUT1 and the ground potential to counter axial radiation noise, etc. The second capacitance element C2 is connected between the second output terminal OUT2 and the ground potential to counter axial radiation noise, etc.

[0046] The third current limiting resistor R3 is connected between the first current limiting resistor R1 and the first node N1, and the fourth current limiting resistor R4 is connected between the second current limiting resistor R2 and the second node N2.

[0047] The fifth class D driver circuit DD5 is configured to be able to switch between a low impedance state in which the fifth driver output terminal is connected to the third node N3 and a high impedance state in which the fifth driver output terminal is not connected to the third node N3, based on a third control signal S3 from the control unit 10. Specifically, the fifth class D driver circuit DD5 includes a fifth driver input terminal connected to the first input terminal IN1, a fifth driver output terminal connected to the third node N3, a fifth pre-driver circuit PD5 operable in accordance with the signal level of the fifth driver input terminal, and a fifth driver switching circuit DSW5 whose connection state can be switched by the fifth pre-driver circuit PD5.

[0048] The sixth class D driver circuit DD6 is configured to be able to switch between a low impedance state in which the sixth driver output terminal is connected to the fourth node N4 and a high impedance state in which the sixth driver output terminal is not connected to the fourth node N4, based on a third control signal S3 from the control unit 10. Specifically, the sixth class D driver circuit DD6 includes a sixth driver input terminal connected to the second input terminal IN2, a sixth driver output terminal connected to the fourth node N4, a sixth pre-driver circuit PD6 operable in accordance with the signal level of the sixth driver input terminal, and a sixth driver switching circuit DSW6 whose connection state can be switched by the sixth pre-driver circuit PD6.

[0049] In this embodiment, the control unit 10 further includes a third control signal generation unit 18. The third control signal generation unit 18 is configured to generate a third control signal S3 based on the polarity determined by the polarity determination unit 12.

[0050] 8, when the first signal level and the second signal level are different from each other and during a predetermined period after the first signal level and the second signal level transition, the third control signal generator 18 generates the third control signal S3 to switch the fifth and sixth class D driver circuits DD5 and DD6 to a low impedance state. During the generation period of the third control signal S3, the second control signals S2a and S2b cause the output of the third and sixth class D driver circuits DD3 and DD4 to be in a high impedance state. As a result, during the predetermined period, the fifth and sixth class D driver circuits DD5 and DD6 are connected to the third and fourth nodes N3 and N4, respectively, thereby making it possible to equalize the output resistances at the first and second output terminals OUT1 and OUT2 and preventing distortion due to a mismatch between the first and second time constants τ1 and τ2.

[0051] In addition, within the scope of the present disclosure, the components in the above-described embodiments may be replaced with well-known components as appropriate, and the above-described embodiments may be combined as appropriate.

[0052] The contents described in each of the above embodiments can be understood, for example, as follows.

[0053] (1) A class D amplifier circuit according to one aspect includes: a first input terminal and a second input terminal to which a ternary PWM signal can be input; a first output terminal and a second output terminal to which both ends of a capacitive load are respectively connected; a first class D driver circuit having a first driver output terminal switchable to a power supply voltage or a ground voltage based on a first signal level of the first input terminal; a second class D driver circuit having a second driver output terminal switchable to the power supply voltage or the ground voltage based on a second signal level of the second input terminal; a first current limiting resistor connected between the first driver output terminal and the first output terminal; a second current limiting resistor connected between the second driver output terminal and the second output terminal; a first switch connected in parallel to the first current limiting resistor; a second switch connected in parallel to the second current limiting resistor; a control unit that controls the switching states of the first switch and the second switch based on the first signal level and the second signal level so that the voltage applied to the capacitive load is equal to or lower than the power supply voltage; Equipped with.

[0054] According to the above aspect (1), a first current limiting resistor is provided between the first driver output terminal and the first output terminal of the first class D driver circuit, and a second current limiting resistor is provided between the second driver output terminal and the second output terminal of the second class D driver circuit. This makes it possible to preferably reduce application costs by incorporating the first current limiting resistor and the second current limiting resistor in the class D amplifier circuit rather than using external elements. In addition, a first switch and a second switch are connected in parallel to the first current limiting resistor and the second current limiting resistor, respectively. The switching states of the first switch and the second switch are controlled by the signal levels of the first input terminal and the second input terminal, so that the voltage applied to the capacitive load becomes equal to or lower than the power supply voltage. This prevents the charge of the capacitive load from being unintentionally discharged by the ESD protection element, and allows a high-quality output waveform to be provided to the capacitive load.

[0055] (2) In another embodiment, in the above embodiment (1), The control unit a polarity determination unit for determining the polarity of the charge stored in the capacitive load based on the first signal level and the second signal level; a first control signal generation unit for generating a first control signal for switching the first switch and the second switch based on the polarity; Equipped with.

[0056] According to the above aspect (2), the polarity of the charge accumulated in the capacitive load is determined based on the signal levels of the first input terminal and the second input terminal. The first switch and the second switch are switched based on the determined polarity of the charge, thereby suppressing the applied voltage of the capacitive load to be equal to or lower than the power supply voltage.

[0057] (3) In another embodiment, in the above embodiment (2), The first control signal generation unit generating the first control signal so that, when the first signal level and the second signal level are H levels, one of the first switch or the second switch, whose polarity of the charge is positive, is switched to an ON state, and the other of the first switch or the second switch, whose polarity of the charge is negative, is switched to an OFF state; When the first signal level and the second signal level are at an L level, the first control signal is generated so as to switch the one of the first switch or the second switch whose polarity is positive to an OFF state, and to switch the one of the first switch or the second switch whose charge polarity is negative to an ON state.

[0058] According to the above aspect (3), when the signal levels of the first input terminal and the second input terminal are both H level, the switch on the positive polarity side is switched on and the switch on the negative polarity side is switched off. On the other hand, when the signal levels of the first input terminal and the second input terminal are both L level, the switch on the positive polarity side is switched off and the switch on the negative polarity side is switched on.

[0059] (4) In another embodiment, in any one of the above (1) to (3), The control unit controls the switching states of the first switch and the second switch so that a resistance value connected to the capacitive load is constant.

[0060] According to the above aspect (4), the first switch and the second switch are each switched so that the resistance value connected to the capacitive load becomes constant.

[0061] (5) In another embodiment, in the above embodiment (4), the first current limiting resistor and the second current limiting resistor have the same resistance value; The control unit controls the switching states so that the first switch and the second switch are not simultaneously in an on state or an off state.

[0062] According to the above aspect (5), by switching the first current limiting resistor and the second current limiting resistor having the same resistance value so that they are not simultaneously in the on or off state, the resistance value connected to the capacitive load can be suitably controlled to a constant value.

[0063] (6) In another embodiment, in any one of the above (1) to (5), the first switch is a class-3D driver circuit capable of switching, based on a second control signal from the control unit, between a high impedance state in which impedance with respect to a first node provided between the first current limiting resistor and the first output terminal is high, and a low impedance state in which impedance is lower than that in the high impedance state; The second switch is a fourth-class D driver circuit that can switch between a high-impedance state in which impedance with respect to a second node provided between the second current-limiting resistor and the second output terminal is high, and a low-impedance state in which impedance is lower than that in the high-impedance state, based on a second control signal from the control unit.

[0064] According to the above aspect (6), the first switch and the second switch can each be configured by a class D driver circuit capable of switching the impedance state based on a second control signal from the control unit.

[0065] (7) In another embodiment, in the above embodiment (6), The control unit a polarity determination unit for determining the polarity of the charge stored in the capacitive load based on the first signal level and the second signal level; a second control signal generator for generating the second control signal based on the polarity; Equipped with.

[0066] According to the above aspect (7), the polarity of the charge accumulated in the capacitive load is determined based on the signal levels of the first input terminal and the second input terminal. The impedance states of the class-D driver circuits constituting the first switch and the second switch are switched based on the determined polarity of the charge, thereby suppressing the voltage applied to the capacitive load to be equal to or lower than the power supply voltage.

[0067] (8) In another embodiment, in the above embodiment (7), The second control signal generation unit generating the second control signal so that, when the first signal level and the second signal level are H levels, one of the class-3D driver circuit and the class-4D driver circuit, which has the positive polarity, is switched to the low-impedance state, and the other of the class-3D driver circuit and the class-4D driver circuit, which has the negative polarity, is switched to the high-impedance state; When the first signal level and the second signal level are at an L level, the second control signal is generated so as to switch one of the class-3D driver circuit and the class-4D driver circuit, which has the positive polarity, to the high impedance state, and to switch one of the class-3D driver circuit and the class-4D driver circuit, which has the negative polarity, to the low impedance state.

[0068] According to the above aspect (8), when the signal levels of the first input terminal and the second input terminal are both H level, the class-D driver circuit on the positive polarity side is switched to a low-impedance state, and the class-D driver circuit on the negative polarity side is switched to a high-impedance state. This makes it possible to suitably realize the switching of the switch on the positive polarity side to an on state and the switching of the switch on the negative polarity side to an off state using the class-D driver circuits, as described above. On the other hand, when the signal levels of both the first input terminal and the second input terminal are L level, the class D driver circuit on the positive polarity side is switched to a high impedance state, and the class D driver circuit on the negative polarity side is switched to a low impedance state, thereby making it possible to suitably achieve the switching of the switch on the positive polarity side to an off state and the switching of the switch on the negative polarity side, as described above, using the class D driver circuit.

[0069] (9) In another embodiment, in the above embodiment (6), a first capacitance element provided between the first output terminal and a ground potential; a second capacitance element provided between the second output terminal and the ground potential; a third current limiting resistor connected between the first current limiting resistor and the first node; a fourth current limiting resistor connected between the second current limiting resistor and the second node; a fifth-class D driver circuit capable of switching between a high-impedance state in which impedance with respect to a third node provided between the third current limiting resistor and the first output terminal is high and a low-impedance state in which impedance is lower than that in the high-impedance state, based on a third control signal from the control unit; a sixth class D driver circuit capable of switching between a high impedance state in which impedance with respect to a fourth node provided between the fourth current limiting resistor and the second output terminal is high and a low impedance state in which impedance is lower than that in the high impedance state, based on the third control signal; Further provided with:

[0070] According to the above aspect (9), a first capacitive element and a second capacitive element are provided between the first output terminal and the ground potential, and between the second output terminal and the ground potential, for example, to prevent axial radiation noise, etc. In this aspect, by switching the impedance states of the class-5D driver circuit and the class-6D driver circuit, it is possible to prevent a mismatch between the first time constant generated by the output resistance of the first output terminal and the first capacitive element and the second time constant generated by the output resistance of the second output terminal and the second capacitive element, and to suitably reduce distortion in the output signal.

[0071] (10) In another embodiment, in the above embodiment (9), The control unit a polarity determination unit for determining the polarity of the charge stored in the capacitive load based on the first signal level and the second signal level; a third control signal generator for generating the third control signal based on the polarity; Equipped with.

[0072] According to the above aspect (10), the polarity of the charge accumulated in the capacitive load is determined based on the signal levels of the first input terminal and the second input terminal. The impedance states of the fifth and sixth class D driver circuits are switched regardless of the polarity of the charge accumulated in the load, thereby making it possible to preferably prevent mismatching of the time constants.

[0073] (11) In another embodiment, in the above embodiment (10), When the first signal level and the second signal level are different from each other, the third control signal generator generates the third control signal so that the fifth and sixth class D driver circuits are in the low impedance state for a predetermined period after a transition of either the first or second signal level, and generates the second control signal so that the third and fourth class D driver circuits are in the high impedance state.

[0074] According to the above aspect (11), when the signal level of either the first input terminal or the second input terminal transitions from a state in which the signal levels are different from each other, the fifth-class D driver circuit and the sixth-class D driver circuit are controlled to be in a low-impedance state for a predetermined period of time, thereby preventing mismatch between the time constants that is likely to occur during the predetermined period of time and effectively reducing distortion in the output signal.

[0075] (12) In another embodiment, in the above embodiment (10), The first current limiting resistor, the second current limiting resistor, the third current limiting resistor, and the fourth current limiting resistor have the same resistance value.

[0076] According to the above aspect (12), it is possible to prevent mismatch between time constants that is likely to occur during a predetermined period, and to suitably reduce distortion in the output signal.

[0077] (13) In another embodiment, in any one of the above (1) to (12), The capacitive load is a piezo buzzer.

[0078] According to the above aspect (13), it is possible to obtain a high-quality sound output with little distortion from a piezo buzzer driven by a class D amplifier circuit. [Explanation of symbols]

[0079] 1(1A,1B,1C) Class D amplifier circuit 10 Control Unit 12 Polarity judgment section 14 First control signal generation unit 16 Second control signal generating unit 18 Third control signal generation unit IN1 First input terminal IN2 Second input terminal OUT1 First output terminal OUT2 Second output terminal VDD power supply pin N1~N4 nodes SW1 First switch SW2 Second switch R1~R4 Current limiting resistors ESD1, ESD2 ESD protection elements CLOAD Capacitive load DD1~DD6 Class D driver circuit DSW1~DSW6 driver switching circuit PD1~PD6 pre-driver circuit

Claims

1. a first input terminal and a second input terminal to which a ternary PWM signal can be input; a first output terminal and a second output terminal to which both ends of a capacitive load are connected, respectively; a first class D driver circuit having a first driver output terminal switchable to a power supply voltage or a ground voltage based on a first signal level of the first input terminal; a second class D driver circuit having a second driver output terminal switchable to the power supply voltage or the ground voltage based on a second signal level of the second input terminal; a first current limiting resistor connected between the first driver output terminal and the first output terminal; a second current limiting resistor connected between the second driver output terminal and the second output terminal; a first switch connected in parallel to the first current limiting resistor; a second switch connected in parallel to the second current limiting resistor; a control unit that controls the switching states of the first switch and the second switch based on the first signal level and the second signal level so that the voltage applied to the capacitive load is equal to or lower than the power supply voltage; A class D amplifier circuit comprising:

2. The control unit a polarity determination unit for determining the polarity of the charge stored in the capacitive load based on the first signal level and the second signal level; a first control signal generating unit configured to generate a first control signal for switching the first switch and the second switch based on the polarity; 2. The class D amplifier circuit of claim 1, comprising:

3. The first control signal generation unit generating the first control signal so that, when the first signal level and the second signal level are H levels, one of the first switch or the second switch, whose polarity of the charge is positive, is switched to an ON state, and the other of the first switch or the second switch, whose polarity of the charge is negative, is switched to an OFF state; 3. The class D amplifier circuit according to claim 2, wherein when the first signal level and the second signal level are at an L level, the first control signal is generated so as to switch one of the first switch or the second switch, whose polarity of the charge is positive, to an OFF state, and to switch one of the first switch or the second switch, whose polarity of the charge is negative, to an ON state.

4. 3. The class D amplifier circuit according to claim 1, wherein the control unit controls the switching states of the first switch and the second switch so that a resistance value connected to the capacitive load is constant.

5. the first current limiting resistor and the second current limiting resistor have the same resistance value; The class D amplifier circuit according to claim 4 , wherein the control unit controls the switching states so that the first switch and the second switch are not simultaneously in an on state or an off state.

6. the first switch is a third-class D driver circuit capable of switching, based on a second control signal from the control unit, between a high-impedance state in which impedance with respect to a first node provided between the first current-limiting resistor and the first output terminal is high, and a low-impedance state in which impedance is lower than the high-impedance state; 2. The class-D amplifier circuit according to claim 1, wherein the second switch is a fourth-class-D driver circuit that is switchable, based on a second control signal from the control unit, between a high-impedance state in which an impedance with respect to a second node provided between the second current-limiting resistor and the second output terminal is high, and a low-impedance state in which an impedance with respect to the second node is lower than the high-impedance state.

7. The control unit a polarity determination unit for determining the polarity of the charge stored in the capacitive load based on the first signal level and the second signal level; a second control signal generator for generating the second control signal based on the polarity; 7. The class D amplifier circuit of claim 6, comprising:

8. The second control signal generation unit generating the second control signal so that, when the first signal level and the second signal level are H levels, one of the third class D driver circuit and the fourth class D driver circuit, which has the positive polarity, is switched to the low impedance state, and the other of the third class D driver circuit and the fourth class D driver circuit, which has the negative polarity, is switched to the high impedance state; 8. The class-D amplifier circuit according to claim 7, wherein when the first signal level and the second signal level are L levels, the second control signal is generated so as to switch one of the third class-D driver circuit and the fourth class-D driver circuit, which has the positive polarity, to the high-impedance state, and to switch one of the third class-D driver circuit and the fourth class-D driver circuit, which has the negative polarity, to the low-impedance state.

9. a first capacitance element provided between the first output terminal and a ground potential; a second capacitance element provided between the second output terminal and the ground potential; a third current limiting resistor connected between the first current limiting resistor and the first node; a fourth current limiting resistor connected between the second current limiting resistor and the second node; a fifth-class D driver circuit capable of switching between a high-impedance state in which impedance with respect to a third node provided between the third current limiting resistor and the first output terminal is high and a low-impedance state in which impedance is lower than that in the high-impedance state, based on a third control signal from the control unit; a sixth class D driver circuit capable of switching between a high impedance state in which impedance with respect to a fourth node provided between the fourth current limiting resistor and the second output terminal is high and a low impedance state in which impedance is lower than that in the high impedance state, based on the third control signal; The class D amplifier circuit of claim 6 further comprising:

10. The control unit a polarity determination unit for determining the polarity of the charge stored in the capacitive load based on the first signal level and the second signal level; a third control signal generator for generating the third control signal based on the polarity; 10. The class D amplifier circuit of claim 9, comprising:

11. 11. The class-D amplifier circuit according to claim 10, wherein, when the first signal level and the second signal level are different from each other, the third control signal generation unit generates the third control signal so that the fifth class-D driver circuit and the sixth class-D driver circuit are in the low-impedance state for a predetermined period after a transition of either the first signal level or the second signal level, and generates the second control signal so that the third class-D driver circuit and the fourth class-D driver circuit are in the high-impedance state.

12. 11. The class D amplifier circuit according to claim 10, wherein the first current limiting resistor, the second current limiting resistor, the third current limiting resistor, and the fourth current limiting resistor have the same resistance value.

13. 3. The class D amplifier circuit according to claim 1, wherein the capacitive load is a piezo buzzer.

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