Display device

Abstract

To reduce the storage of unnecessary charge.SOLUTION: A display device has a driving circuit including a logic circuit having a depletion type first transistor and an enhancement type second transistor, a signal line electrically connected to the driving circuit, a pixel unit including a pixel of which display condition is controlled by input of a signal serving as pixel data from the driving circuit through the signal line, a reference-voltage line to which the voltage serving as a reference is applied, and a depletion type third transistor to control the conduction between the signal line and the reference-voltage line. The first to the third transistors include an oxide semiconductor layer having a channel-forming region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a display device including a transistor including an oxide semiconductor. [Background technology]

[0002] Thin film transistors formed on flat plates such as glass substrates, as typified by liquid crystal display devices. (also called TFT: Thin Film Transistor) is mainly made of amorphous It is made of semiconductor materials such as silicon or polycrystalline silicon. Although TFTs using capacitors have low field-effect mobility, they can be used on large glass substrates. On the other hand, TFTs using polycrystalline silicon have high field effect mobility but are not suitable for laser diodes. Crystallization processes such as annealing are required, and this is not necessarily suitable for large-area glass substrates. It has the following characteristics:

[0003] In contrast, a TFT is fabricated using an oxide semiconductor as the semiconductor material, and the TFT is used as an electronic device. For example, the technology of using niobium as a semiconductor material in semiconductor devices such as silicon dioxide is attracting attention. TFTs were fabricated using lead and In-Ga-Zn-O oxide semiconductors, and used as switches for image display devices. Techniques used for etching elements and the like are disclosed in Patent Documents 1 and 2.

[0004] TFTs with a channel formation region in an oxide semiconductor are similar to TFTs using amorphous silicon. The oxide semiconductor film is formed by sputtering or other methods. This allows film formation at temperatures below 300°C, and TFTs using oxide semiconductor films are The manufacturing process is simpler than that of TFTs using polycrystalline silicon.

[0005] TFTs formed on glass substrates, plastic substrates, etc. using such oxide semiconductors LCDs, electroluminescent displays (also known as EL displays), It is expected that this technology will be applied to display devices such as LCDs, electronic paper, etc.

[0006] When the TFT using the oxide semiconductor is applied to a display device, for example, the TFT constituting the pixel portion The display device driver circuit can be applied to, for example, TFTs that configure the FT and driver circuit. For example, it is composed of a shift register circuit, a buffer circuit, etc., and further, The path and buffer circuit are configured by a logic circuit. By applying TFTs using oxide semiconductors to the It is possible.

[0007] In the above display device, unnecessary current is generated in elements, electrodes, wiring, etc. during the manufacturing stage or during operation. For example, in the case of a transistor, the accumulation of such charges If accumulation occurs, a parasitic channel will occur, causing leakage current. In the case of a type transistor, the back channel portion in the semiconductor layer (the upper portion in the semiconductor layer) Charges accumulate on or in the region between the source electrode and the drain electrode, Parasitic channels may occur. Furthermore, oxide semiconductors have a relatively wide The compound semiconductor has a band gap and has a high off-state resistance when used in a channel formation layer of a transistor. Therefore, in a transistor using an oxide semiconductor for a channel formation layer, unnecessary charges are accumulated. The accumulated charge easily generates a parasitic channel, which easily generates leakage current. In order to perform desired operations in the driver circuit and pixel section, the cause of the occurrence of a parasitic channel must be eliminated. It is preferable that the accumulation of unnecessary charges is small. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to reduce accumulation of unnecessary charge. [Means for solving the problem]

[0010] One embodiment of the present invention is a pixel including a driver circuit and a pixel electrically connected to the driver circuit through a signal line. and a pixel portion including a signal line and an element, an electrode, or a wiring electrically connected to the signal line. By selectively turning on the device when charge is accumulated, unnecessary accumulated charge is removed. This prevents unnecessary charge accumulation. This reduces the product and reduces leakage current.

[0011] One embodiment of the present invention is a semiconductor device including a first transistor which is a depletion type transistor and an enhancement type transistor. a driver circuit including a logic circuit having a second transistor that is an excitation transistor; , and a signal that becomes image data is input from a driving circuit via the signal line. a pixel section including pixels whose display states are controlled; a depletion type transistor; The transistor has a gate, a source, and a drain, and a reference voltage is applied to one of the source and the drain. The other of the source and drain is electrically connected to a signal line, and the gate is a third transistor to which a signal is input, The transistor is a display device including an oxide semiconductor layer having a channel formation region.

[0012] In one embodiment of the present invention, the first to third transistors each include a gate electrode and a gate insulating layer provided on the gate electrode; and an oxide semiconductor layer provided on the gate insulating layer. Each of the electrodes is provided on a part of the conductor layer and functions as a source electrode or a drain electrode. a first conductive layer and a second conductive layer, The semiconductor device may further include an oxide insulating layer provided on the conductive layer.

[0013] In one embodiment of the present invention, the thickness of the oxide semiconductor layer in the first transistor is the thickness of the oxide semiconductor layer in the first transistor is larger than the thickness of the oxide semiconductor layer in the second transistor; The thickness of the oxide semiconductor layer is larger than that of the oxide semiconductor layer in the second transistor. It's okay.

[0014] In one embodiment of the present invention, a conductive layer is provided on a channel formation region with an oxide insulating layer sandwiched therebetween. It may have a layer. [Effects of the Invention]

[0015] According to one embodiment of the present invention, when unnecessary charges are accumulated, the charges can be released to the outside. Therefore, it is possible to reduce the accumulation of unnecessary charges. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 illustrates an example of the structure of a display device in Embodiment 1. [Figure 2] 10A and 10B are diagrams illustrating an example of a structure of a display device in Embodiment 2. [Figure 3] FIG. 3 is a diagram showing an equivalent circuit of the display device shown in FIG. [Figure 4] 10A and 10B are diagrams illustrating an example of a structure of a display device in Embodiment 2. [Figure 5] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the display device shown in FIG. [Figure 6] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the display device shown in FIG. [Figure 7] 10A and 10B are diagrams illustrating an example of a structure of a display device in Embodiment 2. [Figure 8] 10A and 10B are diagrams illustrating an example of a structure of a display device in Embodiment 2. [Figure 9] 8A to 8C are cross-sectional views illustrating an example of a method for manufacturing the display device shown in FIG. [Figure 10] FIG. 11 is a circuit diagram showing an example of a circuit configuration of a logic circuit according to a third embodiment. [Figure 11] 11 is a timing chart showing an example of the operation of the logic circuit shown in FIG. [Figure 12] FIG. 11 is a circuit diagram showing an example of a circuit configuration of a shift register according to a fourth embodiment. [Figure 13] FIG. 10 is a circuit diagram showing an example of a circuit configuration of a NAND circuit according to a fourth embodiment. [Figure 14] 13 is a timing chart showing an example of the operation of the shift register shown in FIG. 12. [Figure 15] FIG. 20 is a block diagram showing the configuration of a display device according to a sixth embodiment. [Figure 16] FIG. 13 is a block diagram showing a configuration of a driver circuit in a display device according to a sixth embodiment. [Figure 17] FIG. 13 is a circuit diagram showing a circuit configuration of a pixel of a display device according to a seventh embodiment. [Figure 18] FIG. 20 is a diagram showing a pixel structure of a display device according to a seventh embodiment. [Figure 19]FIG. 20 is a diagram showing a pixel structure of a display device according to a seventh embodiment. [Figure 20] FIG. 20 is a circuit diagram showing a circuit configuration of a pixel of a display device according to an eighth embodiment. [Figure 21] FIG. 20 is a cross-sectional view showing the structure of a pixel of a display device in accordance with an eighth embodiment. [Figure 22] 13A and 13B are a top view and a cross-sectional view showing the structure of a display device in accordance with an eighth embodiment. [Figure 23] FIG. 20 is a cross-sectional view showing the structure of electronic paper in a ninth embodiment. [Figure 24] FIG. 20 is a diagram showing an electronic device to which electronic paper according to a ninth embodiment is applied. [Figure 25] 13A and 13B are a top view and a cross-sectional view showing the structure of a display device in accordance with a tenth embodiment. [Figure 26] FIG. 22 is a diagram showing an electronic device according to an eleventh embodiment. [Figure 27] FIG. 22 is a diagram showing an electronic device according to an eleventh embodiment. [Figure 28] FIG. 22 is a diagram showing an electronic device according to an eleventh embodiment. [Figure 29] FIG. 23 is a diagram showing an example of the structure of a display device according to a twelfth embodiment. [Figure 30] FIG. 23 is a diagram showing an example of the structure of a display device according to a thirteenth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] An example of an embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the following description, and the embodiments may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the embodiments shown.

[0018] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described.

[0019] A structural example of a display device in this embodiment will be described with reference to FIG. 1 is a diagram illustrating an example of the configuration of a display device in FIG.

[0020] The display device shown in FIG. 1 is composed of a drive circuit section 101 and a pixel section 102. The device has a signal line 103 .

[0021] The driver circuit unit 101 includes a driver circuit 111 and a transistor 112 .

[0022] The drive circuit 111 is a circuit for controlling the display operation of the display device, and is, for example, a combinational logic circuit. Combinatorial logic circuits include inverters, and The inverter may be, for example, a depletion mode transistor and an enhancement mode transistor. It is constructed using

[0023] Note that a depletion type transistor is an N-channel transistor with a threshold voltage of 0.1V. The threshold voltage is a negative value, and in the case of a P-channel transistor, the threshold voltage is a positive value. An enhancement type transistor is an N-channel transistor. In the case of a P-channel transistor, the threshold voltage is positive. A negative threshold voltage is a transistor in which the threshold voltage is negative.

[0024] The transistor 112 is a depletion-mode transistor and has a gate, a source, and a Has a drain.

[0025] The term "gate" refers to a gate electrode and a part or all of a gate wiring. The gate electrode of at least one transistor is electrically connected to another electrode or another wiring. For example, the scanning lines in a display device are included in the gate wiring.

[0026] The source refers to the source region, the source electrode, and part or all of the source wiring. The source region is the region of the semiconductor layer where the resistivity is below a certain value. The source wiring is a conductive layer that is connected to the source region. A wiring for electrically connecting the source electrode of one transistor to another electrode or another wiring. For example, when a signal line in a display device is electrically connected to a source electrode The source wiring also includes the signal line.

[0027] The drain refers to the drain region, drain electrode, and part or all of the drain wiring. The drain region is the region of the semiconductor layer whose resistivity is below a certain value. The drain electrode is the conductive layer connected to the drain region. The drain electrode of at least one transistor is electrically connected to another electrode or another wiring. For example, a signal line in a display device connects to a drain electrode. When electrically connected, the drain wiring also includes the signal line.

[0028] In addition, in this document (specification, claims, drawings, etc.), The and drain are interchangeable depending on the transistor structure and operating conditions. Therefore, it is difficult to determine whether the source or drain is the In the patent application, claims, drawings, etc., the source and drain may be arbitrarily selected. The selected terminal is referred to as one of the source and drain terminals, and the other terminal is referred to as the source and drain terminal. It will be referred to as the other.

[0029] Generally, voltage refers to the difference in potential between two points (also called the potential difference). However, voltage and potential values ​​are sometimes expressed in volts (V), making it difficult to distinguish between them. Therefore, in the documents of this application (specification and claims), unless otherwise specified, The potential difference between the potential at a point and the reference potential (also called the reference potential) is defined as the voltage at that point. It may be used in this way.

[0030] Furthermore, one of the source and drain of the transistor 112 is electrically connected to the signal line 103. The transistor is connected to the transistor and is in an on state (also called ON) or an off state (also called OFF) depending on the gate voltage. For example, as shown in FIG. 1, a separate scanning line 107 is provided, and the gate voltage is applied to the transistor The gate of 112 is electrically connected to the scanning line 107, and the transistor is The scanning line 10 is controlled by inputting a gate signal to the gate of the transistor 112. 7 is electrically connected to, for example, a scanning line driving circuit, In addition, the voltage applied to the other of the source and drain of the transistor 112 can be controlled. is either grounded or given a voltage of a predetermined value (also called a reference voltage or Vref). For example, as shown in FIG. 1, a reference voltage line 108 is provided separately, and the reference voltage is supplied to the transistor 11. The other of the two sources and drains is electrically connected to the reference voltage line 108. is applied to the other of the source and drain of the transistor 112. 12 is turned on or off, and during the non-selection period, the signal line 103 or In other words, charges are accumulated in other elements, electrodes, wiring, etc. electrically connected to the signal line 103. If the switch is turned on, the accumulated charge is discharged to the outside via the signal line 103. It functions as a switching element.

[0031] Note that the structure of the display device is not limited to that shown in FIG. 1. The transistor can have a multi-gate structure having multiple regions. A structure in which a plurality of transistors having the same structure as the transistor 112 are electrically connected in parallel. It is also possible.

[0032] The pixel section 102 has pixels 104. The pixel section 102 has a plurality of pixels 104 arranged in rows and columns. In the case where a plurality of pixels 104 are arranged in the row direction, In the case where the number of scanning lines is the same as the number of pixels in the row direction and a plurality of pixels 104 are arranged in the column direction, In this case, the number of signal lines is the same as the number of pixels in the column direction. In this case, a transistor 112 is provided for each signal line, and the source and One of the drains may be electrically connected to a corresponding signal line.

[0033] The pixel 104 receives a signal as image data from a driving circuit 111 via a signal line 103. The pixel 104 is a pixel formed of a switch such as a transistor. The state is controlled by the switching element being turned on or off. and a display element such as a liquid crystal element or a light-emitting element. The timing at which data is input can be controlled by providing a separate scanning line 105 as shown in FIG. , and is set in accordance with the signal input via the scanning line 105.

[0034] In the display device shown in FIG. 1, the depletion type transistor used in the driving circuit 111 The depletion type transistor used as the transistor 112 is For example, the semiconductor device may have a structure including an oxide semiconductor layer having a channel formation region. In the display device shown in FIG. 1, the depletion The depletion-mode transistor and the depletion-mode transistor used as transistor 112 However, it is not limited to this, and for example, For example, the transistor 112 may have a different structure from the transistor used in the driving circuit 111. It can also be done as follows.

[0035] The transistors used in the driver circuit 111 and the transistor 112 are, for example, For example, a bottom gate transistor can be used.

[0036] In addition, the channel width of the transistor 112 is set to the channel width of the transistor used in the driver circuit 111. The channel width of the transistor 112 may be made wider than the channel width. This reduces the influence of unnecessary charge accumulation on the switching operation of the transistor 112. It is possible.

[0037] Next, an example of the operation of the display device shown in FIG. The transistor 112 is an N-channel transistor, and the scanning lines 105 and 107 The input scanning signal is converted into a binary digital signal having a first voltage state and a second voltage state. The scanning signal input via the scanning line 105 is in the first voltage state. In the second voltage state, the voltage V1 (also simply referred to as V1) is applied, and in the second voltage state, the voltage V2 (also simply referred to as V2) is applied. In addition, the scanning signal input via the scanning line 107 is in the first voltage state and has a voltage V 2, and in the second voltage state, the voltage becomes V3 (also simply referred to as V3). V1 is a voltage greater than V2, and V3 is a voltage less than V2. The voltage V2 is set to the ground potential. The reference voltage line 108 is set to the ground potential (also referred to as Vgnd). Let us suppose that the following is given:

[0038] An example of the operation of the display device shown in FIG. 1 is a period during which the pixel 104 is not selected (a non-selection period). The period is divided into a period in which the pixel 104 is selected (also called a selection period) and a period in which the pixel 104 is selected (also called a row selection period). When a plurality of pixels 104 are arranged in the column direction, all of the pixels 104 are selected. A period in which no pixel 104 is selected is defined as a non-selection period, and a period in which any pixel 104 is selected is defined as a selection period. .

[0039] First, in the non-selection period, the voltage value of the scanning line 105 is voltage V2, and the voltage value of the scanning line 107 is voltage V3. (V 107 The value of this voltage (also called voltage V2) becomes voltage V2.

[0040] At this time, the transistor 112 is turned on in response to the voltage of the scanning line 107. , the signal line 103 and the reference voltage line 108 are in a conductive state, and the signal line 103 or the signal line 103 If electric charges are accumulated in electrically connected elements, electrodes, or wiring, The charge is released to the reference voltage line 108 via the signal line 103 and the transistor 112 .

[0041] Next, during the selection period, the voltage value of the scanning line 105 becomes voltage V1, and the voltage value of the scanning line 107 becomes The value becomes voltage V3.

[0042] At this time, the transistor 112 is turned off, and the signal is transmitted to the driving circuit 111 via the signal line 103. A signal that becomes image data is input to the pixel 104 from the The pixel 104 is then brought into a display state according to the input image data.

[0043] The same applies to a configuration in which a plurality of pixels 104 are arranged in rows and columns. During this period, the transistors 112 electrically connected to the signal lines 103 are turned on. By bringing each signal line 103 and the reference voltage line 108 into a conductive state, In other words, charges are accumulated in elements, electrodes, or wiring electrically connected to each signal line 103. In this case, the reference voltage is supplied to the reference voltage line 108 via the signal lines 103 and the transistors 112. During the selection period, each transistor 112 is turned off, and the scan line 10 Image data is input to the pixels 104 in sequence every 5, and the pixels to which the image data is input are displayed in the Become a pose.

[0044] In addition, the transistor 112 may be turned on multiple times during the non-selection period. For example, a non-selection period can be inserted between a selection period in one frame and a selection period in the next frame. may be provided to turn on the transistor 112.

[0045] As described above, the display device of this embodiment mode includes an element, an electrode, or a When electric charge accumulates in the wiring, the accumulated electric charge is selectively transferred to the reference voltage line via the signal line. In addition, a display device can be constructed using a bottom gate type transistor. In this case, even if charges are accumulated in the back channel, the accumulated charges are not transmitted to the signal. This can be used to prevent the generation of parasitic channels. This can also reduce leakage current.

[0046] In addition, the transistor for discharging unnecessary accumulated charge is called a depletion type transistor. By using a resistor, it can be turned on without applying voltage. When the device is not in operation, unnecessary accumulated charges can be discharged, so the display operation This can reduce the impact on production.

[0047] (Embodiment 2) In this embodiment, a structural example of a driver circuit portion in a display device according to one embodiment of the present invention will be described. explain.

[0048] The structure of the drive circuit unit in this embodiment will be described with reference to FIG. 2A and 2B are diagrams showing an example of the structure of a driver circuit portion in the embodiment, FIG. 2A is a top view, and FIG. 2(B) is a cross-sectional view taken along lines Z1-Z2 and Z3-Z4 in FIG. 2(A).

[0049] The driving circuit section shown in FIGS. 2A and 2B is a transistor provided on a substrate 201. The transistor 251, the transistor 252, and the transistor 253.

[0050] The transistor 251 and the transistor 252 are logic elements that form the driver circuit 111 shown in FIG. This is an example of an element used in logic circuits, and its equivalent circuit configuration is shown in Figure 3.

[0051] The transistor 251 is a depletion-mode transistor, and one of the source and drain A high power supply voltage (also called Vdd) is applied to the gate, source, and drain. The other of the two is electrically connected (also called diode connection).

[0052] Note that the transistor 251 shown in FIG. 3 has a gate and the other of the source and the drain electrically connected to each other. However, the present invention is not limited to this configuration. For example, the gate is electrically connected to one of the source and drain of the transistor 251. It can also be configured so that another signal is input via a gate. do.

[0053] The transistor 252 is an enhancement type transistor and receives a signal through its gate. is input, and one of the source and drain is connected to the other of the source and drain of the transistor 251. The other of the source and drain is electrically connected to a low power supply voltage (also called Vss). The low power supply voltage is, for example, a ground potential or a predetermined voltage.

[0054] The high power supply voltage is a potential that is relatively higher than the low power supply voltage. The potential is relatively lower than the power supply voltage. Each value is set appropriately depending on the circuit specifications. For example, if the value of Vdd is greater than the value of Vss, However, this does not necessarily mean that the value of |Vdd| is greater than |Vss|. Even if the value of Vdd is greater than Vss, the value of Vgnd is not necessarily equal to or greater than the value of Vss. It doesn't necessarily have to be above that.

[0055] For example, a high-state digital signal is input to transistor 251 When a low digital signal is input to the gate of A low digital signal is input to the gate of transistor 251. When activated, the logic circuit outputs a high digital signal as the output signal.

[0056] The transistor 253 corresponds to the transistor 112 shown in FIG. be.

[0057] The structure of each transistor will be described below. a gate electrode 211a provided on the gate electrode 211a; and a gate insulating film provided on the gate electrode 211a. The gate insulating layer 202 is sandwiched between the oxide semiconductor layer 202 and the gate electrode 211a. The conductive layer 21 is provided on the conductor layer 223a and a part of the oxide semiconductor layer 223a. 5a and a conductive layer 215b.

[0058] The transistor 252 includes a gate electrode 211b provided on the substrate 201 and a gate electrode The gate insulating layer 202 is provided on the gate electrode 211b. An oxide semiconductor layer 223b provided on the electrode 211b and a part of the oxide semiconductor layer 223b and conductive layers 215b and 215c provided on the respective conductive layers.

[0059] The transistor 253 includes a gate electrode 211c provided on the substrate 201 and a gate electrode The gate insulating layer 202 is provided on the gate electrode 211c. An oxide semiconductor layer 223c provided on the electrode 211c and a part of the oxide semiconductor layer 223c and conductive layers 215b and 215d provided on the respective conductive layers.

[0060] The conductive layers 215a to 215d function as source electrodes and drain electrodes, respectively. Possess the ability.

[0061] The oxide semiconductor layers 223a to 223c are subjected to dehydration or dehydrogenation treatment. In addition, the oxide semiconductor layers 223a to 223c are in contact with the oxide semiconductor layers 223a to 223c. The oxide semiconductor layer is used as a channel forming layer. Resistors are highly reliable because they are less likely to experience Vth shifts due to long-term use or high loads. .

[0062] Note that a nitride insulating layer may be provided over the oxide insulating layer 207. The insulating layer 207 is configured to be in contact with the gate insulating layer 202 or the underlying insulating layer provided below the insulating layer 207. It is preferable that moisture, hydrogen ions, and OH ions from the vicinity of the side surface of the substrate are removed. - Impurities such as In particular, the gate insulating layer 20 provided below the oxide insulating layer 207 It is effective to use a silicon nitride layer as the insulating layer 2 or the base layer. By providing a silicon nitride layer so as to surround the upper and side surfaces, the reliability of the display device is improved.

[0063] The driver circuit section shown in FIGS. 2A and 2B is formed on a planarized oxide insulating layer 207. The insulating layer 216 is provided, and the oxide insulating layer 207 and the planarization insulating layer 216 are sandwiched between the insulating layer 216 and the oxide insulating layer 207. The conductive layer 217a is provided over the semiconductor layer 223a, and the oxide insulating layer 207 and the planarizing insulating layer 2 The conductive layer 217b is provided over the oxide semiconductor layer 223b with the insulating layer 16 sandwiched therebetween, and the oxide insulating layer 207 and a conductive layer 217c is provided over the oxide semiconductor layer 223c with a planarization insulating layer 216 sandwiched therebetween. The conductive layers 217a to 217c each function as a second gate electrode. By applying a second gate voltage to the conductive layers 217a to 217c, The threshold voltages of the transistors 251 to 253 can be controlled.

[0064] Note that the planarization insulating layer 216 is not necessarily provided. In this case, on the oxide insulating layer 207 (on the nitride insulating layer if a nitride insulating layer is provided) Alternatively, the conductive layers 217a to 217c may be provided.

[0065] For example, the voltage of each of the conductive layers 217a to 217c is set to be equal to or higher than the voltage of the source electrode. When a voltage is applied to this, the threshold voltage of the transistor shifts in the negative direction, and the voltage of the source electrode When a voltage is applied to each of the conductive layers 217a to 217c so that the voltage is lower than the , the threshold voltage of the transistor shifts in the positive direction.

[0066] For example, in the case of a depletion type transistor, the voltage of the second gate electrode is set to the voltage of the source electrode. By setting the voltage sufficiently lower than the threshold voltage, the threshold voltage can be shifted in the positive direction. By using a gate electrode, the depletion type transistor can be selectively converted into an enhancement type transistor. It can be changed into star.

[0067] In the case of an enhancement type transistor, the voltage of the second gate electrode is applied to the source electrode If the voltage is made sufficiently higher than the second gate, the threshold voltage can be shifted in the negative direction. By using electrodes, enhancement type transistors can be selectively converted into depletion type transistors. It can be changed to .

[0068] In the case of an enhancement type transistor, the voltage of the second gate electrode is applied to the source electrode If the voltage is made sufficiently lower than the second voltage, the threshold voltage can be shifted further in the positive direction. By applying a sufficiently low voltage to the gate electrode, the off state is maintained regardless of the high-state input signal. You can change it into a trait you want to keep.

[0069] As described above, the threshold voltage of the transistor having the second gate electrode is This allows the second gate electrode to be controlled by the voltage applied to the second gate electrode. A gate voltage of 1 V is applied to the transistor 251 to make it a depletion-mode transistor. By making the transistor 252 an enhancement type transistor, an oxide semiconductor is used. The transistors can be used to provide logic circuits, and the transistor 253 can be depleted. By using a transistor as a transistor of a switching type, a signal line or an element electrically connected to the signal line, To release unnecessary charges when they accumulate on electrodes or wiring. In addition, a depletion type transistor using an oxide semiconductor can be provided. Even in a display device using a transistor, leakage current can be reduced. When a display device is configured using a bottom gate transistor, a back channel portion Even if electric charge accumulates in the This can suppress the occurrence of parasitic channels and reduce leakage current. It is also possible.

[0070] In the driver circuit portion shown in FIG. 2, each of the transistors 251 to 253 Although the example in which the conductive layers 217a to 217c are provided thereon has been described, the present invention is not limited to this. For example, the upper surface of a transistor that functions as an enhancement type transistor The second transistor is disposed only on the transistor that functions as a depletion-mode transistor. A conductive layer having a function as a gate electrode can also be provided.

[0071] In the display device of this embodiment, the gate electrode of one transistor constituting the logic circuit and a source electrode or a drain electrode of another transistor are directly connected to each other. For example, an opening can be formed in the gate insulating layer 202 to form a gate electrode of the transistor 251. By using a structure in which the electrode 211a and the conductive layer 215b of the transistor 252 are in contact with each other, A good contact can be obtained and the contact resistance can be reduced. The number of openings can be reduced, thereby reducing the occupied area.

[0072] In addition, in the display device of this embodiment, as shown in FIG. 4, the transistor 251 is an oxide semiconductor. The oxide conductive layer 214a and the oxide conductive layer 214b functioning as a pair of buffer layers are formed on the oxide conductive layer 223a. The oxide conductive layer 214b is provided so as to be in contact with the oxide conductive layer 214a and the oxide conductive layer 214b. A structure in which a pair of electrodes, a conductive layer 215a and a conductive layer 215b, are provided is used. The oxide conductive layer 252 is formed on the oxide semiconductor layer 223b. The oxide conductive layer 252 functions as a pair of buffer layers. The oxide conductive layer 214c and the oxide conductive layer 214d are provided. A pair of electrodes, conductive layers 215b and 215c, were provided so as to contact 14d. The transistor 253 is provided over the oxide semiconductor layer 223c as a pair of buffer layers. The oxide conductive layer 214e and the oxide conductive layer 214f ​​are provided. The conductive layer 215b and the conductive layer 215c are a pair of electrodes in contact with the oxide conductive layer 214f. 215d may also be provided.

[0073] The oxide conductive layer 214a and the oxide conductive layer 214b, and the oxide conductive layer 214c and the oxide conductive layer The oxide semiconductor layer 214d has a higher conductivity than the oxide semiconductor layer 223a and the oxide semiconductor layer 223b. The source and drain regions of transistor 251 and transistor 252 have a dielectric constant. It serves as an in-area.

[0074] The oxide conductive layers 214a to 214f ​​are formed by using an oxide conductive material. The film may be made of a conductive material that is transparent to visible light, such as In-Sn-Zn- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In -Sn-O, In-O, Sn-O, and Zn-O metal oxides can be used. The film thickness is appropriately selected within the range of 1 nm to 300 nm. When using a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less, the film is formed. In the subsequent process, SiOx (x>0) that inhibits crystallization is contained in the conductive film having light-transmitting properties. It is preferable to suppress crystallization during the heat treatment for dehydration or dehydrogenation. It's nice.

[0075] Furthermore, when an In-Ga-Zn-O based film is used for the oxide semiconductor layer and the oxide conductive layer, , the oxide semiconductor layers 223a to 223c functioning as channel formation regions. and the oxide conductive layers 214a to 214b functioning as source and drain regions. 214f can be produced by different film formation conditions.

[0076] For example, when a film is formed by a sputtering method, an oxide semiconductor film formed in argon gas is The oxide conductive layers 214a to 214f ​​formed by the above process have N-type conductivity. The activation energy (ΔE) is 0.01 eV or more and 0.1 eV or less.

[0077] In this embodiment, the oxide conductive layers 214a to 214f ​​are formed of In The film is a Ga-Zn-O system film and contains at least an amorphous component. In addition, crystal grains (also called nanocrystals) are formed in the oxide conductive layers 214a to 214f. The crystal grains in the oxide conductive layers 214a to 214f ​​may include The diameter is 1 nm to 10 nm, typically about 2 nm to 4 nm.

[0078] The oxide conductive layers 214a to 214f ​​are not necessarily provided, but The oxide semiconductor layers 223a to 223c function as panel-forming layers, and the oxide semiconductor layers 223a to 223c function as source An oxide film is formed between the conductive layers 215a to 215d, which function as an electrode and a drain electrode. By providing the conductive layers 214a to 214f, good electrical connection can be obtained. As a result, the transistors 251 to 253 can operate stably. It is also possible to maintain high mobility even at a high drain voltage.

[0079] Next, a method for manufacturing the driver circuit shown in FIG. 2 will be described with reference to FIGS. 5 and 6. 6A to 6C are cross-sectional views showing an example of a method for manufacturing the drive circuit section shown in FIG.

[0080] First, a substrate 201 is prepared, a conductive film is formed on the substrate 201, and then a first photolithography is performed. The gate electrodes 211a, 211b, and 211c are formed by a polishing process. (See FIG. 5(A)). The end of the gate electrode thus formed is tapered. It is preferable that:

[0081] The substrate 201 has an insulating surface and is at least heat-resistant enough to withstand the subsequent heat treatment. The substrate 201 is, for example, a glass substrate. It is possible.

[0082] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point will be 730°C or higher. The glass substrate may be made of, for example, aluminosilicate glass, aluminum Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boric acid, it is more practical. Therefore, it is recommended to use a glass substrate containing more BaO than B2O3. It is preferable that:

[0083] Instead of the glass substrate, the substrate 201 may be a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. Alternatively, a substrate made of an insulating material such as a glass substrate may be used. It is possible.

[0084] Further, an insulating film serving as a base film is formed between the substrate 201 and the gate electrodes 211a to 211c. The base film has a function of preventing the diffusion of impurity elements from the substrate 201. and one or more selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. It can be formed by a laminated structure of a plurality of films.

[0085] Examples of materials for the conductive film for forming the gate electrodes 211a to 211c include For example, molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Metallic materials such as aluminum and scandium, or alloy materials containing these as main components, can be used. The conductive film for forming the gate electrodes 211a to 211c is made of these materials. The film may be formed of a single layer or a laminated film including one or more of the above.

[0086] In addition, as a conductive film for forming the gate electrodes 211a to 211c, for example, For example, a titanium film, an aluminum film provided on the titanium film, and a a three-layer laminated film of a titanium film coated with a molybdenum film, or a molybdenum film, and an aluminum film formed on the molybdenum film; A three-layer laminate film consisting of an aluminum film and a molybdenum film provided on the aluminum film is used. Of course, the metal conductive film may be a single layer film, a two-layer laminated film, or a four or more layer laminated film. Alternatively, a stack of a titanium film, an aluminum film, and a titanium film may be used as the conductive film. When a conductive film is used, it can be etched by dry etching using chlorine gas. Cut.

[0087] Next, the gate insulating layer 202 is formed on the gate electrodes 211a to 211c. .

[0088] The gate insulating layer 202 is formed by depositing a silicon oxide layer using a plasma CVD method, a sputtering method, or the like. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer may be formed as a single layer or a stacked layer. For example, when forming a silicon oxynitride layer, the deposition gas is SiH4, oxygen, and A silicon oxynitride layer can be formed by plasma CVD using nitrogen. The thickness of O2 is 100 nm or more and 500 nm or less. In the case of a laminated film, for example, the thickness is 50 nm. a first gate insulating layer having a thickness of 5 nm or more and a thickness of 200 nm or less; The second gate insulating layer is a stack of 300 nm or less. Silicon oxide film formed using a silicon target material doped with phosphorus or boron By using - To prevent the intrusion of can be done.

[0089] In this embodiment, a silicon nitride layer having a thickness of 200 nm or less is formed by plasma CVD. A protective insulating layer 202 is formed.

[0090] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 202. Even if heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film, the oxide semiconductor film In order to make the semiconductor film amorphous, it is preferable to make the film thickness as thin as 50 nm or less. By thinning the oxide semiconductor film, when a heat treatment is performed after the formation of the oxide semiconductor film, the resulting Crystallization can be suppressed.

[0091] Before the oxide semiconductor film was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and a film is formed on the surface of the gate insulating layer 202. It is preferable to remove the powdery material that is generated when the target is reverse sputtered. Without applying a voltage, a voltage was applied to the substrate using an RF power supply in an argon atmosphere. This is a method of modifying the surface by forming plasma. Umium, oxygen, etc. may also be used.

[0092] The oxide semiconductor film includes In-Ga-Zn-O based films, In-Sn-Zn-O based films, In- Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Z nO series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-Sn-O series In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor films are used. Film formation by sputtering using an In-Ga-Zn-O oxide semiconductor target The oxide semiconductor film can be formed under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Or by sputtering in a mixed atmosphere of rare gas (typically argon) and oxygen. When the sputtering method is used, the SiO2 content is 2% by weight or more. The oxide semiconductor film is formed using a target containing 10% by weight or less of the above-mentioned element, and the oxide semiconductor film is then subjected to crystallization-inhibiting treatment. SiOx (x>0) may be included, which allows for the dehydration or dehydrogenation to be carried out in the subsequent step. The oxide semiconductor layer formed later is prevented from being crystallized during heat treatment for crystallization. It is possible.

[0093] The oxide semiconductor film is preferably an oxide semiconductor film containing In, more preferably an oxide semiconductor film containing In and an oxide semiconductor film containing Ga.

[0094] Here, an oxide semiconductor target containing In, Ga, and Zn (composition ratio: In2 Using O3:Ga2O3:ZnO=1:1:1 [molar ratio], the substrate and target The distance between the sample and the oxygen sensor was 100 mm, the pressure was 0.6 Pa, the DC power supply was 0.5 kW, and the oxygen (oxygen flow rate) The oxide semiconductor film is formed in an atmosphere containing 100% of the oxide. The use of this agent is preferable because it can reduce the amount of powdery material generated during film formation and also makes the film thickness distribution uniform. In this embodiment, an In—Ga—Zn—O-based oxide semiconductor film is used as the oxide semiconductor film. An In-Ga-Zn-O based film is formed by sputtering using a get.

[0095] The sputtering method includes RF sputtering, which uses a high frequency power supply for the sputtering power supply, and There is a DC sputtering method that uses a DC power supply for the sputtering power supply, and there is also a pulse There is also a pulsed DC sputtering method that applies a bias. RF sputtering is mainly used for insulating DC sputtering is used to form conductive metal films. It is used in cases where

[0096] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0097] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0098] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. There is also a bias sputtering method in which a voltage is applied to the substrate during film formation.

[0099] Next, the oxide semiconductor film is processed into an island shape by a second photolithography process. The oxide semiconductor layer 223a, the oxide semiconductor layer 223b, and the oxide semiconductor layer 223c are formed (FIG. 5 Note that after the second photolithography step, the oxide semiconductor layers 223a to 223b are The oxide semiconductor layer 223c is heated in an inert gas atmosphere (nitrogen, helium, neon, argon, or the like). ) and heat treatment (400℃ or more but less than 750℃) Impurities such as oxygen and water may be removed.

[0100] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment is 400°C or higher and lower than 750°C, preferably 425°C or higher and 750°C or lower. If the temperature is 425°C or higher, the heat treatment time may be 1 hour or less. If the temperature is below 750°C, the heat treatment time is longer than 1 hour. The substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated in a nitrogen atmosphere. After the heat treatment under the above-mentioned conditions, the oxide semiconductor layer was prevented from being exposed to the air. In this embodiment, the heating temperature at which the oxide semiconductor layer is dehydrated or dehydrogenated is From T to a temperature that is high enough to prevent water from entering again, specifically 100°C higher than the heating temperature T The same furnace is used to slowly cool the temperature in a nitrogen atmosphere until the temperature drops to 100°C or more. Dehydration or dehydrogenation is carried out under helium, neon, argon, or the like.

[0101] The heat treatment device is not limited to an electric furnace, and may be a device that uses heat conduction or heat from a heating element such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. A rare gas such as argon or nitrogen that hardly reacts with the material to be treated by heat treatment. A suitable inert gas is used.

[0102] The oxide semiconductor layer is subjected to a heat treatment at a temperature of 400°C or higher and lower than 750°C. This dehydration and dehydrogenation of the carbon dioxide prevents subsequent re-impregnation with water (H2O).

[0103] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the mixture does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the device must be 6N (99. 9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0104] Note that the oxide semiconductor layer may be annealed depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer. It may crystallize to form a microcrystalline or polycrystalline layer. For example, the crystallization rate may be 90% or more, or In some cases, the oxide semiconductor layer is microcrystalline by 80% or more. Alternatively, depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer that does not contain crystalline components. In some cases, this may be the case.

[0105] After the first heat treatment, the oxide semiconductor layer becomes oxygen-deficient, becomes n-type, and has low resistance. The oxide semiconductor layer after the heat treatment in 1 has a higher carrier concentration than the oxide semiconductor layer immediately after deposition. Preferably, 1×10 18 / cm 3 The oxide semiconductor layer has a carrier concentration of 1000 or more. do.

[0106] Note that the gate electrodes 211a to 211c are formed under the conditions of the first heat treatment or Some materials may crystallize to form a microcrystalline or polycrystalline layer. When an indium oxide / tin oxide alloy layer is used as the electrode 211a to the gate electrode 211c, are crystallized by a first heat treatment at 450° C. for 1 hour, and the gate electrodes 211 a to 211 b are formed. When an indium oxide / tin oxide alloy layer containing silicon oxide is used as c, crystallization does not occur.

[0107] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0108] Next, the gate insulating layer 202 and the oxide semiconductor layers 223a to 223c were A conductive film for forming source and drain electrodes of a transistor is formed thereon.

[0109] The conductive film is made of an element selected from Ti, Mo, W, Al, Cr, Cu, and Ta, or The conductive film is made of an alloy containing the above elements or an alloy combining the above elements. The layer is not limited to a single layer containing the above-mentioned elements, but may be a laminate of two or more layers. In the form of titanium film (thickness 100 nm), aluminum film (thickness 200 nm) and titanium A three-layer conductive film (100 nm thick) is formed. In addition, titanium nitride is used instead of the Ti film. A membrane may also be used.

[0110] When heat treatment is performed at 200 to 600°C, the conductive film must have heat resistance to withstand this heat treatment. For example, an aluminum alloy containing an element to prevent hillocks, It is preferable to use a conductive film laminated with a heat-resistant conductive film. Sputtering method, vacuum deposition method (electron beam deposition method, etc.), arc discharge ion plating The coating method and spraying method are used. Also, conductive nanopastes such as silver, gold, and copper are used for coating. It may also be formed by discharging using a screen printing method, an ink jet method, or the like, and then baking.

[0111] Next, the source and drain electrodes of the transistor are formed by a third photolithography process. A resist mask 233a, a resist mask 233b, and a resist mask 233c are formed on the conductive film for forming the resist pattern. A resist mask 233c and a resist mask 233d are formed, and the resist mask 233a Part of the conductive film is etched using the resist mask 233d to form the conductive layer 215a , a conductive layer 215b, a conductive layer 215c, and a conductive layer 215d are formed (see FIG. 5C). ).

[0112] In the third photolithography step, only the conductive film in contact with the oxide semiconductor layer is formed. For example, a metal conductor in contact with an In-Ga-Zn-O-based oxide semiconductor layer is selectively removed. In order to selectively remove only the conductive film, an alkaline etchant containing ammonia hydrogen peroxide (composite When the weight ratio of the components is hydrogen peroxide: ammonia: water = 5:2:2, the metal conductor The conductive film can be selectively removed, leaving the oxide semiconductor layer made of the oxide semiconductor. .

[0113] In addition, depending on the etching conditions, the oxide semiconductor The exposed areas of the layer may be etched. In that case, the source and drain electrode layers The oxide semiconductor layer in the region sandwiched between the conductive layers 215a and 215b is The oxide semiconductor layer in the region where the source electrode layer overlaps the gate electrode 211a, or the drain electrode The thickness of the oxide semiconductor layer is thinner than that of the oxide semiconductor layer in the area where the source electrode layer and the drain electrode layer overlap. Oxide in the region sandwiched between the inner electrode layers (region sandwiched between the conductive layer 215b and the conductive layer 215c) The semiconductor layer is an oxide semiconductor layer in a region where the source electrode layer overlaps the gate electrode 211b, or The thickness of the oxide semiconductor layer is thinner than that of the region where the drain electrode layer overlaps. The region sandwiched between the electrode layer and the drain electrode layer (the region sandwiched between the conductive layer 215b and the conductive layer 215d) The oxide semiconductor layer of the gate electrode 211c is the oxide semiconductor layer of the region where the source electrode layer overlaps. The thickness of the oxide semiconductor layer is thinner than that of the oxide semiconductor layer in the region where the oxide semiconductor layer overlaps with the drain electrode layer.

[0114] Next, the gate insulating layer 202, the oxide semiconductor layer 223a, the oxide semiconductor layer 223b, and the oxide semiconductor layer 223b were The oxide insulating layer 207 is formed on the oxide semiconductor layer 223c. Parts of the oxide semiconductor layers 223a to 223c are in contact with the oxide insulating layer 207. The region of the oxide semiconductor layer that overlaps with the gate electrode across the gate insulating layer becomes the channel formation region. .

[0115] The oxide insulating layer 207 has a thickness of at least 1 nm and is formed by an oxide method such as a sputtering method. The insulating layer can be formed by any suitable method that does not allow impurities such as water and hydrogen to be mixed into the insulating layer. In this embodiment mode, a silicon oxide film is formed as the oxide insulating layer by a sputtering method. The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower. In this embodiment, the substrate temperature is set to 100° C. The silicon oxide film is formed by sputtering in a rare gas (typically argon) atmosphere. In air, oxygen, or a mixture of rare gas (typically argon) and oxygen In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used to perform sintering under an oxygen and rare gas atmosphere. A silicon oxide film can be formed by a sputtering method. The oxide insulating layer formed in contact with the oxide semiconductor layer 223d is resistant to moisture, hydrogen ions, OH - It does not contain impurities such as fluorine, and uses an inorganic insulating film that blocks these from entering from the outside. Typically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film Note that an oxide insulating layer formed by a sputtering method is particularly dense. It can be used as a single layer as a protective film to suppress the phenomenon of impurities diffusing into adjacent layers. In addition, a target doped with phosphorus (P) or boron (B) can be used to form an oxide insulating layer. Phosphorus (P) and boron (B) can also be added.

[0116] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering, and the film thickness is 300 nm.

[0117] Note that the oxide insulating layer 207 is in contact with a region that serves as a channel formation region of the oxide semiconductor layer. It also functions as a channel protection layer.

[0118] Next, a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, at 250°C or higher and 35°C or lower) is performed. 0°C or less) may be carried out in an inert gas atmosphere or a nitrogen gas atmosphere. The second heat treatment is carried out at 250°C for 1 hour in an atmosphere. A state in which parts of the semiconductor layers 223a to 223c are in contact with the oxide insulating layer 207 In addition, other parts of the oxide semiconductor layers 223a to 223c are introduced. The conductive layers 215a to 215d are heated while in contact with each other.

[0119] The oxide semiconductor layers 223a to 223c whose resistance is reduced by the first heat treatment When the second heat treatment is performed while the oxide insulating layer 207 is in contact with the oxide insulating layer 207, the oxide insulating layer 207 As a result, the oxide semiconductor layer 223a to the oxide semiconductor layer 223b are in an oxygen-excess state. The oxide semiconductor layers 223a to 223c are in contact with the oxide insulating layer 207. The compound semiconductor layer 223c is made to be I-type (high resistance) in the depth direction (see FIG. 6(A)).

[0120] The timing for performing the second heat treatment is immediately after the end of the third photolithography process. There are no particular limitations as long as it is a process subsequent to the third photolithography process.

[0121] Next, a planarization insulating layer 216 is formed over the oxide insulating layer 207. Examples include polyimide, acrylic, polyimide amide, benzocyclobutene, polyamide, Heat-resistant organic materials such as epoxy can be used. , low-k materials, siloxane resins, PSG (phosphor glass), BPS G (phosphor boron glass), etc. can be used. Insulation formed from these materials A planarization insulating layer may be formed by stacking a plurality of films.

[0122] The siloxane resin is a Si—O— compound formed using a siloxane material as a starting material. It corresponds to a resin containing Si bonds. Siloxane resins contain organic groups (e.g., alkane) as substituents. Alternatively, an alkyl group or an aryl group, or a fluoro group may be used. It's fine.

[0123] The method for forming the planarization insulating layer 216 is not particularly limited, and may be a sputtering method depending on the material. , SOG method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater A coater, knife coater, etc. can be used.

[0124] Next, after removing the resist mask, a light-transmitting conductive film is formed. The conductive film material is indium oxide (In2O3) or indium oxide tin oxide alloy ( In2O3-SnO2 (abbreviated as ITO) and other materials are deposited by sputtering or vacuum deposition. As another material for the conductive film having light-transmitting properties, nitrogen-containing Al-Zn- O-based films, i.e., Al-Zn-ON-based films, Zn-O-based films containing nitrogen, and A Sn-Zn-O based film may also be used. The aluminum composition ratio ( The aluminum composition ratio (atomic %) in the Al-Zn-ON film is The composition ratio (atomic %) of nitrogen in the Al-Zn-ON film is larger than that in the Al-Zn-ON film. The etching process is carried out using a hydrochloric acid solution. However, when etching ITO in particular, residues are generated. Therefore, indium oxide zinc oxide alloy (In2O 3-ZnO) may also be used.

[0125] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and is measured by an electron probe microanalyzer. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be evaluated by analysis.

[0126] Next, a fourth photolithography step is performed to form a resist mask, and then etching is performed. Then, unnecessary portions are removed to form conductive layers 217a to 217c (see FIG. 6B). .).

[0127] In this manner, the driver circuit portion can be manufactured.

[0128] In the method for manufacturing the driver circuit section described with reference to FIGS. 5 and 6, the driver circuit is formed in the same process. Depletion-type transistors and enhancement-type transistors in the logic circuits Unwanted current flows between the transistor and the signal line or the element, electrode, or wiring electrically connected to the signal line. When a charge is accumulated, a depletion element is used as a switching element to release the accumulated charge. A cushion type transistor can be fabricated.

[0129] In the method for manufacturing the driver circuit portion described with reference to FIGS. 5 and 6, a resist mask is used. If the resist mask is formed by the inkjet method, the photoresist mask can be formed by the inkjet method. Since no mask is used, manufacturing costs can be reduced.

[0130] Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0131] (Embodiment 3) In this embodiment mode, another structural example of the driver circuit unit shown in Embodiment Mode 1 will be described.

[0132] An example of the structure of the driver circuit unit in this embodiment will be described with reference to FIG. 7A and 7B are diagrams showing an example of the structure of a drive circuit unit in the embodiment, FIG. 7A is a top view; FIG. 7B is a cross-sectional view taken along lines Z1-Z2 and Z3-Z4 in FIG. 7A.

[0133] The drive circuit shown in FIGS. 7(A) and 7(B) is the same as the drive circuit shown in FIGS. 2(A) and 2(B). Similarly to the path portion, a transistor 251, a transistor 252, and a and a transistor 253.

[0134] The transistor 251 and the transistor 252 are logic elements that form the driver circuit 111 shown in FIG. This is an example of an element used in a logic circuit, and when expressed as an equivalent circuit, it has the configuration shown in Figure 3. The transistor 253 is the same as the transistor 112 shown in FIG. The structure of each transistor will now be described.

[0135] The transistor 251 includes a gate electrode 211a provided on the substrate 201 and a gate electrode The gate insulating layer 202 is provided on the gate electrode 211a. an oxide semiconductor layer 243a provided on the electrode 211a; and a second insulating film provided on a part of the oxide semiconductor layer 263a. The conductive layer 215a and the conductive layer 215b are formed by bonding the conductive layer 215a and the conductive layer 215b together.

[0136] The transistor 252 includes a gate electrode 211b provided on the substrate 201 and a gate electrode The gate insulating layer 202 is provided on the gate electrode 211b. An oxide semiconductor layer 263b provided on the electrode 211b and a part of the oxide semiconductor layer 263b and conductive layers 215b and 215c provided on the respective conductive layers.

[0137] The transistor 253 includes a gate electrode 211c provided on the substrate 201 and a gate electrode The gate insulating layer 202 is provided on the gate electrode 211c. an oxide semiconductor layer 243b provided on the electrode 211c; and a second oxide semiconductor layer 263c formed on the first oxide semiconductor layer 263c. The conductive layer 215b and the conductive layer 215d are formed by the conductive layer 215a.

[0138] The conductive layers 215a to 215d function as source electrodes and drain electrodes, respectively. Possess the ability.

[0139] The oxide semiconductor layer 243a, the oxide semiconductor layer 243b, and the oxide semiconductor layer 263a The oxide semiconductor layer 263c is not only subjected to dehydration or dehydrogenation treatment but also to oxidation. The oxide insulating layer 207 is formed in contact with the oxide semiconductor layer 263a to the oxide semiconductor layer 263c. A transistor using the oxide semiconductor layer for a channel formation layer has a long-term use and a high High reliability as Vth shift due to load is unlikely to occur.

[0140] Note that a nitride insulating layer may be provided over the oxide insulating layer 207. The nitride insulating layer may be an oxide The insulating layer 207 is in contact with the gate insulating layer 202 or a base insulating layer provided below the insulating layer 207. It is preferable to remove moisture, hydrogen ions, and OH ions from the vicinity of the side surface of the substrate. - Impurities such as In particular, the gate insulating layer 202 or the oxide insulating layer 207 in contact with the gate insulating layer 202 In this case, it is effective to use a silicon nitride layer as the insulating layer serving as the base. By providing a silicon nitride layer so as to surround the front and side surfaces, the reliability of the display device is improved.

[0141] Also, on the oxide insulating layer 207 (on the nitride insulating layer if the nitride insulating layer is provided) A planarizing insulating layer may also be provided.

[0142] In addition, on the oxide insulating layer 207 (when the planarizing insulating layer is not provided and a nitride insulating layer is provided), on the nitride insulating layer, and on the planarizing insulating layer if the planarizing insulating layer is provided) The first conductive layer is formed on the oxide semiconductor layer 243a and the oxide semiconductor layer 263a with the layer 207 interposed therebetween. a second conductive layer is provided over the oxide semiconductor layer 263b with the oxide insulating layer 207 interposed therebetween; The oxide semiconductor layer 243b and the oxide semiconductor layer 263c are formed with the oxide insulating layer 207 interposed therebetween. The first conductive layer, the second conductive layer, and the third conductive layer may be formed on the first conductive layer. Each of them functions as a second gate electrode. By applying a gate voltage to the first conductive layer to the third conductive layer, the transistors 251 to The threshold voltage of the transistor 253 can be controlled.

[0143] In addition, the oxide semiconductor layer (the oxide semiconductor layer 243a and the oxide semiconductor layer 243b) included in the transistor 251 The thickness of the oxide semiconductor layer (stacked layer of the semiconductor layer 263a) is The thickness of the oxide semiconductor layer 263b of the transistor 253 is larger than that of the oxide semiconductor layer 263a. The thickness of the oxide semiconductor layer (the stack of the oxide semiconductor layer 243b and the oxide semiconductor layer 263c) is The thickness is larger than that of the oxide semiconductor layer (oxide semiconductor layer 263b) included in the sta 252. The larger the value of The absolute value of the required negative voltage of the gate electrode becomes large. As a result, a thick oxide layer is formed in the channel formation layer. Transistors using a nitride semiconductor layer exhibit depletion-type behavior.

[0144] As shown in FIGS. 7A and 7B as an example, the display device of this embodiment mode is By adjusting the thickness of the semiconductor layer, it is possible to fabricate a depletion type transistor and a A driver circuit including an enhancement type transistor and a signal line or a transistor electrically connected to the signal line When unnecessary charges are accumulated in the elements, electrodes, or wiring, the accumulated charges are released. and a depletion type transistor for achieving the desired output. Furthermore, the accumulation of charge can be reduced by using a bottom-gate transistor. When configuring a display device, even if charges are accumulated in the back channel portion, the accumulation The parasitic charge can be released to the reference voltage line via the signal line. It is also possible to suppress the occurrence of holes and reduce leakage current.

[0145] In addition, in the display device of this embodiment, as shown in FIG. 8, the transistor 251 is an oxide semiconductor. On the conductive layer 263a, an oxide conductive layer 214a and an oxide conductive layer 214b functioning as a pair of buffer layers are formed. The oxide conductive layer 214b is provided in contact with the oxide conductive layer 214a and the oxide conductive layer 214b. A pair of electrodes, that is, a conductive layer 215a and a conductive layer 215b, is provided on the transistor. The oxide semiconductor layer 263b is provided with a pair of conductive oxide layers 252, which function as buffer layers. The oxide conductive layer 214c and the oxide conductive layer 214d are provided. A pair of electrodes, ie, conductive layers 215b and 215c, are provided so as to contact 214d. The transistor 253 is provided over the oxide semiconductor layer 263c as a pair of buffer layers. The oxide conductive layer 214e and the oxide conductive layer 214f ​​are provided. The conductive layer 215b and the conductive layer 214f ​​are in contact with the oxide conductive layer 214e and the oxide conductive layer 214f. A layer 215d may also be provided.

[0146] The oxide conductive layers 214a to 214f ​​are formed by the oxide semiconductor layer 243a and 243b, and the oxide semiconductor layers 263a to 263c. The transistors 251, 252, and These serve as the source and drain regions of the transistor 253.

[0147] The oxide conductive layers 214a to 214f ​​are formed by using an oxide conductive material. The film may be made of a conductive material that is transparent to visible light, such as an In—Sn—O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-G a-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al -Zn-O, In-O, Sn-O, and Zn-O metal oxides can be used. The thickness of the oxide conductive film is set to be in the range of 1 nm to 300 nm. When using the annealing method, a metal oxide target containing 2% to 10% by weight of SiO2 is used. The transparent conductive film is formed using SiOx (x>0) which inhibits crystallization. This prevents crystallization during the heat treatment for dehydration or dehydrogenation in the subsequent process. It is preferable to suppress it.

[0148] Furthermore, when an In-Ga-Zn-O based film is used for the oxide semiconductor layer and the oxide conductive layer, the oxide semiconductor layers 243a and 243b which function as channel formation layers; The oxide semiconductor layers 263a to 263c, the source region, and the drain region are The oxide conductive layers 214a to 214f ​​functioning as the oxide conductive layers are formed under different deposition conditions. Therefore, they can be made differently.

[0149] For example, when a film is formed by a sputtering method, an oxide semiconductor film formed in argon gas is The formed oxide conductive layers 214a to 214f ​​have N-type conductivity and are active The conversion energy (ΔE) is 0.01 eV or more and 0.1 eV or less.

[0150] In this embodiment, the oxide conductive layers 214a to 214f ​​are formed of In The film is a Ga-Zn-O system film and contains at least an amorphous component. In addition, crystal grains (nanocrystals) are formed in the oxide conductive layers 214a to 214f. At this time, crystal grains in the oxide conductive layers 214a to 214f ​​may be included. (Nanocrystals) have a diameter of 1 nm to 10 nm, typically about 2 nm to 4 nm.

[0151] The oxide conductive layers 214a to 214f ​​are not necessarily provided, but an oxide semiconductor layer 243a and an oxide semiconductor layer 243b which function as a panel-forming layer; The oxide semiconductor layers 263a to 263c, the source electrode, and the drain electrode The oxide conductive layers 214a to 214d are disposed between the conductive layers 215a to 215d. The conductive layer 214f ​​provides a good electrical connection, and the transistor 251 The transistor 253 can perform stable operation even at a high drain voltage. High mobility can also be maintained.

[0152] Next, an example of a method for manufacturing the driver circuit portion shown in FIG. 7 will be described with reference to FIG. 8A and 8B are cross-sectional views showing an example of a method for manufacturing the driver circuit unit shown in FIG. 7.

[0153] First, a substrate 201 is prepared, and a conductive film is formed on the substrate 201 in the same manner as in the process shown in FIG. 5(A). After the formation of the conductive film, a resist mask is formed on a part of the conductive film by a first photolithography process. The conductive film is then etched using the resist mask to form the gate electrode 21. Gate electrodes 11a to 211c are formed.

[0154] Next, the resist mask is removed, and gate electrodes 211a to 211c are formed on the gate electrodes 211a to 211c. A gate insulating layer 202 is formed, and oxide semiconductor layers with different thicknesses are formed on the gate insulating layer 202. In this embodiment, a thick oxide film is formed on the gate electrode 211a with the gate insulating layer 202 sandwiched therebetween. A thin oxide semiconductor layer is formed on the gate electrode 211b with the gate insulating layer 202 sandwiched therebetween. A semiconductor layer is formed, and a thick oxide semiconductor is formed on the gate electrode 211c with the gate insulating layer 202 sandwiched therebetween. In this embodiment, the gate electrode 2 is formed with the gate insulating layer 202 sandwiched therebetween. As an example of a method for forming a thick oxide semiconductor layer on the gate electrode 211a and the gate electrode 211c, A method for forming an oxide semiconductor film overlying an island-shaped oxide semiconductor layer will be described.

[0155] First, a first oxide semiconductor film is formed. The first oxide semiconductor film is made of In—Ga—Zn— O-based film, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O The oxide semiconductor films are based on Al-Zn-O, In-O, Sn-O, and Zn-O. The first oxide semiconductor film is formed under a rare gas (typically, argon) atmosphere and an oxygen atmosphere. Sputtering method under an atmosphere of rare gas (typically argon) and oxygen When the sputtering method is used, SiO2 is used in a 2 wt. % or more and 10 wt % or less of a target containing ZnO, and The SiOx (x>0) is included, which is harmful to the SiOx, and the SiOx (x>0) is heated for dehydration or dehydrogenation in the subsequent process. During the treatment, it is preferable to prevent the oxide semiconductor layer to be formed later from being crystallized. stomach.

[0156] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), dehydration is performed. Hydrogenation or dehydrogenation is effective.

[0157] Here, an oxide semiconductor target containing In, Ga, and Zn (composition ratio: In2 O3:Ga2O3:ZnO=1:1:1 [molar ratio]) was used to The distance between the two was 100 mm, the pressure was 0.6 Pa, the DC power was 0.5 kW, and oxygen (oxygen flow) The oxide semiconductor film is formed in an atmosphere containing 100% of the fluorine-containing compound. The use of a film is preferable because it can reduce the amount of powdery material generated during film formation and also makes the film thickness distribution uniform. In this embodiment, the first oxide semiconductor film is an In—Ga—Zn—O-based oxide semiconductor. An In-Ga-Zn-O based film is formed by sputtering using a conductive target.

[0158] In this embodiment, the total thickness of the first oxide semiconductor film and the second oxide semiconductor film is The film thickness is preferably 50 nm or more and 100 nm or less. The appropriate thickness varies depending on the oxide semiconductor material, and the thickness may be selected appropriately depending on the material.

[0159] Before the first oxide semiconductor film was formed by sputtering, argon gas was introduced. The reverse sputtering is performed by introducing the silicon dioxide into the gate insulating layer 202 to generate plasma. It is preferable to remove the powdery material that is generated during the film formation. The substrate was then heated by applying a voltage to the substrate using an RF power supply in an argon atmosphere without applying a voltage to the substrate. This is a method of forming plasma on a plate to modify its surface. Note that the nitrogen atmosphere is used instead of the argon atmosphere. , helium, oxygen, etc. may also be used.

[0160] Next, a resist is formed on a part of the first oxide semiconductor film by a second photolithography process. forming a resist mask and etching the first oxide semiconductor film using the resist mask; The first oxide semiconductor film is processed into an island shape by the above-mentioned process. A base layer 243b is formed (see FIG. 9(A)). Thereafter, the oxide semiconductor layer 243a and the oxide semiconductor layer 243b are heated in an inert gas atmosphere (nitrogen, Heat treatment (400℃ or higher, up to 750℃) under helium, neon, argon, etc. (less than 1000 nm) to remove impurities such as hydrogen and water contained in the layer, and then the second oxide semiconductor It is preferable to form a solid film.

[0161] Next, the resist mask is removed, and a second oxide semiconductor film is formed. The film can be formed using the same material as the first oxide semiconductor film. The second oxide semiconductor film is preferably 5 nm or thicker. The thickness is set to 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be selected appropriately depending on the application.

[0162] The second oxide semiconductor film is formed on the oxide semiconductor layer 243a over the gate electrode 211a. On the other hand, on the gate electrode 211b, The oxide semiconductor film 2 is formed in contact with the gate insulating layer 202, and therefore has a thin oxide film. A second oxide semiconductor layer is formed on the gate electrode 211c. , and are stacked on the oxide semiconductor layer 243b to form a thick oxide semiconductor layer.

[0163] Next, a resist is formed on a part of the second oxide semiconductor film by a third photolithography process. forming a resist mask and etching the second oxide semiconductor film using the resist mask; The second oxide semiconductor film is processed into an island shape by the above-mentioned method. The oxide semiconductor layer 243a and the oxide semiconductor layer 263a are stacked to form a thick island-shaped oxide semiconductor layer. An oxide semiconductor layer 243b and an oxide semiconductor layer 243c are formed on the gate electrode 211c. The oxide semiconductor layer 263c is stacked on the gate electrode 263a to form a thick island-shaped oxide semiconductor layer. An oxide semiconductor layer 263c is formed over the electrode 211b (see FIG. 9B).

[0164] Next, the resist mask is removed, and the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment for dehydrogenation is preferably 400°C or higher and lower than 750°C. The temperature is usually between 425℃ and 750℃. If the temperature is between 425℃ and 750℃, the heat treatment is The heating time can be less than one hour, but if the temperature is below 425°C, the heating time should be longer than one hour. Here, the oxide semiconductor layer is formed in the upper part in an electric furnace, which is one of the heat treatment devices. The substrate on which the oxide semiconductor layer was formed was introduced, and heat treatment was performed on the oxide semiconductor layer in a nitrogen atmosphere. After that, the oxide semiconductor layer is not exposed to the air, preventing water and hydrogen from re-entering the oxide semiconductor layer. In this state, the temperature is increased from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated to a temperature at which water does not enter again. The same furnace is used until the temperature reaches a sufficient level, specifically, until the temperature drops by 100°C or more below the heating temperature T. The atmosphere is not limited to nitrogen, and may be helium, neon, or argon. Dehydration or dehydrogenation is carried out under a rare gas atmosphere such as toluene.

[0165] The heat treatment device is not limited to an electric furnace, and may be, for example, a GRTA (Gas Rapid T thermal annealing) equipment, LRTA (Lamp Rapid Thermal) RTA (Rapid Thermal Anneal) equipment such as LRTA devices can be used with halogen lamps, metal halide lamps, xenon lamps, etc. Arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. This device heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp. The device heats the gas by thermal radiation from the light emitted from the lamp and the light emitted from the lamp. The object to be treated is heated by thermal conduction from the heated gas. An inert gas such as a rare gas such as argon or nitrogen that does not react with the material to be treated by heat treatment. In addition, the LRTA and GRTA devices use not only lamps but also resistive gases. It may also be equipped with a device that heats the object to be treated by heat conduction or heat radiation from a heating element such as a heater. good.

[0166] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. or 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably It is preferable to keep the concentration below 0.1 ppm.

[0167] Note that depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may It may crystallize to form a microcrystalline or polycrystalline layer. For example, the crystallization rate may be 90% or more. In some cases, the oxide semiconductor layer is microcrystalline at 80% or more. Alternatively, depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer containing no crystalline components. This may also be the case.

[0168] After the first heat treatment, the oxide semiconductor layer becomes oxygen-deficient, becomes n-type, and has low resistance. The oxide semiconductor layer after the heat treatment in 1 has a higher carrier concentration than the oxide semiconductor layer immediately after deposition. Preferably, 1×10 18 / cm 3 The oxide semiconductor layer has a carrier concentration of 1000 or more. do.

[0169] The gate electrodes 211a, 211b, and 211c are formed by the first process. Depending on the heat treatment conditions or the material, it may crystallize and become a microcrystalline or polycrystalline layer. For example, the gate electrode 211a, the gate electrode 211b, and the gate electrode 211c are When an indium oxide tin oxide alloy layer is used, the first heat treatment at 450°C for 1 hour results in crystallization. and oxidized to form gate electrodes 211a, 211b, and 211c. When an indium oxide tin oxide alloy film containing silicon is used, crystallization does not occur.

[0170] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0171] Next, the gate insulating layer 202 and the oxide semiconductor layer 263 are formed in the same manner as in the step shown in FIG. The source and drain electrodes of the transistor are formed over the oxide semiconductor layers 263a to 263c. A conductive film for forming the conductive layer is formed, and a third photolithography process is performed to form a pattern on a part of the conductive film. A resist mask is formed, and the conductive film is etched to form conductive layers 215a to 215d. The resist mask is removed, and the gate insulating layer 202 and the oxide semiconductor layers 263a to 263b are removed. The oxide insulating layer 207 is formed on the oxide semiconductor layer 263c. Parts of the oxide semiconductor layers 63a to 263c are in contact with the oxide insulating layer 207.

[0172] Note that after the oxide insulating layer 207 is formed, second heat treatment (preferably at a temperature of 200° C. or higher and 40° C. or higher) is performed. 0°C or less, for example, 250°C to 350°C) in an inert gas atmosphere or nitrogen gas atmosphere For example, the second heat treatment may be performed at 250° C. for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, parts of the oxide semiconductor layers 263a to 263c are removed. The oxide semiconductor layers 263a to 263b are heated in contact with the oxide insulating layer 207. The other part of the compound semiconductor layer 263c is heated in a state where it is in contact with the conductive layers 215a to 215d. will be done.

[0173] The oxide semiconductor layers 263a to 263c whose resistance is reduced by the first heat treatment When the second heat treatment is performed while the oxide insulating layer 207 is in contact with the oxide insulating layer 207, the oxide insulating layer 207 As a result, the oxide semiconductor layer 26 The oxide semiconductor layers 3a to 263c are formed in regions in contact with the oxide insulating layer 207. The layers 263a to 263c are made i-type (have high resistance) in the depth direction.

[0174] On the other hand, the oxide semiconductor layer 243a and the oxide semiconductor layer 263a are stacked together to form a large oxide semiconductor layer. The oxide semiconductor layer 243b and the oxide semiconductor layer 263c are stacked to form a large film thickness. In the oxide semiconductor layer, the thickness of the oxide insulating layer 207 is also increased from the interface with the gate insulating layer 20 2, an I-type (high resistance) region is formed. 3a and the oxide semiconductor layer 263a, and the oxide semiconductor layer 243b and the oxide semiconductor layer 26 Since the layered structure of 3c is thick, it is I-shaped (high resistance) up to the interface where it contacts the gate insulating layer 202. The oxide semiconductor layer in which the resistance change does not progress and a region with low resistance remains in the channel formation region. This becomes:

[0175] In this way, the transistors in the driving circuit section of this embodiment are made high resistance (I-type) The channel formation layer has oxide semiconductor layers with different regions. The transistors will have different operating characteristics.

[0176] The transistor 251 has a thick oxide semiconductor layer and a low resistance layer in part of a channel formation layer. Since the oxide semiconductor layer is formed as it is, the threshold voltage shows a negative value, and the depth The transistor 252 has a thin oxide semiconductor layer. Since an i-type (high-resistance) oxide semiconductor layer is formed in the channel formation layer, , the threshold voltage is positive, and the transistor 25 exhibits enhancement-type behavior. 3 has a thick oxide semiconductor layer, and a part of the channel forming layer is left with low resistance. Since a nitride semiconductor layer is formed, the threshold voltage shows a negative value, and the behavior is depletion-type. Shows.

[0177] Note that the conductive layers 215a to 215d each formed of a metal conductive film and the oxide semiconductor layer 243 a stack of the oxide semiconductor layer 243a and the oxide semiconductor layer 263a, or a stack of the oxide semiconductor layer 243b and the oxide semiconductor layer 263 When the second heat treatment is performed on the region where the stack of layers c contacts, oxygen easily moves to the metal conductive film side. The oxide semiconductor layer becomes N-type. In this case, the area near the interface with the metal conductive film becomes N-type, but the area below it becomes I-type or N-type. - Type It becomes a transformed state.

[0178] In this manner, the driver circuit portion shown in FIG. 7 can be manufactured (see FIG. 9C).

[0179] In the method for manufacturing the driver circuit section described with reference to FIGS. 5 and 6, the driver circuit is formed in the same process. Depletion-type transistors and enhancement-type transistors in the logic circuits Unwanted current flows between the transistor and the signal line or the element, electrode, or wiring electrically connected to the signal line. Depletion-type transistor for discharging the accumulated charge when a charge is accumulated. In addition, a display device using a transistor including an oxide semiconductor can be provided. Even if the voltage is too high, the leakage current can be reduced.

[0180] In the method for manufacturing the driver circuit portion described with reference to FIG. 9, the resist mask is formed by inkjet printing. If the resist mask is formed by the ink-jet method, the photomask Since no external power supply is used, manufacturing costs can be reduced.

[0181] Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0182] (Fourth embodiment) In this embodiment, a sequential logic applicable to a driver circuit in a display device according to one embodiment of the present invention will be described. The logic circuit will now be described.

[0183] The circuit configuration of a logic circuit using a combinational circuit will be explained using Figure 10. FIG. 2 is a circuit diagram showing a circuit configuration of a logic circuit according to the present embodiment.

[0184] The logic circuit shown in FIG. 10 includes a transistor 611, an inverter 6121, and an inverter 6122. 122, an inverter 6123, and a transistor 613.

[0185] The transistor 611 receives a first clock signal (also referred to as CL1) at its gate. A first signal is input to one of the source and the drain. The signal that is input is also called the input signal, and the voltage of the input signal is also called Vin.

[0186] The inverter 6121 has an input terminal connected to the other of the source and drain of the transistor 611. electrically connected.

[0187] The input terminal of the inverter 6122 is electrically connected to the output terminal of the inverter 6121. .

[0188] The inverter 6123 has an input terminal electrically connected to the output terminal of the inverter 6121, The second signal is output from the output terminal. The signal output by the inverter 6123 is used as the output signal. The voltage of the output signal is also called Vout.

[0189] The logic circuit shown in FIG. 3 is applied to each of the inverters 6121 to 6123. It is possible.

[0190] A second clock signal (also referred to as CL2) is input to the gate of the transistor 613. One of the source and drain of the transistor 611 is electrically connected to the other of the source and drain of the transistor 612. The other of the source and drain is electrically connected to the output terminal of the inverter 6122. do.

[0191] The first clock signal and the second clock signal have two states: a high state and a low state. At this time, the high state or a voltage equivalent to the high state is also called VH, and the low state or a voltage equivalent to the low state is also called VH. The voltage equivalent to this is also called VL.

[0192] The first clock signal and the second clock signal have opposite phases, for example, During a given period, when the first clock signal is in a high state, the second clock signal is When the first clock signal is in a low state, the second clock signal is in a high state. This is the state.

[0193] In this embodiment, the first clock signal is input to the gate of the transistor 611. , a case where a second clock signal is input to the gate of the transistor 613 will be described. However, the present invention is not limited to this. For example, a second clock signal is input to the gate of the transistor 611, The first clock signal may be input to the gate of the transistor 613. .

[0194] Next, the operation of the logic circuit shown in FIG. 10 will be explained with reference to FIG. 11. 10 is a timing chart illustrating the operation of the logic circuit shown in FIG.

[0195] The operation of the logic circuit shown in Figure 10 can be divided into four periods. This is explained below.

[0196] First, in the first period, the first clock signal is in a high state as shown in FIG. When the clock signal goes low, transistor 611 turns on, The transistor 613 is turned off. Furthermore, the input signal is turned high. The pressure becomes VH.

[0197] At this time, since the transistor 611 is in an on state, the voltage of the node 614 (V614 Furthermore, the voltage at node 614 is applied to the input terminal of inverter 6121. Therefore, the inverter 6121 outputs a signal VL, and the voltage of the node 615 ( Furthermore, the voltage of node 615 is equal to the voltage of inverter 6122. Since it is given to the input terminal, the VH signal is output from the inverter 6122. Since the resistor 613 is in the off state, the voltage of the output signal of the inverter 6122 is applied to the node 614. The potential of the node 615 is also applied to the input terminal of the inverter 6123. Therefore, the inverter 6123 outputs a VH signal. It is an action.

[0198] Next, in the second period, the first clock signal goes low as shown in FIG. The high state of the clock signal turns off transistor 611, The transistor 613 is turned on, and the input signal is turned low.

[0199] At this time, since the transistor 611 is in an off state, even if the input signal is in a low state, V 614=VH. Furthermore, the potential of the node 614 is maintained at the input of the inverter 6121. Since the voltage is applied to the output terminal, the VL signal is output from inverter 6121, and V615 = V Furthermore, the potential of the node 615 is applied to the input terminal of the inverter 6122. Then, the inverter 6122 outputs a VH signal, and the transistor 613 turns on. In this state, the potential of the signal from the inverter 6122 is applied to the node 614. The potential of 615 is also given to the input terminal of inverter 6123, so inverter 6123 A VH signal is output from the output terminal 1. The above is the operation in the second period.

[0200] Next, in the third period, the first clock signal goes high and the second clock signal goes high as shown in FIG. When the clock signal goes low, transistor 611 turns on. The transistor 613 is turned off. Furthermore, Vin remains equal to VL.

[0201] At this time, since the transistor 611 is in an on state, V614=VL. The potential of the board 614 is applied to the input terminal of the inverter 6121, A signal of VH is output from node 615, and V615=VH. Since the voltage is applied to the input terminal of the inverter 6122, the VL signal is output from the inverter 6122. However, since the transistor 613 is in an off state, the node 614 is connected to the inverter 612. The voltage of the output signal of inverter 6123 is not applied. Since it is also given to the input terminal, the VL signal is output from the inverter 6123. This is the operation in the third period.

[0202] Next, in the fourth period, the first clock signal goes low and the second clock signal goes high as shown in FIG. The high state of the clock signal turns off transistor 611, The transistor 613 is turned on. Furthermore, Vin remains equal to VL.

[0203] At this time, since the transistor 611 is in the off state, V614 is maintained at VL. Furthermore, since V614=VL, a VH signal is output from inverter 6121, V615 is maintained at VH. Furthermore, since V615 is VH, inverter 6122 Since the transistor 613 is on, the signal VL is output from the node 614. The voltage of the signal of inverter 6122 is applied to node 615. This is also given to the input terminal of inverter 6123, so the VL signal is output from inverter 6123. The above is the operation in the fourth period.

[0204] By the above operation, the logic circuit shown in FIG. 10 generates an output signal based on the state of the input signal. It can be achieved.

[0205] (Embodiment 5) In this embodiment, a shift register according to one embodiment of the present invention will be described.

[0206] The shift register in this embodiment has a plurality of sequential logic circuits. The specific configuration is shown in Figure 12. 12 is a circuit diagram showing the configuration of a shift register in this embodiment.

[0207] The shift register shown in FIG. 12 includes a logic circuit 3011, a logic circuit 3012, and a logic circuit 3013. 013, a NAND circuit 3140, a NAND circuit 3141, and a NAND circuit 3142. 12, the NAND circuit 3143 is arranged in three stages (also referred to as three stages). Although a logic circuit is shown, it is not limited to this and any circuit having two or more stages may be used.

[0208] In FIG. 12, the logic circuit constituting the shift register is, for example, the logic circuit shown in the fourth embodiment. A logic circuit including a transistor 611 and a transistor 613 is included. .

[0209] The logic circuit 3011 includes a transistor 3111, an inverter 3121A, and an inverter 3121B. Logic circuit 3 includes a transistor 3131, an inverter 3122A, an inverter 3123A, and a transistor 3131. In 011, the first clock signal is input to the gate of the transistor 3111, and the transistor The second clock signal is input to the gate of the starter 3131 .

[0210] The logic circuit 3012 includes a transistor 3112, an inverter 3121B, and an inverter 3121C. 122B, an inverter 3123B, and a transistor 3132. In the circuit 3012, a second clock signal is input to the gate of the transistor 3112. The first clock signal is input to the gate of the transistor 3132 .

[0211] The logic circuit 3013 includes a transistor 3113, an inverter 3121C, and an inverter 3122C. 122C, an inverter 3123C, and a transistor 3133. In the circuit 3013, a first clock signal is input to the gate of the transistor 3113. The second clock signal is input to the gate of the transistor 3133 .

[0212] In addition, the logic circuit 3011 has an output terminal of the inverter 3123A. The logic circuit 30 is electrically connected to one of the source and drain of the transistor 3112. 12 is a diagram showing the output terminal of the inverter 3123B and the transistor 31 in the logic circuit 3013. 13. The transistor 13 is electrically connected to one of the source and drain of the transistor 13.

[0213] Furthermore, the logic circuit 3011 has a transistor 3111 in which one of the source and drain is NA. The inverter 3123A is electrically connected to a first input terminal of the ND circuit 3140. The input terminal is connected to the second input terminal of the NAND circuit 3140 and the first input terminal of the NAND circuit 3141. The logic circuit 3012 is electrically connected to the source and One of the drains is connected to the second input terminal of the NAND circuit 3140 and the other to the drain of the NAND circuit 3141. The output terminal of the inverter 3123B is electrically connected to the first input terminal of the NAND circuit 3123B. 141 and a first input terminal of the NAND circuit 3142. In addition, the logic circuit 3013 is configured such that one of the source and drain of the transistor 3113 is A second input terminal of the NAND circuit 3141 and a first input terminal of the NAND circuit 3142 are supplied with a voltage. The output terminal of the inverter 3123C is electrically connected to the second input terminal of the NAND circuit 3142. terminal and the first input terminal of the NAND circuit 3143. One of the source and drain of the transistor 3111 in the circuit 3011 and the NAND circuit The connection point of the first input terminal of the circuit 3140 is also referred to as a node 316 .

[0214] The NAND circuits 3140 to 3143 are all transistors that form logic circuits. The transistors can be configured using the same conductivity type as the transistors. By using a capacitor, it can be formed in the same process as the logic circuit, making fabrication easier. The circuit configuration of a NAND circuit using transistors of the same conductivity type is shown in Figure 13. 13 is a circuit diagram showing the circuit configuration of the NAND circuit in this embodiment. .

[0215] The NAND circuit shown in FIG. 13 includes a transistor 321, a transistor 322, and a transistor 323.

[0216] The transistor 321 is a depletion-mode transistor, and one of the source and drain One of the source and drain is electrically connected to a power supply line 325, and a high power supply voltage is applied to one of the source and drain. The gate is electrically connected to the other of the source and the drain.

[0217] The transistor 322 is an enhancement type transistor, and the source and drain One of the terminals is electrically connected to the other of the source and drain of the transistor 321 .

[0218] The transistor 323 is an enhancement type transistor, and the source and drain One of the terminals is electrically connected to the other of the source and drain of the transistor 322, and the other of the terminals is electrically connected to the source and drain of the transistor 322. The other of the source and drain is electrically connected to a power supply line 324, and a low voltage is applied to the other of the source and drain. A source voltage is applied.

[0219] In the logic circuit of this embodiment, the first input signal is input to the gate of the transistor 323. The second input signal is input to the gate of transistor 322, and the second input signal is input to the gate of transistor 321. The voltage at node 326 (also called V326) between transistor 322 and the Be encouraged.

[0220] Next, the operation of the NAND circuit shown in FIG. 13 will be described.

[0221] The operation of the NAND circuit shown in FIG. 13 is performed by determining the voltage of the first input signal (also referred to as Vin1) and At least one or all of the voltages of the first and second input signals (Vin2) are low voltages, or The voltage of the input signal and the voltage of the second input signal can be divided into two types depending on whether they are high voltages or not. Each case will be explained. In this embodiment, the The explanation will be given assuming that the low state is data 0 and the high state is data 1. However, it is not limited to this, and when it is in a low state, it is data 1, and when it is in a high state, it is data 0. It is also possible to do so.

[0222] First, Vin1=VH and Vin2=VL, Vin1=VL and Vin2=VH, and V When Vin1=VL and Vin2=VL, the voltages of transistors 322 and 323 are One or both of the transistors are turned off, and the resistance values ​​( R322+R323) is greater than the resistance of transistor 321 (also called R321). In other words, R322+R323>R321, so V326=VH, The voltage of the output signal (also called Vout) is VH.

[0223] Also, when Vin1=VH and Vin2=VH, the transistor 321 and the transistor 322 is turned on, R322+R323 <R321となるため、V326=VLと Therefore, Vout=VL. This is the operation of the NAND circuit shown in FIG.

[0224] As described above, by configuring the NAND circuit with transistors of the same conductivity type, The logic circuit can be manufactured in the same process as the logic circuit shown in FIG. Other circuit configurations may also be applied as long as they have the function.

[0225] Next, an example of the operation of the shift register shown in FIG. 12 will be described with reference to FIG. 4 is a timing chart showing the operation of the shift register shown in FIG.

[0226] The operation of the shift register in this embodiment is divided into 10 periods as shown in FIG. In the first period, the voltage Vin of the input signal to the logic circuit 3011 becomes VH, and in the second period, From the second period to the third period, the node 317 between the logic circuit 3011 and the logic circuit 3012 The voltage of 1 (also called V3171) changes from VH to VL. In the period 4, the voltage of the output signal of the NAND circuit 3140 becomes VH.

[0227] The logic circuit 3012 receives the input signal (the output signal) changes from VL to VH, and the logic circuit 301 The voltage at node 3172 (also called V3172) between node 2 and logic circuit 3013 is changed from VH to VL In the sixth and seventh periods, the voltage of the output signal of the NAND circuit 3141 changes to becomes VH.

[0228] The logic circuit 3013 receives the input signal (the output signal) changes from VL to VH, and the logic circuit 301 The voltage at node 3173 (also called V3173) between 3 and the next logic circuit changes from VH to VL. The voltage of the output signal of the NAND circuit 3142 in the ninth and tenth periods becomes VH.

[0229] If another logic circuit is connected to the output terminal of the logic circuit 3013, the other logic circuit As mentioned above, the input signal changes from VL to VH during a certain period, and The output signal changes to VH. Furthermore, during the period when the output signal of another logic circuit is VL, The voltage of the output signal of the AND circuit 3143 becomes VH.

[0230] As described above, a shift register is formed using a logic circuit having TFTs using an oxide semiconductor. In addition, TFTs using oxide semiconductors can be constructed in a manner similar to conventional amorphous silicon. Since the mobility is higher than that of TFTs using oxide semiconductors, TFTs using oxide semiconductors are used for shift registers. By applying the above, the shift register can be driven at high speed.

[0231] Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0232] (Embodiment 6) In this embodiment, another structural example of the display device according to one embodiment of the present invention will be described.

[0233] The display device according to one embodiment of the present invention is, for example, a liquid crystal display device or an electroluminescence display device. The display device according to the present embodiment can be configured as various display devices. This will be described with reference to FIG. 15. FIG. 15 is a block diagram showing the configuration of the display device according to this embodiment. This is a block diagram.

[0234] As shown in FIG. 15, the display device of this embodiment includes a pixel portion 701 and a scanning line driving circuit. The signal line driver circuit 703 includes a signal line driver circuit 702 .

[0235] The pixel section 701 has a dot matrix structure having a plurality of pixels 704. Specifically, The pixels 704 are arranged in rows and columns. and is electrically connected to the scanning line driving circuit 702 via a signal line. 15. In FIG. 15, the scanning lines and signal lines are shown as For example, the scanning line corresponds to the scanning line 105 shown in FIG. 1, and the signal line corresponds to the 1 corresponds to the signal line 103. The scanning line 107 shown in FIG. It can also be controlled by the same scanning line driving circuit as the scanning lines.

[0236] The scanning line driving circuit 702 is a circuit for selecting pixels 704 to which a data signal is input. A selection signal is output to the pixel 704 via a line.

[0237] The signal line driver circuit 703 is a circuit that outputs data to be written to the pixel 704 as a signal. Pixel data is sent to the pixel 704 selected by the scanning line driving circuit 702 via the signal line. In addition, the display device of this embodiment uses the same transistor 112 as that shown in FIG. When the transistor is electrically connected to the signal line and is turned on, the signal line and the reference voltage line are connected. It has a transistor for turning on the transistor.

[0238] The pixel 704 is composed of at least a display element and a switching element. For example, a light emitting element such as a liquid crystal element or an EL element can be used. The element may be, for example, a transistor.

[0239] Next, a configuration example of the scanning line driver circuit 702 and the signal line driver circuit 703 will be explained with reference to FIG. FIG. 16 is a block diagram showing the configuration of the driving circuit, and FIG. 16(A) shows the scanning line driving circuit. FIG. 16(B) is a block diagram showing the configuration of a signal line driver circuit. This is a diagram.

[0240] First, the scanning line driving circuit 702 includes a shift register 900, a level The shifter 901 and the buffer 902 are included.

[0241] The shift register 900 receives a gate start pulse (GSP), a gate clock signal (GC K) are input, and each sequential logic circuit outputs a selection signal in sequence. The shift register shown in the above-described embodiment 2 can be applied to the shift register 900. do.

[0242] 16B, the signal line driver circuit 703 includes a shift register 903, a A first latch circuit 904, a second latch circuit 905, a level shifter 906, and a buffer 907 and,

[0243] A signal such as a start pulse (SSP) is input to the shift register 903, and each sequential logic The logic circuit outputs the selection signals sequentially.

[0244] A data signal is input to the first latch circuit 904. The first latch circuit is, for example, The logic circuit can be configured using one or more of the logic circuits described in the embodiment modes.

[0245] The buffer 907 has a function of amplifying a signal and includes an operational amplifier. 07 is configured using one or more of the logic circuits shown in the above embodiments, for example. It is possible.

[0246] The second latch circuit 905 can temporarily hold a latch (LAT) signal. The latched signals are simultaneously output to the pixel section 701 in FIG. 15. This is called line sequential driving. Therefore, if the pixel is driven dot-sequentially rather than line-sequentially, the second latch circuit The second latch circuit 905 may be omitted. The present invention can be configured using one or more of the logic circuits shown in the embodiments.

[0247] Next, the operation of the display device shown in FIG. 15 will be described.

[0248] First, a scanning line is selected by the scanning line driving circuit 702, and the pixel 70 connected to the selected scanning line is 4 is a signal line driver circuit that is driven by a signal input from a scanning line driver circuit 702 via a signal line. A data signal is output from 703. As a result, the pixel 70 connected to the selected scanning line is 4 is written with data and becomes a display state. Also, if there are multiple scanning lines, The scanning lines are selected sequentially by the scanning line driving circuit 702, and data is input to all the pixels 704. The writing is performed. The above is the operation of the display device according to this embodiment.

[0249] The circuits of the display device shown in FIG. 15 can all be provided on the same substrate. It can be configured with a transistor of the same conductivity type. The process can be simplified by using transistors of the same conductivity type. It is possible.

[0250] Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0251] (Embodiment 7) In this embodiment, a liquid crystal display device is used as an example of the display device shown in the sixth embodiment. I will explain.

[0252] An example of a circuit configuration of a pixel in a display device in this embodiment will be described with reference to FIG. 17 is a circuit diagram showing the circuit configuration of a pixel of the display device according to the present embodiment.

[0253] As shown in FIG. 17, the pixel includes a transistor 821, a liquid crystal element 822, and a capacitor 82 3 and has.

[0254] The transistor 821 functions as a selection switch, and the gate is electrically connected to the scanning line 804. One of the source and drain is electrically connected to a signal line 805 .

[0255] The liquid crystal element 822 has a first terminal and a second terminal. The first terminal is connected to the source of the transistor 821. The second terminal is electrically connected to the other of the source and drain, and the ground potential or a constant voltage is applied to the second terminal. The liquid crystal element 822 has a first electrode which is a part or the whole of the first terminal and a second electrode which is a part or the whole of the second terminal. A voltage is applied between the second electrode, which is a part or all of the first electrode, and the second electrode. The liquid crystal layer is made up of a layer containing liquid crystal molecules whose transmittance changes depending on the applied voltage.

[0256] The capacitor 823 has a first terminal and a second terminal. The first terminal is connected to the source of the transistor 821. The second terminal is electrically connected to the other of the source and drain, and the ground potential or a constant voltage is applied to the second terminal. The capacitor 823 has a first electrode which is a part or the whole of the first terminal and a second electrode which is a part or the whole of the second terminal. The capacitor element 823 is configured by a part or the whole of the second electrode and a dielectric layer. The capacitor 823 does not necessarily have to be provided. By providing the capacitor 823, the influence of the leakage current of the transistor 821 can be suppressed. It can be controlled.

[0257] The display device in this embodiment is a TN (Twisted Nematic) model. Mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Ve rtical Alignment) mode, PVA(Patterned Verti cal Alignment) mode, ASM (Axially Symmetric) mode aligned micro-cell mode, OCB (Optically Com Pensated Birefringence mode, FLC (Ferroelec tric Liquid Crystal) mode, AFLC (AntiFerroel) mode You can use modes such as Electric Liquid Crystal.

[0258] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. To achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used in the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs to 100 μs. It has a short wavelength of s, is optically isotropic, does not require alignment treatment, and has little viewing angle dependency.

[0259] Next, the operation of the pixel shown in FIG. 17 will be described.

[0260] First, a pixel to which data is to be written is selected. The selected pixel receives input from the scan line 804. The signal causes the transistor 821 to turn on.

[0261] At this time, the data signal from the signal line 805 is input via the transistor 821, and the liquid crystal The voltage at the first terminal of the element 822 is the voltage of the data signal, and the liquid crystal element 822 is The transmittance is set according to the voltage applied between the two terminals. After writing the data, the scan line 8 The transistor 821 is turned off by a signal input from the line 04, and the liquid crystal element 822 The set transmittance is maintained during the display period, and the display state is achieved. The above operations are carried out for all pixels in sequence.

[0262] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, causing image retention, or In order to improve the moving image characteristics of LCD devices, There is a driving technique called black insertion, which displays every other frame.

[0263] In addition, the response speed is improved by increasing the normal vertical synchronization frequency by 1.5 times, preferably by more than 2 times. There is also a driving technology called double speed driving, which achieves this.

[0264] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode light source or multiple EL light sources. There is also a driving technology that drives each light source to light intermittently within one frame period. Three or more types of LEDs may be used, or white light emitting LEDs may be used. Since it is possible to control a large number of LEDs, the LEDs can be switched in accordance with the timing of the optical modulation of the liquid crystal layer. This driving technology can also synchronize the timing of LEDs to be turned off partially. This is especially useful when the image display has a large proportion of black areas occupying the entire screen. This can reduce power consumption.

[0265] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0266] Next, the structure of the display device including the above-described pixels according to this embodiment will be described with reference to FIG. FIG. 18 is a diagram showing the structure of a pixel of a display device in this embodiment mode. 18(A) is a top view, and FIG. 18(B) is a cross-sectional view. The dotted lines B1-B2 correspond to the cross sections A1-A2 and B1-B2 in FIG. 18(B). do.

[0267] As shown in FIGS. 18A and 18B, the display device according to the present embodiment includes A1- In the cross section A2, a gate electrode 2001 is formed on a substrate 2000, and a gate electrode 2001 is formed on the gate electrode 2001. an insulating film 2002 provided thereon; and an oxide semiconductor layer 2003 provided thereon. a pair of electrodes 2005a and 2005b provided over the oxide semiconductor layer 2003; The oxide insulating film provided on the electrode 2005a, the electrode 2005b, and the oxide semiconductor layer 2003 The insulating layer 2007 is connected to the electrode 2005b through an opening provided in the insulating oxide layer 2007. and an electrode 2020.

[0268] In the cross section of B1-B2, an electrode 2008 is provided on the substrate 2000, and a An insulating film 2002, an oxide insulating layer 2007 provided on the insulating film 2002, and an oxide insulating and an electrode 2020 provided on the layer 2007.

[0269] Electrode 2022 and electrode 2029, and electrodes 2023, 2024, and 2028 It serves as an electrode or wiring for connecting to the FPC.

[0270] The transistor used in this embodiment is, for example, the transistor 252 shown in FIG. Therefore, detailed explanations will be omitted here.

[0271] The electrodes 2020, 2022, and 2028 are made of indium oxide (In2O3) or oxide. Indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO) is used to It is formed by sputtering or vacuum deposition. Etching of such materials is It is done using a hydrochloric acid solution. However, since etching ITO is particularly prone to leaving residue, Indium oxide-zinc oxide alloy (In2O3-ZnO) to improve etching processability may also be used.

[0272] 19(A1) and 19(A2) are a top view and a cross-sectional view of the gate wiring terminal portion, respectively. FIG. 19(A1) is a cross-sectional view taken along the line C1-C2 in FIG. 19(A2). In FIG. 19(A1), the transparent conductive film 20 formed on the protective insulating film 2054 55 is a terminal electrode for connection that functions as an input terminal. In the terminal section, a first terminal 2051 made of the same material as the gate wiring and a source wiring The connection electrode 2053 made of the same material as the gate insulating layer 2052 overlaps with the transparent The connection electrode 2053 is electrically connected via the conductive film 2055. The transparent conductive film 2055 is electrically connected to the contact hole formed through the transparent conductive film 2055. do.

[0273] 19(B1) and 19(B2) are a top view and a cross-sectional view of a source wiring terminal portion. Also, Fig. 19(B1) is taken along the line C3-C4 in Fig. 19(B2). In FIG. 19(B1), a transparent insulating film formed on the protective insulating film 2054 is The conductive film 2055 is a terminal electrode for connection that functions as an input terminal. In 1), the electrode 2056 made of the same material as the gate wiring is connected to the source A gate insulating layer 2052 is placed below a second terminal 2050 that is electrically connected to a wiring. The electrode 2056 is not electrically connected to the second terminal 2050. is set to a potential different from that of the second terminal 2050, for example, floating, GND, 0V, etc. This makes it possible to form a capacitance for noise countermeasures or static electricity countermeasures. The second terminal 2050 is connected to a contact hole provided through the protective insulating film 2054. It is electrically connected to the transparent conductive film 2055 by the

[0274] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0275] In this way, the pixel TFT portion having the bottom gate type N-channel TFT, the holding Then, these are connected to the individual pixels in a matrix. An active matrix display device is fabricated by arranging the electrodes in a pattern to form a pixel section. For convenience, such a substrate is referred to herein as an active substrate. This is called a matrix substrate.

[0276] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for connecting the

[0277] The N-channel transistor obtained in this embodiment is made of an In-Ga-Zn-O based film. These driving technologies are combined to produce a high-quality, high-performance optical fiber. It is possible.

[0278] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of the organic light-emitting element is In order to set a low power supply voltage, for example, GND or 0V, the cathode is connected to the terminal. A fourth terminal is provided for setting the voltage, for example, GND, 0V, etc. When manufacturing a device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a fifth terminal that is electrically connected to the power supply line.

[0279] The gate line driving circuit or the source line driving circuit is formed by TFTs using an oxide semiconductor. This reduces the manufacturing cost. By directly connecting the line or drain wiring, the number of contact holes is reduced, and A display device capable of reducing the area occupied by circuits can be provided.

[0280] Therefore, according to this embodiment, a display device with high electrical characteristics and high reliability can be provided at low cost. It is possible.

[0281] Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0282] (Embodiment 8) In this embodiment mode, a light-emitting display device will be described as an example of the display device described in Embodiment Mode 6. In the present embodiment, electroluminescence is used as an example of a light emitting element. A light-emitting display device using the above-mentioned structure will be described.

[0283] Light-emitting elements that utilize electroluminescence are either organic or inorganic. Generally, the former is an organic EL element, and the latter is an inorganic EL element. It is called.

[0284] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. These carriers are then injected into a layer containing a light-emitting organic compound, causing a current to flow. The recombination of electrons and holes causes light emission. Such a light-emitting element is called a current-excited light-emitting element.

[0285] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0286] The circuit configuration of a pixel of a display device in this embodiment will be described with reference to FIG. 1 is a circuit diagram showing the circuit configuration of a pixel of a display device according to the present embodiment.

[0287] As shown in FIG. 20, a pixel of the display device according to the embodiment includes a transistor 851 and a pixel A capacitor 852 having a function as a storage capacitor, a transistor 853, and a light-emitting element 854 and has.

[0288] The transistor 851 has a gate electrically connected to a scanning line 855 and a source and a drain One of them is electrically connected to a signal line 856 .

[0289] The capacitive element 852 has a first terminal and a second terminal. The first terminal of the capacitive element 852 is connected to a transformer. The second terminal of the capacitor 852 is electrically connected to the other of the source and drain of the resistor 851. A high power supply voltage is applied to the child.

[0290] The transistor 853 has a gate electrically connected to the other of the source and drain of the transistor 851. The transistor is electrically connected to one of the source and drain, and a high power supply voltage is applied to the other of the source and drain.

[0291] The light emitting element 854 includes a first terminal and a second terminal, and the first terminal is connected to the source of the transistor 853. The second terminal is electrically connected to the other of the source and drain, and a low power supply voltage is applied to the second terminal.

[0292] Next, the operation of the pixel shown in FIG. 20 will be described.

[0293] First, the pixel to which data is written is selected. The selected pixel receives the input from the scan line 855. The input scanning signal turns on the transistor 851, and a voltage of a predetermined value is applied. A video signal (also called a data signal) is input from a signal line 856 to the gate of a transistor 853. will be done.

[0294] The transistor 853 is turned on or off by a voltage corresponding to a data signal input to the gate. When the transistor 853 is turned on, the first terminal and the second terminal of the light-emitting element 854 are turned off. The voltage applied between the second terminals is in response to the gate voltage of transistor 853 and the high power supply voltage. At this time, the voltage applied between the first terminal and the second terminal of the light emitting element 854 is A current flows depending on the voltage, and the light emitting element 854 detects the amount of current flowing between the first terminal and the second terminal. The capacitor 852 controls the gate voltage of the transistor 853. is maintained for a certain period of time, the light emitting element 854 maintains the light emitting state for a certain period of time.

[0295] In addition, when the data signal input to the pixel from the signal line 856 is in digital format, the pixel By switching the transistor on and off, the light is emitted or not emitted. The gradation can be displayed using area gradation or time gradation. The pixel is divided into multiple sub-pixels, and each sub-pixel is configured as shown in Figure 20 and is independently connected to a data signal. The time gray scale method is a driving method that performs gray scale display by driving the liquid crystal display based on the time gray scale. This is a driving method that displays gradations by controlling the period during which the pixels emit light.

[0296] Light-emitting elements have a higher response speed than liquid crystal elements, making them more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, in accordance with the video signal, the light emitting element of the pixel is By dividing the period into multiple subframes, The total length of time that pixels actually emit light during a frame is controlled by the video signal. This allows for gradation to be displayed.

[0297] In addition, in the light-emitting display device, the driver circuit may be configured with an N-channel TFT. A part of the driver circuit can be formed on the same substrate as the TFT in the pixel area. It is also possible to fabricate the signal line driver circuit and the scanning line driver circuit using only N-channel TFTs. .

[0298] Next, the configuration of the light emitting element will be described with reference to FIG. 21. Here, the driving TFT is N The cross-sectional structure of a pixel will be explained using the channel type as an example. (C) TFTs 7001, 7011, and 7021, which are driving TFTs used in the display device can be manufactured in the same manner as the enhancement-type TFT described in the above embodiment, and It is a highly reliable TFT that contains a layer as a semiconductor layer.

[0299] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, TFTs and light emitting elements are formed on the substrate, and the light is extracted from the surface opposite the substrate. The light is emitted from the bottom surface of the substrate, or from the surface opposite the substrate. There are light emitting elements with a double-sided emission structure that extracts light, and the pixel configuration of the present invention is It can also be applied to elements.

[0300] A light emitting element with a top emission structure will be described with reference to FIG.

[0301] In FIG. 21(A), a TFT 7001 which is a driving TFT is an N-channel type, and a light emitting element 700 21(A) shows a cross-sectional view of a pixel when light emitted from the cathode 2 exits to the anode 7005 side. ) the cathode 7003 of the light emitting element 7002 and the TFT 7001 which is the driving TFT are electrically The cathode 7003 is connected to the light emitting layer 7004, and the anode 7005 are laminated in this order on the cathode 7003. The material for the cathode 7003 should have a small work function and reflect light. Various materials can be used, such as Ca, Al, MgAg, or AlLi. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers stacked. When it is made up of multiple layers, the cathode 700 An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are laminated on top of 3 in this order. It is not necessary to provide all of these layers except for the light-emitting layer. The insulating film is formed using a light-transmitting conductive material that transmits light, for example, an insulating film containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, titanium oxide-containing indium tin oxide, indium tin oxide (hereinafter referred to as "IT O), indium zinc oxide, indium tin oxide doped with silicon oxide, etc. A light-transmitting conductive film may be used.

[0302] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 21(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0303] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. 011 is an N-channel type, and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side. FIG. 21(B) shows a cross-sectional view of a pixel when the driving TFT 7011 is electrically connected to the A cathode 7013 of the light-emitting element 7012 is formed on the light-transmitting conductive film 7017 connected to the light-emitting element 7012. A light-emitting layer 7014 and an anode 7015 are laminated in this order on a cathode 7013. When the anode 7015 is light-transmitting, a light-reflecting or light-shielding layer is formed on the anode. The cathode 7013 may be formed in the same manner as in FIG. In addition, various conductive materials with small work functions can be used. The film thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). An aluminum film having a thickness of 100 μm can be used as the cathode 7013. The optical layer 7014 may be composed of a single layer, as in FIG. 21(A), or may be composed of a plurality of layers stacked together. The anode 7015 does not need to be light-transmitting. However, similarly to FIG. 21A, the light-transmitting conductive material can be used. The shielding film 7016 can be made of, for example, a metal that reflects light. For example, a resin to which a black pigment is added may also be used.

[0304] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 21B, light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0305] Next, a light emitting element with a dual emission structure will be described with reference to FIG. Then, on the conductive film 7027 having light-transmitting properties and electrically connected to the driving TFT 7021, A cathode 7023 of the light-emitting element 7022 is formed as a film. A light-emitting layer 7024 is formed on the cathode 7023. The cathode 7023 is laminated in the same manner as in FIG. Various conductive materials with small electrical conductivity can be used. For example, Al having a thickness of 20 nm is used as the cathode 7023. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be formed by laminating a plurality of layers. 25 is formed using a light-transmitting conductive material, similar to that shown in FIG. It is possible.

[0306] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 21C, the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0307] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0308] In this embodiment, a TFT (also referred to as a driving TFT) for controlling the driving of a light-emitting element is Although an example in which the light emitting element is electrically connected has been shown, it is possible to prevent a current from flowing between the driving TFT and the light emitting element. A control TFT may be connected.

[0309] Next, the appearance and cross section of the display device (also referred to as a light-emitting panel) in this embodiment will be described. This will be explained using Figure 22. Figure 22 shows the TFTs and light-emitting elements formed on the first substrate. FIG. 10 is a top view of the display device of this embodiment, which is sealed between the second substrate and the display device by a sealing material. 22(B) corresponds to a cross-sectional view taken along line HI in FIG. 22(A).

[0310] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0311] In addition, a pixel portion 4502, a signal line driver circuit 4503a, 4503b and the scanning line driver circuits 4504a and 4504b have a plurality of TFTs, In FIG. 22B, a TFT 4510 included in a pixel portion 4502 and a signal line driver circuit 450 3a includes TFT4509 and TFT4555.

[0312] The TFT4509, 4510, and 4555 are highly reliable devices that contain an oxide semiconductor layer as the semiconductor layer. Any one of the transistors described in Embodiment 2 and Embodiment 3 can be used. In this embodiment, the TFTs 4509, 4510, and 4555 are N-channel TFTs. In addition, an insulating layer 4542 is formed on the TFTs 4509, 4510, and 4555. An insulating layer 4544 is formed on the insulating layer 4542. The conductive layer 4540 is disposed on the TFT 4509 with the second gate electrode 4 sandwiched therebetween. Further, an insulating layer 4545 and an insulating layer 4546 are formed on the insulating layer 4544. An edge layer 4543 and an insulating layer 4546 are formed.

[0313] 22 includes a light-emitting element 4511. The light-emitting element 4511 has the following structure: , a stacked structure of a first electrode 4517, an electroluminescent layer 4512, and a second electrode 4513. The first electrode 4517 is a thin film transistor (TFT) 4510 having a structure other than that shown in this embodiment. The light-emitting element 4511 is electrically connected to a source electrode or a drain electrode 4548. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light to be extracted from the do.

[0314] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. A photosensitive material is used to form an opening on the first electrode 4517, and the sidewall of the opening is continuous. It is preferable to form the inclined surface with a continuous curvature.

[0315] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0316] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 4511, A protective layer may be formed over the electrode 4513 and the partition wall 4520. The protective layer may be formed of silicon nitride. It is possible to form a bare film, a silicon nitride oxide film, a DLC film, etc.

[0317] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b , or various signals and voltages given to the pixel portion 4502 are given by FPC 4518a, 4518b is supplied by

[0318] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode 45 of the light-emitting element 4511. The terminal electrode 4516 is formed from the same conductive film as the TFTs 4509, 4510, and 45 The source electrode and drain electrode 55 are formed from the same conductive film.

[0319] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0320] The second substrate located in the direction of light extraction from the light emitting element 4511 must be transparent. In that case, glass plate, plastic plate, polyester film or acrylic A light-transmitting material such as a film is used.

[0321] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of PVC (polyvinyl chloride), acrylic, or thermosetting resin. Imide, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (Elastomer) In this embodiment, nitrogen is used as the filler. There are.

[0322] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0323] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0324] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured.

[0325] This embodiment mode can be combined with other embodiment modes as appropriate.

[0326] (Embodiment 9) In this embodiment mode, electronic paper will be described as an example of the display device shown in Embodiment Mode 6. Reveal.

[0327] The logic circuit shown in the above embodiment can also be used for electronic paper. Also known as electrophoretic display (electrophoretic display), it is as easy to read as paper. It has the advantage of being able to consume less power and be made thinner and lighter than other display devices. There are.

[0328] Electrophoretic displays can be of various forms, but the first particle has a positive charge. The microcapsules containing the negatively charged second particles are mixed with a solvent or solute. By applying an electric field to the microcapsules, By moving the particles in the capsule in opposite directions, only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and are not mobile in the absence of an electric field. The first particles and the second particles are different in color (including colorless).

[0329] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. Since the polarizing plate and counter substrate required for a display device are not required, the thickness and weight are reduced.

[0330] The microcapsules dispersed in a solvent are called electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Furthermore, color display is possible by using color filters or particles containing pigments.

[0331] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cell, display can be performed. It is possible to use an active matrix substrate obtained by an enhancement type TFT. Cut.

[0332] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, a semiconductor, or the like. Conductive materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A material selected from magnetochromic materials, magnetophoretic materials, or a composite material of these materials is used. That's fine.

[0333] Next, an example of the structure of electronic paper in this embodiment will be described with reference to FIG. 3 is a cross-sectional view showing the structure of electronic paper in this embodiment.

[0334] The electronic paper shown in FIG. 23 has a TFT 581 on a substrate 580 and a The insulating layers 583, 584, and 585 are provided, and the insulating layers 583 to 585 are The source electrode or drain electrode of the TFT 581 is in contact with the opening provided in the TFT 585. A black area 59 is formed between the electrode 587 and an electrode 588 provided on a substrate 596. Sphere 590a and white region 590b, and a liquid-filled cavity 594 around it. The particle 589 has a filler 595 provided around the spherical particle 589 .

[0335] The TFT581 is a highly reliable TFT that contains an oxide semiconductor layer as a semiconductor layer. For example, the transistor can be manufactured in a manner similar to that of the transistor described in the above embodiment mode.

[0336] The method using spherical particles 589 is called the twisting ball display method. The term "display element" refers to a method of applying black and white spherical particles to a first electrode and a second electrode, which are electrodes used in a display element. The spherical particles are placed between the first electrode and the second electrode, and a potential difference is generated between the first electrode and the second electrode to change the direction of the spherical particles. This is a method of displaying by controlling the amount of light.

[0337] It is also possible to use electrophoretic elements instead of spherical elements. It contains charged white particles and negatively charged black particles, with a diameter of about 10 μm to 200 μm. The microcapsules are placed between the first electrode and the second electrode. When an electric field is applied to the capsule by the first and second electrodes, the capsule is divided into white particles and black particles. The particles move in opposite directions, allowing for the display of white or black. The element is an electrophoretic display element. The electrophoretic display element has a higher reflectance than the liquid crystal display element. Therefore, auxiliary lights are not required, the power consumption is low, and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display unit, the display can be displayed. Since it is possible to hold the image, it is possible to transmit the image from the radio wave source to a semiconductor device with a display function (simply display Even if the display device (also called a display device or a semiconductor device equipped with a display device) is placed far away, the display This allows the captured image to be stored.

[0338] The driving circuits shown in the second and third embodiments are, for example, The transistor in the display portion can also be formed using an oxide semiconductor layer. Since the transistors used in the present invention can be applied, for example, a driver circuit and a display unit can be formed on the same substrate. It is also possible to provide:

[0339] The electronic paper can be used in electronic devices in all fields as long as it displays information. For example, electronic books, posters, Suitable for in-car advertising on trains and other vehicles, and for displaying on various cards such as credit cards. An example of an electronic device is shown in FIG. 24. FIG. 24 shows an example of an electronic book. There are.

[0340] As shown in FIG. 24, the electronic book 2700 has two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft 2711. With this configuration, opening and closing operations can be performed around the shaft portion 2711. It is possible to operate like a paper book.

[0341] The housing 2701 incorporates a display unit 2705, and the housing 2703 incorporates a display unit 2707. The display unit 2705 and the display unit 2707 are configured to display a series of images. Alternatively, a different image may be displayed. By doing so, for example, a text image is displayed on the right display section (display section 2705 in FIG. 24) and A different image can be displayed on the display unit on the side (display unit 2707 in FIG. 24).

[0342] 24 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable). The configuration is provided with a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. good.

[0343] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0344] (Embodiment 10) In this embodiment, a system-on-panel is used as one form of the display device in the sixth embodiment. A display device of this type will now be described.

[0345] The logic circuit of the invention disclosed in this specification is a display unit and a driver circuit provided on the same substrate. It can also be applied to a system-on-panel type display device. explain.

[0346] The display device in this embodiment includes a display element. A light-emitting element (also called a display element) or a light-emitting element (also called a light-emitting display element) can be used. The term "luminance control element" includes elements whose brightness is controlled by current or voltage, and specifically refers to elements that are These include electroluminescence (EL) elements and organic EL elements. It also applies to display media such as electronic ink, whose contrast changes due to electrical effects. It is possible.

[0347] The display device according to the present embodiment includes a panel in which a display element is sealed, and the It also includes modules in which ICs including controllers are mounted on panels. In the process of manufacturing the display device, an element substrate corresponding to one form before the display element is completed the device substrate comprises means for supplying a current to the display element for each of a plurality of pixels. Specifically, the element substrate may be in a state where only pixel electrodes of the display element are formed. After forming the conductive film that will become the pixel electrode and before etching to form the pixel electrode, It can be a state or any form.

[0348] In this specification, the term "display device" refers to an image display device, a display device, or a light source ( Also, modules equipped with connectors are included in the display device category. For example, FPC (Flexible printed circuit), TAB (Ta Automated Bonding (TCP) tape or TCP (Tape Ca Modules with attached TAB tape or TCP A module with a printed wiring board mounted on the display element, or a COG (Chip On Glass) All modules with ICs (integrated circuits) directly mounted using the CLASS method are included in the display device. It can be enjoyed.

[0349] Next, an appearance and a cross section of a liquid crystal display panel corresponding to one mode of the display device in this embodiment will be described. This will be explained with reference to FIG.

[0350] 25(A1) and 25(A2) show the fourth embodiment formed on a first substrate 4001. TFTs 4010, 4011, and 4014 containing the In-Ga-Zn-O based film shown in The liquid crystal element 4013 is attached to the second substrate 4006 by a sealant 4005. 25(A) is a top view of the sealed display device according to this embodiment. 1) This corresponds to the cross-sectional view at MN in (A2).

[0351] The display device in this embodiment mode includes a pixel portion 4002 provided over a first substrate 4001 and a A sealant 4005 is provided so as to surround the scanning line driver circuit 4004. A second substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are connected to the first substrate 4001. The liquid crystal layer 4008 is sealed by the sealing material 4005 and the second substrate 4006. In addition, a region different from the region surrounded by the sealing material 4005 on the first substrate 4001 is In the signal line driver region, a signal line driver formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is An operating circuit 4003 is implemented.

[0352] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, a wire The ear bonding method, the TAB method, etc. can be used. FIG. 25(A2) is a diagram showing an example of mounting a signal line driver circuit 4003 by the OG method. FIG. 4 is a diagram showing an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0353] In addition, the pixel portion 4002 and the scanning line driver circuit 4004 provided on the first substrate 4001 are 25B, the pixel portion 4002 includes a TFT 401. 0 and a TFT 4011 and a TFT 4113 included in the scanning line driving circuit 4004. On the TFTs 4010, 4011, and 4113, insulating layers 4020, 4021, and 4042 are formed. Furthermore, a conductive film is provided on the TFT 4011 with insulating layers 4020 and 4042 sandwiched therebetween. The conductive layer 4040 functions as a second gate electrode. do.

[0354] The TFTs 4010, 4011, and 4113 are formed using the oxide semiconductor layer described in the above embodiment. In this embodiment, a TFT including the TFT 40 as a semiconductor layer can be applied. 10, 4011, and 4113 are N-channel TFTs.

[0355] The pixel electrode 4030 of the liquid crystal element 4013 is electrically connected to the TFT 4010. The counter electrode 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The pixel electrode 4030, the counter electrode 4031, and the liquid crystal layer 4008 are overlapped. The portion corresponds to the liquid crystal element 4013. The pixel electrode 4030 and the counter electrode 4031 are Insulating layers 4032 and 4033 are provided, each of which functions as an alignment film. A liquid crystal layer 4008 is sandwiched between them via 4033 .

[0356] The first substrate 4001 and the second substrate 4006 are the same as those in the above embodiment. The materials and manufacturing methods applicable to 201 can be applied.

[0357] The spacers 4035 are columnar partition walls obtained by selectively etching an insulating film. and controls the distance (cell gap) between the pixel electrode 4030 and the counter electrode 4031. A spherical spacer may also be used. , and is electrically connected to a common potential line provided on the same substrate as the TFT 4010. By using the part, a common potential is established with the counter electrode 4031 via conductive particles arranged between the pair of substrates. The conductive particles are contained in the sealing material 4005. do.

[0358] Although this embodiment is an example of a transmissive liquid crystal display device, the present invention is not limited to a reflective liquid crystal display device. However, it can also be applied to semi-transmissive liquid crystal display devices.

[0359] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a polarizing plate is provided on the inner side. In this example, the colored layer and the electrode used for the display element are provided in this order, but the polarizing plate is provided on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. The setting may be made appropriately depending on the material of the color layer and the manufacturing process conditions. A light-shielding film that functions as a light-shielding film may be provided.

[0360] In this embodiment, in order to reduce the surface irregularities caused by the TFT and to improve the reliability of the TFT, To improve the performance, the TFT is covered with an insulating layer (insulating layer 4) that functions as a protective layer and a planarizing insulating film. The protective layer is made of a metal, and is covered with an insulating layer 4020, an insulating layer 4021, and an insulating layer 4042. It is designed to prevent the intrusion of polluting impurities such as organic matter, metals, and water vapor floating in the air. Therefore, a dense film is preferable as the protective layer. Silicon film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, aluminum nitride A single layer or multilayer of aluminum film, aluminum oxynitride film, or aluminum nitride oxide film In this embodiment mode, an example in which the protective layer is formed by sputtering is shown. The protective layer is not particularly limited and may be formed by various methods. can also function as a reduction prevention layer.

[0361] Here, an insulating layer having a laminated structure is formed as a protective layer. A silicon oxide film is formed by sputtering to form an insulating layer 4042. When a silicon oxide film is used as the protective layer, the aluminum used as the source and drain electrodes It is effective in preventing hillocks in the silicon film.

[0362] In addition, a silicon nitride film is formed as the second protective layer by using a sputtering method. When a silicon nitride film is used as a protective layer, a volatile material such as sodium can be easily removed. To prevent mobile ions from penetrating into the semiconductor region and changing the electrical characteristics of the TFT. can be done.

[0363] After the protective layer is formed, the semiconductor layer may be subjected to a heat treatment.

[0364] An insulating layer 4021 is formed as a planarization insulating film. amide, acrylic, polyimide amide, benzocyclobutene, polyamide, epoxy, etc. In addition to the above organic materials, low dielectric constant materials can be used. low-k materials, siloxane resins, PSG (phosphor glass), BPSG (phosphor boro) In addition, multiple insulating films made of these materials can be stacked. The insulating layer 4021 may be formed by layering the insulating layer 4021.

[0365] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a S OG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, lean printing, offset printing, etc.), doctor knife, roll coater, curtain coater The insulating layer 4021 is formed using a material liquid. In this case, the semiconductor layer may be annealed at the same time as the baking step. By combining the baking process with the annealing of the semiconductor layer, it is possible to efficiently manufacture display devices. This becomes:

[0366] The pixel electrode 4030 and the counter electrode 4031 are made of indium oxide containing tungsten oxide. Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide , indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO) , indium zinc oxide, indium tin oxide doped with silicon oxide, etc. Any conductive material can be used.

[0367] The pixel electrode 4030 and the counter electrode 4031 are made of a conductive polymer (also called a conductive polymer). The conductive composition can be used to form the conductive film. The electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% at a wavelength of 550 nm. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0. It is preferable that the resistivity is 1 Ω·cm or less.

[0368] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or a copolymer of two or more of these.

[0369] In addition, a signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel portion 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0370] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode 403 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive film as the source electrode 4010 of the TFT 4011. The gate electrode and drain electrode are formed from the same conductive film.

[0371] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0372] In FIG. 25, a signal line driver circuit 4003 is formed separately and is mounted on the first substrate 4001. However, the present embodiment is not limited to this configuration. Alternatively, a circuit may be formed separately and mounted, or a circuit may be formed as part of a signal line driver circuit or a part of a scanning line driver circuit. Alternatively, the circuit board may be formed separately and mounted.

[0373] As described above, a system-on-panel type display device can be produced. In the display device of this embodiment, the logic circuit of the above embodiment is used in, for example, a drive circuit. It is also possible to fabricate logic circuits in the same process as the TFTs in the display section.

[0374] Note that this embodiment mode can be appropriately combined with the structures described in other embodiments. .

[0375] (Embodiment 11) The display devices described in the above-described Embodiments 6 to 10 can be used in various electronic devices (including game machines). The electronic device can be applied to, for example, a television device (including a television (also called television receivers), computer monitors, digital cameras, cameras such as digital video cameras, digital photo frames, mobile phones (mobile phones, (also called mobile phone devices), portable game machines, personal digital assistants, audio playback devices, pachinko machines, etc. Examples include large game consoles.

[0376] FIG. 26(A) shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. The figure shows the configuration.

[0377] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0378] The television device 9600 is configured to include a receiver, a modem, and the like. It is possible to receive more general television broadcasts, and also to receive them by wire or wirelessly via a modem. By connecting to a communication network, it can be transmitted in one direction (sender to receiver) or two directions (transmit to receiver). It is also possible to communicate information between followers and recipients, or between recipients themselves.

[0379] FIG. 26(B) shows an example of a digital photo frame. The frame 9700 has a display unit 9703 built into a housing 9701. 3 is capable of displaying various images, for example, images taken with a digital camera. By displaying data, it can function like a regular photo frame.

[0380] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US It is equipped with a terminal that can be connected to various cables such as B cable, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but if they are provided on the side or back, For example, it is preferable to insert a recording medium into a digital photo frame. Insert a memory that stores image data taken with a digital camera and import the image data. The captured image data can be displayed on the display portion 9703 .

[0381] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0382] FIG. 27(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9882 is incorporated in the housing 9891, and a display unit 9883 is incorporated in the housing 9891. 27(A) also includes a speaker unit 9884, a recording medium insertion unit 9 886, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor Sa9888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature Degree, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient , vibration, odor or infrared measuring functions), microphones 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above. It is sufficient that the configuration includes a display device, and other auxiliary equipment may be provided as appropriate. The portable gaming machine shown in FIG. 27(A) can be used to play a program or data recorded on a recording medium. It has the function of reading data and displaying it on the display, and communicating information wirelessly with other portable gaming machines. The functions of the portable gaming machine shown in Figure 27(A) are not limited to these. The function is not limited and can have a variety of functions.

[0383] FIG. 27(B) shows an example of a slot machine, which is a large gaming machine. 9900 has a display unit 9903 built into a housing 9901. The 9900 also has other controls such as a start lever and stop switch, and a coin slot. , speakers, etc. Of course, the configuration of the slot machine 9900 is the same as that described above. There is no limitation, and it is sufficient if the display device according to the present invention is included, and other accessories are not included. The configuration can be such that appropriate equipment is provided.

[0384] 28A shows an example of a mobile phone. The mobile phone 9000 has a housing 9001. In addition to the display unit 9002 incorporated in the It is equipped with a speaker 9005, a microphone 9006, etc.

[0385] In the mobile phone 9000 shown in FIG. 28A, information is displayed by touching the display portion 9002 with a finger or the like. You can also make calls or write emails using the This can be done by touching the display unit 9002 with a finger or the like.

[0386] The screen of the display unit 9002 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines the display mode and the input mode.

[0387] For example, when making a call or creating an email, the display unit 9002 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 9002. It's nice.

[0388] In addition, the mobile phone 9000 includes a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above, the orientation of the mobile phone 9000 (portrait or landscape) can be determined, The screen display on the display unit 9002 can be automatically switched.

[0389] The screen mode can be switched by touching the display unit 9002 or by operating the housing 9001. This is done by operating the button 9003. Also, depending on the type of image displayed on the display unit 9002, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, the display mode is switched to, and if it is text data, the input mode is switched to.

[0390] In the input mode, the optical sensor of the display unit 9002 detects a signal and displays it. If there is no input by touch operation of the part 9002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0391] The display unit 9002 can also function as an image sensor. By touching the palm or fingers to the 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be provided with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to capture images of finger veins, palm veins, etc.

[0392] FIG. 28B is also an example of a mobile phone. The mobile phone in FIG. 28B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 is mounted on a housing 9401. An operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and The communication device 9400 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9400 having a telephone function in two directions as shown by the arrows. Therefore, the display device 9410 and the communication device 9400 can be attached to each other with their short axes facing each other. The display device 9410 and the communication device 9400 can be attached to each other with their long axes facing each other. When only the function is required, the display device 9410 is removed from the communication device 9400. The communication device 9400 and the display device 9410 can be used independently. Images or input information can be sent and received via wired or wireless communication, and each can be recharged with a battery. Having Terry.

[0393] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0394] (Embodiment 12) In this embodiment mode, a logic circuit using transistors having a different configuration from that of the above embodiment mode will be described. and explain.

[0395] The display device according to one embodiment of the present invention is not limited to the transistor having the structure shown in FIG. 2 and may include transistors having other structures. It can also be configured using transistors of other structures. The control circuit will be described with reference to Fig. 29. Fig. 29 shows the structure of the drive circuit unit in this embodiment. 29(A) is a top view, and FIG. 29(B) is a view showing the drive mechanism shown in FIG. 29(A). 29 is a cross-sectional view of the operating circuit portion taken along line Z1-Z2 and line Z3-Z4. In the logic circuit shown in FIG. 2, the same parts as those in the display device shown in FIG. 2 are explained in the same manner as in the logic circuit shown in FIG. The explanation will be cited as appropriate.

[0396] The logic circuit shown in FIG. 29 includes transistors 251 and 252, similar to the logic circuit shown in FIG. 252 and a transistor 253.

[0397] The structure of each transistor will be described below. a gate electrode 211a provided on the gate electrode 211a; and a gate insulating film provided on the gate electrode 211a. The conductive layer 215a and the conductive layer 215b are respectively provided on the gate insulating layer 202. 15b, which is provided on the gate electrode 211a with the gate insulating layer 202 interposed therebetween, and which is a conductive layer and an oxide semiconductor layer 223a provided over the conductive layer 215a and the conductive layer 215b.

[0398] The transistor 252 includes a gate electrode 211b provided on the substrate 201 and a gate electrode The gate insulating layer 202 is provided on the gate insulating layer 211b. The gate electrode is formed by sandwiching the gate insulating layer 202 between the conductive layer 215b and the conductive layer 215c. An oxide film is provided on the conductive layer 211b and on the conductive layer 215b and the conductive layer 215c. and a compound semiconductor layer 223b.

[0399] The transistor 253 includes a gate electrode 211c provided on the substrate 201 and a gate electrode The gate insulating layer 202 is provided on the gate insulating layer 211c, and The gate electrode is formed by sandwiching the gate insulating layer 202 between the conductive layer 215b and the conductive layer 215d. An oxide film is provided on the conductive layer 211c and on the conductive layer 215b and the conductive layer 215d. and a compound semiconductor layer 223c.

[0400] The conductive layers 215a to 215d function as source electrodes and drain electrodes, respectively. Possess the ability.

[0401] The oxide semiconductor layers 223a to 223c are subjected to dehydration or dehydrogenation treatment. In addition, the oxide semiconductor layers 223a to 223c are in contact with the oxide semiconductor layers 223a to 223c. After dehydration or dehydrogenation treatment, an oxide insulating layer 207 is formed. A transistor using the oxide semiconductor layer on which 207 is formed as a channel formation layer can be used for a long time. High reliability because Vth shifts caused by use or high loads are unlikely to occur.

[0402] 29(A) and 29(B) is a flat oxide insulating layer 207. The oxide insulating layer 207 and the planarizing insulating layer 216 are sandwiched between the oxide insulating layer 207 and the planarizing insulating layer 216. The conductive layer 217a is disposed on the oxide semiconductor layer 223a, and the oxide insulating layer 207 and the planarizing insulating layer 217b are disposed on the oxide semiconductor layer 223a. The conductive layer 217b is disposed on the oxide semiconductor layer 223b with the oxide insulating layer 216 sandwiched therebetween. A conductive layer 217c is provided on the oxide semiconductor layer 223c with a planarization insulating layer 216 sandwiched therebetween. The conductive layers 217a to 217c each function as a second gate electrode. By applying a second gate voltage to the conductive layers 217a to 217c, The threshold voltages of the transistors 251 to 253 can be controlled.

[0403] The transistors 251 to 253 shown in FIG. 29 are bottom-contact transistors. By using bottom-contact transistors, The contact area between the oxide semiconductor layer and the conductive layer serving as the source electrode or the drain electrode can be increased. This can prevent peeling and other problems.

[0404] In addition, similarly to the configuration of the driver circuit section shown in FIG. 4, the oxide semiconductor layer and the source electrode or the drain electrode are A structure in which an oxide conductive layer is provided between the conductive layer serving as an electrode and the conductive layer can also be used.

[0405] Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0406] (Embodiment 13) In this embodiment mode, a logic circuit using transistors having a different configuration from that of the above embodiment mode will be described. and explain.

[0407] The display device according to one embodiment of the present invention is not limited to the transistor having the structure shown in FIG. 2 and may include transistors having other structures. It can also be configured using transistors of other structures. The control circuit will be described with reference to Fig. 30. Fig. 30 shows the structure of the drive circuit section in this embodiment. 30(A) is a top view, and FIG. 30(B) is a view showing the drive mechanism shown in FIG. 30(A). 30 is a cross-sectional view of the operating circuit portion taken along line Z1-Z2 and line Z3-Z4. In the logic circuit shown in FIG. 2, the same parts as those in the display device shown in FIG. 2 are the same as those in the logic circuit shown in FIG. The explanations will be cited as appropriate.

[0408] The logic circuit shown in FIG. 30 includes transistors 251 and 252, similar to the logic circuit shown in FIG. 252 and a transistor 253.

[0409] The structure of each transistor will be described below. a gate electrode 211a provided on the gate electrode 211a; and a gate insulating film provided on the gate electrode 211a. The conductive layer 215a and the conductive layer 215b are respectively provided on the gate insulating layer 202. 15b, which is provided on the gate electrode 211a with the gate insulating layer 202 interposed therebetween, and which is a conductive layer an oxide semiconductor layer 243a provided over the conductive layer 215a and the conductive layer 215b; and an oxide semiconductor layer 263a provided over the layer 243a.

[0410] The transistor 252 includes a gate electrode 211b provided on the substrate 201 and a gate electrode The gate insulating layer 202 is provided on the gate insulating layer 211b. The gate electrode is formed by sandwiching the gate insulating layer 202 between the conductive layer 215b and the conductive layer 215c. An oxide film is provided on the conductive layer 211b and on the conductive layer 215b and the conductive layer 215c. and a compound semiconductor layer 263b.

[0411] The transistor 253 includes a gate electrode 211c provided on the substrate 201 and a gate electrode The gate insulating layer 202 is provided on the gate insulating layer 211c, and The gate electrode is formed by sandwiching the gate insulating layer 202 between the conductive layer 215b and the conductive layer 215d. An oxide film is provided on the conductive layer 211c and on the conductive layer 215b and the conductive layer 215d. an oxide semiconductor layer 263 provided on the oxide semiconductor layer 243b; c and

[0412] The conductive layers 215a to 215d function as source electrodes and drain electrodes, respectively. Possess the ability.

[0413] In addition, the oxide semiconductor layer (the oxide semiconductor layer 243a and the oxide semiconductor layer 243b) included in the transistor 251 The thickness of the oxide semiconductor layer (stacked layer of the semiconductor layer 263a) is The thickness of the oxide semiconductor layer 263b of the transistor 253 is larger than that of the oxide semiconductor layer 263a. The thickness of the oxide semiconductor layer (the stack of the oxide semiconductor layer 243b and the oxide semiconductor layer 263c) is The thickness is larger than that of the oxide semiconductor layer (oxide semiconductor layer 263b) included in the sta 252. The larger the absolute value of the negative voltage of the gate electrode required to completely deplete the oxide semiconductor layer, the As a result, the transistor using a thick oxide semiconductor layer as a channel formation layer exhibits depletion-type behavior.

[0414] The transistors 251 to 253 shown in FIG. 30 are bottom-contact transistors. By using bottom-contact transistors, The contact area between the oxide semiconductor layer and the conductive layer serving as the source electrode or the drain electrode can be increased. This can prevent peeling and other problems.

[0415] In addition, similarly to the configuration of the driver circuit section shown in FIG. 8, the oxide semiconductor layer and the source electrode or the drain electrode are A structure in which an oxide conductive layer is provided between the conductive layer serving as an electrode and the conductive layer can also be used.

[0416] Note that this embodiment mode can be combined with other embodiment modes as appropriate. [Explanation of symbols]

[0417] 101 Drive circuit section 102 Pixel section 103 Signal Line 104 pixels 105 scan lines 107 scan lines 108 Reference voltage line 111 Drive circuit 112 transistors 201 Substrate 202 Gate insulating layer 207 Oxide insulating layer 211a Gate electrode 211b Gate electrode 211c gate electrode 214a Oxide conductive layer 214b Oxide conductive layer 214c Oxide conductive layer 214d Oxide conductive layer 214e Oxide conductive layer 214f oxide conductive layer 215a conductive layer 215b Conductive layer 215c conductive layer 215d conductive layer 216 Planarizing insulating layer 217a Conductive layer 217b Conductive layer 217c conductive layer 223a Oxide semiconductor layer 223b Oxide semiconductor layer 223c Oxide semiconductor layer 223d Oxide semiconductor layer 233a Resist mask 233b Resist mask 233c Resist mask 233d resist mask 243a Oxide semiconductor layer 243b Oxide semiconductor layer 251 transistors 252 transistors 253 transistors 263a Oxide semiconductor layer 263b Oxide semiconductor layer 263c Oxide semiconductor layer 316 nodes 321 Transistor 322 transistor 323 Transistor 324 Power line 325 power line 326 nodes 580 board 581 TFT 583 Insulating Layer 584 Insulating Layer 585 Insulation Layer 587 Electrode 588 Electrode 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filler 596 PCB 611 Transistor 613 Transistor 614 nodes 615 nodes 701 Pixel section 702 Scanning line driving circuit 703 Signal Line Driver Circuit 704 pixels 804 scan lines 805 signal line 821 Transistor 822 Liquid crystal element 823 Capacitor 851 Transistor 852 Capacitor 853 Transistor 854 Light-emitting element 855 scan lines 856 signal line 900 Shift Register 901 Level Shifter 902 buffer 903 Shift Register 904 Latch Circuit 905 Latch Circuit 906 Level Shifter 907 Buffer 2000 boards 2001 Gate electrode 2002 Insulating film 2003 Oxide semiconductor layer 2005a electrode 2005b electrode 2007 Oxide insulating layer 2008 Electrode 2020 Electrode 2022 Electrode 2023 Electrode 2024 Electrode 2028 Electrode 2029 Electrode 2050 terminal 2051 terminal 2052 gate insulating layer 2053 connecting electrode 2054 Protective insulating film 2055 Transparent conductive film 2056 Electrode 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 3011 Logic Circuit 3012 Logic Circuit 3013 Logic Circuit 3111 Transistor 3112 Transistor 3113 Transistor 3121A Inverter 3121B Inverter 3121C Inverter 3122A Inverter 3122B Inverter 3122C Inverter 3123A Inverter 3123B Inverter 3123C Inverter 3131 Transistor 3132 Transistor 3133 Transistor 3140 NAND circuit 3141 NAND circuit 3142 NAND circuit 3143 NAND circuit 3171 nodes 3172 nodes 3173 nodes 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 TFT 4011 TFT 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 pixel electrode 4031 Counter electrode 4032 Insulation layer 4035 Spacer 4040 Conductive layer 4042 Insulation layer 4113 TFT 4501 Circuit Board 4502 Pixel section 4503a Signal line driver circuit 4504a Scanning line driver circuit 4505 Sealing material 4506 board 4507 Filling material 4509 TFT 4510 TFT 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode 4518a FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4542 Insulation layer 4543 Insulation layer 4544 Insulation layer 4545 Insulation layer 4546 Insulation layer 4548 Drain electrode 4555 TFT 6121 Inverter 6122 Inverter 6123 Inverter 7001 TFT 7002 Light-emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7011 Driving TFT 7012 Light-emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7021 Driving TFT 7022 Light-emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 9000 mobile phones 9001 Case 9002 Display section 9003 Operation button 9004 External connection port 9005 Speaker 9006 Microphone 9400 Communication Equipment 9401 Housing 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 Housing 9412 Display section 9413 Operation button 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section

Claims

[Claim 1] a driver circuit including a logic circuit having a first transistor that is a depletion mode transistor and a second transistor that is an enhancement mode transistor; A signal line and a pixel section including pixels whose display state is controlled by receiving signals serving as image data from the drive circuit via the signal lines; a third transistor which is a depletion type transistor having a gate, a source, and a drain, one of which is supplied with a reference voltage, the other of which is electrically connected to the signal line, and to which a gate signal is input; A display device in which the first to third transistors each include an oxide semiconductor layer having a channel formation region.

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