Metal oxide

Abstract

To provide a novel metal oxide.SOLUTION: A metal oxide has a crystal. The crystal has a structure in which a first layer, a second layer, and a third layer are stacked. The first layer, the second layer, and the third layer are substantially parallel to a formation surface of the metal oxide. The first layer has a first metal and oxygen. The second layer has a second metal and oxygen. The third layer has a third metal and oxygen. The first layer has an octahedron structure. The second layer has a trigonal bipyramid structure or a tetrahedron structure. The third layer has a trigonal bipyramid structure or a tetrahedron structure. The octahedron structure of the first layer has an atom of the first metal at a center. The trigonal bipyramid structure or the tetrahedron structure of the second layer has an atom of the second metal at a center. The trigonal bipyramid structure or the tetrahedron structure of the third layer has an atom of the third metal at a center. A valence of the first metal is the same as that of the second metal. The valence of the first metal is different from that of the third metal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a metal oxide and a transistor including the metal oxide. Another embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] Technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0005] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a novel metal oxide.Another object of one embodiment of the present invention is to provide a novel transistor.Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current.Another object of one embodiment of the present invention is to provide a semiconductor device with high frequency characteristics.Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability.Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics.

[0009] Another object of one embodiment of the present invention is to provide a semiconductor device that can retain data for a long period of time.Another object of one embodiment of the present invention is to provide a semiconductor device that can write data at a high speed.Another object of one embodiment of the present invention is to provide a semiconductor device that can consume less power.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a metal oxide having a crystal. The crystal has a structure in which a first layer, a second layer, and a third layer are stacked. The first layer, the second layer, and the third layer are each approximately parallel to the surface on which the metal oxide is formed. The first layer has a first metal and oxygen. The second layer has a second metal and oxygen. The third layer has a third metal and oxygen. The first layer has an octahedral structure. The second layer has a trigonal bipyramidal structure or a tetrahedral structure. The third layer has a trigonal bipyramidal structure or a tetrahedral structure. The octahedral structure of the first layer has a first metal atom at its center and oxygen atoms at its vertices. The trigonal bipyramidal structure or the tetrahedral structure of the second layer has a second metal atom at its center and oxygen atoms at its vertices. The third layer has a trigonal bipyramidal or tetrahedral structure with a third metal atom at the center and oxygen atoms at the vertices. The valence of the first metal is the same as that of the second metal. The valence of the first metal is different from that of the third metal.

[0012] Another embodiment of the present invention is a metal oxide having a crystal. The crystal has a structure in which a first layer, a second layer, and a third layer are stacked. The first layer, the second layer, and the third layer are each approximately parallel to the surface on which the metal oxide is formed. The first layer and the second layer each contain a first metal, a second metal, and oxygen. The third layer contains a third metal and oxygen. The first layer has an octahedral structure. The second layer has a trigonal bipyramidal structure or a tetrahedral structure. The third layer has a trigonal bipyramidal structure or a tetrahedral structure. The octahedral structure of the first layer has an atom of the first metal or the second metal at the center and oxygen atoms at the vertices. The trigonal bipyramidal or tetrahedral structure of the second layer has a first metal atom or a second metal atom at the center and oxygen atoms at the vertices. The trigonal bipyramidal or tetrahedral structure of the third layer has a third metal atom at the center and oxygen atoms at the vertices. The valence of the first metal is the same as the valence of the second metal. The valence of the first metal is different from the valence of the third metal.

[0013] In the above metal oxide, the crystal preferably has a YbFe2O4 type structure or a Yb2Fe3O7 type structure.

[0014] In the metal oxide, it is preferable that the first metal is indium, the second metal is gallium, and the third metal is zinc.

[0015] Another embodiment of the present invention is a transistor including any of the above metal oxides in a channel formation region. [Effects of the Invention]

[0016] According to one embodiment of the present invention, a novel metal oxide can be provided. According to another embodiment of the present invention, a novel transistor can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided.

[0017] According to one embodiment of the present invention, a semiconductor device capable of retaining data for a long period of time can be provided. According to another embodiment of the present invention, a semiconductor device capable of writing data at a high speed can be provided. According to another embodiment of the present invention, a semiconductor device capable of reducing power consumption can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 2] 2A to 2C illustrate crystals contained in a metal oxide according to one embodiment of the present invention. [Figure 3] 3A is a diagram illustrating crystals contained in a metal oxide according to one embodiment of the present invention, and FIGS. 3B to 3D are diagrams illustrating polyhedra contained in the crystals. [Figure 4] Fig. 4A is a diagram illustrating a calculation model, Fig. 4B is a diagram illustrating the number of Ga atoms, Fig. 4C is a diagram illustrating the electron density at the bottom of the conduction band, and Fig. 4D is a diagram illustrating a map of LDOS. [Figure 5]5A and 5B are diagrams for explaining the calculation model. [Figure 6] 6A to 6D are diagrams for explaining a calculation model. [Figure 7] Fig. 7A is a diagram showing a map of LDOS, and Fig. 7B is a diagram explaining the density of states. [Figure 8] 8A and 8B are diagrams illustrating the number of Ga atoms, and 8C and 8D are diagrams illustrating LDOS maps. [Figure 9] 9A and 9B are diagrams illustrating the number of Ga atoms, and 9C and 9D are diagrams illustrating LDOS maps. [Figure 10] 10A and 10B are diagrams illustrating transmittance. [Figure 11] FIG. 11 is a diagram illustrating the transmittance and the derivative of the Fermi distribution function. [Figure 12] FIG. 12 is a diagram illustrating the transmission electron density. [Figure 13] 13A to 13D are diagrams illustrating the transmission electron density. [Figure 14] 14A to 14D are cross-sectional views illustrating a film forming method. [Figure 15] 15A to 15D are cross-sectional views of a metal oxide according to one embodiment of the present invention. [Figure 16] 16A to 16D are cross-sectional views illustrating a film forming method. [Figure 17] 17A to 17C are cross-sectional views illustrating a film forming method. [Figure 18] 18A and 18B are a top view and a cross-sectional view illustrating a film forming apparatus. [Figure 19] 19A to 19C are cross-sectional views illustrating a film forming apparatus. [Figure 20] 20A to 20C are diagrams illustrating a film forming method. [Figure 21] Fig. 21A is a top view of the semiconductor device, and Fig. 21B to Fig. 21D are cross-sectional views of the semiconductor device. [Figure 22]22A and 22B are diagrams for explaining the calculation model. [Figure 23] 23A to 23F are diagrams illustrating the trajectories of hydrogen. [Figure 24] FIG. 24 is a diagram showing a pathway by which hydrogen in an oxygen vacancy is released from the oxygen vacancy. [Figure 25] 25A and 25B are diagrams for explaining the transition of energy. [Figure 26] 26A to 26G are diagrams illustrating the atomic structure. [Figure 27] 27A to 27G are diagrams illustrating the atomic structure. [Figure 28] FIG. 28 is a histogram of activation energies. [Figure 29] Fig. 29A is a top view of the semiconductor device, and Fig. 29B to Fig. 29D are cross-sectional views of the semiconductor device. [Figure 30] Fig. 30A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 30B to Fig. 30D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 31] Fig. 31A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 31B to Fig. 31D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 32] Fig. 32A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 32B to Fig. 32D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 33] Fig. 33A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 33B to Fig. 33D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 34] Fig. 34A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 34B to Fig. 34D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 35] Fig. 35A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 35B to Fig. 35D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 36]Fig. 36A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 36B to Fig. 36D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 37] Fig. 37A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 37B to Fig. 37D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 38] Fig. 38A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 38B to Fig. 38D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 39] 39A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. 39B to 39D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 40] Fig. 40A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 40B to Fig. 40D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 41] Fig. 41A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 41B to Fig. 41D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 42] Fig. 42A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 42B to Fig. 42D are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 43] Fig. 43A is a top view of the semiconductor device, and Fig. 43B to Fig. 43D are cross-sectional views of the semiconductor device. [Figure 44] 44A and 44B are cross-sectional views of a semiconductor device. [Figure 45] FIG. 45 is a cross-sectional view showing the configuration of a storage device. [Figure 46] FIG. 46 is a cross-sectional view showing the configuration of a storage device. [Figure 47] Fig. 47A is a block diagram showing an example of the configuration of a storage device, and Fig. 47B is a schematic diagram showing an example of the configuration of a storage device. [Figure 48] 48A to 48H are circuit diagrams showing configuration examples of memory devices. [Figure 49] Fig. 49A is a block diagram of a semiconductor device, and Fig. 49B is a schematic diagram of the semiconductor device. [Figure 50]50A and 50B are diagrams illustrating an example of an electronic component. [Figure 51] 51A to 51E are schematic diagrams of a storage device. [Figure 52] 52A to 52H are diagrams showing electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0021] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions across different drawings, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular symbols may be assigned.

[0022] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0023] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0024] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0025] For example, if it is explicitly stated in this specification that X and Y are connected, it is assumed that the specification also discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is assumed that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0026] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0027] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0028] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0029] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0030] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0031] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0032] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0033] Note that impurities in semiconductors refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. O It may be written as . ) may be formed.

[0034] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0035] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0036] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0037] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0038] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0039] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0040] (Embodiment 1) In this embodiment, a metal oxide that can be used for a semiconductor layer of a transistor and a method for forming the metal oxide will be described with reference to FIGS.

[0041] FIG. 1 is a cross-sectional view in the channel length direction of a transistor 10 including a metal oxide according to one embodiment of the present invention.

[0042] As shown in FIG. 1, the transistor 10 includes an oxide 230 disposed on a substrate (not shown), an insulator 250 disposed on the oxide 230, and a conductor 260 disposed on the insulator 250. The oxide 230 includes a region 234 that functions as a region where the channel of the transistor 10 is formed (hereinafter also referred to as a channel formation region), and regions 231a and 231b that function as source and drain regions. The insulator 250 functions as a gate insulator. The conductor 260 functions as a gate electrode.

[0043] A conductor functioning as a source electrode or a drain electrode may be provided so as to be in contact with the oxide 230. In this case, if an element contained in the conductor has the function of absorbing oxygen from the oxide 230, a low-resistance region may be partially formed between the oxide 230 and the conductor or near the surface of the oxide 230. In this case, oxygen vacancies and impurities (hydrogen, nitrogen, metal elements, etc.) that have entered the oxygen vacancies may function as donors in the low-resistance region, increasing the carrier concentration. Furthermore, at least a portion of the low-resistance region is included in the region 231a or the region 231b, which functions as a source region or a drain region.

[0044] The resistance of the channel of a transistor can be controlled by applying a voltage to the gate, i.e., the potential applied to the gate can control the conduction (transistor on) or non-conduction (transistor off) between the source and drain.

[0045] In the transistor, a metal oxide (hereinafter also referred to as an oxide semiconductor) functioning as a semiconductor is preferably used for a semiconductor layer including a channel formation region.

[0046] Furthermore, the metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0047] A transistor using an oxide semiconductor for a channel formation region has an extremely small leakage current (off-state current) in an off-state; therefore, a semiconductor device with low power consumption can be provided.

[0048] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors, such as c-axis aligned crystalline oxide semiconductors (CAAC-OS), polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0049] A metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0050] When a metal oxide is composed of multiple metal elements, one of the scattering factors that contribute to carrier transmission is the random arrangement of metal atoms at cation sites (so-called cation disorder). Therefore, to increase the mobility of a metal oxide used in a transistor, it is preferable that the cation disorder of the metal oxide be reduced.

[0051] Therefore, it is preferable to use a metal oxide having crystals (also referred to as a crystalline metal oxide) for the metal oxide including the channel formation region. Furthermore, the crystal preferably has a crystal structure in which a first layer, a second layer, and a third layer are stacked. That is, the crystal has a layered crystal structure (also referred to as a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the first layer, the second layer, and the third layer are stacked. Examples of the metal oxide having crystals include a single-crystal oxide semiconductor and a CAAC-OS described later.

[0052] Furthermore, the c-axis of the crystal is preferably oriented in the normal direction to the surface on which the metal oxide is formed or the film surface. This allows the first to third layers to be arranged approximately parallel to the surface on which the metal oxide is formed or the film surface. In other words, the first to third layers extend in the channel length direction.

[0053] The first layer has an octahedral structure with a metal atom contained in the first layer at the center and oxygen atoms at the vertices. The second layer has a trigonal bipyramidal or tetrahedral structure with a metal atom contained in the second layer at the center and oxygen atoms at the vertices. The third layer has a trigonal bipyramidal or tetrahedral structure with a metal atom contained in the third layer at the center and oxygen atoms at the vertices.

[0054] Examples of the crystal structure of the above crystal include a YbFe2O4 type structure, a Yb2Fe3O7 type structure, and modified structures thereof.

[0055] Furthermore, each of the first to third layers is preferably composed of one metal element or multiple metal elements with the same valence and oxygen. The valence of the one or more metal elements constituting the first layer is preferably the same as the valence of the one or more metal elements constituting the second layer. The first and second layers may also contain the same metal element. The valence of the one or more metal elements constituting the first layer is preferably different from the valence of the one or more metal elements constituting the third layer.

[0056] The above structure can reduce the cation disorder of the metal oxide and increase the mobility of the metal oxide. Therefore, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor can be increased, and the electrical characteristics of the transistor can be improved. Note that the cation disorder of a crystalline metal oxide will be described later.

[0057] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition, it is preferable that it contains a metal element having the same valence as that of indium or zinc. Examples of such metal elements include aluminum, gallium, and yttrium. It may also contain one or more elements selected from iron, cobalt, nickel, lanthanum, cerium, neodymium, magnesium, calcium, and the like.

[0058] Here, we consider a case where the metal oxide is an In-M-Zn oxide having indium (In), element M, and zinc (Zn). The element M is aluminum, gallium, yttrium, etc. Other elements that can be used for element M include iron, cobalt, nickel, lanthanum, cerium, neodymium, magnesium, calcium, etc. However, there are cases where a combination of the above elements can be used as element M.

[0059] Here, when the metal oxide is an In-M-Zn oxide, the atomic arrangement in the crystal of the metal oxide will be described.

[0060] 2A to 2C are diagrams showing the atomic arrangement in the crystal of the oxide 230. Note that FIGS. 2A to 2C are also enlarged views of a region 51 of the oxide 230 shown in FIG. 1. Here, the composition of the oxide 230 shown in FIGS. 2A to 2C is In:M:Zn=1:1:1 [atomic ratio], and the crystal structure is a YbFe2O4 type structure. The element M is a metal element with a valence of +3. Note that in FIGS. 2A to 2C, the element M is referred to as M for convenience. 3+ 2A to 2C, atoms are represented by spheres (circles), and metal atoms (In, M 3+ , or Zn) and an oxygen atom (O) are represented by lines.

[0061] 2A to 2C, the c-axis direction in the crystal structure of the In-M-Zn oxide is indicated by an arrow, and the ab-plane direction in the crystal structure of the In-M-Zn oxide is perpendicular to the c-axis direction indicated by the arrow in FIGS.

[0062] 2A, the crystals of oxide 230 are formed by repeatedly laminating a layer 21 containing indium (In) and oxygen, a layer 31 containing element M and oxygen, and a layer 41 containing zinc (Zn) and oxygen in this order. Here, layer 21 corresponds to the first layer, layer 31 corresponds to the second layer, and layer 41 corresponds to the third layer.

[0063] As shown in FIG. 2A, each of layers 21, 31, and 41 of the crystal is composed of one metal element and oxygen, thereby reducing cation disorder and increasing the mobility of the metal oxide.

[0064] 2A, the stacking order of layers 21, 31, and 41 is not limited to that shown in Fig. 2A, and the stacking order of layers 31 and 41 located between two layers 21 is not important. For example, layers 21, 41, and 31 may be repeatedly stacked in this order, or as shown in Fig. 2B, layers 21, 41, 31, 21, 31, and 41 may be repeatedly stacked in this order.

[0065] 2C, the crystals of oxide 230 are formed by repeatedly stacking a layer 22 containing indium, element M, and oxygen, a layer 32 containing indium, element M, and oxygen, and a layer 41 containing zinc and oxygen, in this order. Here, layer 22 corresponds to the first layer, and layer 32 corresponds to the second layer. The stacking order of layers 22, 32, and 41 is not important, as is the stacking order of layers 21, 31, and 41, and the stacking order of layers 32 and 41, which are located between two layers 22, is not important.

[0066] Furthermore, when the ionic radius of indium is larger than that of element M, the atomic ratio of indium to element M in layer 22 is preferably larger than the atomic ratio of indium to element M in layer 32. This makes it easier to form crystals in the In-M-Zn oxide.

[0067] In Figures 2A to 2C, the atomic arrangement in the crystal is represented by spheres (circles) and lines. Next, the atomic arrangement in the crystal is displayed as a polyhedron. Figure 3A is a diagram showing the atomic arrangement in the crystal shown in Figure 2A as a polyhedron. Note that the polyhedron that layer 21 has is shown in Figure 3B, the polyhedron that layer 31 may have is shown in Figure 3C, and the polyhedron that layer 41 may have is shown in Figure 3D.

[0068] The polyhedron shown in Figure 3B is an octahedral structure. The octahedral structure has an indium atom at the center and oxygen atoms at the vertices. In layer 21, the octahedral structure is edge-shared. Note that an atom of element M may be present at the center of the octahedral structure.

[0069] The polyhedron shown in FIG. 3C has a trigonal bipyramidal structure. The trigonal bipyramidal structure has an atom of element M or a zinc atom at the center and oxygen atoms at the vertices. The polyhedron shown in FIG. 3D has a tetrahedral structure. The tetrahedral structure has a zinc atom at the center and oxygen atoms at the vertices. In each of layers 31 and 41, the trigonal bipyramidal structures share edges. Alternatively, the trigonal bipyramidal structures share vertices. Alternatively, the tetrahedral structures share vertices. Note that an indium atom may be present at the center of the trigonal bipyramidal structure.

[0070] Layer 21 shares a vertex with layer 31 or layer 41. Layer 31 and layer 41 also share a vertex or an edge.

[0071] 2A to 2C and 3A, a crystalline In-M-Zn oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] is shown as an example of the oxide 230, but the composition of the oxide 230 is not limited to this. (1+α) M (1-α) O3(ZnO) m (α is a real number greater than 0 and less than 1, and m is a positive number). When m is a real number greater than 0 and less than 1, some of the multiple layers located between two layers 21 may be composed of layer 31 alone. When m is a real number greater than 1, some of the multiple layers located between two layers 21 may be composed of layer 31 and two or more layers 41.

[0072] Furthermore, elements with different valences may be combined as the element M. For example, an In-M-Zn oxide containing a +3 valent metal element (element Ma) and a +2 valent metal element (element Mb) as the element M preferably has a crystal in which a first layer containing either one or both of indium and element Ma and oxygen, a second layer containing either one or both of indium and element Ma and oxygen, and a third layer containing element Mb, zinc, and oxygen are repeatedly stacked in this order. This reduces cation disorder and increases the mobility of the metal oxide.

[0073] <Effect of random cation arrangement in metal oxides> In this section, we explain the effect of random cation placement in metal oxides using the results of first-principles calculations.

[0074] In investigating the mechanism of carrier transmission, the path taken by the carriers (also called conduction electrons), i.e., the wave function of the conduction band, is important. For example, if the wave function of the conduction band is localized, carrier transmission is suppressed and mobility decreases. Therefore, the first-principles calculations in this section were performed focusing on the distribution of cation valence and the localization of the wave function of the conduction band in the crystal structure of In-Ga-Zn oxide.

[0075] As a calculation model used in the first-principles calculation, a crystal structure of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn:O = 1:1:1:4 is prepared. The crystal structure has the layered structure shown in Figure 2A, and Ga with a valence of +3 or Zn with a valence of +2 is located at the cation site of the layer located between layers containing In and O.

[0076] The calculation model is shown in Figure 4A. In Figure 4A, the c-axis direction of the calculation model is represented by a solid arrow. The b-axis direction of the calculation model is represented by a dashed arrow. The a-axis direction of the calculation model is perpendicular to the c-axis direction represented by the solid arrow and the b-axis direction represented by the dashed arrow. In this case, the ac plane is perpendicular to the b-axis direction represented by the dashed arrow. The number of atoms arranged in the calculation model is 288.

[0077] Figure 4B shows the number of Ga atoms in the ac plane. In Figure 4B, the horizontal axis represents the coordinate along the b axis, and the vertical axis represents the number of Ga atoms in the ac plane. As shown in Figure 4B, the calculation model has regions in the ac plane where Ga atoms are agglomerated (regions in Figure 4B where the number of Ga atoms is 2) and regions in the ac plane where Zn atoms are agglomerated (regions in Figure 4B where the number of Ga atoms is 0).

[0078] Using the calculation model shown in Figure 4A, first-principles calculations were performed to calculate the wave function of the conduction band. The calculations were performed using the first-principles calculation software VASP (Vienna Ab initio simulation Package). The calculation conditions are shown in Table 1.

[0079] [Table 1]

[0080] The electronic state pseudopotential was generated by the Projector Augmented Wave (PAW) method, and the functional was GGA-PBE (Generalized-Gradient-Approximation-Perdew-Burke-Ernzerhof).

[0081] Next, the wave function of the conduction band minimum obtained by the above calculation is projected along the b-axis. Then, the square of the absolute value of the wave function of the conduction band minimum projected along the b-axis is calculated. The square of the absolute value of the wave function is sometimes called the electron density.

[0082] Figure 4C shows the electron density at the bottom of the conduction band projected along the b-axis direction. In Figure 4C, the horizontal axis represents the coordinate along the b-axis (nm), and the vertical axis represents the electron density at the bottom of the conduction band projected along the b-axis (electron density [au]). As shown in Figure 4C, the electron density at the bottom of the conduction band appears to be localized around the region where Ga atoms are condensed. In other words, the wave function at the bottom of the conduction band is localized in the region where Ga atoms are condensed. In other words, this suggests that conduction electrons are localized in the region where Ga atoms are condensed.

[0083] Next, the density of states projected onto real space is calculated. The density of states projected onto real space is also called the local density of states (LDOS). The LDOS is calculated using the following formula:

[0084]

number

[0085] where E is the energy, x, y, and z are coordinates, σ is the blur width, ψ is the wave function, and ε is an eigenvalue.

[0086] Figure 4D shows the calculated LDOS map. In Figure 4D, the horizontal axis represents the coordinate along the b axis (nm), and the vertical axis represents energy (eV). Specifically, the darker the color, the larger the LDOS value, and the lighter the color, the smaller the LDOS value.

[0087] In Figure 4D, the upper end of the valence band is located on the low energy side of the energy values ​​at which the LDOS value changes significantly. For example, when the horizontal axis value is 0 nm, the upper end of the valence band is located at an energy value near 0 eV. Also, the lower end of the conduction band is located on the high energy side of the energy values ​​at which the LDOS value changes significantly. For example, when the horizontal axis value is 0 nm, the lower end of the conduction band is located at an energy value near 1.5 eV.

[0088] Figure 4D shows that in the region where Ga atoms are aggregated, the conduction band edge is depressed toward the lower energy side. In other words, in the region where conduction electrons are localized, the conduction band (also called the band) is significantly bent. Furthermore, the band bending saturates from the Ga aggregation region to the Ga-poor (Zn-rich) region, and beyond that (when the horizontal axis value is near 0 nm or near 5 nm), a flat band is formed.

[0089] Therefore, in the layer between the In and O layers, the localization of Ga, which has a high valence (a valence imbalance) causes a gradient in the electrostatic potential. It is presumed that the application of an electric field causes the band to bend, resulting in localization of the wave function at the bottom of the conduction band (localization of conduction electrons).

[0090] The above suggests that the aggregation of Ga atoms (the imbalance of valence) at cation sites where different valences can be arranged causes band bending (localization of conduction electrons), which is a source of scattering in electrical conduction, and leads to a decrease in mobility. Therefore, by suppressing the aggregation of Ga atoms, it is possible to suppress the decrease in mobility.

[0091] Next, a calculation model different from the above-mentioned calculation model will be described below.

[0092] A calculation model different from the calculation model used in the above calculation is shown in Figure 5A. The calculation model shown in Figure 5A is a crystal model of IGZO composed of In, Ga, Zn, and O. Region 901 corresponds to the channel formation region, region 902 corresponds to one of the source region and drain region, and region 903 corresponds to the other of the source region and drain region.

[0093] As shown in Figure 5A, in the calculation model for this calculation, the a-axis direction is the direction from region 902 to region 903, the c-axis direction is the direction perpendicular to the layer consisting of In and O (sometimes referred to as the InO layer), and the b-axis direction is the direction perpendicular to the a-axis direction and the c-axis direction.

[0094] Here, calculation models (Models 1A to 1E) are prepared that share the region 902 and the region 903 but have different cation arrangements in the region 901. The region 901 of Model 1A is illustrated in Figure 5B, the region 901 of Model 1B is illustrated in Figure 6A, the region 901 of Model 1C is illustrated in Figure 6B, the region 901 of Model 1D is illustrated in Figure 6C, and the region 901 of Model 1E is illustrated in Figure 6D.

[0095] Region 911a shown in Figure 5B is a region in Model 1A where the cation configuration is swapped. Region 912a and region 913a are pinned layers in Model 1A. The pinned layers correspond to the electrode regions (region 902 or region 903) in the conduction calculation. Also, as shown in Figure 5B, Model 1A has Ga atoms with no bias in their configuration with respect to the a-axis and c-axis.

[0096] Region 911b shown in FIG. 6A is a region in Model 1B where the cation arrangement is swapped. Region 912b and region 913b are fixed layers in Model 1B. Region 911b is a region surrounded by a dotted line in FIG. 6A, and the cation arrangement in the region 911b is different from that in the corresponding region in region 911a. Specifically, in region 911b, the Ga and Zn atoms in the corresponding region in region 911a are swapped in the region surrounded by a dotted line in FIG. 6A. In other words, Model 1B has a Ga atom arrangement that is biased with respect to the a-axis.

[0097] Region 911c shown in FIG. 6B is a region in Model 1C where the cation configuration is swapped. Region 912c and region 913c are fixed layers in Model 1C. Region 911c is two regions surrounded by dotted lines in FIG. 6B, and the cation configurations in the two regions are different from those in the corresponding region of region 911a. Specifically, in region 911c, Ga and Zn are swapped in the same locations in region 911a in each of the two regions surrounded by dotted lines in FIG. 6A. In other words, Model 1C has Ga atoms that are not biased with respect to the a-axis and c-axis.

[0098] Region 911d shown in FIG. 6C is a region in Model 1D where the cation arrangement is swapped. Regions 912d and 913d are fixed layers in Model 1D. Region 911d has a cation arrangement that is different from that of region 911a, which is the region surrounded by the dotted line and the region surrounded by the dashed line in FIG. 6C. Specifically, region 911d has an arrangement in which the cations in region 911a corresponding to the region surrounded by the dotted line in FIG. 6C are swapped with the cations in region 911a corresponding to the region surrounded by the dashed line in FIG. 6C. In other words, Model 1D has an arrangement in which Ga atoms are biased with respect to the c-axis.

[0099] Region 911e shown in FIG. 6D is a region in Model 1E where the cation arrangements are swapped. Regions 912e and 913e are fixed layers in Model 1E. In Region 911e, the cation arrangements of the regions surrounded by dotted lines and dashed lines in FIG. 6D are different from those of Region 911a. Specifically, Region 911e has an arrangement in which the cations in Region 911a corresponding to the region surrounded by dotted lines in FIG. 6D are swapped with the cations in Region 911a corresponding to the region surrounded by dashed lines in FIG. 6D. In other words, Model 1E has an arrangement in which Ga atoms are biased relative to the a-axis.

[0100] Using Models 1A to 1E, first-principles calculations were performed to calculate the density of states and LDOS. The calculations were performed using the first-principles calculation software VASP, which is capable of calculating electronic states based on density functional theory (DFT). The calculation conditions are shown in Table 2.

[0101] [Table 2]

[0102] Here, the DFT+U method is used in the first-principles calculations. In the DFT+U method, on-site Coulomb U-parameters are set for each of the atoms that make up the calculation model (In, Ga, Zn, and O in the case of IGZO). As shown in Table 2, when using VASP as the first-principles calculation software, the U-parameters for the metal atoms (In, Ga, and Zn) are set to 10 eV, and the U-parameter for the oxygen atom is set to 20 eV. This allows the calculated band gap value to be close to the measured band gap value.

[0103] Figure 7A shows the LDOS map calculated for Model 1A. In Figure 7A, the horizontal axis represents the coordinate [nm] along the a-axis, and the vertical axis represents energy [eV]. Specifically, the darker the color (black), the larger the LDOS value, and the lighter the color (white), the smaller the LDOS value. F is the Fermi energy.

[0104] 7A, it can be seen that the band is hardly bent in the region 911a. Therefore, in Model 1A, which has a structure in which the number of Ga atoms is not biased in the a-axis direction (carrier conduction direction), a flat band is obtained.

[0105] Figure 7B shows the density of states calculated for Model 1A. In Figure 7B, the horizontal axis represents the density of states [states / eV], and the vertical axis represents the energy [eV]. F is the Fermi energy, E VBM is the energy at the top of the valence band, and E CBM is the energy at the bottom of the conduction band.

[0106] FIG. 8A shows the number of Ga atoms in the bc plane in Model 1B. FIG. 8B shows the number of Ga atoms in the bc plane in Model 1C. FIG. 9A shows the number of Ga atoms in the bc plane in Model 1D. FIG. 9B shows the number of Ga atoms in the bc plane in Model 1E. In FIGS. 8A, 8B, 9A, and 9B, the horizontal axis corresponds to the coordinate in the a-axis direction, and the vertical axis represents the number of Ga atoms in the bc plane.

[0107] As shown in Figures 8A and 9B, Models 1B and 1E have Ga atoms arranged in a biased manner relative to the a-axis, while Models 1C and 1D have Ga atoms arranged in a non-biased manner relative to the a-axis, as shown in Figures 8B and 9A.

[0108] FIG. 8C shows a map of the LDOS calculated for Model 1B. FIG. 8D shows a map of the LDOS calculated for Model 1C. FIG. 9C shows a map of the LDOS calculated for Model 1D. FIG. 9D shows a map of the LDOS calculated for Model 1E. In FIGS. 8C, 8D, 9C, and 9D, the horizontal axis represents the coordinate [nm] along the a-axis, and the vertical axis represents energy [eV]. Specifically, the darker the color (black), the larger the LDOS value, and the lighter the color (white), the smaller the LDOS value.

[0109] 8C and 9D, bending of the band is confirmed in Models 1B and 1E. Also, FIG. 8D confirms that the band bends slightly in Model 1C. Also, FIG. 9C confirms that the band barely bends in Model 1D.

[0110] From the above, it is speculated that when the Ga atoms are arranged in a biased manner with respect to the a-axis, an electric dipole is formed due to the difference in the valence of Ga (+3) and Zn (+2), causing a tilt in the electrostatic potential. When this happens, the bottom of the conduction band moves up and down, hindering the conduction of carriers (mainly electrons in the case of IGZO). This suggests that carrier scattering occurs in real space. On the other hand, it is suggested that when the Ga atoms are arranged without bias with respect to the a-axis, carrier scattering does not occur.

[0111] Next, carrier scattering will be explained using the results of first-principles calculations. Specifically, we will investigate whether carriers flowing from the fixed layer (regions 912a to 912e) in contact with region 902 to the fixed layer (regions 913a to 913e) in contact with region 903 are scattered in the regions (regions 911a to 911e) where the cation configuration is swapped. In this case, the carrier conduction direction is along the a-axis.

[0112] Here, we perform a first-principles calculation of conductance using the non-equilibrium Green's function (NEGF) method to calculate the conductance and transmittance.

[0113] Conductance is the reciprocal of electrical resistance and is an index that indicates how easily electricity flows. Conductance G is calculated using the following formula:

[0114]

number

[0115] where E is the energy, T(E) is the transmittance at energy E, f(E) is the Fermi distribution function, and μ C is the chemical potential. In other words, the conductance G can be calculated by calculating the transmittance T(E) at energy E. Hereafter, the transmittance T(E) at energy E may be simply referred to as the transmittance T.

[0116] The transmittance T(E) at energy E is calculated using the following formula:

[0117]

number

[0118] In the above equation, Σ L (E), and Σ R (E) is the self-energy at energy E, and G(E) is the Green's function at energy E.

[0119] First-principles calculations were performed using Models 1A to 1E to calculate the transmittance and conductance. The calculations were performed using the DFT-based calculation program OpenMX. The calculation conditions are shown in Table 3.

[0120] [Table 3]

[0121] Here, the DFT+U method is applied in the first-principles calculations. As shown in Table 3, when using OpenMX as the first-principles calculation software, the U parameter for metal atoms (In, Ga, Zn) is set to 10 eV, and the U parameter for oxygen atoms is set to 3.7 eV. This allows the band gap value obtained by calculation to be close to the actually measured band gap.

[0122] The transmittance spectra of Models 1A to 1E calculated using the NEGF method are shown in Figures 10A and 10B. Figure 10A shows the transmittance spectrum of each model near the band gap, and Figure 10B shows the transmittance spectrum of each model at and near the bottom of the conduction band. In Figures 10A and 10B, the horizontal axis represents energy [eV], and the vertical axis represents transmittance T.

[0123] 10A and 10B, it can be seen that among Models 1A to 1E, Model 1A has the highest transmittance. It can also be seen that Model 1E has the lowest transmittance. It can also be seen that the transmittance of Models 1C and 1D at and near the bottom of the conduction band is almost the same as that of Model 1A.

[0124] Considering the above results and the calculation results of the band bending described above, it can be seen that a structure with a large band bending significantly reduces the transmittance. This suggests that carriers are more likely to be scattered when the cation valence is biased in the conduction direction. In other words, it suggests that the decrease in electron mobility can be suppressed by reducing the bias of the cation valence in the conduction direction.

[0125] FIG. 11 shows the transmittance spectrum of Model 1A and the shape obtained by differentiating the Fermi distribution function. In FIG. 11, the horizontal axis is energy [eV], the first vertical axis (left vertical axis) is transmittance T, and the second vertical axis (right vertical axis) is the derivative of the Fermi distribution function [ / eV]. The solid line in FIG. 11 is the transmittance spectrum of Model 1A, and the dotted line in FIG. 11 is the shape obtained by differentiating the Fermi distribution function. The Fermi distribution function is calculated by dividing the carrier concentration by 6×10 20 cm -3 The calculation is based on the electron temperature of 300K.

[0126] The conductance calculated for each of Models 1A to 1E is shown in Table 4.

[0127] [Table 4]

[0128] From Table 4, we can see that Model 1A has the largest conductance and Model 1E has the smallest. Note that the conductances of Models 1C and 1D are almost the same as that of Model 1A.

[0129] 12 and 13A to 13D show the transmission electron densities in Models 1A to 1E. The meshed surfaces in FIGS. 12 and 13A to 13D are for electrons with a carrier concentration of 6×10 20 cm -3 and the isosurface level is 22 nm -3 is the isosurface of the electron density.

[0130] Figure 12 confirms the presence of continuous transmission electron density in the InO layer. It also confirms that transmission electron density exists around Ga atoms compared to Zn atoms. Therefore, it is inferred that Ga atoms contribute more to carrier transport than Zn atoms. It also confirms the presence of transmission electron density originating from the s orbitals of O atoms. Therefore, it is inferred that the conduction of the s orbitals of O atoms cannot be ignored.

[0131] Figures 8C and 13A show that in Model 1B, carrier scattering occurs in the region where the band is curved and in its vicinity, but some carriers are transmitted. Figure 13B shows that carrier scattering is not clearly observed in Model 1C. Figure 13C suggests that in Model 1D, carriers are selectively conducted at the position of Ga atoms. Figures 9D and 13D show that in Model 1E, carrier scattering occurs in the region where the band is curved and in its vicinity, and almost no carriers are transmitted.

[0132] From the above, it can be seen that the transmittance decreases due to the disordered arrangement of cations (Ga, Zn). This tendency is particularly pronounced in structures where the number of Ga atoms is biased in the conduction direction. It can also be seen that in structures where a significant decrease in transmittance is observed, the band is significantly bent. It can also be seen that the main conduction paths are in In and Ga, which have high valences. It can also be seen that the transmittance decreases significantly in and near the region where the band is bent.

[0133] This concludes the explanation of the effect of random cation placement in metal oxides.

[0134] Methods for forming metal oxide films include sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD).

[0135] To form the above-mentioned crystalline metal oxide with reduced cation disorder, it is preferable to deposit atoms layer by layer. For example, the ALD method can be used as a method for forming the metal oxide.

[0136] The ALD method utilizes the self-regulating properties of precursor molecules or atoms contained in the precursors to deposit atoms layer by layer. This allows for the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films formed at low temperatures. The ALD method also includes plasma-enhanced ALD (PEALD), a film formation method that uses plasma. The use of plasma can sometimes be preferable because it enables film formation at lower temperatures. Note that some precursors used in ALD contain elements such as carbon and chlorine. Therefore, films formed by ALD may contain higher amounts of elements such as carbon and chlorine than films formed by other film formation methods. The quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS).

[0137] Unlike the film formation method in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of the object to be processed. Therefore, it is less affected by the shape of the object to be processed and is a film formation method having good step coverage. In particular, since the ALD method has excellent step coverage and excellent thickness uniformity, it is suitable for covering the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferably used in combination with other film formation methods such as the CVD method having a high film formation rate.

[0138] The composition of the obtained film can be controlled by the introduction amount of the source gas in the ALD method. For example, in the ALD method, a film with an arbitrary composition can be formed by the introduction amount and the number of introductions (also referred to as the number of pulses) of the source gas. Further, for example, in the ALD method, a film with a continuously changing composition can be formed by changing the source gas while forming the film. When forming a film while changing the source gas, the time required for film formation can be shortened because the time required for transfer and pressure adjustment is not required as compared with the case of forming a film using a plurality of film formation chambers. Therefore, the productivity of the semiconductor device may be increased.

[0139] <Film Formation Apparatus Using ALD Apparatus and ALD Method> Here, a film formation apparatus using the ALD method (hereinafter, also referred to as an ALD apparatus) that can be used for forming a metal oxide according to an aspect of the present invention, and a film formation method using the ALD method will be described.

[0140] ALD film formation systems alternately introduce a first source gas (also called a precursor, metal precursor, or reactant) and a second source gas (also called a reactant, non-metal precursor) into a chamber, and then repeat the introduction of these source gases to form a film. The introduction of the source gases can be switched, for example, by switching the respective switching valves (also called high-speed valves). Furthermore, when introducing the source gases, an inert gas such as nitrogen (N) or argon (Ar) may be introduced into the chamber together with the source gas as a carrier gas. Using a carrier gas prevents the source gas from adsorbing to the inside of piping or valves, even when the source gas has low volatility or a low vapor pressure. This also improves the uniformity of the formed film, which is preferable.

[0141] An example of a film formation method using the ALD method will be described with reference to FIGS. 14A to 14D. First, a first source gas is introduced into the chamber (see FIG. 14A), causing a precursor 601 to adsorb onto the substrate surface (first step). The adsorption of the precursor 601 onto the substrate surface activates a self-limiting mechanism for the surface chemical reaction, preventing further adsorption of the precursor onto the precursor layer on the substrate (see FIG. 14B). The optimum substrate temperature range within which the self-limiting mechanism for the surface chemical reaction operates is also referred to as the ALD window. The ALD window is determined by the precursor's temperature characteristics, vapor pressure, decomposition temperature, and other factors, but is generally between 100°C and 500°C, preferably between 200°C and 400°C. Next, excess precursor and reaction products are removed from the chamber by evacuation (second step). Alternatively, an inert gas (such as argon or nitrogen) may be introduced into the chamber to remove excess precursor and reaction products. The second step is also called purging. Next, a reactant 602 (e.g., an oxidant (ozone (O3), oxygen (O2), water (H2O), and their plasma, radicals, ions, etc.)) is introduced into the chamber as a second source gas (see FIG. 14C). This reactant reacts with the precursor 601 adsorbed on the substrate surface, causing some of the components contained in the precursor 601 to desorb (see FIG. 14D), while leaving the constituent molecules of the film adsorbed to the substrate. Next, the excess reactant 602 and reaction products are removed from the chamber by vacuum evacuation or by introducing an inert gas (see FIG. 14D).

[0142] In the following description of this specification, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or oxidant, it is not limited to a gaseous or molecular state, but also includes a plasma state, a radical state, and an ion state. When forming a film using an oxidant in a plasma state, a radical state, or an ion state, a radical ALD apparatus or a plasma ALD apparatus, which will be described later, may be used.

[0143] To remove carbon from the precursor, it is preferable to use water as an oxidizing agent. The hydrogen contained in the water reacts with the carbon contained in the precursor, efficiently separating the carbon from the precursor. On the other hand, if it is desired to minimize the amount of hydrogen contained in the film to be formed, it is preferable to use ozone or oxygen, which do not contain hydrogen, as an oxidizing agent. Alternatively, water may be introduced into the chamber as a first oxidizing agent to remove the carbon contained in the precursor, followed by evacuation. Alternatively, ozone or oxygen, which do not contain hydrogen, may be introduced into the chamber as a second oxidizing agent to remove the hydrogen, followed by evacuation. Steps 1 to 4 are then repeated until the desired film thickness is obtained.

[0144] In the above description, an example in which the first source gas is introduced into the chamber and then the second source gas is introduced into the chamber has been described. However, this is not a limitation of the present invention. The second source gas may be introduced into the chamber and then the first source gas may be introduced into the chamber. That is, the third step may be performed first, followed by the fourth step, and then the first, second, third, and fourth steps may be performed, and then the first to fourth steps may be repeated to form a film. Furthermore, the third and fourth steps may be repeated multiple times, and then the first to fourth steps may be repeated to form a film.

[0145] In this way, performing the third and fourth steps once or multiple times before the first step is preferable because it allows for control of the film formation atmosphere in the chamber. For example, by introducing an oxidizing agent in the third step, the chamber can be filled with an oxygen atmosphere. Starting film formation in an oxygen atmosphere is preferable because it increases the oxygen concentration in the film being formed. Furthermore, oxygen can be supplied to the insulator or oxide underlying the film. A semiconductor device formed using this method has excellent characteristics and high reliability.

[0146] Furthermore, after the first and second steps, the introduction of the second source gas in the third step and the evacuation or introduction of an inert gas in the fourth step may be repeated multiple times. That is, the first step, second step, third step, fourth step, third step, fourth step, and so on may be repeated, and then the first and second steps may be performed.

[0147] For example, O3 and O2 may be introduced as oxidizing agents in the third step, and evacuation may be performed in the fourth step, and this process may be repeated multiple times.

[0148] Furthermore, when repeating the third and fourth steps, it is not necessary to repeatedly introduce the same type of source gas. For example, H2O may be used as the oxidizing agent in the first third step, and O3 may be used as the oxidizing agent in the second and subsequent third steps.

[0149] In this way, by repeatedly introducing an oxidizing agent and evacuating the chamber (or introducing an inert gas) multiple times in a short period of time, excess hydrogen atoms, carbon atoms, chlorine atoms, etc. can be more reliably removed from the precursor adsorbed on the substrate surface and expelled to the outside of the chamber. Furthermore, by increasing the number of types of oxidizing agents to two, more excess hydrogen atoms, etc. can be removed from the precursor adsorbed on the substrate surface. In this way, by preventing hydrogen atoms from being incorporated into the film during film formation, the amount of water, hydrogen, etc. contained in the formed film can be reduced.

[0150] By using this method, the amount of water molecules desorbed was 1.0 × 10 in the surface temperature range of 100°C to 700°C or 100°C to 500°C in TDS analysis. 13 molecule / cm 2 Over 1.0 x 10 16 molecule / cm 2 Less than or equal to 1.0 × 10 13 molecule / cm 2 Over 3.0 x 10 15 molecule / cm2 The following films can be formed:

[0151] In this way, a first layer can be formed on the substrate surface, and a second layer can be stacked on the first layer by repeating steps 1 to 4 again. By repeating steps 1 to 4 multiple times while controlling the gas introduction until the film reaches the desired thickness, a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of repetitions, allowing for precise film thickness adjustment, making this method suitable for fabricating fine transistors.

[0152] Furthermore, the film formed by the above method may have a layered structure. Furthermore, when the film formed by the above method has a crystalline structure, the c-axis of the film is oriented in a direction approximately parallel to the normal direction of the surface on which the film is formed. That is, the c-axis of the film is oriented perpendicular to the surface on which the film is formed. As will be described in detail later, in this specification, such a crystalline structure is referred to as a CAAC structure, and an oxide semiconductor (metal oxide) having the CAAC structure may be referred to as a CAAC-OS. By using the ALD method, it is possible to form a metal oxide having a CAAC structure.

[0153] The ALD method is a film formation method that uses thermal energy to react precursors and reactants. The temperature required for the precursor and reactant reaction depends on their temperature characteristics, vapor pressure, decomposition temperature, etc., but is generally between 100°C and 500°C, preferably between 200°C and 400°C. Furthermore, an ALD method that uses a plasma-excited reactant as a third source gas in addition to the precursor and reactant reaction is sometimes called a plasma ALD method. In this case, a plasma generator is installed at the introduction point for the third source gas. Inductively coupled plasma (ICP) can be used to generate the plasma. In contrast, an ALD method that uses thermal energy to react precursors and reactants is sometimes called a thermal ALD method.

[0154] In the plasma ALD method, a plasma-excited reactant is introduced in the third step to form a film. Alternatively, the first to fourth steps are repeated while a plasma-excited reactant (second reactant) is introduced. In this case, the reactant introduced in the third step is called the first reactant. In the plasma ALD method, the second reactant used in the third source gas can be the same material as the oxidizer. That is, plasma-excited ozone, oxygen, and water can be used as the second reactant. In addition to the oxidizer, a nitriding agent can also be used as the second reactant. Nitrogen (N2) or ammonia (NH3) can be used as the nitriding agent. A mixed gas of nitrogen (N2) and hydrogen (H2) can also be used as the nitriding agent. For example, a mixed gas of 5% nitrogen (N2) and 95% hydrogen (H2) can be used as the nitriding agent. Nitride films such as metal nitride films can be formed by introducing plasma-excited nitrogen or ammonia during film formation.

[0155] Argon (Ar) or nitrogen (N2) may also be used as a carrier gas for the second reactant. The use of a carrier gas such as argon or nitrogen facilitates plasma discharge, making it easier to generate a plasma-excited second reactant, which is preferable. When forming an oxide film such as a metal oxide film using the plasma ALD method, using nitrogen as a carrier gas may result in nitrogen contamination in the film, making it difficult to obtain the desired film quality. In this case, it is preferable to use argon as a carrier gas.

[0156] The ALD method can deposit extremely thin films with uniform thickness and has a high surface coverage even on uneven surfaces.

[0157] Furthermore, plasma ALD allows for film deposition at even lower temperatures than thermal ALD. For example, plasma ALD allows for film deposition at temperatures below 100°C without reducing the deposition rate. Furthermore, plasma ALD can use a variety of reactants, including not only oxidizing agents but also nitriding agents, allowing for the deposition of a wide variety of films, including not only oxides but also nitrides, fluorides, and metals.

[0158] Furthermore, when performing plasma ALD, plasma can be generated at a distance from the substrate, such as in ICP, which can reduce plasma damage.

[0159] By the above method, a film containing atoms contained in the first source gas as one of its components, an oxide film, or a nitride film can be formed.

[0160] On the other hand, when forming a film containing multiple metals as metal oxides, multiple precursors for each metal may be prepared and introduced into the chamber sequentially.

[0161] When forming an In-M-Zn oxide as a metal oxide, a source gas containing a first precursor containing indium is introduced into the chamber, and excess source gas is exhausted (purged). Next, an oxidizing agent is introduced into the chamber as a reactant, and excess reactant is exhausted. Next, a source gas containing a second precursor containing element M is introduced into the chamber, and excess source gas is exhausted (purged). Next, an oxidizing agent is introduced into the chamber as a reactant, and excess reactant is exhausted. Next, a source gas containing a third precursor containing zinc is introduced into the chamber, and excess source gas is exhausted (purged). Next, an oxidizing agent is introduced into the chamber as a reactant, and excess reactant is exhausted. By repeating the above steps, a metal oxide containing a layer containing indium, a layer containing element M, and a layer containing zinc can be formed.

[0162] The order of introducing the source gases is not limited to the above. After the introduction of the source gas containing the first precursor, the source gas containing the third precursor may be introduced, followed by the source gas containing the second precursor. This order can be appropriately determined by the practitioner depending on the desired film properties. After the introduction of each source gas, the excess source gas may be evacuated, and a reactant may be introduced and evacuated as appropriate. The metal oxide is not limited to In-M-Zn oxide. As described above, the metal oxide preferably contains at least indium or zinc, and more preferably contains indium and zinc. The metal oxide may contain two types of metals, or four or more types of metals.

[0163] In the above, an example of forming an In-M-Zn oxide with a composition of In:M:Zn=1:1:1 [atomic ratio] was shown. (1+α) M (1-α) O3(ZnO) m When forming a crystalline In-M-Zn oxide represented by the formula (α) (α is a real number greater than 0 and less than 1, and m is a positive number), the order of introducing the source gases is not limited to the above. When m is a real number greater than 0 and less than 1, a process of introducing a source gas containing a first precursor, followed by introducing a source gas containing a second precursor, and then introducing the source gas containing the first precursor may be performed. Note that after the introduction of each source gas, exhaust of excess source gas, introduction of a reactant, and exhaust may be performed as appropriate. Also, when m is a real number greater than 1, a process of introducing a source gas containing a first precursor, followed by introducing a source gas containing a second precursor, followed by introducing a source gas containing a third precursor multiple times, and then introducing the source gas containing the first precursor may be performed as appropriate. Note that the order of introducing the source gas containing the second precursor and the source gas containing the third precursor is not limited to the above. Also, after the introduction of each source gas, exhaust of excess source gas, introduction of a reactant, and exhaust may be performed as appropriate.

[0164] The atomic ratio of metals contained in the metal oxide can be controlled by adjusting the number of times a source gas containing a precursor containing the desired metal is introduced into the chamber or by adjusting the film formation temperature. For example, if it is desired to increase the atomic ratio of element M relative to indium or zinc, a source gas containing a second precursor containing element M is introduced into the chamber, excess source gas is evacuated, an oxidizing agent is introduced into the chamber as a reactant, and the excess reactant is evacuated. After that, a source gas containing the second precursor containing element M is again introduced into the chamber, excess source gas is evacuated, an oxidizing agent is introduced into the chamber as a reactant, and the excess reactant is evacuated.

[0165] Alternatively, multiple precursors may be introduced into the chamber. For example, a source gas containing a first precursor and a second precursor may be introduced into the chamber, the excess source gas may be evacuated, a reactant may be introduced into the chamber, the excess reactant may be evacuated, a source gas containing the first precursor and the second precursor may be introduced into the chamber, the excess source gas may be evacuated, a reactant may be introduced into the chamber, the excess reactant may be evacuated, a source gas containing a third precursor may be introduced into the chamber, the excess source gas may be evacuated, a reactant may be introduced into the chamber, and the excess reactant may be evacuated, thereby forming a metal oxide containing In-M-Zn oxide. Note that the combination of precursors introduced into the chamber described above is based on the assumption that the valence of element M is +3. However, if the valence of element M is +2, a source gas containing a second precursor and a third precursor may be introduced into the chamber.

[0166] Alternatively, source gases containing different precursors may be introduced into the chamber sequentially. For example, a source gas containing a first precursor may be introduced into the chamber, the excess source gas may be evacuated, and then a reactant may be introduced into the chamber without introducing the reactant. Subsequently, a source gas containing a second precursor may be introduced into the chamber, the excess source gas may be evacuated, a reactant may be introduced into the chamber, and the excess reactant may be evacuated. Subsequently, a source gas containing the first precursor may be introduced into the chamber, the excess source gas may be evacuated, and then a source gas containing a second precursor may be introduced into the chamber, the excess source gas may be evacuated, a reactant may be introduced into the chamber, and the excess reactant may be evacuated. Subsequently, a source gas containing a third precursor may be introduced into the chamber, the excess source gas may be evacuated, a reactant may be introduced into the chamber, and the excess reactant may be evacuated. This process may result in the formation of a metal oxide containing an In-M-Zn oxide. The order and combination of precursors introduced into the chamber sequentially are not limited to those described above. After the source gas containing the second precursor is introduced into the chamber, the source gas containing the first precursor may be introduced into the chamber. The above-described order and combination of precursors to be successively introduced into the chamber assumes that the valence of element M is +3. However, if the valence of element M is +2, it is preferable to introduce the source gas containing the second precursor into the chamber, and then introduce the source gas containing the third precursor into the chamber without introducing a reactant.

[0167] Alternatively, a metal oxide may be formed using a precursor containing multiple metals, such as a precursor containing indium and an element M with a valence of +3 in one molecule, or a precursor containing an element M with a valence of +2 and zinc in one molecule.

[0168] The following provides a detailed explanation of the above-mentioned CAAC-OS.

[0169] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0170] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0171] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0172] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0173] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0174] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0175] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0176] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0177] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0178] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0179] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0180] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0181] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0182] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0183] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0184] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm3 The following applies.

[0185] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0186] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0187] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0188] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0189] As described above, the ALD method allows for deposition on structures with high aspect ratios and can also form films with excellent coverage on the side surfaces of structures. Using the ALD method, metal oxides with a CAAC structure can be easily formed regardless of the orientation of the deposition surface. For example, even if the structure has a convex or concave shape, metal oxides can be formed with good coverage on the top, bottom, side, and inclined surfaces of the structure. That is, metal oxides with a substantially constant film thickness in the normal direction can be formed on each deposition surface. The ratio of the minimum film thickness to the maximum film thickness of the metal oxides formed on the top, bottom, side, and inclined surfaces of the structure can be 0.5 to 1, preferably 0.7 to 1, and more preferably 0.9 to 1. In this case, if the metal oxide has crystals, the c-axis of the metal oxide is oriented in a direction substantially parallel to the normal direction of each deposition surface. That is, the c-axis is oriented perpendicular to each deposition surface.

[0190] FIG. 15A is a diagram showing an oxide 230 having an In-M-Zn oxide formed on a structure 50. Here, the term "structure" refers to an element constituting a semiconductor device such as a transistor. The structure 50 includes conductors such as a substrate, gate electrode, source electrode, and drain electrode, insulators such as a gate insulating film, an interlayer insulating film, and a base insulating film, and semiconductors such as metal oxides and silicon. FIG. 15A shows a case where the surface of the structure 50 to be deposited is arranged parallel to the substrate (or base, not shown). FIG. 15B is an enlarged view of a region 53, which is a part of the oxide 230 in FIG. 15A. FIG. 15B shows a state in which a layer containing indium (In), a layer containing element M, and a layer containing zinc (Zn) are stacked on the top or bottom surface of the structure 50. The indium-containing layer is arranged parallel to the surface of the structure 50 to be deposited, a layer containing element M is arranged parallel to the surface of the structure 50 to be deposited, and a layer containing zinc is arranged parallel to the surface of the structure 50 to be deposited. That is, the ab-plane of the oxide 230 is approximately parallel to the surface of the structure 50 on which the film is to be formed, and the c-axis of the oxide 230 is approximately parallel to the normal direction of the surface of the structure 50 on which the film is to be formed.

[0191] FIG. 15C shows a case where the deposition surface of the structure 50 is arranged perpendicular to the substrate (or base, not shown). FIG. 15D is an enlarged view of a region 54, which is a part of the oxide 230 in FIG. 15C. FIG. 15D shows a state where a layer containing indium (In), a layer containing element M, and a layer containing zinc (Zn) are stacked on the side surface of the structure 50. The indium-containing layer is arranged parallel to the deposition surface of the structure 50, a layer containing element M is arranged on top of it, parallel to the deposition surface of the structure 50, and a layer containing zinc is arranged on top of it, parallel to the deposition surface of the structure 50. That is, the ab-plane of the oxide 230 is approximately parallel to the deposition surface of the structure 50, and the c-axis of the oxide 230 is approximately parallel to the normal direction of the deposition surface of the structure 50.

[0192] 16A to 17C, a method for forming an oxide 230 containing In-M-Zn oxide will be described in detail. While FIGS. 16A to 17C illustrate an example in which a layer 21 containing indium is formed, a layer 31 containing element M is formed thereon, and a layer 41 containing zinc is further formed thereon, the present embodiment is not limited to this. Alternatively, one of the layers 31 and 41 may be formed, the layer 21 may be formed thereon, and the other of the layers 31 and 41 may be formed thereon. Alternatively, one of the layers 31 and 41 may be formed, the other of the layers 31 and 41 may be formed thereon, and the layer 21 may be formed thereon.

[0193] First, a source gas containing an indium-containing precursor is introduced into the chamber, and the precursor is adsorbed onto the surface of the structure 50 (see FIG. 16A). Here, the source gas contains the precursor as well as a carrier gas such as argon or nitrogen. Examples of indium-containing precursors that can be used include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, and cyclopentadienylindium. Next, the chamber is purged to remove excess precursor and reaction products.

[0194] Next, an oxidizing agent introduced into the chamber as a reactant is reacted with the adsorbed precursor, leaving indium adsorbed on the substrate while removing components other than indium, forming a layer 21 composed of indium and oxygen (see Figure 16B). Examples of oxidizing agents that can be used include ozone, oxygen, and water. Next, the chamber is purged to remove excess reactant and reaction products from the chamber.

[0195] Next, a source gas containing a precursor containing element M is introduced into the chamber, and the precursor is adsorbed onto layer 21 (see FIG. 16C). The source gas contains a carrier gas such as argon or nitrogen in addition to the precursor. When gallium is used as element M, precursors containing gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium. Next, the chamber is purged to remove excess precursor and reaction products.

[0196] Next, an oxidizing agent introduced into the chamber as a reactant is reacted with the adsorbed precursor to remove components other than element M while leaving element M adsorbed on the substrate, thereby forming layer 31 composed of element M and oxygen (see FIG. 16D). At this time, some of the oxygen constituting layer 41 may be adsorbed onto layer 31. Next, the chamber is purged to remove excess reactant, reaction products, etc. from the chamber.

[0197] Next, a source gas containing a zinc-containing precursor is introduced into the chamber, and the precursor is adsorbed onto layer 31 (see FIG. 17A). At this time, part of layer 41 composed of zinc and oxygen may be formed. In addition to the precursor, the source gas contains a carrier gas such as argon or nitrogen. Examples of zinc-containing precursors that can be used include dimethylzinc, diethylzinc, and zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate). Next, the chamber is purged to remove excess precursor and reaction products from the chamber.

[0198] Next, an oxidizing agent introduced into the chamber as a reactant is reacted with the adsorbed precursor to remove components other than zinc while leaving zinc adsorbed on the substrate, thereby forming layer 41 composed of zinc and oxygen (see FIG. 17B). Next, the chamber is purged to remove excess reactant and reaction products from the chamber. Note that, by forming layers 31 and 41 multiple times before forming the next layer 21, a stack of layers 31 and 41 with the desired number of atoms, number of layers, and thickness may be formed between the two layers 21.

[0199] Next, layer 21 is formed again on layer 41 by the above-described method (see FIG. 17C). By repeating the above method, oxide 230 can be formed on the substrate or structure.

[0200] The precursors may contain one or both of carbon and chlorine in addition to the metal element. A film formed using a precursor containing carbon may contain carbon. A film formed using a precursor containing chlorine may contain chlorine.

[0201] As described above, by forming oxide 230 using the ALD method, it is possible to form a metal oxide having a CAAC structure in which the c-axis is oriented approximately parallel to the normal direction of the deposition surface.

[0202] 18A and 18B, the configuration of a film formation apparatus 4000 will be described as an example of an apparatus capable of forming a film using the ALD method. Fig. 18A is a schematic diagram of a multi-chamber type film formation apparatus 4000, and Fig. 18B is a cross-sectional view of an ALD apparatus that can be used for the film formation apparatus 4000.

[0203] <Configuration example of film formation equipment> The film formation apparatus 4000 includes a loading / unloading chamber 4002, a loading / unloading chamber 4004, a transfer chamber 4006, a film formation chamber 4008, a film formation chamber 4009, a film formation chamber 4010, and a transfer arm 4014. The loading / unloading chamber 4002, the loading / unloading chamber 4004, the film formation chamber 4008, the film formation chamber 4009, and the film formation chamber 4010 are each independently connected to the transfer chamber 4006. This allows continuous film formation in the film formation chamber 4008, the film formation chamber 4009, and the film formation chamber 4010 without exposure to the atmosphere, preventing impurities from being mixed into the film. Furthermore, contamination of the interface between the substrate and the film and the interface between each film is reduced, resulting in clean interfaces.

[0204] In addition, it is preferable that the loading / unloading chamber 4002, the loading / unloading chamber 4004, the transfer chamber 4006, and the film forming chambers 4008 to 4010 are filled with an inert gas (such as nitrogen gas) with a controlled dew point to prevent moisture from adhering, and it is desirable to maintain a reduced pressure.

[0205] In addition, an ALD apparatus can be used in the film deposition chambers 4008 to 4010. Also, a configuration may be adopted in which a film deposition apparatus other than the ALD apparatus is used in any one of the film deposition chambers 4008 to 4010. Examples of the film deposition apparatus that can be used in the film deposition chambers 4008 to 4010 include a sputtering apparatus, a plasma CVD (PECVD: Plasma Enhanced CVD) apparatus, a thermal CVD (TCVD: Thermal CVD) apparatus, a photo CVD apparatus, a metal CVD (MCVD: Metal CVD) apparatus, a metal organic CVD (MOCVD: Metal Organic CVD) apparatus, and the like. Further, a device having a function other than the film deposition apparatus may be provided in any one or more of the film deposition chambers 4008 to 4010. Examples of such a device include a heating device (typically, a vacuum heating device), a plasma generation device (typically, a microwave plasma generation device), and the like.

[0206] For example, when the film deposition chamber 4008 is an ALD apparatus, the film deposition chamber 4009 is a PECVD apparatus, and the film deposition chamber 4010 is a metal CVD apparatus, a metal oxide can be formed in the film deposition chamber 4008, an insulating film that functions as a gate insulating film can be formed in the film deposition chamber 4009, and a conductive film that functions as a gate electrode can be formed in the film deposition chamber 4010. At this time, the metal oxide, the insulating film thereon, and the conductive film thereon can be continuously formed without exposing them to the atmosphere.

[0207] Moreover, although the film deposition apparatus 4000 is configured to include the loading / unloading chambers 4002 and 4004 and the film deposition chambers 4008 to 4010, one aspect of the present invention is not limited thereto. A configuration may be adopted in which the number of film deposition chambers of the film deposition apparatus 4000 is four or more. Also, the film deposition apparatus 4000 may be a single wafer type or a batch type in which a plurality of substrates are deposited simultaneously.

[0208] <ALD apparatus> 18B, the configuration of an ALD apparatus that can be used in film formation apparatus 4000 will be described. The ALD apparatus includes a film formation chamber (chamber 4020), a raw material supply unit 4021 (raw material supply unit 4021a and raw material supply unit 4021b), a raw material supply unit 4031, high-speed valves 4022a and 4022b that serve as introduction amount controllers, a raw material inlet 4023 (raw material inlet 4023a and raw material inlet 4023b), a raw material inlet 4033, a raw material outlet 4024, and an exhaust device 4025. Raw material inlet 4023a, raw material inlet 4023b, and raw material inlet 4033 installed in chamber 4020 are connected to raw material supply units 4021a, 4021b, and 4031 via supply pipes and valves, respectively, and raw material outlet 4024 is connected to exhaust device 4025 via an exhaust pipe, valve, and pressure regulator.

[0209] Furthermore, as shown in FIG. 18B, by connecting a plasma generator 4028 to the chamber 4020, film formation can be performed by the plasma ALD method in addition to the thermal ALD method. The plasma generator 4028 is preferably an ICP-type plasma generator using a coil 4029 connected to a high-frequency power source. The high-frequency power source can output power having a frequency of 10 kHz to 100 MHz, preferably 1 MHz to 60 MHz, and more preferably 10 MHz to 60 MHz. For example, it can output power having a frequency of 13.56 MHz or 60 MHz. The plasma ALD method allows film formation without reducing the film formation rate even at low temperatures, so it is suitable for use in single-wafer film formation equipment with low film formation efficiency.

[0210] A substrate holder 4026 is placed inside the chamber, and a substrate 4030 is placed on the substrate holder 4026. The substrate holder 4026 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, the substrate holder 4026 may be floating or grounded. A heater 4027 is provided on the outer wall of the chamber, which can control the temperature of the inside of the chamber 4020, the substrate holder 4026, and the surface of the substrate 4030. The heater 4027 can preferably control the temperature of the surface of the substrate 4030 to between 100°C and 500°C, and more preferably between 200°C and 400°C. The temperature of the heater 4027 itself can preferably be set to between 100°C and 500°C.

[0211] In raw material supplying unit 4021a, raw material supplying unit 4021b, and raw material supplying unit 4031, a raw material gas is formed from a solid raw material or a liquid raw material by a vaporizer, a heating means, etc. Alternatively, raw material supplying unit 4021a, raw material supplying unit 4021b, and raw material supplying unit 4031 may be configured to supply a gaseous raw material gas.

[0212] 18B shows an example in which two raw material supply units 4021 and one raw material supply unit 4031 are provided, but this embodiment is not limited to this. One, or three or more raw material supply units 4021 may be provided. Two or more raw material supply units 4031 may be provided. High-speed valve 4022a and high-speed valve 4022b can be precisely controlled in time, and are configured to control the supply of raw material gas supplied from raw material supply unit 4021a and raw material supply unit 4021b.

[0213] 18B, a substrate 4030 is loaded onto a substrate holder 4026, and the chamber 4020 is sealed. Then, the heater 4027 heats the substrate 4030 to a desired temperature (for example, 100°C to 500°C, preferably 200°C to 400°C). A thin film is formed on the substrate surface by repeating the steps of supplying a source gas from a source supply unit 4021a, exhausting the gas by an exhaust unit 4025, and supplying a source gas from a source supply unit 4031, and exhausting the gas by an exhaust unit 4025. Furthermore, in forming the thin film, a source gas from a source supply unit 4021b may be supplied, and exhausting the gas by an exhaust unit 4025 may be performed. The temperature of the heater 4027 may be determined as appropriate depending on the type of film to be formed, the source gas, the desired film quality, and the heat resistance of the substrate and the films and elements provided thereon. For example, the temperature of the heater 4027 may be set to 200° C. or higher and 300° C. or lower during film formation, or may be set to 300° C. or higher and 500° C. or lower during film formation.

[0214] By forming a film while heating the substrate 4030 using the heater 4027, it is possible to omit a heat treatment of the substrate 4030 that is required in a later step. That is, by using the chamber 4020 or the film formation apparatus 4000 provided with the heater 4027, the formation of a film on the substrate 4030 and the heat treatment of the substrate 4030 can be performed at the same time.

[0215] In the film formation apparatus shown in FIG. 18B, a metal oxide can be formed by appropriately selecting raw materials (such as volatile organometallic compounds) used in raw material supply units 4021 and 4031. When forming an In-Ga-Zn oxide containing indium, gallium, and zinc as the metal oxide, it is preferable to use a film formation apparatus provided with at least three raw material supply units 4021 and at least one raw material supply unit 4031. It is preferable that a precursor containing indium is supplied from the first raw material supply unit 4021, a precursor containing gallium is supplied from the second raw material supply unit 4021, and a precursor containing zinc is supplied from the third raw material supply unit 4021. When a precursor containing indium and gallium is used to form the metal oxide, at least two raw material supply units 4021 may be provided. The precursors described above can be used as the precursor containing indium, the precursor containing gallium, and the precursor containing zinc.

[0216] Furthermore, a reactant is supplied from the raw material supply unit 4031. As the reactant, an oxidizing agent containing at least one of ozone, oxygen, and water can be used.

[0217] 19A to 19C illustrate different configurations of an ALD apparatus that can be used for the film formation apparatus 4000. Note that detailed description of the same configurations and functions as those of the ALD apparatus shown in FIG. 18B may be omitted.

[0218] FIG. 19A is a schematic diagram showing one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4100 includes a reaction chamber 4120 and a plasma generation chamber 4111 disposed above the reaction chamber 4120. The reaction chamber 4120 can be referred to as a chamber. Alternatively, the reaction chamber 4120 and the plasma generation chamber 4111 can be collectively referred to as a chamber. The reaction chamber 4120 includes a raw material inlet 4123 and a raw material outlet 4124, and the plasma generation chamber 4111 includes a raw material inlet 4133. Furthermore, a plasma generation device 4128 can apply high frequency waves such as RF or microwaves to gas introduced into the plasma generation chamber 4111 to generate plasma 4131 within the plasma generation chamber 4111. When generating plasma 4131 using microwaves, microwaves with a frequency of 2.45 GHz are typically used. Plasma generated using such microwaves is sometimes called ECR (Electron Cyclotron Resonance) plasma.

[0219] The reaction chamber 4120 also has a substrate holder 4126, on which a substrate 4130 is placed. The source gas introduced through the source gas inlet 4123 is decomposed by heat from a heater installed in the reaction chamber 4120 and deposited on the substrate 4130. The source gas introduced through the source gas inlet 4133 is converted into a plasma state by the plasma generator 4128. The source gas in the plasma state recombines with electrons and other molecules before reaching the surface of the substrate 4130, becoming a radical state that reaches the substrate 4130. An ALD apparatus that uses radicals to form a film in this way is sometimes called a radical-enhanced ALD (radical-enhanced ALD) apparatus. While the plasma ALD apparatus 4100 has a configuration in which the plasma generation chamber 4111 is installed above the reaction chamber 4120, this embodiment is not limited to this. The plasma generation chamber 4111 may also be installed adjacent to the side of the reaction chamber 4120.

[0220] FIG. 19B is a schematic diagram showing one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4200 includes a chamber 4220. The chamber 4220 includes an electrode 4213, a raw material outlet 4224, and a substrate holder 4226. A substrate 4230 is placed on the substrate holder 4226. The electrode 4213 includes a raw material inlet 4223 and a showerhead 4214 that supplies the introduced raw material gas into the chamber 4220. A power supply 4215 capable of applying high-frequency power is connected to the electrode 4213 via a capacitor 4217. A mechanism for applying a constant potential or high-frequency power may be provided to the substrate holder 4226. Alternatively, the substrate holder 4226 may be floating or grounded. The electrode 4213 and the substrate holder 4226 function as an upper electrode and a lower electrode, respectively, for generating a plasma 4231. The raw material gas introduced from the raw material inlet 4223 is decomposed by heat from a heater provided in the chamber 4220 and deposited on the substrate 4230. Alternatively, the raw material gas introduced from the raw material inlet 4223 becomes a plasma state between the electrode 4213 and the substrate holder 4226. The raw material gas in a plasma state is incident on the substrate 4230 due to a potential difference (also called an ion sheath) generated between the plasma 4231 and the substrate 4230.

[0221] FIG. 19C is a schematic diagram showing an embodiment of a plasma ALD apparatus different from that shown in FIG. 19B. The plasma ALD apparatus 4300 includes a chamber 4320. The chamber 4320 includes an electrode 4313, a raw material outlet 4324, and a substrate holder 4326. A substrate 4330 is placed on the substrate holder 4326. The electrode 4313 includes a raw material inlet 4323 and a showerhead 4314 that supplies the introduced raw material gas into the chamber 4320. A power supply 4315 capable of applying high frequency power is connected to the electrode 4313 via a capacitor 4317. A mechanism for applying a constant potential or high frequency power may be provided to the substrate holder 4326. Alternatively, the substrate holder 4326 may be floating or grounded. The electrode 4313 and the substrate holder 4326 function as an upper electrode and a lower electrode, respectively, for generating plasma 4331. The plasma ALD apparatus 4300 differs from the plasma ALD apparatus 4200 in that it includes a mesh 4319 connected to a power supply 4321 capable of applying high-frequency voltage via a capacitor 4322 between an electrode 4313 and a substrate holder 4326. The provision of the mesh 4319 allows the plasma 4231 to be separated from the substrate 4130. The source gas introduced through the source gas inlet 4323 is decomposed by heat from a heater provided in the chamber 4320 and deposited on the substrate 4330. Alternatively, the source gas introduced through the source gas inlet 4323 becomes a plasma between the electrode 4313 and the substrate holder 4326. The charge of the plasma-state source gas is removed by the mesh 4319, and the source gas reaches the substrate 4130 in an electrically neutral state, such as in the form of radicals. This allows for film formation with reduced ion incidence and plasma damage.

[0222] <Film formation sequence> FIG. 20A shows a film formation sequence using the ALD apparatus shown in FIG. 18B. First, the substrate 4030 is set on the substrate holder 4026 in the chamber 4020 (step S101). Next, the temperature of the heater 4027 is adjusted (step S102). Next, the substrate 4030 is held on the substrate holder 4026 so that the temperature of the substrate 4030 is uniform across the substrate surface (step S103). Next, film formation is performed by the first to fourth steps described above. That is, a first source gas and a second source gas are alternately introduced into the chamber 4020, and a film is formed on the substrate 4030 (step S104). Alternatively, between steps S103 and S104, a process of creating an oxygen atmosphere inside the chamber 4020 may be performed. By creating an oxygen atmosphere inside the chamber 4020 after setting and holding the substrate 4030, oxygen may be added to the substrate 4030 and the film formed on the substrate 4030. Furthermore, hydrogen may be desorbed from the substrate 4030 before film formation and from a film provided on the substrate 4030. Hydrogen in the substrate 4030 or in the film may react with oxygen added to the substrate 4030 or in the film to become water (HO), which may be desorbed from the substrate 4030 or the film.

[0223] 20B shows a specific example of the film formation sequence. In accordance with steps S101 to S103, the substrate 4030 is set on the substrate holder 4026, the temperature of the heater 4027 is adjusted, and the substrate 4030 is held.

[0224] Next, the first and second source gases are alternately introduced to form a film on the substrate 4030 (step S104). The introduction of the first and second source gases is performed in pulses. In FIG. 20B, the introduction of the first and second source gases is indicated by ON, and periods when no source gases are introduced are indicated by OFF. During periods when neither the first nor second source gas is introduced, the chamber 4020 is evacuated. The pulse time for introducing the first source gas into the chamber 4020 is preferably 0.1 to 1 second, and more preferably 0.1 to 0.5 seconds. Furthermore, the period during which the first source gas is not introduced, i.e., the time for evacuating the chamber 4020, is 1 to 15 seconds, and preferably 1 to 5 seconds. The pulse time for introducing the second source gas into chamber 4020 is preferably 0.1 to 30 seconds, more preferably 0.3 to 15 seconds. The period during which the second source gas is not introduced, i.e., the time for evacuating chamber 4020, is 1 to 15 seconds, preferably 1 to 5 seconds.

[0225] The film formation is performed by repeating one cycle of introducing the first raw material gas (first step above), exhausting the first raw material gas (second step above), introducing the second raw material gas (third step above), and exhausting the second raw material gas (fourth step above), to form a film having a desired thickness.

[0226] Furthermore, when performing a process to create an oxygen atmosphere inside the chamber 4020 between steps S103 and S104, a second source gas may be introduced into the chamber 4020. The second source gas preferably includes one or more oxidizing agents selected from ozone (O), oxygen (O), and water (H). In this embodiment, ozone (O) and oxygen (O) are used as the second source gas. The second source gas is preferably introduced in a pulsed manner, as in step S104, but this is not a limitation of the present invention. The second source gas may also be introduced continuously. During periods when the second source gas is not being introduced, the chamber 4020 is evacuated. The pulse time for introducing the second source gas into the chamber 4020 is preferably 0.1 seconds or more and 30 seconds or less, and more preferably 0.3 seconds or more and 15 seconds or less. The period during which the second source gas is not introduced, i.e., the time during which the chamber 4020 is evacuated, is set to 1 second or more and 15 seconds or less, preferably 1 second or more and 5 seconds or less. By introducing the second source gas such as an oxidant into the chamber 4020, the substrate 4030 or a film provided on the substrate 4030 is exposed to the second source gas such as an oxidant.

[0227] It should be noted that if temperature adjustment of heater 4027 is not required after setting substrate 4030 (step S101), this step may be omitted. Also, if it is not necessary to create an oxygen atmosphere inside chamber 4020 after holding substrate 4030 (step S103), this step may be omitted.

[0228] 20C shows an example of a sequence for forming a film using multiple precursor-containing source gases. In FIG. 20C, the precursor-containing source gases are designated as the first, third, and fourth source gases, and the oxidizer-containing source gas is designated as the second source gas. Following steps S101 to S103, the substrate 4030 is set on the substrate holder 4026, the heater 4027 is adjusted to a certain temperature, and the substrate 4030 is held.

[0229] Next, the first source gas, the second source gas, the third source gas, the second source gas, the fourth source gas, and the second source gas are sequentially introduced to form a film on the substrate 4030 (step S104). The introduction of the first to fourth source gases is performed in a pulsed manner. In FIG. 20C, the introduction of the first to fourth source gases is indicated by ON, and a period in which no source gas is introduced is indicated by OFF. During a period in which none of the first to fourth source gases is introduced, the chamber 4020 is evacuated. The pulse time for introducing the first, third, and fourth source gases into the chamber 4020 is preferably 0.1 to 1 second, and more preferably 0.1 to 0.5 seconds. Furthermore, the period during which the first, third, and fourth source gases are not introduced, i.e., the time during which chamber 4020 is evacuated, is from 1 to 15 seconds, preferably from 1 to 5 seconds. The pulse time during which the second source gas is introduced into chamber 4020 is preferably from 0.1 to 30 seconds, more preferably from 0.3 to 15 seconds. Furthermore, the period during which the second source gas is not introduced, i.e., the time during which chamber 4020 is evacuated, is from 1 to 15 seconds, preferably from 1 to 5 seconds.

[0230] The film formation is performed in one cycle, which consists of introducing a first raw material gas, exhausting the first raw material gas, introducing a second raw material gas, exhausting the second raw material gas, introducing a third raw material gas, exhausting the third raw material gas, introducing the second raw material gas, exhausting the second raw material gas, introducing a fourth raw material gas, exhausting the fourth raw material gas, introducing the second raw material gas, and exhausting the second raw material gas. By repeating this cycle, a film having a desired thickness is formed.

[0231] For example, if the first source gas contains a precursor containing indium, the third source gas contains a precursor containing gallium, and the fourth source gas contains a precursor containing zinc, In—Ga—Zn oxide can be formed by the sequence shown in FIG. 20C.

[0232] In the sequence shown in FIG. 20C, the order in which the first, third, and fourth source gases are introduced is not limited to this. Furthermore, the number of times the first, third, and fourth source gases are introduced in one cycle is not limited to one. By introducing a certain source gas multiple times in one cycle, a film containing a high concentration of metal elements contained in that source gas can be formed. In other words, by changing the number of times each gas is introduced, the atomic ratio of the formed film can be controlled. Furthermore, the first, third, and fourth source gases, or two types of source gases selected from these source gases, may be introduced into chamber 4020 simultaneously.

[0233] This embodiment mode can be implemented in appropriate combination with any of the structures described in the other embodiment modes.

[0234] (Embodiment 2) In this embodiment, an example of a semiconductor device including a transistor having a metal oxide described in the above embodiment and a manufacturing method thereof will be described with reference to FIGS. 21A to 44B.

[0235] <Configuration example of semiconductor device> The structure of a semiconductor device including a transistor 200 having a metal oxide described in the previous embodiment will be described with reference to FIGS. 21A to 21D. FIGS. 21A to 21D are top views and cross-sectional views of a semiconductor device including the transistor 200. FIG. 21A is a top view of the semiconductor device. FIGS. 21B to 21D are cross-sectional views of the semiconductor device. FIG. 21B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 21A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 21C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 21A and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 21D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 21A. Note that some elements are omitted from the top view in FIG. 21A for clarity.

[0236] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, and an insulator 284 over the insulator 283. The insulators 212, 214, 280, 282, 283, and 284 function as interlayer films. The semiconductor device also includes a conductor 240a and a conductor 240b that are electrically connected to the transistor 200 and function as plugs. Note that an insulator 241a is provided in contact with a side surface of the conductor 240a, and an insulator 241b is provided in contact with a side surface of the conductor 240b. Furthermore, a conductor 246a electrically connected to the conductor 240a and functioning as a wiring is provided on the insulator 284, the conductor 240a, and the conductor 240b, and a conductor 246b electrically connected to the conductor 240b and functioning as a wiring is provided on the insulator 284, the conductor 240a, and the conductor 240b. Furthermore, an insulator 286 is provided on the conductor 246a, the conductor 246b, and the insulator 284.

[0237] Insulator 241a is provided in contact with the inner walls of the openings of insulators 280, 282, 283, and 284, etc., and a first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, with a second conductor of conductor 240a provided further inward. In addition, insulator 241b is provided in contact with the inner walls of the openings of insulators 280, 282, 283, and 284, etc., and a first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, with a second conductor of conductor 240b provided further inward. Here, the height of the upper surface of conductor 240a (conductor 240b) and the height of the upper surface of insulator 284 in the region overlapping with conductor 246a (conductor 246b) can be made approximately the same. Although the transistor 200 has been described with a stacked structure of the first conductors of the conductors 240a and 240b and the second conductor of the conductor 240, the present invention is not limited to this. For example, the conductors 240a and 240b may each be configured as a single layer or a stacked structure of three or more layers. When a structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to indicate the order of formation.

[0238] [Transistor 200] As shown in FIGS. 21A to 21D, the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) disposed so as to be embedded in the insulator 214 and / or the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 243a, an oxide 243b, and an oxide 230c on the oxide 230b. conductor 242a on oxide 243a, conductor 242b on oxide 243b, oxide 230d on oxide 230c, insulator 250 on oxide 230d, conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping with part of oxide 230c, and insulator 254 in contact with the top surface of insulator 224, the side of oxide 230a, the side of oxide 230b, the side of conductor 242a, the top surface of conductor 242a, the side of conductor 242b, and the top surface of conductor 242b. Oxide 230c also contacts the side of oxide 243a, the side of oxide 243b, the side of conductor 242a, and the side of conductor 242b. Additionally, the insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, the oxide 230d, the oxide 230c, and the insulator 280.

[0239] An opening reaching the oxide 230b is provided in the insulator 280. The oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 are disposed in the opening. In addition, the conductor 260, the insulator 250, the oxide 230d, and the oxide 230c are disposed between the conductor 242a and the oxide 243a and between the conductor 242b and the oxide 243b in the channel length direction of the transistor 200. The insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. The oxide 230c has a region in contact with the oxide 230b, a region overlapping with the side surface of the conductor 260 via the oxide 230d and the insulator 250, and a region overlapping with the bottom surface of the conductor 260 via the oxide 230d and the insulator 250.

[0240] Preferably, oxide 230 comprises oxide 230a disposed on insulator 224, oxide 230b disposed on oxide 230a, oxide 230c disposed on oxide 230b and at least partially in contact with oxide 230b, and oxide 230d disposed on oxide 230c.

[0241] Note that, in the transistor 200, the oxide 230 has a four-layer structure of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d. However, the present invention is not limited to this. For example, the oxide 230 may have a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230d, or a stacked structure of five or more layers. Alternatively, each of the oxides 230a, the oxide 230b, the oxide 230c, and the oxide 230d may have a stacked structure.

[0242] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulators 250, 224, and 222 function as gate insulators. The conductor 242a functions as one of a source and a drain, and the conductor 242b functions as the other of the source and the drain. The oxide 230 functions as a channel formation region.

[0243] The oxide 230 has a region 234 (not shown) that functions as a channel formation region of the transistor 200 and regions 236 (not shown) that function as source or drain regions, sandwiching the region 234. The region 234 at least partially overlaps with the conductor 260. The conductors 242a and 242b are provided on the oxide 230b, and regions with lower resistance are formed in the region 236 near the conductors 242a and 242b.

[0244] The region 236 functioning as a source region or a drain region is a region with a low resistance due to an increased carrier concentration caused by a low oxygen concentration, the inclusion of impurities such as hydrogen, nitrogen, or metal elements, etc. That is, the region 236 is a region with a higher carrier concentration and a lower resistance than the region 234. The region 234 functioning as a channel formation region is a region with a lower carrier concentration and a higher resistance due to a higher oxygen concentration or a lower impurity concentration than the region 236. Furthermore, a region with an oxygen concentration equal to or higher than that of the region 236 and equal to or lower than that of the region 234 may be formed between the regions 234 and 236.

[0245] In the transistor 200, the metal oxide described in the above embodiment may be used for the oxide 230 (the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d) including the channel formation region.

[0246] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Also, the oxide 230 preferably has a stacked structure of multiple oxide layers that have a common element (main component) other than oxygen.

[0247] Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 230a or oxide 230d is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b or oxide 230c. The greater the atomic ratio of element M to In, the easier it is to suppress the diffusion of impurities or oxygen. Therefore, by providing oxide 230a below oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below oxide 230a to oxide 230b. Furthermore, by providing oxide 230d on oxide 230c, it is possible to suppress the diffusion of impurities from structures formed above oxide 230d to oxide 230c.

[0248] In other words, the atomic ratio of In to element M in the metal oxide used for oxide 230b or oxide 230c is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a or oxide 230d. In this case, the main carrier path is oxide 230b, oxide 230c, or the vicinity thereof, for example, the interface between oxide 230b and oxide 230c. Furthermore, since oxide 230b and oxide 230c have a common element other than oxygen (as a main component), the defect level density at the interface between oxide 230b and oxide 230c can be reduced, thereby minimizing the effect of interface scattering on carrier conduction and achieving a high on-current.

[0249] To make the oxide 230c the main carrier path, the atomic ratio of indium to the main metal element in the oxide 230c is preferably larger than the atomic ratio of indium to the main metal element in the oxide 230b. Using a metal oxide with a high indium content for the channel formation region can increase the on-state current of the transistor. Therefore, this structure allows the oxide 230c to serve as the main carrier path.

[0250] Furthermore, to make the oxide 230c the main carrier path, the conduction band minimum of the oxide 230c is preferably farther from the vacuum level than the conduction band minimums of the oxides 230a, 230b, and 230d. In other words, the electron affinity of the oxide 230c is preferably greater than the electron affinity of the oxides 230a, 230b, and 230d.

[0251] The oxide 230b and the oxide 230c are preferably crystalline. In particular, it is preferable to use the metal oxides described in the previous embodiments as the oxide 230b and the oxide 230c. The oxide 230d may also be crystalline.

[0252] By using the above metal oxide for the oxide 230b and the oxide 230c, it is possible to reduce impurities and oxygen vacancies in the regions where channels are formed in the oxide 230b and the oxide 230c, thereby suppressing fluctuations in electrical characteristics, realizing stable electrical characteristics, and providing a transistor with improved reliability.

[0253] Furthermore, the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0254] Furthermore, the metal oxide has the property of easily transferring oxygen in a direction perpendicular to the c-axis of the crystal of the metal oxide, so that oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b.

[0255] The metal oxide has a highly crystalline, dense structure with few impurities and defects (such as oxygen vacancies). In particular, after forming the metal oxide, the metal oxide can be made to have a more crystalline, dense structure by being heat-treated at a temperature (e.g., 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize. In this way, by further increasing the density of the metal oxide, the diffusion of impurities or oxygen in the metal oxide can be further reduced.

[0256] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in the channel formation region of the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies is formed as a defect where hydrogen enters the oxygen vacancy (hereinafter referred to as V OOxygen vacancies may be formed in the channel formation region of an oxide semiconductor, generating electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and current flows through the transistor). Therefore, it is preferable that impurities and oxygen vacancies are reduced as much as possible in the channel formation region of an oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region of an oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0257] To address this issue, an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) may be provided near the oxide semiconductor, and heat treatment may be performed to supply oxygen from the insulator to the oxide semiconductor. This allows oxygen vacancies in the channel formation region in the oxide semiconductor to be repaired by the supplied oxygen. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide semiconductor, and the hydrogen can be removed as HO (dehydration). This allows V to be added to the oxide semiconductor. O The formation of H defects can be suppressed.

[0258] However, if an excessive amount of oxygen is supplied to the source region or the drain region, the carrier concentration in the source region or the drain region may decrease, which may cause a decrease in the on-current or the field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device having the transistor.

[0259] Therefore, in the oxide semiconductor, the region 234 that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, while the region 236 that functions as a source or drain region preferably has a high carrier concentration and is n-type. In other words, it is preferable to supply oxygen to the region 234 of the oxide semiconductor and to prevent excessive oxygen from being supplied to the region 236.

[0260] As mentioned above, the defect where hydrogen enters the oxygen vacancy (V O H defects) may generate electrons that act as carriers. Therefore, oxide semiconductors have O It is preferable that the diffusion of H defects is suppressed. O H defects are V O There are two cases: diffusion as H defects, and diffusion of hydrogen that has been desorbed from oxygen defects and then enters other oxygen defects.

[0261] For example, by increasing the crystallinity of the metal oxide used for the oxide 230b, it is possible to suppress the hydrogen in the oxygen vacancies from being desorbed or diffused from the oxygen vacancies. O Diffusion of H defects can be suppressed. Therefore, it is possible to maintain an i-type or substantially i-type region and an n-type region in the oxide semiconductor. Therefore, it is possible to manufacture a semiconductor device having a highly reliable transistor. Furthermore, it is possible to manufacture a semiconductor device with little variation in transistor characteristics. The diffusion of hydrogen in oxygen vacancies in metal oxides and desorption from the oxygen vacancies will be described later.

[0262] Furthermore, for example, oxygen can be injected into the insulator 224 by forming the insulator 254 by a sputtering method. Then, the oxygen injected into the insulator 224 is supplied to the oxide 230b via the oxide 230c. This allows oxygen to be selectively supplied to the oxide 230c, which occupies most of the region 234, and to the region of the oxide 230b in contact with the oxide 230c.

[0263] Furthermore, by using the metal oxide described in the previous embodiment as the oxide 230b, it is possible to reduce the diffusion of impurities and oxygen in the oxide 230b, thereby reducing the diffusion of oxygen supplied to the region 234 of the oxide 230b into the region 236 of the oxide 230b.

[0264] Furthermore, a portion of the excess oxygen that has diffused into the oxide 230c also diffuses into the oxide 230d. Since oxygen is less likely to diffuse into the oxide 230d than into the oxide 230c, the diffusion of oxygen into the insulator 250 is relatively suppressed. This makes it possible to suppress the oxidation of the conductor 260 via the insulator 250.

[0265] In this manner, oxygen is selectively supplied to the oxide semiconductor region 234, making the region 234 i-type or substantially i-type, and oxygen diffusion into the region 236 functioning as a source or drain region is suppressed, thereby maintaining the n-type nature of the region 236. This suppresses fluctuations in the electrical characteristics of the transistor 200, and thus suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0266] <Hydrogen diffusion in oxygen vacancies or desorption from oxygen vacancies> In this section, we use calculations to evaluate the diffusion of hydrogen into oxygen vacancies and the desorption of hydrogen from oxygen vacancies in metal oxides. Specifically, we use first-principles molecular dynamics calculations and first-principles calculations that incorporate chemical reaction path search techniques.

[0267] <<Calculation model 1>> Here, we will explain the calculation model used in the first-principles molecular dynamics calculation.

[0268] As calculation models, we prepared a model of single-crystal In-Ga-Zn oxide and a model of amorphous In-Ga-Zn oxide. Hereafter, the model of single-crystal In-Ga-Zn oxide will be referred to as the c-IGZO model, and the model of amorphous In-Ga-Zn oxide will be referred to as the a-IGZO model. The a-IGZO model was created using the melt-quench method.

[0269] The compositions of the c-IGZO model and the a-IGZO model are In:Ga:Zn:O=1:1:1:4 [atomic ratio]. The c-IGZO model is composed of 56 atoms, while the a-IGZO model is composed of 84 atoms. The density of the a-IGZO model is 5.8 g / cm 3 is.

[0270] Next, one oxygen atom is replaced with one hydrogen atom in each of the c-IGZO model and the a-IGZO model. After the replacement, the c-IGZO model and the a-IGZO model each have a defect (V O H defect, or H O This is sometimes called a defect.

[0271] V O The c-IGZO and a-IGZO models containing H defects are shown in Figures 22A and 22B, respectively.

[0272] This concludes the explanation of the calculation model.

[0273] <<Calculation conditions 1>> Next, the calculation conditions for the first-principles molecular dynamics calculation will be explained.

[0274] The first-principles molecular dynamics calculations were performed using the first-principles electronic structure calculation package VASP. The calculation conditions are shown in Table 5.

[0275] [Table 5]

[0276] The electronic state pseudopotential was generated by the PAW method, and the functional was GGA-PBE. The k-point grid was set to 1×1×1.

[0277] The lattice vectors (axis lengths and angles between axes) of the calculation model are fixed. In other words, first-principles molecular dynamics calculations are performed under constant conditions (NVT ensemble) for the number of particles (N), volume (V), and temperature (T). In addition, a Nose-Hoover thermostat is used to control the temperature in first-principles molecular dynamics calculations.

[0278] V O c-IGZO model containing H defects and V O For each a-IGZO model containing H defects, the temperature was set to 600°C, 800°C, or 1000°C, and the simulation time was set to 50p (=5 × 10 -11 ) seconds and perform ab initio molecular dynamics calculations.

[0279] <<Hydrogen diffusion in oxygen vacancies>> The trajectories of hydrogen atoms during the first-principles molecular dynamics calculations are shown in Figures 23A to 23F. O 23D to 23F show the trajectories of hydrogen atoms during first-principles molecular dynamics calculations in a c-IGZO model containing H defects. O These figures show the trajectories of hydrogen atoms during first-principles molecular dynamics calculations for an a-IGZO model containing H defects. Figures 23A and 23D show the trajectories of hydrogen atoms during first-principles molecular dynamics calculations when the temperature is set to 600°C. Figures 23B and 23E show the trajectories of hydrogen atoms during first-principles molecular dynamics calculations when the temperature is set to 800°C. Figures 23C and 23F show the trajectories of hydrogen atoms during first-principles molecular dynamics calculations when the temperature is set to 1000°C.

[0280] From Figures 23A to 23C, V OIn the c-IGZO model containing H vacancies, the hydrogen in the oxygen vacancies remained within the oxygen vacancies at all temperatures, and no desorption behavior from the oxygen vacancies was observed.

[0281] On the other hand, from FIGS. 23D to 23F, V O In the a-IGZO model containing H vacancies, hydrogen in the oxygen vacancies was observed to desorb from the oxygen vacancies and diffuse within the model at all temperatures. It was also confirmed that hydrogen desorbed from the oxygen vacancies bound to lattice oxygen and diffused.

[0282] This suggests that increasing the crystallinity of the metal oxide makes it difficult for hydrogen in the oxygen vacancies to be released from the oxygen vacancies.

[0283] <<Calculation model 2>> Next, a calculation model used in first-principles calculations that utilize a chemical reaction path search method will be described.

[0284] As a calculation model, V O We prepare c-IGZO and a-IGZO models containing H defects.

[0285] In addition, V O The c-IGZO model containing H defects is based on the V O The c-IGZO model containing H defects has the same composition and density, but the number of constituent atoms is different. O The c-IGZO model containing the H defect consists of 112 atoms.

[0286] Also, V O The a-IGZO model containing H defects is based on the V O We use an a-IGZO model containing H defects.

[0287] <<Calculation conditions 2>> Next, the calculation conditions for the first-principles calculation using the chemical reaction path search method will be explained.

[0288] For the first-principles calculations, the first-principles electronic structure calculation package VASP was used, and the Nudged Elastic Band (NEB) method, a chemical reaction path search method, was employed. The NEB method is a method for finding the state with the lowest required energy among the states connecting the initial and final states. The activation energy is defined as the difference between the maximum energy within the path and the energy of the most stable structure on the path.

[0289] The calculation conditions shown in Table 5 were used for the first-principles calculation using the NEB method. The k-point grid was V O For the c-IGZO model containing H defects, we set the value to 2 × 2 × 3, and V O For the a-IGZO model containing H defects, we used 2 × 2 × 2.

[0290] Figure 24 shows V O This shows the pathway by which hydrogen in oxygen vacancies desorbs from the oxygen vacancies in a c-IGZO model containing H vacancies. O In the c-IGZO model containing H defects, calculations are performed using the NEB method for the four paths (paths A to D) indicated by arrows in FIG.

[0291] In the amorphous state, the structure is arbitrary, so it is difficult to perform calculations using the NEB method. O In the first-principles molecular dynamics calculations performed on an a-IGZO model containing H defects at a temperature of 600°C, the atomic structure before the hydrogen in the oxygen vacancy is released from the oxygen vacancy is taken as the initial state, and the atomic structure after the hydrogen in the oxygen vacancy is released from the oxygen vacancy is taken as the final state. Calculations are performed using the atomic structures in the initial and final states with the aid of the NEB method. In this calculation, 45 pairs of atomic structures in the initial and final states are prepared. That is, V O For the a-IGZO model containing H defects, calculations are performed using the NEB method for 45 paths.

[0292] <<Activation energy>> The transition of energy during the process in which hydrogen in an oxygen vacancy is desorbed from the oxygen vacancy, which was obtained by calculation using the NEB method, is shown in Figures 25A and 25B. O FIG. 25B shows the energy transition in the path C (see FIG. 24) of the c-IGZO model containing H defects. O 25A and 25B show the transition of energy in a certain path in an a-IGZO model containing H defects. In Fig. 25A and Fig. 25B, the horizontal axis is the reaction coordinate and the vertical axis is energy (eV).

[0293] From Figures 25A and 25B, the energy required for hydrogen in the oxygen vacancy to be released from the oxygen vacancy (activation energy) is V O 1.50 eV for path C of the c-IGZO model containing H defects, and V O For the a-IGZO model containing H defects, it was 0.85 eV.

[0294] The atomic structures in the reaction coordinates indicated by the numbers on the horizontal axis of Figure 25A are shown in Figures 26A to 26G. Figures 26A to 26G show the atomic structures in the reaction coordinates indicated by the numbers 1 to 7 on the horizontal axis of Figure 25A, respectively. Figures 27A to 27G show the atomic structures in the reaction coordinates indicated by the numbers on the horizontal axis of Figure 25B, respectively. Figures 27A to 27G show the atomic structures in the reaction coordinates indicated by the numbers 1 to 7 on the horizontal axis of Figure 25B, respectively.

[0295] From Figures 27A to 27G, V O In the a-IGZO model containing H vacancies, it was confirmed that the oxygen that captures hydrogen assists the desorption of hydrogen from the oxygen vacancies by approaching the hydrogen. O Compared with the c-IGZO model containing H defects, V O In the a-IGZO model containing H vacancies, it is estimated that the activation energy for hydrogen desorption from oxygen vacancies is lower.

[0296] Next, the reaction frequency Γ was calculated using the calculated activation energy and the following formula.

[0297]

number

[0298] In the above formula, E a is the activation energy, and k B is the Boltzmann constant, T is the absolute temperature, and ν is the frequency factor.

[0299] The calculated reaction frequency Γ is shown in Table 6. The reaction frequency Γ is calculated by multiplying the frequency factor ν by 10 13 s -1 The calculation is based on the assumption that the absolute temperature T is 125°C.

[0300] [Table 6]

[0301] From the value of the reaction frequency Γ shown in Table 6, V O In the a-IGZO model containing H defects, it is clear that hydrogen desorption from oxygen vacancies occurs easily at 125°C. O In the c-IGZO model containing H defects, it is clear that hydrogen desorption from oxygen vacancies is difficult to occur at 125°C. O The c-IGZO model containing H defects exhibits V O It can be seen that hydrogen desorption from oxygen vacancies is less likely to occur than in the a-IGZO model containing H vacancies. This suggests that increasing the crystallinity of the metal oxide makes it more difficult for hydrogen in oxygen vacancies to desorb from the oxygen vacancies.

[0302] The activation energies of the four routes (route A to route D) indicated by arrows in FIG. 24 are shown in Table 7.

[0303] [Table 7]

[0304] From Table 7, V OIn the c-IGZO model containing H defects, it can be seen that among routes A to D, route C has the smallest activation energy.

[0305] V O A histogram of activation energies for 45 paths in the a-IGZO model containing H defects is shown in Fig. 28. In Fig. 28, the horizontal axis represents the activation energy E a (eV), and the vertical axis is the number of structures. O In the a-IGZO model containing H defects, the activation energy E a The average value of is 0.75 eV, and the activation energy E a The minimum value of is 0.25 eV.

[0306] From Table 7 and Figure 28, V O In the a-IGZO model containing H defects, the energy required for hydrogen in the oxygen vacancy to desorb from the oxygen vacancy (activation energy) is V O It can be seen that this is much smaller than the c-IGZO model containing H defects.

[0307] As described above, increasing the crystallinity of the metal oxide can suppress desorption of hydrogen from oxygen vacancies. Therefore, using a highly crystalline metal oxide for the oxide 230 can suppress diffusion of hydrogen from the source or drain region to the channel formation region. Therefore, in the oxide semiconductor, an i-type or substantially i-type region and an n-type region can be maintained. Therefore, a semiconductor device having a highly reliable transistor can be manufactured. Furthermore, a semiconductor device with little variation in transistor characteristics can be manufactured. Furthermore, a semiconductor device that can be miniaturized can be provided.

[0308] The above is an explanation of the diffusion of hydrogen in oxygen vacancies or desorption from oxygen vacancies in metal oxides.

[0309] The oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230c, and more preferably contains all of the metal elements. For example, the oxide 230c may be an In-M-Zn oxide, an In-Zn oxide, or an indium oxide, and the oxide 230d may be an In-M-Zn oxide, an M-Zn oxide, or an oxide of element M. This reduces the defect state density at the interface between the oxide 230c and the oxide 230d.

[0310] Furthermore, the oxide 230d is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c. By providing the oxide 230d between the insulator 250 and the oxide 230c, it is possible to suppress the diffusion of oxygen contained in the insulator 280 into the insulator 250. Therefore, the oxygen can be efficiently supplied to the oxide 230b via the oxide 230c.

[0311] Furthermore, by making the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230d smaller than the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230c, it is possible to suppress diffusion of In toward the insulator 250. Because the insulator 250 functions as a gate insulator, if In gets mixed into the insulator 250, etc., it will cause poor transistor characteristics. Therefore, by providing the oxide 230d between the oxide 230c and the insulator 250, it is possible to provide a highly reliable semiconductor device.

[0312] Here, the conduction band minimum changes smoothly at the junctions between the oxides 230a, 230b, 230c, and 230d. In other words, the conduction band minimum at the junctions between the oxides 230a, 230b, 230c, and 230d changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layers formed at the interfaces between the oxides 230a and 230b, between the oxides 230b and 230c, and between the oxides 230c and 230d.

[0313] Specifically, when the oxide 230a and the oxide 230b, the oxide 230b and the oxide 230c, and the oxide 230c and the oxide 230d have a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a, the oxide 230c, and the oxide 230d may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, indium oxide, or the like.

[0314] Specifically, oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. Oxide 230b and oxide 230c may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Oxide 230d may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, an atomic ratio of M:Zn=2:1 or a similar composition, or an atomic ratio of M:Zn=2:5 or a similar composition, or an oxide of element M. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0315] By configuring the oxides 230a, 230b, 230c, and 230d as described above, the defect state density can be reduced at the interface between the oxides 230a and 230b, the interface between the oxides 230b and 230c, and the interface between the oxides 230c and 230d, which reduces the effect of interface scattering on carrier conduction, allowing the transistor 200 to achieve a large on-state current and high frequency characteristics.

[0316] In addition, in a cross-sectional view of the transistor in the channel length direction, a groove is preferably formed in the oxide 230b, and the oxide 230c having the CAAC-OS is preferably filled in the groove. In this case, the oxide 230c is disposed so as to cover the inner wall (side wall and bottom surface) of the groove.

[0317] Furthermore, in a cross-sectional view of the transistor in the channel length direction, the depth of the groove in the oxide 230b preferably roughly coincides with the film thickness of the oxide 230c. In other words, it is preferable that the top surface of the oxide 230c in the region overlapping with the oxide 230b be positioned so that it roughly coincides with the interface between the oxide 230b and the oxide 243a or the oxide 243b. For example, with respect to the bottom surface of the insulator 222, the difference in height between the interface between the oxide 230b and the oxide 243a or the oxide 243b and the interface between the oxide 230c and the oxide 230d is preferably equal to or less than the film thickness of the oxide 230c, and more preferably equal to or less than half the film thickness of the oxide 230c.

[0318] By using the above configuration, V O The influence of defects and impurities such as H can be reduced, and a channel can be formed in the oxide 230c. This allows the transistor to have good electrical characteristics. Furthermore, a semiconductor device with little variation in transistor characteristics and good reliability can be provided.

[0319] 21B shows a configuration in which the side surface of the opening into which the conductor 260 and the like are embedded, including the groove portion of the oxide 230b, is substantially perpendicular to the surface on which the oxide 230b is formed, but this is not a limitation of one embodiment of the present invention. The bottom of the opening may be U-shaped, with a gently curved surface.

[0320] Here, in the oxide 230c, the c-axis of the crystal of the metal oxide described in the previous embodiment preferably faces in a direction substantially perpendicular to the surface of the oxide 230c on which the oxide 230c is formed or the surface in contact with the oxide 230d. Therefore, the crystal layer has a region extending substantially parallel to the bottom and side surfaces of the opening. It is more preferable that the oxide 230d also have a crystal structure similar to that of the oxide 230c.

[0321] 21C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0322] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242a or 242b, or smaller than half the length of the region of the top surface of the oxide 230b that does not have the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape improves the coverage of the groove with the insulator 250 and conductor 260 formed in a later process. Furthermore, it is possible to prevent a decrease in the length of the region of the top surface of the oxide 230b that does not have the curved surface, thereby suppressing a decrease in the on-state current and mobility of the transistor 200. Therefore, a semiconductor device with excellent electrical characteristics can be provided.

[0323] Note that the oxide 230c may be provided for each transistor 200. That is, the oxide 230c of one transistor 200 and the oxide 230c of another transistor 200 adjacent to the transistor 200 may not be in contact with each other. Alternatively, the oxide 230c of one transistor 200 and the oxide 230c of another transistor 200 adjacent to the transistor 200 may be separated from each other. In other words, the oxide 230c may not be disposed between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0324] In a semiconductor device in which multiple transistors 200 are arranged in the channel width direction, the above structure allows the oxide 230c to be independently provided in each transistor 200. This can prevent a parasitic transistor from being formed between a transistor 200 and a transistor 200 adjacent to the transistor 200, thereby preventing a leakage path from being formed along the conductor 260. This makes it possible to provide a semiconductor device that has favorable electrical characteristics and can be miniaturized or highly integrated.

[0325] For example, if the distance between the side edge of the oxide 230c of one transistor 200 and the side edge of the oxide 230c of another transistor 200 adjacent to the transistor 200, which face each other in the channel width direction of the transistor 200, is represented as L1, L1 is set to be greater than 0 nm. Furthermore, if the distance between the side edge of the oxide 230a of one transistor 200 and the side edge of the oxide 230a of another transistor 200 adjacent to the transistor 200, which face each other in the channel width direction of the transistor 200, is represented as L2, the ratio of L1 to L2 (L1 / L2) is preferably greater than 0 and less than 1, more preferably 0.1 to 0.9, and even more preferably 0.2 to 0.8. Note that L2 may also be the distance between the side edge of the oxide 230b of one transistor 200 and the side edge of the oxide 230b of another transistor 200 adjacent to the transistor 200, which face each other.

[0326] By reducing the ratio of L1 to L2 (L1 / L2), even if a misalignment occurs in the region where oxide 230c is not located between transistor 200 and the transistor 200 adjacent to said transistor 200, oxide 230c of transistor 200 can be separated from oxide 230c of the transistor 200 adjacent to said transistor 200.

[0327] Furthermore, by increasing the ratio of L1 to L2 (L1 / L2), the minimum processing dimension width can be ensured even if the distance between transistor 200 and the transistor 200 adjacent to that transistor 200 is narrowed, and further miniaturization or high integration of the semiconductor device can be achieved.

[0328] Note that the conductor 260 and the insulator 250 may be shared between adjacent transistors 200. That is, the conductor 260 of one transistor 200 has a region provided continuously with the conductor 260 of another transistor 200 adjacent to the transistor 200. Furthermore, the insulator 250 of one transistor 200 has a region provided continuously with the insulator 250 of another transistor 200 adjacent to the transistor 200.

[0329] With the above structure, the oxide 230d has a region in contact with the insulator 224 between the transistor 200 and another transistor 200 adjacent to the transistor 200. Note that the oxide 230d of one transistor 200 may be separated from the oxide 230d of another transistor 200 adjacent to the transistor 200. In this case, the insulator 250 has a region in contact with the insulator 224 between the transistor 200 and another transistor 200 adjacent to the transistor 200.

[0330] The insulators 212, 214, 254, 282, 283, 284, and 286 preferably function as barrier insulating films that suppress the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, the insulators 212, 214, 254, 282, 283, 284, and 286 are preferably made of an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, the insulators 212, 214, 254, 282, 283, 284, and 286 are preferably made of an insulating material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (i.e., through which the above oxygen is less likely to permeate).

[0331] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0332] For example, it is preferable to use silicon nitride or the like for the insulators 212, 283, and 284, and aluminum oxide or the like for the insulators 214, 254, and 282. This can prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 through the insulators 212 and 214. Alternatively, it can prevent oxygen contained in the insulator 224 or the like from diffusing to the substrate side through the insulators 212 and 214. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 254, 282, 283, and 284, which have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0333] It may also be preferable to reduce the resistivity of the insulators 212, 284, and 286. For example, it may be preferable to reduce the resistivity of the insulators 212, 284, and 286 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulator 212, the insulator 284, and the insulator 286 may be able to reduce charge-up of the conductor 205, the conductor 242a, the conductor 242b, the conductor 260, the conductor 246a, or the conductor 246b in a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulator 212, the insulator 284, and the insulator 286 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0334] Note that the insulator 283 or the insulator 284 does not necessarily have to be provided.

[0335] Furthermore, the insulators 216 and 280 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 216 and 280 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0336] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0337] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260 .

[0338] As shown in FIG. 21A, the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 21C, the conductor 205 preferably extends to areas outside the ends of the oxides 230a and 230b that intersect with the channel width direction. In other words, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator outside the side surfaces of the oxide 230 in the channel width direction. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gate electrodes is referred to as a surrounded channel (S-channel) structure.

[0339] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0340] 21C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0341] Note that, in the transistor 200, the conductor 205 has a stacked structure of the conductor 205a and the conductor 205b, but the present invention is not limited to this. For example, the conductor 205 may have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, it may be distinguished by assigning an ordinal number to the order of formation.

[0342] Here, the conductor 205a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0343] By using a conductive material capable of suppressing oxygen diffusion for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials capable of suppressing oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be a multilayer of tantalum, tantalum nitride, ruthenium, or ruthenium oxide with titanium or titanium nitride.

[0344] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 205b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the conductive material.

[0345] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0346] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 or the oxygen contained in the oxide 230.

[0347] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0348] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0349] The insulator 224 in contact with the oxide 230 preferably releases oxygen by heating. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0350] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 224. The oxide film from which oxygen is released by heating is an oxide film from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0351] Furthermore, one or more of heat treatment, microwave treatment, and RF treatment may be performed while the insulator having the excess oxygen region is in contact with the oxide 230. By performing such treatment, water or hydrogen in the oxide 230 can be removed. In addition, some of the hydrogen may be diffused or captured (also called gettering) in the conductor 242a and the conductor 242b.

[0352] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 230 or an insulator near the oxide 230 by applying RF to the substrate side. The microwave treatment may be performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0353] During the manufacturing process of the transistor 200, heat treatment is preferably performed while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100°C to 450°C, more preferably 350°C to 400°C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230, thereby reducing oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to replenish desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more, followed by another heat treatment in a nitrogen gas or inert gas atmosphere.

[0354] By subjecting the oxide 230 to oxygen addition treatment, the oxygen vacancies in the oxide 230 can be repaired by the supplied oxygen. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 230, and the hydrogen can be removed as H2O (dehydrated). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0355] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structures are not limited to those made of the same material, and may be those made of different materials.

[0356] Oxide 243a and oxide 243b may be provided on oxide 230b.

[0357] The oxide 243a and the oxide 243b preferably have a function of suppressing oxygen permeation. By disposing the oxide 243a (oxide 243b) having a function of suppressing oxygen permeation between the conductor 242a (conductor 242b) functioning as a source electrode or a drain electrode and the oxide 230b, the electrical resistance between the conductor 242a (conductor 242b) and the oxide 230b is reduced, which is preferable. This structure can improve the electrical characteristics and reliability of the transistor 200. Note that if the electrical resistance between the conductor 242a (conductor 242b) and the oxide 230b can be sufficiently reduced, the oxide 243a (oxide 243b) may not be provided.

[0358] Metal oxides containing the element M may be used for the oxides 243a and 243b. The element M may be aluminum, gallium, yttrium, or tin. The oxides 243a and 243b preferably have a higher concentration of the element M than the oxide 230b. Gallium oxide may be used for the oxides 243a and 243b. Metal oxides such as In-M-Zn oxide may be used for the oxides 243a and 243b. Specifically, the atomic ratio of the element M to In in the metal oxide used for the oxides 243a and 243b is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. The film thickness of the oxides 243a and 243b is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. The oxides 243a and 243b preferably have crystallinity. When the oxide 243a and the oxide 243b are crystalline, they can suitably suppress the release of oxygen from the oxide 230. For example, if the oxide 243a and the oxide 243b have a crystalline structure such as a hexagonal crystal, they may be able to suppress the release of oxygen from the oxide 230.

[0359] The conductor 242a is provided over the oxide 243a, and the conductor 242b is provided over the oxide 243b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0360] For example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum are preferably used as the conductors 242a and 242b. In one embodiment of the present invention, nitrides containing tantalum are particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel may also be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0361] A curved surface may exist between the side surface of the conductor 242a (conductor 242b) and the top surface of the conductor 242a (conductor 242b). In other words, the end of the side surface and the end of the top surface may be curved. The curved surface has a radius of curvature of, for example, 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of each of the conductors 242a and 242b. The lack of corners at the end improves film coverage in the subsequent film formation process.

[0362] If the oxide 243a (oxide 243b) is not provided, contact between the conductor 242a (conductor 242b) and the oxide 230b or the oxide 230c may cause oxygen in the oxide 230b or the oxide 230c to diffuse into the conductor 242a (conductor 242b), resulting in oxidation of the conductor 242a (conductor 242b). The oxidation of the conductors 242a and 242b is likely to result in a decrease in the conductivity of the conductors 242a and 242b. The diffusion of oxygen in the oxide 230b or the oxide 230c to the conductors 242a and 242b can be expressed as the conductors 242a and 242b absorbing the oxygen in the oxide 230b or the oxide 230c.

[0363] Furthermore, oxygen in the oxide 230b or the oxide 230c diffuses into the conductor 242a and the conductor 242b, which may form layers between the conductor 242a and the oxide 230b, between the conductor 242b and the oxide 230b, or between the conductor 242a and the oxide 230c, and between the conductor 242b and the oxide 230c. Because these layers contain more oxygen than the conductor 242a or the conductor 242b, they are presumed to have insulating properties. In this case, the three-layer structure of the conductor 242a or the conductor 242b, the layer, and the oxide 230b or the oxide 230c can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and can be regarded as a metal-insulator-semiconductor (MIS) structure or a diode junction structure primarily based on the MIS structure.

[0364] Note that hydrogen contained in the oxide 230b, the oxide 230c, and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b, the oxide 230c, and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b, the oxide 230c, and the like may be absorbed by the conductor 242a or the conductor 242b.

[0365] Insulator 254 is provided to cover the side surfaces of oxide 230a, oxide 230b, oxide 243a, oxide 243b, conductor 242a, the top surface of conductor 242a, the side surfaces of conductor 242b, and the top surface of conductor 242b.

[0366] The insulator 254 preferably has a function of suppressing oxygen diffusion. For example, the insulator 254 preferably has a function of suppressing oxygen diffusion more than the insulator 280. As the insulator 254, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed.

[0367] Furthermore, the insulator 254 is preferably formed by depositing aluminum oxide or hafnium oxide in an oxygen-containing atmosphere using a bias sputtering method. Bias sputtering is a method of sputtering while applying RF power to a substrate. By applying RF power to the substrate, the potential of the substrate becomes negative relative to the plasma potential (called the bias potential), and positive ions in the plasma are accelerated by this bias potential and implanted into the substrate. The bias potential can be controlled by the magnitude of the RF power applied to the substrate. Therefore, oxygen can be implanted into the insulator 224 by depositing aluminum oxide or hafnium oxide in an oxygen-containing atmosphere using the bias sputtering method.

[0368] In the bias sputtering method, the amount of oxygen implanted into the insulator 224 that serves as the base of the insulator 254 can be controlled by adjusting the magnitude of the RF power applied to the substrate. For example, the RF power is set to 0.31 W / cm 2 or more, preferably 0.62 W / cm 2 More preferably, 1.86 W / cm 2 The above bias can be applied to the substrate. In other words, the amount of oxygen injected can be changed to suit the characteristics of the transistor by adjusting the RF power used when forming the insulator 254. Also, an amount of oxygen suitable for improving the reliability of the transistor can be injected. Furthermore, the RF frequency is preferably 10 MHz or higher. A typical frequency is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate. Therefore, by adjusting the RF power applied to the substrate, the amount of oxygen injected into the insulator 224 can be controlled, and therefore the amount of oxygen injected into the insulator 224 can be optimized.

[0369] As described above, the insulator 254 has the function of injecting oxygen into the underlying film, but also has the function of suppressing oxygen permeation. Therefore, when the insulator 280 is formed on the insulator 254 in a later step and oxygen is diffused from the insulator 280, the insulator 254 can prevent oxygen from diffusing directly from the insulator 280 into the oxide layers that become the oxides 230a, 230b, 243a, and 243b, and the conductive layers that become the conductors 242a and 242b.

[0370] By providing the insulator 254 as described above, the oxide 230a, the oxide 230b, the oxide 243a, the oxide 243b, the conductor 242a, and the conductor 242b can be separated from the insulator 280. This makes it possible to suppress direct diffusion of oxygen from the insulator 280 to the oxide 230a, the oxide 230b, the oxide 243a, the oxide 243b, the conductor 242a, and the conductor 242b. This prevents excessive oxygen from being supplied to the source and drain regions of the oxide 230, which would reduce the carrier concentration in the source and drain regions. It also prevents excessive oxidation of the conductors 242a and 242b, which would increase their resistivity and reduce their on-current.

[0371] The insulator 250 is preferably disposed in contact with at least a portion of the oxide 230d. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0372] The insulator 250 is preferably formed using an insulator that releases oxygen upon heating, similar to the insulator 224. By providing the insulator that releases oxygen upon heating as the insulator 250 in contact with at least a portion of the oxide 230d, oxygen can be effectively supplied to the channel formation region of the oxide 230, thereby reducing oxygen vacancies in the channel formation region of the oxide 230. Therefore, fluctuations in the electrical characteristics can be suppressed, stable electrical characteristics can be achieved, and a transistor with improved reliability can be provided. Furthermore, similar to the insulator 224, the concentrations of impurities such as water and hydrogen in the insulator 250 are preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0373] Although the insulator 250 is illustrated as a single layer in FIGS. 21B and 21C , it may have a laminated structure of two or more layers. When the insulator 250 has a laminated structure of two layers, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen when heated, and the upper layer of the insulator 250 is formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the lower layer of the insulator 250 into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 can be formed using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be formed using a material similar to that of the insulator 222.

[0374] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material, which is a high-k material with a high dielectric constant. By forming the gate insulator into a laminated structure consisting of the lower layer of the insulator 250 and the upper layer of the insulator 250, a laminated structure that is stable against heat and has a high dielectric constant can be achieved. This makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0375] Specifically, the upper layer of the insulator 250 can be made of a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0376] By forming the insulator 250 into a two-layer laminated structure, the physical thickness of the insulator 250 maintains the distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. Furthermore, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily adjusted as needed.

[0377] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0378] It is preferable that the metal oxide functions as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 can be used as the metal oxide. In this case, by forming the conductor 260a by a sputtering method, the electrical resistance value of the metal oxide can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0379] The presence of the metal oxide can improve the on-state current of the transistor 200 without weakening the influence of the electric field from the conductor 260.

[0380] Conductor 260 preferably includes conductor 260a and conductor 260b disposed on conductor 260a. For example, conductor 260a is preferably disposed so as to surround the bottom and side surfaces of conductor 260b. As shown in FIGS. 21B and 21C, the top surface of conductor 260 is disposed so as to substantially coincide with the top surfaces of insulator 250, oxide 230d, and oxide 230c. While conductor 260 is shown in FIGS. 21B and 21C as having a two-layer structure of conductor 260a and conductor 260b, it may have a single-layer structure or a stacked structure of three or more layers.

[0381] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0382] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0383] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0384] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductor 242a and the conductor 242b without alignment.

[0385] 21C, in the channel width direction of the transistor 200, the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the bottom surface of the oxide 230b. The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, making it easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0386] The insulator 280 is provided on the insulator 254. The upper surface of the insulator 280 may be flattened.

[0387] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. The insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be formed using, for example, the same material as the insulator 216. The insulator 280 may also have a stacked structure of the above materials, such as a stacked structure of silicon oxide formed by sputtering and silicon oxynitride formed by CVD thereon. Silicon nitride may also be stacked on top of this.

[0388] The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 and the insulator 283 may be made of, for example, aluminum oxide, silicon nitride, or silicon nitride oxide. For example, the insulator 282 may be made of aluminum oxide, which has a high blocking property against oxygen, and the insulator 283 may be made of silicon nitride, which has a high blocking property against hydrogen.

[0389] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0390] Furthermore, the conductor 240a and the conductor 240b may each have a layered structure. When the conductor 240a and the conductor 240b each have a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the insulators 284, 283, 282, 280, and 254. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 284 from mixing into the oxide 230 through the conductors 240a and 240b.

[0391] The insulators 241a and 241b may be made of, for example, silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 241a and 241b are provided in contact with the insulator 254, and therefore can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0392] Furthermore, a conductor 246a that functions as wiring and is in contact with the upper surface of the conductor 240a, and a conductor 246b that functions as wiring and is in contact with the upper surface of the conductor 240b, may be disposed. The conductors 246a and 246b are preferably made of a conductive material primarily composed of tungsten, copper, or aluminum. The conductors 246a and 246b may each have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductors may be formed so as to be embedded in openings provided in an insulator.

[0393] Insulator 286 is provided on conductor 246a, conductor 246b, and insulator 284. As a result, the top surface of conductor 246a, the side surface of conductor 246a, the top surface of conductor 246b, and the side surface of conductor 246b are in contact with insulator 286, and the bottom surface of conductor 246a and the bottom surface of conductor 246b are in contact with insulator 284. In other words, conductor 246a and conductor 246b can be configured to be surrounded by insulator 284 and insulator 286, respectively. This configuration suppresses the permeation of oxygen from the outside and prevents oxidation of conductor 246a and conductor 246b. This is also preferable because it can prevent impurities such as water and hydrogen from conductor 246a and conductor 246b from diffusing to the outside.

[0394] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0395] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, or the like.

[0396] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0397] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0398] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0399] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0400] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0401] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0402] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0403] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0404] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0405] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0406] <Modification of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 29A to 29D.

[0407] Fig. 29A shows a top view of the semiconductor device. Fig. 29B is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in Fig. 29A. Fig. 29C is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in Fig. 29A. Fig. 29D is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A5-A6 in Fig. 29A. Some elements have been omitted from the top view of Fig. 29A for clarity.

[0408] 29A to 29D, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> can be used as the constituent materials of the semiconductor device.

[0409] <<Semiconductor Device Variation 1>> The semiconductor device shown in Figures 29A to 29D is a modified example of the semiconductor device shown in Figures 21A to 21D. The semiconductor device shown in Figures 29A to 29D differs from the semiconductor device shown in Figures 21A to 21D in the shape of the insulator 283. Also, it differs in that it has insulators 287 and 274. Also, it differs in that it does not have insulator 284.

[0410] 29A to 29D, insulators 214, 216, 222, 224, 254, 280, and 282 are patterned. In addition, insulators 287 and 283 are structured to cover insulators 214, 216, 222, 224, 254, 280, and 282. That is, insulator 287 contacts the top surface of insulator 282, the side surface of insulator 282, the side surface of insulator 280, the side surface of insulator 254, the side surface of insulator 224, the side surface of insulator 222, the side surface of insulator 216, the side surface of insulator 214, and the top surface of insulator 212, and insulator 283 contacts the top surface and side surface of insulator 287. As a result, oxide 230, insulator 214, insulator 216, insulator 222, insulator 224, insulator 254, insulator 280, and insulator 282 are isolated from the outside by insulator 287, insulator 283, and insulator 212. In other words, transistor 200 is disposed within an area sealed by insulator 287, insulator 283, and insulator 212.

[0411] For example, it is preferable to form the insulators 214, 282, and 287 using a material that can capture and fix hydrogen, and to form the insulators 212 and 283 using a material that can suppress the diffusion of hydrogen and oxygen. Typically, aluminum oxide can be used for the insulators 214, 282, and 287. Typically, silicon nitride can be used for the insulators 212 and 283.

[0412] With this structure, hydrogen contained outside the sealed region can be prevented from entering the sealed region, thereby maintaining a low hydrogen concentration in the transistor.

[0413] 29A to 29D show a structure in which the insulator 212, the insulator 287, and the insulator 283 are provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 212, the insulator 287, and the insulator 283 may have a stacked structure of two or more layers.

[0414] The insulator 287 does not necessarily have to be provided. With this structure, the transistor 200 is disposed in a region sealed by the insulator 212 and the insulator 283. With this structure, hydrogen contained outside the sealed region can be further prevented from entering the sealed region. Therefore, a low hydrogen concentration in the transistor can be further maintained.

[0415] The insulator 274 functions as an interlayer film. The insulator 274 preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator 274 can be formed using, for example, a material similar to that of the insulator 280.

[0416] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device shown in FIGS. 29A to 29D, which is one embodiment of the present invention, will be described with reference to FIGS. 30A to 42D.

[0417] Figures 30A, 31A, 32A, 33A, 34A, 35A, 36A, 37A, 38A, 39A, 40A, 41A, and 42A are top views, and Figures 30B, 31B, 32B, 33B, 34B, 35B, 36B, 37B, 38B, 39B, 40B, 41B, and 42B are cross-sectional views corresponding to the portions indicated by the dashed dotted line A1-A2 in Figures 30A, 31A, 32A, 33A, 34A, 35A, 36A, 37A, 38A, 39A, 40A, 41A, and 42A, respectively, and are cross-sectional views of the transistor 200 in the channel length direction. 30C, 31C, 32C, 33C, 34C, 35C, 36C, 37C, 38C, 39C, 40C, 41C, and 42C are cross-sectional views corresponding to the portions indicated by the dashed dotted lines A3-A4 in FIGS. 30A, 31A, 32A, 33A, 34A, 35A, 36A, 37A, 38A, 39A, 40A, 41A, and 42A, respectively, and are also cross-sectional views in the channel width direction of transistor 200. 30D, 31D, 32D, 33D, 34D, 35D, 36D, 37D, 38D, 39D, 40D, 41D, and 42D are cross-sectional views of the portion indicated by the dashed dotted line A5-A6 in 30A, 31A, 32A, 33A, 34A, 35A, 36A, 37A, 38A, 39A, 40A, 41A, and 42A, respectively. Note that some elements have been omitted from the top views of 30A, 31A, 32A, 33A, 34A, 35A, 36A, 37A, 38A, 39A, 40A, 41A, and 42A for clarity.

[0418] First, a substrate (not shown) is prepared, and then a film of the insulator 212 is formed on the substrate. The insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0419] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0420] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0421] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0422] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. The PEALD (Plasma Enhanced ALD) method utilizes plasma, which can be preferable because it allows film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using XPS.

[0423] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0424] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0425] In this embodiment, a silicon nitride film is formed by sputtering as the insulator 212. By using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212 in this manner, even if a metal that easily diffuses, such as copper, is used in a conductor below the insulator 212 (not shown), the metal can be prevented from diffusing upward through the insulator 212. Furthermore, by using an insulator that is impermeable to impurities, such as water and hydrogen, such as silicon nitride, the diffusion of impurities, such as water and hydrogen, contained in the layer below the insulator 212 can be prevented.

[0426] Next, the insulator 214 is deposited over the insulator 212. The insulator 214 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used as the insulator 214.

[0427] The hydrogen concentration of the insulator 214 is preferably lower than that of the insulator 212. By forming a silicon nitride film by a sputtering method as the insulator 212, a silicon nitride film with a low hydrogen concentration can be formed. Furthermore, by using aluminum oxide as the insulator 214, the hydrogen concentration can be lower than that of the insulator 212.

[0428] In a subsequent process, the transistor 200 is formed on the insulator 214, and it is preferable that the film close to the transistor 200 has a relatively low hydrogen concentration, and it is preferable that the film with a relatively high hydrogen concentration be placed farther from the transistor 200.

[0429] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 216. The insulator 216 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration in the insulator 216 to be reduced.

[0430] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region where the opening is formed may also be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, it is preferable to use silicon nitride, aluminum oxide, or hafnium oxide for the insulator 214.

[0431] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. The dry etching apparatus having a high-density plasma source may be, for example, an ICP etching apparatus.

[0432] After the opening is formed, a conductive film that will become the conductor 205a is formed. The conductive film preferably contains a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0433] In this embodiment, the conductive film that becomes the conductor 205a has a multilayer structure. First, a tantalum nitride film is formed by sputtering, and then a titanium nitride film is laminated on the tantalum nitride film. By using such a metal nitride film as the lower layer of the conductor 205b, even if a metal that easily diffuses, such as copper, is used in the conductive film that becomes the conductor 205b (described later), the metal can be prevented from diffusing out of the conductor 205a.

[0434] Next, a conductive film that will become the conductor 205b is formed. The conductive film can be formed by plating, sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a low-resistance conductive material such as copper is deposited as the conductive film.

[0435] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216. As a result, the conductors 205a and 205b remain only in the openings. This allows the formation of a conductor 205 with a flat upper surface (see Figures 30A to 30D). Note that the CMP process may remove a portion of the insulator 216.

[0436] Note that in the above description, the conductor 205 is formed to fill the opening of the insulator 216; however, one embodiment of the present invention is not limited to this. For example, the conductor 205 may be formed over the insulator 214, the insulator 216 may be formed over the conductor 205, and the insulator 216 may be subjected to CMP treatment to remove part of the insulator 216 and expose the surface of the conductor 205.

[0437] Next, the insulator 222 is formed over the insulator 216 and the conductor 205. The insulator 222 may be an insulator containing one or both of an oxide of aluminum and hafnium. The insulator containing one or both of an oxide of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water prevents hydrogen and water contained in structures provided around the transistor 200 from diffusing into the inside of the transistor 200 through the insulator 222, thereby preventing the generation of oxygen vacancies in the oxide 230.

[0438] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0439] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0440] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the insulator 222 as much as possible.

[0441] In this embodiment, after the insulator 222 is formed, heat treatment is performed at 400° C. for 1 hour with a nitrogen gas flow rate of 4 slm and an oxygen gas flow rate of 1 slm. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment can improve the crystallinity of the insulator 222. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0442] Next, the insulator 224 is deposited on the insulator 222. The insulator 224 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide or silicon oxynitride is deposited by CVD as the insulator 224. The insulator 224 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulator 224 to be reduced. Since the insulator 224 will be the insulator 224 that comes into contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0443] Here, to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using, for example, microwaves. Alternatively, a power source that applies RF (radio frequency) to the substrate side may be provided. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, a plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In this case, heat treatment is not required.

[0444] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, CMP processing may be performed until the aluminum oxide reaches the insulator 224. This CMP processing can planarize and smooth the surface of the insulator 224. By placing the aluminum oxide on the insulator 224 and performing the CMP processing, it becomes easier to detect the end point of the CMP processing. Furthermore, the CMP processing may polish a portion of the insulator 224, resulting in a thinner film of the insulator 224. However, the film thickness can be adjusted during the formation of the insulator 224. Planarizing and smoothing the surface of the insulator 224 may prevent a deterioration in the coverage of the oxide film to be formed later and may prevent a decrease in the yield of the semiconductor device. Furthermore, forming an aluminum oxide film on the insulator 224 by a sputtering method is preferable because it allows oxygen to be added to the insulator 224.

[0445] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (see FIGS. 30A to 30D). Preferably, oxide films 230A and 230B are successively formed without being exposed to the atmosphere. By forming the films without being exposed to the atmosphere, impurities or moisture from the atmosphere can be prevented from adhering to oxide films 230A and 230B, and the vicinity of the interface between oxide films 230A and 230B can be kept clean.

[0446] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0447] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0448] In particular, during the deposition of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0449] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0450] In this embodiment, the oxide film 230A and the oxide film 230B are formed by the ALD method described in the previous embodiment, using the metal oxide film described in the previous embodiment.

[0451] Next, an oxide film 243A is formed on the oxide film 230B (see FIGS. 30A to 30D). The oxide film 243A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 243A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0452] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A without exposing them to the atmosphere, for example, by using a multi-chamber film forming apparatus.

[0453] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A do not polycrystallize, i.e., 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to replenish the desorbed oxygen.

[0454] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the moisture content of the gas used in the heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into oxide film 230A, oxide film 230B, oxide film 243A, etc. as much as possible.

[0455] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 550°C for one hour, followed by another heat treatment in an oxygen atmosphere at 550°C for one hour. This heat treatment can remove impurities such as water and hydrogen from the oxide films 230A, 230B, and 243A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser, more compact structure. This can suppress the diffusion of oxygen or impurities in the oxide film 230B.

[0456] Next, a conductive film 242A is formed on the oxide film 243A (see FIGS. 30A to 30D). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 200° C.

[0457] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into island shapes using lithography to form the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B. This processing can be performed using dry etching or wet etching. Dry etching is suitable for fine processing. The oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A may be processed under different conditions. During this process, the thickness of the insulator 224 in the region not overlapping with the oxide 230a may be reduced (see FIGS. 31A to 31D).

[0458] Here, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are formed so that at least a portion thereof overlaps with the conductor 205. Furthermore, the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are preferably approximately perpendicular to the top surface of the insulator 222. Having the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B approximately perpendicular to the top surface of the insulator 222 enables a reduction in area and a high density when providing multiple transistors 200. Alternatively, the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B may be configured so that the angles formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B and the top surface of the insulator 222 are small. Such a shape improves coverage by the insulator 254 and the like in subsequent processes, thereby reducing defects such as voids.

[0459] Furthermore, a curved surface is present between the side surface of the conductive layer 242B and the top surface of the conductive layer 242B. In other words, it is preferable that the end of the side surface and the end of the top surface are curved. For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the conductive layer 242B. The lack of corners at the end improves film coverage in the subsequent film formation process.

[0460] Next, the insulator 254 is deposited over the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B (see FIGS. 32B to 32D). The insulator 254 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is deposited as the insulator 254 by a sputtering method.

[0461] Next, an insulating film to be the insulator 280 is formed on the insulator 254. The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed by a sputtering method, and a silicon oxide film can be formed thereon by a PEALD method or a thermal ALD method. The insulating film is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in the insulator 280. Heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 254 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be reduced. The heat treatment may be performed under the above-described heat treatment conditions.

[0462] Next, the insulating film is subjected to CMP processing to form an insulator 280 with a flat upper surface (see FIGS. 32B to 32D). Note that, similar to the insulator 224, an aluminum oxide film may be formed on the insulator 280 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 280.

[0463] Here, microwave treatment may be performed. The microwave treatment is preferably performed in an oxygen-containing atmosphere under reduced pressure. By performing microwave treatment, the hydrogen concentration in the oxide 230b and the oxide 230a can be reduced. In addition, some of the hydrogen may be gettered to the conductive layer 242B via the insulator 254. In addition, V in the oxide 230a and the oxide 230b may be reduced. O can be repaired or compensated for.

[0464] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen in the insulator 280, the oxide 230b, and the oxide 230a can be efficiently removed. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.

[0465] Furthermore, microwave treatment can modify the film quality of the insulator 280, thereby suppressing the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230 via the insulator 280 in post-processing steps after the formation of the insulator 280 or by heat treatment, etc.

[0466] Next, a portion of the insulator 280, a portion of the insulator 254, a portion of the conductive layer 242B, and a portion of the oxide layer 243B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed (see FIGS. 33A to 33D).

[0467] When forming the opening, the upper portion of the oxide 230b is removed. By removing a portion of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening.

[0468] Furthermore, a portion of the insulator 280, a portion of the insulator 254, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b can be processed by dry etching or wet etching. Dry etching is suitable for fine processing. The processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 254 may be processed by wet etching, and a portion of the oxide layer 243B, a portion of the conductive layer 242B, and a portion of the oxide 230b may be processed by dry etching. The processing of a portion of the oxide layer 243B and a portion of the conductive layer 242B may be performed under different conditions from the processing of a portion of the oxide 230b.

[0469] Here, when a part of the oxide 230b is removed by dry etching to form the groove, it is preferable to perform the process by increasing the bias power. For example, the power density of the bias power is set to 0.03 W / cm. 2 It is preferable to set it to 0.06W / cm or more. 2 The dry etching time may be appropriately set in accordance with the depth of the groove.

[0470] Here, it is preferable to remove impurities attached to the surface of or diffused into oxide 230a, oxide 230b, etc. Examples of such impurities include those originating from components contained in insulator 280, insulator 254, and conductive layer 242B, components contained in materials used in the device used to form the openings, and components contained in the gas or liquid used in etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0471] In order to remove the impurities, a cleaning process is performed. The cleaning method may be wet cleaning using a cleaning solution, plasma treatment using plasma, or cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0472] For wet cleaning, cleaning treatment may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be used in combination as appropriate.

[0473] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as "diluted hydrofluoric acid," and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be referred to as "diluted ammonia water." The concentration, temperature, and other parameters of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0474] It is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning, as this frequency can reduce damage to the oxide 230b and the like.

[0475] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0476] In this embodiment, the cleaning process involves wet cleaning using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. This cleaning process can remove impurities that have adhered to the surfaces of or diffused into the oxides 230a and 230b. Furthermore, it can improve the crystallinity of the oxide 230c formed on the oxide 230b.

[0477] Previous processes such as dry etching or the above-mentioned cleaning process may result in the thickness of the insulator 224 in the area that overlaps with the opening but does not overlap with the oxide 230b being thinner than the thickness of the insulator 224 in the area that overlaps with the oxide 230b.

[0478] A heat treatment may be performed after the etching or cleaning. The heat treatment may be performed at a temperature between 100°C and 450°C, preferably between 350°C and 400°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. Furthermore, such a heat treatment can improve the crystallinity of the oxide 230b and also improve the crystallinity of the oxide 230c formed in the grooves of the oxide 230b. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, a subsequent heat treatment in a nitrogen atmosphere may be performed without exposure to the atmosphere.

[0479] Next, the oxide film 230C is formed. Heat treatment may be performed before the formation of the oxide film 230C. The heat treatment is preferably performed under reduced pressure, and the oxide film 230C is formed immediately after the formation without exposure to the atmosphere. The heat treatment is also preferably performed in an oxygen-containing atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 200°C.

[0480] Here, the oxide film 230C is preferably provided so as to contact at least the inner wall of the groove formed in the oxide 230b, part of the side surface of the oxide 243a, part of the side surface of the oxide 243b, part of the side surface of the conductor 242a, part of the side surface of the conductor 242b, part of the side surface of the insulator 254, and part of the side surface of the insulator 280. By being surrounded by the oxide 243a (oxide 243b), the insulator 254, and the oxide film 230C, the conductor 242a (conductor 242b) can be prevented from decreasing in conductivity due to oxidation of the conductor 242a (conductor 242b) in subsequent steps.

[0481] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, etc. Depending on the desired characteristics of the oxide film 230C, the oxide film 230C may be formed by the same film formation method as that for the oxide film 230A or the oxide film 230B.

[0482] When the oxide film 230C is formed by sputtering, some of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Alternatively, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280 during the formation of the oxide film 230C. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C should be 70% or more, preferably 80% or more, and more preferably 100%. Furthermore, forming the oxide film 230C in such an oxygen-rich atmosphere makes it easier to convert the oxide film 230C into a CAAC-OS film.

[0483] The oxide film 230C is preferably formed while the substrate is heated. At this time, by setting the substrate temperature to 200°C or higher, oxygen vacancies in the oxide film 230C and the oxide 230b can be reduced. By forming the oxide film 230C while heating the substrate, the crystallinity of the oxide film 230C and the oxide 230b can be improved.

[0484] In this embodiment, the oxide film 230C is formed by the ALD method described in the previous embodiment using the metal oxide described in the previous embodiment.

[0485] Next, a portion of the oxide film 230C is selectively removed by lithography (see FIGS. 34A, 34C, and 34D). It is preferable to remove the portion of the oxide film 230C by wet etching or the like. This process can remove the portion of the oxide film 230C located between the transistors 200 adjacent to each other in the channel width direction.

[0486] In the above process, in the region where part of oxide film 230C has been removed, the surfaces of insulators 224 and 280 are exposed. At this time, the film thickness of insulators 224 and 280 in that region may become thinner. Also, insulator 224 may be removed in that region, exposing the surface of insulator 222.

[0487] Next, the oxide film 230D is formed (see FIGS. 35A to 35D). The oxide film 230D can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230D may be formed by the same film formation method as that for the oxide film 230A or 230B, depending on the desired characteristics of the oxide film 230D. In this embodiment, the oxide film 230D is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0488] When forming the oxide film 230D, some of the oxygen contained in the sputtering gas may be supplied to the oxide film 230C. Alternatively, when forming the oxide film 230D, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230D may be 70% or more, preferably 80% or more, and more preferably 100%.

[0489] Next, the insulating film 250A is formed (see FIGS. 35A to 35D). A heat treatment may be performed before the formation of the insulating film 250A. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed immediately after the formation of the insulating film 250A without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230D can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0490] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in the insulating film 250A. The insulating film 250A will become the insulator 250 that contacts the oxide 230d in a later process, so it is preferable that the hydrogen concentration be reduced in this way.

[0491] Here, after the insulating film 250A is formed, microwave treatment may be performed in an oxygen-containing atmosphere under reduced pressure. By performing microwave treatment, the hydrogen concentration in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be reduced. In addition, some of the hydrogen may be gettered by the conductor 242a and the conductor 242b. In addition, the V in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be reduced. O can be repaired or compensated for.

[0492] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a. Some of the hydrogen may be gettered to the conductor 242a and the conductor 242b. Alternatively, a heat treatment step may be performed multiple times while maintaining the reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0493] Furthermore, microwave treatment can modify the film quality of the insulating film 250A, thereby suppressing the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. via the insulator 250 in a post-process such as film formation of a conductive film that becomes the conductor 260, or in a post-treatment such as heat treatment.

[0494] Next, a conductive film 260A and a conductive film 260B are formed in this order (see FIGS. 36A to 36D). The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed by an ALD method, and the conductive film 260B is formed by a CVD method.

[0495] Next, the oxide film 230C, the oxide film 230D, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIGS. 37A to 37D). As a result, the oxide 230c is arranged to cover part of the inner walls (side walls and bottom surface) of the opening that reaches the oxide 230b and the groove of the oxide 230b. The oxide 230d is arranged to cover the inner walls of the opening and the groove via the oxide 230c. The insulator 250 is arranged to cover the inner walls of the opening and the groove via the oxide 230c and the oxide 230d. Furthermore, the conductor 260 is disposed so as to fill the opening and the groove via the oxide 230c, the oxide 230d, and the insulator 250.

[0496] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0497] Next, the insulator 282 is formed over the oxide 230c, the oxide 230d, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 38B to 38D). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to form an aluminum oxide film by a sputtering method as the insulator 282. By forming the insulator 282 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280 during film formation. At this time, it is preferable to form the insulator 282 while heating the substrate. Furthermore, it is preferable to form the insulator 282 in contact with the top surface of the conductor 260, because this can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 260 during subsequent heat treatment.

[0498] Next, a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 254, a portion of the insulator 224, a portion of the insulator 222, a portion of the insulator 216, and a portion of the insulator 214 are processed to form an opening that reaches the insulator 212 (see FIGS. 39A to 39D ). The opening may be formed to surround the transistor 200. Alternatively, the opening may be formed to surround a plurality of transistors 200. Thus, in the opening, the side surfaces of the insulator 282, the side surfaces of the insulator 280, the side surfaces of the insulator 254, the side surfaces of the insulator 224, the side surfaces of the insulator 222, the side surfaces of the insulator 216, and the side surfaces of the insulator 214 are exposed.

[0499] A dry etching method or a wet etching method can be used to process a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 254, a portion of the insulator 224, a portion of the insulator 222, a portion of the insulator 216, and a portion of the insulator 214. Processing by the dry etching method is suitable for fine processing. Furthermore, the processing may be performed under different conditions. Note that in this process, the film thickness of the insulator 212 in the region overlapping with the opening may become thin.

[0500] Next, the insulator 287 is formed to cover the insulators 282, 280, 254, 224, 222, 216, and 214 (see FIGS. 40B to 40D). The insulator 287 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 287 may also have a multilayer structure. For example, an aluminum oxide film may be formed by a sputtering method, and a silicon nitride film may be formed on the aluminum oxide by a sputtering method. As shown in FIGS. 40B to 40D, the insulator 287 contacts the insulator 212 at the bottom of the opening. That is, the upper and side surfaces of the transistor 200 are surrounded by the insulator 287, and the lower surface is surrounded by the insulator 212. In this manner, the transistor 200 is surrounded by the insulators 287 and 212, which have high barrier properties, and thus moisture and hydrogen can be prevented from entering from the outside.

[0501] Next, the insulator 283 may be formed on the insulator 287 (see FIGS. 40B to 40D). Note that the insulator 283 is preferably formed using a film formation method with high film-forming properties. For example, the insulator 283 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the insulator 283 is preferably formed using the same material as the insulator 212.

[0502] Specifically, silicon nitride may be deposited by a CVD method, particularly, the insulator 283 may be deposited by a CVD method using a compound gas that does not contain hydrogen atoms or that contains a small amount of hydrogen atoms.

[0503] Next, an insulating film to become the insulator 274 is formed on the insulator 283. The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed using a CVD method. It is also preferable to form the insulating film using a gas in which hydrogen atoms are reduced or removed as described above. This allows the hydrogen concentration of the insulating film to be reduced.

[0504] Next, the insulating film that will become the insulator 274 is subjected to CMP processing to form the insulator 274 with a flat upper surface (see FIGS. 40B to 40D).

[0505] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. This heat treatment allows oxygen added by the formation of the insulator 282 to diffuse into the insulator 280 and to be further supplied to the oxide 230a and the oxide 230b via the oxide 230c. Note that this heat treatment may be performed not only after the formation of the insulator 274 but also after the formation of the insulator 282 or the insulator 283.

[0506] Next, openings reaching conductor 242a and conductor 242b are formed in insulators 254, 280, 282, 287, and 283 (see FIGS. 41A and 41B). The openings may be formed using lithography. Note that while the shape of the openings is circular in top view in FIG. 41A, this is not limiting. For example, the openings may have a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in top view.

[0507] Next, an insulating film that will become insulators 241a and 241b is formed, and the insulating film is anisotropically etched to form insulators 241a and 241b (see Figures 41A and 41B). The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film. For example, it is preferable to form an aluminum oxide film using the ALD method. Alternatively, it is preferable to form a silicon nitride film using the PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0508] Furthermore, the anisotropic etching of the insulating film that will become the insulators 241a and 241b can be performed by, for example, dry etching. By providing the insulators 241a and 241b on the sidewalls of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b.

[0509] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film preferably has a layered structure including a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of a film of tantalum nitride, titanium nitride, or the like, and a film of tungsten, molybdenum, copper, or the like. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0510] Next, CMP processing is performed to remove portions of the conductive film that will become conductors 240a and 240b, exposing the upper surfaces of insulators 283 and 274. As a result, the conductive film remains only in the openings, allowing conductors 240a and 240b to be formed with flat upper surfaces (see FIGS. 41A and 41B). Note that the CMP processing may remove portions of the upper surfaces of insulators 283 and 274.

[0511] Next, a conductive film that will become the conductors 246a and 246b is formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0512] Next, the conductive film that will become the conductors 246a and 246b is processed by lithography to form the conductor 246a that contacts the upper surface of the conductor 240a and the conductor 246b that contacts the upper surface of the conductor 240b. At this time, a part of the insulator 283 may be removed in a region where the conductors 246a and 246b do not overlap with the insulator 283 (see FIGS. 42A and 42B).

[0513] Next, the insulator 286 is formed on the conductor 246a, the conductor 246b, and the insulator 283 (see FIGS. 29A to 29D). The insulator 286 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulator 286 may also be multi-layered. For example, a silicon nitride film may be formed by sputtering, and another silicon nitride film may be formed on the silicon nitride by CVD.

[0514] 29A to 29D can be manufactured. As shown in FIGS. 30A to 42D, the transistor 200 can be manufactured by the manufacturing method of a semiconductor device described in this embodiment.

[0515] <Modification 2 of Semiconductor Device> An example of a semiconductor device in this embodiment will be described below with reference to FIGS. 43A to 43D.

[0516] FIG. 43A shows a top view of a semiconductor device having a transistor 200A. FIG. 43B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in FIG. 43A. FIG. 43C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in FIG. 43A. FIG. 43D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in FIG. 43A. Some elements are omitted from the top view of FIG. 43A for clarity.

[0517] 43A to 43D, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor devices shown in <Configuration Example of Semiconductor Device> and <Variation Example 1 of Semiconductor Device>. Also in this section, the materials described in detail in <Configuration Example of Semiconductor Device> and <Variation Example 1 of Semiconductor Device> can be used as the materials constituting the semiconductor device.

[0518] The semiconductor device shown in Figures 43A to 43D is a modified example of the semiconductor device shown in Figures 29A to 29D. The semiconductor device shown in Figures 43A to 43D differs from the semiconductor device shown in Figures 29A to 29D in that it has insulators 271a and 271b and does not have oxides 230c and 230d.

[0519] In the semiconductor device shown in FIGS. 43A to 43D, an insulator 271a is provided between the conductor 242a and the insulator 254, and an insulator 271b is provided between the conductor 242b and the insulator 254. In the semiconductor device shown in FIGS.

[0520] Here, the insulators 271a and 271b preferably have a function of suppressing oxygen diffusion. This can suppress the absorption of excess oxygen from the insulator 280 by the conductors 242a and 242b, which function as source and drain electrodes. Furthermore, suppressing oxidation of the conductors 242a and 242b can suppress an increase in contact resistance between the transistor and wiring. Therefore, the transistor 200A can have good electrical characteristics and reliability. The insulators 271a and 271b can be formed using, for example, a material similar to that of the insulator 254.

[0521] 43A to 43D, insulating layers to be the insulators 271a and 271b and conductive layers provided on the insulating layers function as masks for the conductive film 242A, whereby the conductors 242a and 242b each have angular ends where their side surfaces intersect with their top surfaces. The angular ends where their side surfaces intersect with their top surfaces of the conductor 242a (conductor 242b) increase the cross-sectional area of ​​the conductor 242a (conductor 242b) compared to when the ends have curved surfaces. This reduces the resistance of the conductors 242a and 242b, thereby increasing the on-state current of the transistor 200A.

[0522] Furthermore, by adopting a structure in which the oxides 230c and 230d are not provided, it is possible to suppress the generation of a parasitic transistor between the transistor 200A and the transistor 200A adjacent to the transistor 200A, and to suppress the generation of a leakage path along the conductor 260. Therefore, it is possible to provide a semiconductor device that has favorable electrical characteristics and allows for miniaturization or high integration.

[0523] <Application examples of semiconductor devices> 44A and 44B will be used to describe an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those described in the above <Structural Example of Semiconductor Device> and the above <Modified Example of Semiconductor Device>. In the semiconductor device shown in FIG. 44A and FIG. 44B, structures having the same functions as those of the semiconductor device described in the <Modified Example of Semiconductor Device> (see FIGS. 29A to 29D) are denoted by the same reference numerals. In this section, the transistor 200 can be made of materials described in detail in the <Structural Example of Semiconductor Device> and the <Modified Example of Semiconductor Device>.

[0524] 44A and 44B show a configuration in which multiple transistors (transistors 200_1 to 200_n) are encapsulated by an insulator 287, an insulator 283, and an insulator 212. Note that although the multiple transistors appear to be aligned in the channel length direction in FIGS. 44A and 44B, this is not a limitation. The multiple transistors may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors may be arranged without any regularity depending on the design.

[0525] As shown in FIG. 44A, a portion where the insulator 287 and the insulator 283 contact with the insulator 212 (hereinafter, this portion may be referred to as a sealing portion 265) is formed outside the plurality of transistors (transistors 200_1 to 200_n). The sealing portion 265 is formed so as to surround the plurality of transistors (also referred to as a transistor group). With this structure, the plurality of transistors can be enclosed by the insulator 287, the insulator 283, and the insulator 212. Therefore, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.

[0526] Also, dicing lines (sometimes called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. The substrate is divided along the dicing lines, so that a group of transistors surrounded by the sealing portion 265 is extracted as one chip.

[0527] 44A shows an example in which multiple transistors (transistors 200_1 to 200_n) are surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in FIG. 44B, multiple transistors may be surrounded by multiple sealing portions. In FIG. 44B, multiple transistors are surrounded by sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0528] In this manner, by using a configuration in which multiple transistors (transistors 200_1 to 200_n) are surrounded by multiple sealing portions, the area in which the insulator 287 and the insulator 212 are in contact with each other increases, which can further improve the adhesion between the insulator 287 and the insulator 212. This makes it possible to more reliably seal the multiple transistors.

[0529] In this case, a dicing line may be provided overlapping the sealing portion 265a or the sealing portion 265b, or may be provided between the sealing portion 265a and the sealing portion 265b.

[0530] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0531] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiments.

[0532] (Embodiment 3) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0533] [Storage device 1] 45 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0534] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced.

[0535] 45, a wiring 1001 is electrically connected to the source of a transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0536] Moreover, the memory device shown in FIG. 45 can be arranged in a matrix to form a memory cell array.

[0537] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0538] Here, in the transistor 300 shown in FIG. 45, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0539] Note that the transistor 300 shown in FIG. 45 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0540] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, the insulator 130 is preferably the insulator that can be used as the insulator 286 described in the above embodiment.

[0541] For example, the conductor 112 over the conductor 240 and the conductor 110 can be formed simultaneously. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0542] 45, the conductor 112 and the conductor 110 are shown as having a single layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0543] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be formed as a stacked layer or a single layer.

[0544] For example, it is preferable to use a layered structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitor 100 can improve its dielectric strength by having an insulator with high dielectric strength, thereby preventing electrostatic breakdown of the capacitor 100.

[0545] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0546] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide or resin with pores, etc.

[0547] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0548] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0549] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0550] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 45, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0551] Similarly, a conductor 218 and a conductor (conductor 205) constituting the transistor 200 are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0552] Here, similar to the insulator 241a and the insulator 241b described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. That is, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0553] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 212, 214, and 222, and therefore can prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0554] The insulator 217 can be formed by a method similar to that for the insulators 241a and 241b. For example, a silicon nitride film may be formed by a PEALD method, and an opening reaching the conductor 356 may be formed by anisotropic etching.

[0555] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0556] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0557] For example, insulators 150, 210, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0558] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen. Therefore, the insulators 214, 212, and 350 can be formed using insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0559] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0560] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0561] For example, the conductors 328, 330, 356, conductor 218, and conductor 112 can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, with tungsten being particularly preferred. Alternatively, they are preferably formed using low-resistance conductive materials such as aluminum and copper. Using a low-resistance conductive material can reduce wiring resistance.

[0562] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0563] 45, for example, an insulator 241 may be provided between the insulator 224 and the insulator 280 containing excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulators 222, 282, 287, and 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0564] That is, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0565] The insulator 241 may be an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. Silicon nitride is particularly preferable because it has a high blocking property against hydrogen. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide.

[0566] As in the above embodiment, the transistor 200 is preferably sealed with the insulators 212, 214, 282, 287, and 283. This structure can reduce the intrusion of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like.

[0567] Here, the conductor 240 penetrates the insulators 283, 287, and 282, and the conductor 218 penetrates the insulators 214 and 212. However, as described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that gets mixed into the inside of the insulators 212, 214, 282, 287, and 283 via the conductors 240 and 218. In this way, the transistor 200 can be more reliably sealed with the insulators 212, 214, 282, 287, 283, 241, and 217, and it is possible to reduce the intrusion of impurities such as hydrogen contained in the insulator 274 from the outside.

[0568] Furthermore, as described in the previous embodiment, the insulators 216, 224, 280, 250, and 274 are preferably formed by a deposition method using a gas in which hydrogen atoms are reduced or removed, thereby reducing the hydrogen concentrations in the insulators 216, 224, 280, 250, and 274.

[0569] In this way, the hydrogen concentration in the silicon-based insulating film near the transistor 200 can be reduced, and the hydrogen concentration in the oxide 230 can be reduced.

[0570] <Dicing line> The following describes dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the multiple semiconductor devices.

[0571] 45, for example, it is preferable to design the insulator 287 so that the area where the insulator 212 contacts overlaps with the dicing line. That is, openings are provided in the insulators 282, 280, 254, 224, 222, 216, and 214 near the area that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0572] That is, the insulator 212 and the insulator 287 are in contact with each other through the openings formed in the insulators 282, 280, 254, 224, 222, 216, and 214. Alternatively, openings may be formed in the insulators 282, 280, 254, 224, 222, 216, and 214, so that the insulators 212 and 287 are in contact with each other. For example, the insulators 212 and 287 may be formed using the same material and the same method. Providing the insulators 212 and 287 with the same material and the same method can improve adhesion. For example, silicon nitride is preferably used.

[0573] With this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, the insulator 287, and the insulator 283. At least one of the insulators 212, the insulator 214, the insulator 282, the insulator 287, and the insulator 283 has a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even when the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side direction of the divided substrate and diffusing into the transistor 200.

[0574] Furthermore, this structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. This allows the oxide in which a channel is formed in the transistor 200 to be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0575] 45, the shape of the capacitor 100 is a planar type, but the memory device described in this embodiment is not limited to this. For example, as shown in FIG. 46, the shape of the capacitor 100 may be a cylindrical type. Note that the configuration below the insulator 150 of the memory device shown in FIG. 46 is the same as that of the semiconductor device shown in FIG.

[0576] An insulator 150 is provided on the insulator 130, and an insulator 142 is provided on the insulator 150. Openings are formed in the insulators 150 and 142.

[0577] 46 includes a conductor 115, an insulator 145 on the conductor 115 and the insulator 142, and a conductor 125 on the insulator 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the opening.

[0578] The conductor 115 functions as the lower electrode of the capacitor 100, the conductor 125 functions as the upper electrode of the capacitor 100, and the insulator 145 functions as the dielectric of the capacitor 100. The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surfaces of the openings in the insulators 150 and 142, allowing for a larger capacitance per unit area. Therefore, the deeper the openings, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0579] An insulator 152 is provided on the conductor 125 and the insulator 145 .

[0580] The insulator 152 may be an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be an insulator that can be used for the insulator 214.

[0581] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area where the openings overlap the transistor 200 in the top view is large. With this configuration, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0582] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The upper surface of the conductor 115 preferably substantially coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening in the insulator 130. The conductor 115 is preferably formed by an ALD method, a ...

Claims

[Claim 1] A crystalline metal oxide, the crystal has a structure in which a first layer, a second layer, and a third layer are stacked; the first layer, the second layer, and the third layer are each substantially parallel to a surface on which the metal oxide is to be formed; the first layer comprises a first metal and oxygen; the second layer comprises a second metal and oxygen; the third layer comprises a third metal and oxygen; the first layer has an octahedral structure; the second layer has a trigonal bipyramidal structure or a tetrahedral structure; the third layer has a trigonal bipyramidal structure or a tetrahedral structure; the octahedral structure of the first layer has an atom of the first metal at the center and oxygen atoms at the vertices; the trigonal bipyramidal structure or the tetrahedral structure of the second layer has an atom of the second metal at its center and oxygen atoms at its vertices; the trigonal bipyramidal structure or the tetrahedral structure of the third layer has an atom of the third metal at its center and oxygen atoms at its vertices; the valence of the first metal is the same as the valence of the second metal; the valence of the first metal is different from the valence of the third metal; Metal oxides.

Images