Error-tolerant quantum computer utilization system and error-tolerant quantum computer utilization method

Abstract

To provide an error-tolerant quantum computer utilization system capable of quickly selecting an appropriate error-tolerant quantum computer that meets a user requirement.SOLUTION: An error-tolerant quantum computer utilization system is configured to: use characteristic information of a quantum computer to estimate code basic gate computation time required for executing a correction code basic gate of a quantum error correction code to be used in a quantum computer; and refer to the code basic gate computation time to select a quantum computer having a quantum error correction code capable of executing a desired-to-be-executed quantum circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a system and a method for utilizing an error-tolerant quantum computer. [Background technology]

[0002] In recent years, the development of quantum computers has accelerated. One of the characteristics of quantum computers is that one quantum bit can assume a superposition state of 0 and 1. Another characteristic of quantum computers is entanglement, where multiple quantum bits are quantum-mechanically correlated. By making good use of the properties of quantum bits, such as superposition states and entanglement, quantum computers are expected to be able to perform calculations faster than conventional computers.

[0003] However, the state of a quantum bit can change unintentionally due to the influence of physical noise. Sources of noise include failure to implement quantum gates or failure to prepare the quantum state. Unless noise countermeasures are implemented, the quantum computer will not be able to output the correct answer.

[0004] One possible countermeasure against noise is to implement quantum error correcting codes in quantum computers, which configure one logical quantum bit with multiple physical quantum bits to provide redundancy and thereby make the computer noise tolerant. A quantum computer equipped with quantum error correcting codes is called an error-tolerant quantum computer.

[0005] In addition, various companies are developing quantum computers, and these companies are expected to provide quantum computing functions using quantum computers as cloud services. It is expected that the characteristics of each quantum computer will differ, and as a result, the noise characteristics of each quantum computer will also differ. Therefore, users who want to run quantum programs need to select a cloud service with quantum computing functions that will enable them to execute their quantum programs with the highest accuracy without being affected by noise.

[0006] In the method disclosed in Patent Document 1, a history of errors that occurred during past execution of a quantum program and quantum program parameters such as the number of qubits required to execute that quantum program are stored in a database. Then, when a new quantum program is executed, a quantum computer that is expected to generate the fewest errors based on the history is selected, and that quantum program is executed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] US2023 / 0229491 Summary of the Invention [Problem to be solved by the invention]

[0008] While bit errors in conventional computers are simply bit inversions, quantum computers can produce more complex errors due to the fact that quantum bits can be in superposition states and entanglement.

[0009] It is possible that an error generated by the execution of a quantum gate in a certain clock depends on the type of quantum gate executed in the previous clock. In other words, the characteristics of the error generated may change depending on the structure of the quantum program.

[0010] The method disclosed in Patent Document 1 does not take into consideration whether the structure of the quantum program executed when collecting error information in the database is similar to the structure of the quantum program that the user subsequently wants to execute. Therefore, when the structure of the quantum program used when collecting error information differs from the structure of the quantum program that the user wants to execute, there is a problem in that the accuracy of estimating the errors that will occur is low.

[0011] Furthermore, when a user who wants to execute a quantum program decides which quantum computer to select, high accuracy of quantum program execution is not necessarily the only factor to be considered.

[0012] Other factors that users consider include the cost of using the quantum computer required to run a quantum program and the time it takes to run the quantum program. It is necessary to select the optimal quantum computer by taking into account all of these multiple user requirements.

[0013] The following method can be considered as a way to select the optimal quantum computer while taking into consideration all of the user's multiple requirements. First, a simulator of each fault-tolerant quantum computer that reflects actual noise trends is used to simulate the quantum program the user wants to run. Next, based on the results, the accuracy, time cost, and monetary cost of the quantum program execution results are evaluated. Finally, the evaluation results are compared with the user's requirements to select an appropriate fault-tolerant quantum computer.

[0014] However, the above quantum computer simulations are time-consuming and require a high load, which means that it takes time to select an appropriate fault-tolerant quantum computer, which results in an increase in the latency required to execute the target quantum program.

[0015] An object of the present invention is to select an appropriate fault-tolerant quantum computer that meets the user's requirements in a short period of time in a system utilizing fault-tolerant quantum computers. [Means for solving the problem]

[0016] An error-tolerant quantum computer utilization system according to one embodiment of the present invention comprises a computation time estimation unit and a quantum computer selection unit executed by a CPU, and selects a quantum computer capable of executing a desired quantum circuit encoded with a quantum error correcting code from among a plurality of quantum computers each having different characteristic information, wherein the computation time estimation unit uses the characteristic information of the quantum computer to estimate the code basic gate computation time required to execute a correction code basic gate of the quantum error correcting code used on the quantum computer, and the quantum computer selection unit refers to the code basic gate computation time to select a quantum computer having a quantum error correcting code capable of executing the desired quantum circuit. [Effects of the Invention]

[0017] According to one aspect of the present invention, in a system utilizing an error-tolerant quantum computer, it is possible to select an appropriate error-tolerant quantum computer that meets the user's requirements in a short period of time. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a block diagram illustrating an example of the configuration of a system utilizing an error-tolerant quantum computer. [Figure 2] FIG. 1 is a block diagram illustrating an example of the hardware configuration of a system utilizing an error-tolerant quantum computer. [Figure 3] FIG. 10 is a diagram showing an example of a program describing a quantum circuit that a user wishes to execute. [Figure 4] 10 is a diagram illustrating an example of quantum computing function characteristic information input to a test circuit generation unit. FIG. [Figure 5] FIG. 10 is a diagram illustrating an example of test circuit conditions. [Figure 6] 10 is a flowchart illustrating an example of a procedure performed by a test circuit generation unit. [Figure 7] FIG. 10 is a diagram showing an example of conversion from a quantum program to be executed to a quantum program using elementary gates of a quantum correcting code. [Figure 8] 1A and 1B are diagrams showing a graph example A illustrating the circuit structure of a quantum circuit to be executed, and test circuit examples A and B. [Figure 9] 10A and 10B are diagrams showing a graph example B illustrating the circuit structure of a quantum circuit desired to be executed and a test circuit example C. [Figure 10] FIG. 2 is a block diagram illustrating an example of the configuration of a calculation accuracy estimation unit. [Figure 11] 10 is a flowchart illustrating an example of a procedure of a calculation accuracy estimation unit. [Figure 12] FIG. 10 is a diagram illustrating an example of an ideal execution result of a test circuit. [Figure 13] FIG. 10 is a diagram illustrating an example of an execution result of a test circuit on an actual device. [Figure 14] FIG. 10 is a diagram illustrating an example of an estimation of calculation accuracy. [Figure 15] FIG. 2 is a block diagram illustrating an example of the configuration of a calculation time estimation unit. [Figure 16] 10 is a diagram showing an example of quantum computing function characteristic information input to a code basic gate computation time estimation unit. FIG. [Figure 17] FIG. 10 is a diagram illustrating an example of an estimate of the calculation time of a code basic gate. [Figure 18] 10 is a flowchart illustrating an example of a procedure of a code basic gate calculation time estimation unit. [Figure 19] FIG. 10 is a diagram illustrating an example of a calculation time estimate. [Figure 20] 10 is a flowchart illustrating an example of a procedure of a calculation time estimation unit. [Figure 21] FIG. 10 is a diagram showing an example of quantum computing function characteristic information input to a monetary cost estimator. [Figure 22] FIG. 10 is a diagram illustrating an example of a monetary cost estimate. [Figure 23] 10 is a flowchart illustrating an example of a procedure of a monetary cost estimating unit. [Figure 24] 10A and 10B are diagrams illustrating examples of user request information and desired execution quantum circuit characteristic information. [Figure 25] FIG. 10 is a diagram illustrating an example of weight information of an evaluation function. [Figure 26] FIG. 10 is a diagram showing an example of evaluation and selection data for a quantum computer. [Figure 27] 10 is a flowchart illustrating an example of a procedure of a quantum computer selection unit. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0019] This example is applied to a system utilizing an error-tolerant quantum computer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0020] FIG. 1 is a block diagram showing an example of the configuration of a system utilizing an error-tolerant quantum computer according to this embodiment.

[0021] The fault-tolerant quantum computer utilization system includes a desired quantum circuit information holding unit 101, a test circuit condition holding unit 102, a test circuit generation unit 103, a test physical quantum circuit information holding unit 104, a calculation accuracy estimation unit 105, a calculation accuracy estimate holding unit 106, a quantum computing function characteristic information holding unit 107, a calculation time estimation unit 108, a calculation time estimate holding unit 109, a monetary cost estimation unit 110, a monetary cost estimate holding unit 111, a user request information / desired quantum circuit characteristic information holding unit 112, an evaluation function weight information holding unit 113, a quantum computer selection unit 114, and a quantum computer evaluation / selection data holding unit 115. The fault-tolerant quantum computer utilization system also includes an input device 206 and a display device 205 shown in FIG.

[0022] The fault-tolerant quantum computer utilization system is realized on a computer having a CPU, memory, a communication device, and an input / output device. The processing unit is executed by the CPU, and each storage unit is provided in the memory. The communication device is used in some of the processing of the processing unit, which requires sending and receiving data between the CPU and the quantum computer.

[0023] The test circuit generation unit 103 acquires the desired quantum circuit from the desired quantum circuit information storage unit 101, acquires test circuit conditions from the test circuit condition storage unit 102, and acquires characteristic information on the candidate quantum computer to be used from the quantum computing function characteristic information storage unit 107, and generates a test physical quantum circuit that includes the characteristic circuit structure of the desired quantum circuit and satisfies the test circuit conditions. Information on the test physical quantum circuit is stored in the test physical quantum circuit information storage unit 104.

[0024] The computational accuracy estimation unit 105 acquires the test physical quantum circuit from the test physical quantum circuit information storage unit 104, and generates an estimate of computational accuracy by comparing the results of executing the test physical quantum circuit using a simulator that simulates an ideal quantum computer that does not generate noise with the results of executing the test physical quantum circuit using a candidate quantum computer.

[0025] Instead of the results of running a test physical quantum circuit using a candidate quantum computer, the results of running a test physical quantum circuit using a simulator that simulates a quantum computer that generates noise may be used. Information regarding the estimate of computational accuracy is stored in the computational accuracy estimate storage unit 106.

[0026] The computation time estimation unit 108 acquires the desired quantum circuit from the desired quantum circuit information storage unit 101 and acquires characteristic information on the candidate quantum computer from the quantum computing function characteristic information storage unit 107, and generates an estimate of the time required for the candidate quantum computer to perform computation on the desired quantum circuit. The generated computation time estimate is then stored in the computation time estimate storage unit 109.

[0027] The monetary cost estimator 110 acquires characteristic information about the candidate quantum computer from the quantum computing function characteristic information storage unit 107 and an estimate of the computation time from the computation time estimate storage unit 109, and generates an estimate of the quantum computer usage fee required to execute the desired quantum circuit on the candidate quantum computer. The generated usage fee estimate is then stored in the monetary cost estimate storage unit 111.

[0028] The quantum computer selection unit 114 obtains an estimate of calculation accuracy from the calculation accuracy estimate storage unit 106, an estimate of calculation time from the calculation time estimate storage unit 109, an estimate of monetary cost from the monetary cost estimate storage unit 111, user request information and characteristic information of the quantum circuit desired to be executed from the user request information / quantum circuit characteristic information storage unit 112, and evaluation function weight information from the evaluation function weight information storage unit 113.

[0029] The quantum computer candidate for use is then evaluated to what extent it meets the user requirements, and the quantum computer that best meets the user requirements is selected based on the evaluation results. The quantum computer evaluation results and selection results are stored in the quantum computer evaluation and selection data storage unit 115.

[0030] FIG. 2 is a diagram showing an example of the hardware configuration of an error-resilient quantum computer utilization system 201 according to this embodiment.

[0031] The fault-tolerant quantum computer utilization system 201 includes a CPU 202 , a memory 203 , an external storage device 204 , a display device 205 , an input device 206 , an external media input / output device 207 , and a communication device 208 .

[0032] The CPU 202 executes various processes by executing programs stored in the memory 203. The memory 203 functions as a work area for the CPU 202, and stores the programs and data necessary for executing the programs.

[0033] Specifically, it stores programs constituting a test circuit generation unit 103, a calculation accuracy estimation unit 105, a calculation time estimation unit 108, a monetary cost estimation unit 110, and a quantum computer selection unit 114, and at the same time stores data stored in a desired execution quantum circuit information storage unit 101, a test circuit condition storage unit 102, a test physical quantum circuit information storage unit 104, a calculation accuracy estimation storage unit 106, a quantum computing function characteristic information storage unit 107, a calculation time estimation storage unit 109, a monetary cost estimation storage unit 111, a desired execution quantum circuit characteristic information storage unit 112, an evaluation function weight information storage unit 113, and a quantum computer evaluation and selection data storage unit 115.

[0034] The external storage device 204 stores various data. The external storage device may be, for example, a hard disk drive or a solid state drive. Specifically, data stored in the execution request quantum circuit information storage unit 101, the test circuit condition storage unit 102, the test physical quantum circuit information storage unit 104, the calculation accuracy estimate storage unit 106, the quantum computing function characteristic information storage unit 107, the calculation time estimate storage unit 109, the monetary cost estimate storage unit 111, the execution request quantum circuit characteristic information storage unit 112, the evaluation function weight information storage unit 113, and the quantum computer evaluation and selection data storage unit 115 are stored.

[0035] Alternatively, at least a portion of the programs constituting the test circuit generation unit 103, the calculation accuracy estimation unit 105, the calculation time estimation unit 108, the monetary cost estimation unit 110, and the quantum computer selection unit 114 may be stored in an external storage device, and when various processes are executed, the CPU 202 may read the programs into the memory 203 and execute them.

[0036] Furthermore, each program may be stored in advance in the memory 203 or the external storage device 204, or may be installed as needed from another device into the memory 203 or the external storage device 204 via an available medium. An available medium refers to, for example, a storage medium that is detachable from the external medium input / output device 207, or a network or a communication medium such as a carrier wave or digital signal that propagates through a network.

[0037] The display device 205 displays the processing results of the program, etc. The display device 205 is, for example, a display. The input device 206 accepts instructions to execute processing and input of information necessary for processing from the user. The input device 206 is, for example, a keyboard and a mouse.

[0038] The external medium input / output device 207 inputs and outputs data stored in an external medium and the external storage device 204. The external medium is a portable storage medium that can be attached to and detached from the external medium input / output device 207, and the external medium output device 207 is a drive device or the like that can read and write data from and to the external medium.

[0039] The communication device 208 is used to transmit information about the test physical quantum circuit to the candidate quantum computer, which information is generated when the calculation accuracy estimation unit 105 obtains the results of execution of the test physical quantum circuit using the candidate quantum computer, and to receive the results of execution of the test physical quantum circuit by the candidate quantum computer. The communication device 208 is assumed to be a network interface card or the like.

[0040] A first embodiment of the error-tolerant quantum computer utilization system 201 will be described using the example program in FIG. 3 that describes the quantum circuit that the user wishes to execute.

[0041] 3 shows an example of source code of a quantum circuit that a user wishes to execute in the fault-tolerant quantum computer utilization system 201 of Example 1. It is assumed that the fault-tolerant quantum computer utilization system 201 receives, as input, a source code 301 that describes a quantum program that the user wishes to process using a quantum computer.

[0042] Source code 301 is stored in the execution target quantum circuit information storage unit 101. A quantum program is written in a programming language such as Python, as exemplified by source code 301, but a quantum program written in source code 301 can also be visually represented in circuit format, as exemplified by circuit representation 302. The circuit exemplified by circuit representation 302 is called a Toffoli gate. For ease of understanding, the following description of the embodiment will be given with the quantum program represented in circuit format.

[0043] FIG. 4 shows an example of quantum computing function characteristic information that is held by the quantum computing function characteristic information holding unit 107 and input to the test circuit generation unit 103.

[0044] The quantum computing function characteristic information 401 includes a quantum computer label 402, a quantum error correcting code 403 to be used, a basic gate 404 of the correcting code, and a physical basic gate 405 of the quantum computer. In the quantum error correcting code 403 to be used, the value d represents the minimum distance of the error correcting code. In the basic gate 404 of the correcting code and the physical basic gate 405 of the quantum computer, H represents a Hadamard gate, T represents a T gate, and CNOT represents a CNOT gate, respectively.

[0045] 4, the basic gates 404 of the correcting code and the physical basic gates 405 of the quantum computer are the same in all quantum computers, but the basic gates 404 of the correcting code and the physical basic gates 405 of the quantum computer do not necessarily have to be the same. Furthermore, when a single quantum computer can use multiple error correcting code methods, multiple lines of characteristic information may be input in the quantum computing function characteristic information 401, in which the quantum computer label 402 has the same value and the quantum error correcting code 403 used and the basic gates 404 of the correcting code are different.

[0046] FIG. 5 shows an example of test circuit conditions that are held by the test circuit condition holding unit 102 and input to the test circuit generation unit 103. In FIG.

[0047] Test circuit conditions 501 include a condition number 502, the number of gates constituting the sequence 503, the number of connections in the sequence 504, and the maximum number of Non-Clifford gates 505. In Fig. 5, three test circuit condition examples 506, 507, and 508 are shown.

[0048] FIG. 6 is a flowchart showing an example of a procedure performed by the test circuit generation unit 103.

[0049] The processing described below is realized by a program executed on memory 203 by CPU 202 of fault-tolerant quantum computer utilization system 201. This program is executed by CPU 202 running test circuit generation unit 103, thereby acquiring a desired quantum circuit to be executed from desired quantum circuit information holding unit 101, test circuit conditions from test circuit condition holding unit 102, and quantum computing function characteristic information from quantum computing function characteristic information holding unit 107 (step 601).

[0050] The test circuit generation unit 103 reads the basic gates of the quantum error correcting code used by the candidate quantum computer from the quantum computing function characteristic information, and then converts the desired quantum program (desired quantum circuit) into a quantum program (quantum circuit) using the basic gates of the quantum error correcting code (step 602).

[0051] Next, a test quantum program (test quantum circuit) is generated from the converted quantum program (quantum circuit) so as to satisfy the test circuit conditions (step 603).

[0052] Then, the physical elementary gates of the candidate quantum computer are read from the quantum computing function characteristic information, the generated test quantum program (test quantum circuit) is converted into a test physical quantum program (test physical quantum circuit) using the physical elementary gates of the quantum computer, and the generated test physical quantum program (test physical quantum circuit) is stored in the test physical quantum circuit information storage unit 104 (step 604).

[0053] The flow of an example of the procedure in FIG. 6 will be illustrated using an example 301 of source code of a quantum circuit that a user wishes to execute, an example 401 of quantum computing function characteristic information, and an example 501 of test circuit conditions.

[0054] Here, an example will be described in which a test quantum program is generated for a quantum computer with quantum computer label 402 A out of three quantum computers listed in quantum computing function characteristic information 401.

[0055] 7 shows an example of an embodiment of step 602. A circuit 701 before conversion is an example of the quantum circuit to be executed obtained in step 601.

[0056] The circuit 701 before conversion is composed of Toffoli gates. However, in the quantum computing function characteristic information 401, when the quantum computer label 402 refers to the basic gates 404 of the correcting code for the quantum computer A, the basic gates are H, T, and CNOT, and the Toffoli gate is not included in the basic gates of the code.

[0057] If the quantum circuit to be executed includes gates that are not basic gates of the correcting code, the gates that are not included in the basic gates of the correcting code are decomposed into basic gates of the correcting code. The converted circuit 702 is an example of a circuit obtained by decomposing the pre-conversion circuit 701, which is composed of Toffoli gates, into H, T, and CNOT.

[0058] 8 and 9 show an example of a graph representing the converted circuit structure, which is used in step 603 to extract a circuit structure characteristic of the converted circuit, and an example of a test circuit generated based on the graph.

[0059] Graph example A801 ​​showing the circuit structure of a quantum circuit desired to be executed is an example of a graph showing the circuit structure of a quantum circuit desired to be executed, which is used to generate a test circuit that matches the test circuit conditions, that is, the circuit condition example 506 or 507, among the test circuit condition examples described in test circuit conditions 501.

[0060] In example graph A801, the vertices represent gates included in circuit 702. For example, in circuit 702, Hadamard gate 703 acting on the third quantum bit corresponds to vertex H(3) 802 in example graph A801.

[0061] In circuit 702, CNOT gate 704, which uses the second quantum bit as a control bit and the third quantum bit as a target bit, corresponds to vertex CNOT(2,3) 803 in graph example A 801. Similarly, when all gates included in circuit 702 are associated with the vertices of the graph, the result is as shown in graph example A 801.

[0062] In graph example A801, arrows connecting vertices represent the order of gates. The arrow from vertex A to vertex B indicates that the quantum gate corresponding to vertex A acts after the quantum gate corresponding to vertex B acts. For example, in circuit 702, the order of Hadamard gate 703 followed by CNOT gate 704 is represented by arrow 804 in graph example A801. The order of other gates included in circuit 702 can also be represented in a similar manner as shown in graph example A801.

[0063] If the same order relationship occurs multiple times in a circuit, the number of occurrences is stored as the weight of the edge, as illustrated by arrow 805. Arrow 805 indicates that an order relationship in which a T-dagger gate acts on the third quantum bit after a CNOT gate with the second quantum bit as the control bit and the third quantum bit as the target bit occurs twice in circuit 702. Graph example A801 ​​is generated by CPU 202 and stored in memory 203.

[0064] Next, an example of generating a test circuit from graph example A801 ​​is shown. Test circuit example A806 is a test quantum program generated from circuit 702 that satisfies test circuit condition 506. Test circuit example B807 is a test quantum program generated from circuit 702 that satisfies test circuit condition 507.

[0065] Circuit condition 506 specifies that the number of gates 503 constituting a sequence is 2, and the number of combinations of the sequence 504 is 2. Here, a sequence is the smallest unit of parts constituting a test circuit. One sequence is composed of multiple gates, and the number of gates included in one sequence is given by the number of gates 503 constituting the sequence. The number of combinations of the sequence represents the number of sequences included in the test circuit.

[0066] In circuit condition 506, the number of gates constituting the sequence 503 is 2 and the number of connections in the sequence 504 is 2, so that among the subgraphs of graph example A801, a circuit corresponding to the graph with the maximum sum of edge weights among directed graphs with a linear topology that have (the number of gates constituting the sequence) × (the number of connections in the sequence) = 4 vertices can be considered as the test circuit.

[0067] In graph example A801, the four gates CNOT(2,3) → T_dag(3) → CNOT(1,3) → T(3) connected by long dashed lines are a circuit structure corresponding to a test circuit that satisfies the conditions of the number of gates constituting the sequence and the number of connections of the sequence, among test circuit conditions 506. Then, when the above circuit structure is converted into a quantum circuit diagram, the circuit shown in test circuit example A806 is obtained.

[0068] The number of Non-Clifford gates included in test circuit example A806 is two, and also satisfies the condition for the maximum number of Non-Clifford gates among test circuit conditions 506. Therefore, test circuit example A806 satisfies all three condition items 503, 504, and 505 exemplified in test circuit conditions 506, and therefore test circuit example A806 becomes a test quantum program for circuit 702 generated by test circuit conditions 506.

[0069] Here, the greater the number of Non-Clifford gates, the longer the time required for a simulator that simulates an ideal quantum computer that does not generate noise to execute a test physical quantum circuit in the calculation accuracy estimation unit 105. Therefore, as a way to quickly estimate calculation accuracy, it is conceivable to include a condition for the maximum number of Non-Clifford gates as an item of the test circuit conditions, as exemplified in FIG.

[0070] The number of Non-Clifford gates included in the test circuit example A806 is 2, and when the test circuit condition is the circuit condition 507, the condition for the maximum number of Non-Clifford gates is not met.

[0071] As in the above example, if the test circuit candidate created by extracting the circuit structure does not satisfy the condition for the maximum number of Non-Clifford gates, (the number of Non-Clifford gates included in the test circuit candidate) - (the maximum number of Non-Clifford gates) are randomly selected from the Non-Clifford gates included in the test circuit candidate, and the selected gates are replaced with gates that are basic gates of the code and are also Clifford gates, thereby generating a test circuit.

[0072] When the maximum number of Non-Clifford gates is 1, one of the two Non-Clifford gates, a T gate and a T dagger gate, is randomly selected in the test circuit example A806.

[0073] If the physical elementary gate 405 of the quantum computer is H, T, or CNOT, the selected gate is replaced with a Hadamard gate, which is a Clifford gate of a 1-bit gate. If a T gate is selected as the gate to be replaced in test circuit example A806, the T gate in test circuit example A806 is replaced with a Hadamard gate, as exemplified in test circuit example B807, to generate a test circuit.

[0074] Since the test circuit example B807 satisfies all three condition items 503, 504, and 505 illustrated in the test circuit condition 507, the test circuit example B807 becomes a test quantum program for the circuit 702 generated by the test circuit condition 507.

[0075] Graph example B901 showing the circuit structure of a quantum circuit desired to be executed is an example of a graph showing the circuit structure of a quantum circuit desired to be executed, which is used to generate a test circuit whose example circuit condition matches the test circuit condition 508 among the example test circuit conditions described in test circuit conditions 501.

[0076] In the circuit condition example 508, the number of gates 503 constituting the sequence is 3. Therefore, the structure of the circuit 702 is analyzed by treating the three gates as a group. Here, an example of generating a test quantum program corresponding to the circuit 702, which is composed of a sequence in which the second gate of the three gates constituting the sequence is a CNOT gate, will be described.

[0077] In graph example B901, the vertices represent gates included in circuit 702. For example, in circuit 702, Hadamard gate 703 corresponds to vertex H(t) 902 in graph example B901.

[0078] Here, in circuit 702, Hadamard gate 703 is followed by CNOT gate 704, and the bit acted upon by Hadamard gate 703 serves as the target bit in the subsequent CNOT gate 704. Therefore, Hadamard gate 703 corresponds to vertex 902 of H(t), which represents the actuation of the Hadamard gate on a bit that acts as a control bit in the subsequent CNOT gate. In circuit 702, CNOT gate 704 corresponds to vertex CNOT(c,t) 903 in graph example B 901.

[0079] In circuit 702, T Dagger gate 705 corresponds to vertex T_dag(t) 904 in graph example B 901. Here, in circuit 702, there is a CNOT gate 704 before T Dagger gate 705, and the bit acted upon by T Dagger gate 705 plays the role of the target bit in the preceding CNOT gate 704. Therefore, T Dagger gate 705 is made to correspond to vertex 904 of T_dag(t), which represents that the T Dagger gate acts on the bit that acts as the control bit in the preceding CNOT gate.

[0080] Similarly, when all gates included in circuit 702 are associated with the vertices of the graph, the result is as shown in graph example B901. In graph example B901, X(c) indicates that gate X acts on a bit that serves as a control bit in the reference CNOT gate. X(o) indicates that gate X acts on a bit that is neither a control bit nor a target bit in the reference CNOT gate.

[0081] In graph example B901, arrows connecting vertices represent the order of gates. An arrow from vertex A to vertex B indicates that the quantum gate corresponding to vertex A acts after the quantum gate corresponding to vertex B acts. When the same order relationship is included multiple times in a circuit, the number of occurrences is stored as the weight of the edge, as exemplified by arrow 905.

[0082] Arrow 905 indicates that a relationship in which a T-dagger gate acts on a bit that serves as a target bit in a CNOT gate occurs twice in circuit 702. Graph example B 901 is generated by CPU 202 and stored in memory 203.

[0083] Next, an example of generating a test circuit from graph example B 901 will be shown. Test circuit example C 906 is a test quantum program generated from circuit 702 that satisfies test circuit condition 508.

[0084] In circuit condition 508, the number of gates constituting the sequence 503 is 3 and the number of connections in the sequence 504 is 1, so that among the subgraphs of graph example B901, the circuit corresponding to the graph with the maximum sum of edge weights among the directed graphs with a linear topology that have (the number of gates constituting the sequence) × (the number of connections in the sequence) = 3 vertices can be considered to be the test circuit.

[0085] In graph example B901, a circuit consisting of three gates T_dag(t) → CNOT(c,t) → T_dag(t), in which the edge weight takes the maximum value of 5, is a circuit structure corresponding to a test circuit that satisfies the conditions of the number of gates constituting the sequence and the number of connections of the sequence, among test circuit conditions 508. Then, when the above circuit structure is converted into a quantum circuit diagram, the circuit shown in test circuit example C906 is obtained.

[0086] The number of Non-Clifford gates included in test circuit example C906 is two, and also satisfies the condition for the maximum number of Non-Clifford gates among test circuit conditions 508. Therefore, test circuit example C906 satisfies all three condition items 503, 504, and 505 exemplified in test circuit conditions 508, and therefore test circuit example C906 becomes a test quantum program for circuit 702 generated by test circuit conditions 508.

[0087] In step 604, the test quantum program generated in step 603 is converted into a test physical quantum circuit that is expressed using physical elementary gates 405 and can be physically implemented by a quantum computer. The generated test physical quantum circuit is stored in the test physical quantum circuit information storage unit 104.

[0088] FIG. 10 is a detailed block diagram of the calculation accuracy estimation unit 105.

[0089] The computational accuracy estimation unit 105 includes a test physical quantum circuit information storage unit 1001, a classical simulator 1002, an available quantum computer 1003, an ideal execution result storage unit 1004 of the test physical quantum circuit, an execution result storage unit 1005 of the actual test physical quantum circuit, a computational accuracy estimation unit 1006, and a computational accuracy estimate storage unit 1007.

[0090] The calculation accuracy estimation unit 105 is realized on a computer having a CPU, memory, communication devices, and input / output devices. The above processing is executed by the CPU, and each storage unit is provided in memory. Among the above processing units, the process of acquiring the execution results of the actual test physical quantum circuit from the test physical quantum circuit involves transmitting information about the test physical quantum circuit from the fault-tolerant quantum computer utilization system to the quantum computer, and transmitting the execution results of the actual test physical quantum circuit from the quantum computer to the fault-tolerant quantum computer utilization system, and the communication device is used to send and receive the above data between the CPU and the quantum computer.

[0091] The classical simulator 1002 acquires the test physical quantum circuit from the test physical quantum circuit information storage unit 1001, and stores the ideal execution result of the test physical quantum circuit, which is the simulation result when the test physical quantum circuit is executed on an ideal quantum computer that does not generate noise, in the test physical quantum circuit ideal execution result storage unit 1004.

[0092] The available quantum computer 1003 acquires the test physical quantum circuit from the test physical quantum circuit information storage unit 1001, and stores the execution results of the actual test physical quantum circuit, which are the results when the test physical quantum circuit is executed on an actual quantum computer, in the execution result storage unit 1005 for the actual test physical quantum circuit.

[0093] The computational accuracy estimation unit 1006 reads the ideal execution result of the test physical quantum circuit from the test physical quantum circuit ideal execution result storage unit 1004 and the execution result of the actual test physical quantum circuit from the test physical quantum circuit actual execution result storage unit 1005, and generates an estimate of the computational accuracy by comparing the two results. Information regarding the estimate of the computational accuracy is stored in the computational accuracy estimate storage unit 1007.

[0094] FIG. 11 is a flowchart showing an example of the procedure of the calculation accuracy estimation unit 1006.

[0095] The processing described below is realized by a program executed on the memory 203 by the CPU 202 of the fault-tolerant quantum computer utilization system 201. The CPU 202 executes the calculation accuracy estimation unit 1006 to obtain the ideal execution result of the test physical quantum circuit from the ideal execution result storage unit for test physical quantum circuit 1004 and the execution result of the actual test physical quantum circuit from the execution result storage unit for test physical quantum circuit 1005 (step 1101).

[0096] The calculation accuracy estimation unit 1006 compares the ideal execution result with the execution result of the actual machine using a statistical testing method or an index of the closeness of the probability distribution (step 1102).

[0097] Next, the computational accuracy estimation unit 1006 estimates the accuracy of the test circuit from the comparison result (step 1103).The computational accuracy estimation unit 1006 then estimates the accuracy of the desired logical quantum circuit to be executed from the accuracy of the test circuit, and stores the accuracy estimate in the computational accuracy estimate holding unit 1007 (step 1104).

[0098] 12 shows an example of an ideal execution result of a test physical quantum circuit that is stored in the ideal execution result storage unit 1004 of the test physical quantum circuit and input to the calculation accuracy estimation unit 1006. The ideal execution result 1201 of the test physical quantum circuit includes a pair of a measurement bit string 1202 and a measurement count 1203.

[0099] 13 shows an example of the execution results of the actual test physical quantum circuit that are stored in the execution result storage unit 1005 of the actual test physical quantum circuit and input to the calculation accuracy estimation unit 1006. The execution result 1301 of the actual test physical quantum circuit includes a pair of a measurement bit string 1302 and a measurement count 1303.

[0100] 14 shows an example of a calculation accuracy estimate generated by the calculation accuracy estimating unit 1006 and stored in the calculation accuracy estimate holding unit 1007. A calculation accuracy estimate 1401 includes a label 1402 of the quantum computer and an accuracy estimate 1403.

[0101] Assuming that the quantum circuit to be executed is circuit 702 and the test physical quantum circuit is test example C906, an example of an embodiment of the computational accuracy estimation unit 1006 will be shown. In this embodiment, the CPU 202 first executes the computational accuracy estimation unit 1006, and in step 1101 reads an ideal execution result 1201 of the test physical quantum circuit from the ideal execution result storage unit 1004 of the test physical quantum circuit, and an actual execution result 1301 of the test physical quantum circuit from the actual execution result storage unit 1005 of the test physical quantum circuit.

[0102] Next, in step 1102, the calculation accuracy estimation unit 1006 compares the ideal execution result 1201 of the test physical quantum circuit with the execution result 1301 of the actual test physical quantum circuit to determine how close the execution result of the actual test physical quantum circuit is to the ideal execution result. When the Bhattacharya coefficient is used as a comparison index for accuracy, the calculation accuracy estimation unit 1006 calculates that the calculation accuracy corresponding to the execution result 1301 of the actual test physical quantum circuit is 95.39%.

[0103] In step 1103, the computational accuracy estimation unit 1006 estimates the accuracy of the desired quantum circuit from the number of layers of the test physical quantum circuit C906, the number of layers of the desired quantum circuit 702, and the accuracy of the test circuit. The desired quantum circuit 702 is composed of 13 layers, and the test physical quantum circuit C906 has 3 layers. Here, the value calculated by dividing 13 by 3 and rounding up to the nearest integer is 5. Therefore, the computational accuracy estimation unit 1006 calculates that the accuracy of the desired quantum circuit is 79%, which is the fifth power of the accuracy of the test circuit.

[0104] In step 1104 , the accuracy estimate calculated in step 1103 is stored in the calculation accuracy estimate holding unit 1007 as shown in calculation accuracy estimate example 1401 .

[0105] In the above embodiment, the Bhattacharya coefficient is used as an index of accuracy, but the index of accuracy is not limited to the Bhattacharya coefficient. For example, the chi-square value and the corresponding significance probability may be used as a measure of the degree of discrepancy between the ideal execution result of the test physical quantum circuit and the execution result of the actual test physical quantum circuit.

[0106] 15 is a detailed block diagram of the calculation time estimation unit 108. The calculation time estimation unit 108 includes a quantum calculation function characteristic information holding unit 1501, a code basic gate calculation time estimation unit 1502, a code basic gate calculation time estimate holding unit 1503, a desired quantum circuit execution information holding unit 1504, a calculation time estimation unit 1505, and a calculation time estimate holding unit 1506.

[0107] The calculation time estimation unit 108 is realized on a computer having a CPU, memory, and input / output devices. The above processing is executed by the CPU, and each holding unit is provided in the memory.

[0108] The code basic gate calculation time estimation unit 1502 acquires quantum computing function characteristic information from the quantum computing function characteristic information storage unit 1501, and estimates the time required to execute the basic gate of the quantum error correcting code used in the quantum computer. The code basic gate calculation time estimate storage unit 1503 then stores the code basic gate calculation time estimate.

[0109] The calculation time estimation unit 1505 acquires an estimate of the calculation time of the code basic gate from the code basic gate calculation time estimate holding unit 1503, acquires the desired quantum circuit information from the desired quantum circuit information holding unit 1504, and estimates the time required to execute the desired quantum circuit encoded with the quantum error correcting code. The above calculation time estimate is stored in the calculation time estimate holding unit 1506.

[0110] 16 shows an example of quantum computing function characteristic information stored in the quantum computing function characteristic information storage unit 1501 and input to the code basic gate calculation time estimation unit 1502. The quantum computing function characteristic information 1601 includes a quantum computer label 1602, a quantum error correcting code to be used 1603, a correcting code basic gate 1604, a gate time 1605 of a physical basic gate, a bit connection graph 1606, and a correspondence table 1607 between logical bits and physical bits.

[0111] 17 shows an example of a calculation time estimate for a code basic gate that the code basic gate calculation time estimator 1502 stores in the code basic gate calculation time estimate holder 1503. A calculation time estimate 1701 for a code basic gate includes a label 1702 of a quantum computer, a quantum error correcting code 1703 to be used, and a gate time 1704 of a logic basic gate.

[0112] FIG. 18 is a flowchart showing an example of the procedure of the code basic gate calculation time estimating unit 1502.

[0113] The following processing is realized by a program executed on the memory 203 by the CPU 202 of the fault-tolerant quantum computer utilization system 201. The CPU 202 executes the code basic gate calculation time estimation unit 1502 to acquire quantum computing function characteristic information from the quantum computing function characteristic information storage unit 1501 (step 1801).

[0114] The code basic gate calculation time estimation unit 1502 decomposes the code basic gates of the quantum computer into physical basic gates of the quantum computer (step 1802).

[0115] Next, the code basic gate calculation time estimation unit 1502 estimates the time required to implement the code basic gate using physical basic gates from the decomposition result and the quantum computing function characteristic information (step 1803).

[0116] Then, the above estimate is stored in the code basic gate calculation time estimate holding unit 1503 (step 1804).

[0117] An example of outputting an estimate of the computation time of the code basic gate shown in FIG. 17 using the example of quantum computation function characteristic information shown in FIG. 16 will be described.

[0118] In step 1801, the code basic gate calculation time estimator 1502 acquires characteristic information about the quantum computer B. In step 1802, the code basic gate calculation time estimator 1502 decomposes the code basic gates of the quantum computer into physical basic gates of the quantum computer.

[0119] For example, in a bit-flip code with d=3, which is a quantum error correcting code used by quantum computer B, one logical CNOT gate can be decomposed using three physical CNOT gates. In step 1803, the time required to implement a logical basic gate using physical basic gates is estimated.

[0120] For example, when estimating the gate time of a logical CNOT gate, the code basic gate calculation time estimation unit 1502 first refers to the bit connection graph 1606 and the correspondence table 1607 between logical bits and physical bits in the quantum computing function characteristic information to identify the numbers of the physical bits corresponding to two adjacent logical bits.

[0121] In the bit connection graph 1606, for example, a first logical bit consisting of three physical bits 1, 2, and 3 and a second logical bit consisting of three physical bits 4, 5, and 6 correspond to two adjacent logical bits.

[0122] Then, the code basic gate calculation time estimator 1502 estimates the gate time of the logic CNOT gate to be the time required to implement the CNOT gate between the first logic bit and the second logic bit.

[0123] In this embodiment, to execute a CNOT gate between the first logical bit and the second logical bit, it is necessary to execute three physical CNOT gates: a physical CNOT gate between physical bits 1 and 4, a physical CNOT gate between physical bits 2 and 5, and a physical CNOT gate between 3 and 6. Therefore, the time required to execute a logical CNOT gate is estimated as three times the gate time of the physical CNOT gate. In step 1804, the code basic gate calculation time estimator 1502 stores the code basic gate calculation time estimate 1701 generated in step 1803 in the code basic gate calculation time estimate holder 1503.

[0124] 19 shows an example of a calculation time estimate that the calculation time estimator 1505 stores in the calculation time estimate holder 1506. A calculation time estimate 1901 includes a label 1902 of the quantum computer and an estimate 1903 of the calculation time.

[0125] FIG. 20 is a flowchart showing an example of the procedure of the calculation time estimation unit 1505.

[0126] The processing described below is realized by a program executed on the memory 203 by the CPU 202 of the fault-tolerant quantum computer utilization system 201. The CPU 202 executes the calculation time estimation unit 1505 to obtain an estimate of the calculation time of the code basic gate from the code basic gate calculation time estimate holding unit 1503 and desired execution quantum circuit information from the desired execution quantum circuit information holding unit 1504 (step 2001).

[0127] The calculation time estimation unit 1505 decomposes the quantum circuit to be executed into code elementary gates (step 2002).

[0128] Next, the calculation time estimation unit 1505 estimates the calculation time of the quantum circuit to be executed from the number of each code basic gate included in the quantum circuit to be executed and the estimated calculation time of the code basic gate (step 2003).

[0129] Then, the above estimate is stored in the calculation time estimate holding unit 1506 (step 2004).

[0130] For example, the time required to execute circuit 702 on quantum computer B, whose code elementary gate calculation time estimate is given in 1701, is estimated to be (number of logic H gates) x (logic H gate time) + (number of logic T gates) x (logic T gate time) + (number of logic CNOT gates) x (logic CNOT gate time) = 2 x 300 + 7 x 650,000 + 6 x 900 = 4,556,000 ns = 4,556 μs.

[0131] In addition, since there are fewer quantum computers than conventional computers and many jobs are concentrated on one quantum computer, job waiting times tend to be long. Therefore, in calculating the estimated computation time, an embodiment can be considered in which, in addition to the time it takes for the quantum computer to process the quantum circuit to be executed, the waiting time until the job including the quantum circuit to be executed is submitted to the quantum computer is also taken into account.

[0132] 21 shows an example of quantum computing function characteristic information stored in the quantum computing function characteristic information storage unit 107 and input to the monetary cost estimation unit 110. Quantum computing function characteristic information 2101 includes a quantum computer label 2102 and an hourly usage fee 2103.

[0133] 22 shows an example of a monetary cost estimate that the monetary cost estimator 110 stores in the monetary cost estimate storage unit 111. A monetary cost estimate 2201 includes a label 2202 of the quantum computer and an estimate 2203 of the monetary cost.

[0134] FIG. 23 is a flowchart showing an example of the procedure of the monetary cost estimate unit 110.

[0135] The following process is realized by a program executed on the memory 203 by the CPU 202 of the fault-tolerant quantum computer utilization system 201. The CPU 202 executes the monetary cost estimation unit 110 to obtain quantum computing function characteristic information from the quantum computing function characteristic information storage unit 107 and an estimate of the computation time from the computation time estimate storage unit 109 (step 2301).

[0136] Next, the monetary cost estimator 110 calculates an estimate of the monetary cost required to run the quantum computer from the quantum computing function characteristic information and the estimated computation time, and stores the estimated monetary cost in the monetary cost estimate storage unit 111 (step 2302). As an example of calculating the monetary cost estimate, it can be considered that the monetary cost estimate is calculated by dividing (hourly usage fee) by (estimated computation time).

[0137] FIG. 24 shows an example of the user request information / quantum circuit characteristic information desired to be executed, which is held in the user request information / quantum circuit characteristic information desired to be executed holding unit 112 and input to the quantum computer selection unit 114.

[0138] The user request information and desired quantum circuit characteristic information includes a user request 2401 and desired quantum circuit characteristic information 2404. The user request 2401 includes a user's request regarding monetary cost 2402 and a user's request regarding computation time 2403. The desired quantum circuit characteristic information 2404 includes a logical quantum circuit number 2405 and an algorithm classification 2406.

[0139] 25 is an example of evaluation function weight information that is held by the evaluation function weight information holding unit 113 and input to the quantum computer selection unit 114. Evaluation function weight information 2501 includes algorithm classification 2502, a weight coefficient for monetary cost 2503, a weight coefficient for calculation time 2504, and a weight coefficient for accuracy 2505.

[0140] FIG. 26 shows an example of the evaluation and selection data of the quantum computer that the quantum computer selection unit 114 stores in the quantum computer evaluation and selection data holding unit 115.

[0141] The quantum computer evaluation and selection data includes quantum computer evaluation data 2601 and quantum computer selection data 2604. The quantum computer evaluation data 2601 includes a quantum computer label 2602 and an evaluation function value 2603. The quantum computer selection data 2604 includes a logical quantum circuit number 2605 and a selected quantum computer 2606.

[0142] FIG. 27 is a flowchart showing an example of the procedure of the quantum computer selection unit 114.

[0143] The processing described below is realized by a program executed on the memory 203 by the CPU 202 of the fault-tolerant quantum computer utilization system 201. The CPU 202 executes the quantum computer selection unit 114 to obtain an estimate of calculation accuracy from the calculation accuracy estimate holding unit 106, an estimate of calculation time from the calculation time estimate holding unit 109, an estimate of monetary cost from the monetary cost estimate holding unit 111, user request information and desired execution quantum circuit characteristic information from the user request information / desired execution quantum circuit characteristic information holding unit 112, and evaluation function weight information from the evaluation function weight information holding unit 113 (step 2701).

[0144] Next, the quantum computer selection unit 114 designs an evaluation function based on the user request information, the desired quantum circuit characteristic information, and the weight information of the evaluation function (step 2702).

[0145] An example of an evaluation function that can be designed is (Evaluation function) = (Weighting coefficient of monetary cost) x [(Estimated monetary cost) / (Desired monetary cost)] + (Weighting coefficient of calculation time) x [(Estimated calculation time) / (Desired calculation time)] + (Weighting coefficient of accuracy) x [100% - (Estimated accuracy (unit: %))].

[0146] The quantum computer selection unit 114 uses the evaluation function designed in step 2702 to calculate the value of the evaluation function for each available quantum computer, enters the value of the evaluation function into the evaluation data of the quantum computer, and stores the evaluation data in the quantum computer evaluation and selection data storage unit 115 (step 2703).

[0147] Then, the quantum computer selection unit 114 enters the label of the quantum computer with the smallest value of the evaluation function into the selection data of the quantum computer, and stores the selection data in the evaluation and selection data holding unit 115 of the quantum computer (step 2704).

[0148] In this embodiment, the fault-tolerant quantum computer utilization system includes an arithmetic unit 105 that evaluates the expected quality of calculation when the quantum processing included in the program is executed using a quantum computing function, an arithmetic unit 109 that evaluates the calculation time required to execute the quantum processing included in the program, and an arithmetic unit 114 that selects a quantum computer to be used to execute the quantum processing included in the program based on the evaluation results of the arithmetic unit 105 and the evaluation results of the arithmetic unit 109.

[0149] According to this embodiment, it is possible to quickly estimate the accuracy, monetary cost, and time cost of a quantum program that a user wants to execute on a selected fault-tolerant quantum computer. This makes it possible to quickly select an appropriate fault-tolerant quantum computer that meets the user's requirements, taking into account the characteristics of the quantum program algorithm, and reduce the latency of quantum program execution. [Explanation of symbols]

[0150] 101 Quantum circuit execution information storage unit 102 Test circuit condition holding unit 103 Test circuit generation unit 104 Test Physics Quantum Circuit Information Storage Unit 105 Calculation Accuracy Estimation Section 106 Calculation accuracy estimate storage unit 107 Quantum calculation function characteristic information storage unit 108 Calculation time estimation part 109 Calculation time estimate storage unit 110 Monetary Cost Estimation Section 111 Monetary Cost Estimates Maintenance Department 112 User request information and desired execution quantum circuit characteristic information storage unit 113 Evaluation function weight information storage unit 114 Quantum Computer Selection Department 115 Evaluation and selection data storage unit of quantum computer

Claims

1. An error-tolerant quantum computer utilization system having a calculation time estimation unit and a quantum computer selection unit executed by a CPU, and selecting a quantum computer capable of executing a desired quantum circuit encoded with a quantum error correcting code from among a plurality of quantum computers each having different characteristic information, The calculation time estimation unit using characteristic information of the quantum computer, estimating a code basic gate calculation time required to execute a correction code basic gate of the quantum error correcting code used in the quantum computer; The quantum computer selection unit An error-tolerant quantum computer utilization system, characterized in that a quantum computer having a quantum error correcting code that can execute the desired quantum circuit is selected by referring to the code basic gate calculation time.

2. The calculation time estimation unit estimating a quantum circuit calculation time required to execute the desired quantum circuit based on the code basic gate calculation time; The quantum computer selection unit 2. The system for utilizing an error-tolerant quantum computer according to claim 1, wherein the quantum computer capable of executing the desired quantum circuit is selected based on the quantum circuit calculation time.

3. The calculation time estimation unit 2. The error-tolerant quantum computer utilization system according to claim 1, wherein the code basic gate is decomposed into physical basic gates of the quantum computer, and the code basic gate calculation time is estimated using the gate times of the decomposed physical basic gates and characteristic information of the quantum computer.

4. The calculation time estimation unit decomposing the quantum circuit to be executed into the correction code elementary gates; 3. The system for utilizing an error-tolerant quantum computer according to claim 2, wherein the quantum circuit calculation time required to execute the desired quantum circuit is estimated using the number of code basic gates included in the desired quantum circuit and the code basic gate calculation time.

5. a monetary cost estimating unit that is executed by a CPU and that estimates a monetary cost of the quantum computer required to execute the desired quantum circuit on the quantum computer based on information on the hourly usage fee of the quantum computer and the quantum circuit calculation time, The quantum computer selection unit 3. The system for utilizing an error-tolerant quantum computer according to claim 2, wherein the quantum computer capable of executing the desired quantum circuit is selected using the monetary cost.

6. A test circuit generation unit and a calculation accuracy estimation unit executed by a CPU are included, The test circuit generation unit Generate a test circuit; converting the quantum circuit to be executed into a quantum circuit using elementary gates of a quantum correcting code; generating a test quantum circuit that satisfies the conditions of the test circuit from the converted quantum circuit; converting the test quantum circuit into a test physical quantum circuit using physical elementary gates of the quantum computer; outputting the test physical quantum circuit; The calculation accuracy estimation unit Estimating the computational accuracy of the desired quantum circuit based on the results of executing the test physical quantum circuit using the quantum computer; The quantum computer selection unit 2. The system for utilizing an error-tolerant quantum computer according to claim 1, wherein the quantum computer capable of executing the desired quantum circuit is selected using the calculation accuracy.

7. The calculation accuracy estimation unit 7. The fault-tolerant quantum computer utilization system according to claim 6, wherein the calculation accuracy is estimated by comparing a result of executing the test physical quantum circuit using a simulator that simulates an ideal quantum computer that does not generate noise with a result of executing the test physical quantum circuit using an actual quantum computer.

8. an input device for inputting at least one of user request information and characteristic information of the quantum circuit to be executed, The quantum computer selection unit 2. The fault-tolerant quantum computer utilization system according to claim 1, wherein the quantum computer that meets the user requirements and is capable of executing the desired quantum circuit is selected using at least one of the user requirement information and the characteristic information of the desired quantum circuit.

9. The quantum computer selection unit Calculating a value of an evaluation function for the quantum computer; 2. The system for utilizing an error-tolerant quantum computer according to claim 1, wherein the quantum computer having the smallest value of the evaluation function is selected.

10. 1. A method for utilizing an error-tolerant quantum computer, comprising a calculation time estimation step and a quantum computer selection step, executed by a CPU, for selecting a quantum computer capable of executing a desired quantum circuit encoded with a quantum error correcting code from among a plurality of quantum computers each having different characteristic information, The calculation time estimation step using characteristic information of the quantum computer, estimating a code basic gate calculation time required to execute a correction code basic gate of the quantum error correcting code used in the quantum computer; The quantum computer selection step includes: A method for utilizing an error-tolerant quantum computer, comprising: selecting a quantum computer having a quantum error correcting code capable of executing the desired quantum circuit by referring to the code basic gate calculation time.

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