Vibration device

Abstract

To provide a vibration device that facilitates easy control of adhesive spread.SOLUTION: A vibration device comprises an IC chip 5 including a heat source circuit 51 that generates heat, a vibration element 6, a base 2 housing the IC chip 5 and vibration element 6, and an adhesive 7 arranged between the IC chip 5 and the base 2. The base 2 has a recess 2b for accommodating the IC chip 5 and a recess 2a having an opening in the upper surface 22f of substrate 22, which serves as the bottom surface of recess 2b, and the adhesive 7 is arranged within the recess 2a as viewed from above.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a vibration device. [Background technology]

[0002] Patent Document 1 describes a piezoelectric device in which an IC chip and a piezoelectric vibrator are built into a package. In Patent Document 1, the IC chip is bonded to a base that constitutes the package with a resin adhesive. It also describes that the amount of resin adhesive applied to the base before the IC chip is mounted is preferably about 1 / 4 to 1 / 3 of the surface area of ​​the IC chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-267363 Summary of the Invention [Problem to be solved by the invention]

[0004] In the method described in Patent Document 1, there is a risk that the resin adhesive will spread excessively when the IC chip is mounted. For example, if the resin adhesive spreads excessively and comes into contact with the bumps of the IC chip, there is a risk that the bumps will break or suffer other problems due to thermal stress caused by heat generated by the IC chip or heat during reflow mounting. [Means for solving the problem]

[0005] A vibration device according to one embodiment of the present application comprises a semiconductor integrated circuit including a heat source circuit that serves as a heat source, a vibration element, a substrate that houses the semiconductor integrated circuit and the vibration element, and an adhesive disposed between the semiconductor integrated circuit and the substrate, wherein the substrate has a first recess that houses the semiconductor integrated circuit and a second recess having an opening at the bottom surface of the first recess, and the adhesive is disposed within the second recess in a planar view. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a vibration device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the vibration device taken along line II-II in FIG. [Figure 3] FIG. 3 is a cross-sectional view of the vibration device taken along line III-III in FIG. [Figure 4] 10 is a graph showing the thermal resistance reduction effect. [Figure 5] FIG. 10 is a plan view of a vibration device according to a second embodiment. [Figure 6] 7 is a cross-sectional view of the vibration device taken along line VII-VII in FIG. 5. [Figure 7] FIG. 10 is a plan view of a vibration device according to a third embodiment. [Figure 8] 8 is a cross-sectional view of the vibration device taken along line VIII-VIII in FIG. 7. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings below, the dimensions of the components may be shown on different scales to make them easier to see. For ease of explanation, the three mutually orthogonal axes will be referred to as the X-axis, Y-axis, and Z-axis below, and the direction parallel to the X-axis will be referred to as the "X-axis direction," the direction parallel to the Y-axis as the "Y-axis direction," and the direction parallel to the Z-axis as the "Z-axis direction." The tip of each axis in the direction of the arrow will also be referred to as the "plus side," and the opposite side as the "minus side." In the following, viewing in the Z-axis direction will be referred to as "planar view." Furthermore, in the following description, the term "upper surface" refers to the surface on the positive side in the Z-axis direction, and the term "lower surface" refers to the surface on the negative side in the Z-axis direction.

[0008] 1. Embodiment 1 Fig. 1 is a plan view of the resonation device 100 of the first embodiment, with the internal configuration indicated by dashed lines. Fig. 2 is a cross-sectional view of the resonation device 100 taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view of the resonation device 100 taken along line III-III in Fig. 1. Fig. 4 is a graph showing the thermal resistance reduction effect according to this embodiment.

[0009] The resonator device 100 is an oscillator that houses an IC chip 5 and a resonator element 6 in a single package 1. The resonator device 100 is installed in electronic devices such as quartz watches, communication devices, computers, display devices, printing devices, industrial robots, automobiles, and aircraft, and is used for timing control, frequency control, and the like.

[0010] The IC chip 5 generates and outputs a clock reference signal using the vibration element 6. The IC chip 5 has a heat source circuit 51. The heat source circuit 51 is, for example, a power supply circuit and / or a PLL (Phase Locked Loop) circuit. The IC chip 5 also has an oscillation circuit, a memory circuit, a temperature sensor, a temperature compensation circuit, an interface circuit, etc. In this embodiment, the IC chip 5 is an example of a semiconductor integrated circuit.

[0011] The vibration element 6 is a quartz crystal resonator formed from an AT-cut quartz crystal substrate. The vibration element 6 may be a quartz crystal resonator formed from an X-cut quartz crystal substrate, a Y-cut quartz crystal substrate, a Z-cut quartz crystal substrate, a BT-cut quartz crystal substrate, an SC-cut quartz crystal substrate, an ST-cut quartz crystal substrate, or the like. The vibration element 6 may also be a resonator formed from a piezoelectric single crystal such as lithium niobate, lithium tantalate, lithium tetraborate, langasite, potassium niobate, or gallium phosphate. The vibration element 6 may also be a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) resonator as a silicon resonator formed using a silicon substrate, or the like.

[0012] The package 1 has a base 2 and a lid 3. By joining the base 2 and the lid 3 via a seal ring 4, an accommodation space S is formed within the package 1 to accommodate an IC chip 5 and a vibration element 6. The accommodation space S is airtight and in a reduced pressure state, preferably closer to a vacuum. This reduces viscous resistance and allows the vibration element 6 to be driven stably. However, the atmosphere within the accommodation space S is not particularly limited.

[0013] The base 2 has a box-like shape with an open top, and houses the IC chip 5 and the vibration element 6 inside. The base 2 is composed of four laminated layers of substrates 21, 22, 23, and 24. The base 2 may be composed of a single layer or multiple layers other than four layers. The substrates 21, 22, 23, and 24 are insulating and made of various ceramics such as aluminum oxide. In this embodiment, the base 2 is an example of a substrate.

[0014] The substrate 22 has a recess 2a. The recess 2a is a hole that penetrates the substrate 22 and exposes the upper surface 21f of the substrate 21 at its bottom. The recess 2a may be a recessed hole having a bottom surface in the substrate 22.

[0015] The adhesive 7 is placed in the recess 2a. In other words, the adhesive 7 is placed inside the recess 2a in plan view. Before flip-chip bonding (FCB) of the IC chip 5, the adhesive 7 is applied to the upper surface 21f of the substrate 21 exposed at the bottom of the recess 2a. Thereafter, when flip-chip bonding the IC chip 5, the adhesive 7 is pressed by the lower surface 5f of the IC chip 5 and spreads between the recess 2a and the IC chip 5 so as to fill the entire recess 2a. In this embodiment, the recess 2a is an example of a second recess.

[0016] The adhesive 7 functions as a heat transfer path that dissipates heat generated during operation of the IC chip 5 to the base 2. Therefore, with this configuration, the junction temperature of the IC chip 5 can be suppressed, and the operating temperature range of the resonator device 100 can be expanded. Furthermore, since this configuration can reduce the temperature difference between the IC chip 5 and the resonator element 6, it can be a configuration that is particularly excellent in dynamic temperature characteristics required for a TCXO (Temperature Compensated Crystal Oscillator).

[0017] In this embodiment, a recess 2a is provided in the base 2, and the adhesive 7 is disposed between the recess 2a and the IC chip 5. This makes it easier to control the spread of the adhesive 7 than in the configuration described in Patent Document 1, which does not have a recess 2a. In other words, with the configuration of this embodiment, the contact area between the adhesive 7 and the IC chip 5 can be easily controlled to a desired value. Hereinafter, the contact area between the adhesive 7 and the IC chip 5 will be referred to as the bonding area.

[0018] As described above, the adhesive 7 spreads between the recess 2a and the IC chip 5 so as to fill the entire recess 2a. Therefore, the bonding area can be rephrased as the area where the lower surface 5f of the IC chip 5 and the recess 2a overlap in a plan view.

[0019] In this embodiment, the bonding area is controlled to 20% to 60% of the lower surface 5f of the IC chip 5. The reason for this will be explained below with reference to FIG. FIG. 4 is a graph showing the thermal resistance reduction effect depending on the bonding area.

[0020] The horizontal axis represents the bonding area ratio between the IC chip 5 and the adhesive 7. The bonding area ratio represents the ratio of the bonding area when the IC chip 5 and the adhesive 7 are in contact over the entire lower surface 5f of the IC chip 5, with 100% representing the bonding area. 0% indicates that the IC chip 5 and the adhesive 7 are not bonded, 60% indicates that 60% of the area of ​​the lower surface 5f of the IC chip 5 is in contact with the adhesive 7, and 80% indicates that 80% of the area of ​​the lower surface 5f of the IC chip 5 is in contact with the adhesive 7. The bonding area ratio can be rephrased as the ratio of the area of ​​the lower surface 5f of the IC chip 5 that overlaps with the recess 2a in a plan view.

[0021] The vertical axis shows the thermal resistance reduction rate. The thermal resistance reduction rate is expressed as a percentage of the thermal resistance between the IC chip 5 and the base 2 when the IC chip 5 and the adhesive 7 are not in contact, which is taken as 100%. 0% indicates that the thermal resistance is zero, and 60% indicates that the thermal resistance is 60% of 100%.

[0022] Based on the graph in FIG. 4 , the inventors conducted a study and found that, from the perspective of preventing defects at the bumps 8 of the IC chip 5 due to excessive spreading of the adhesive 7 and from the perspective of the heat dissipation effect of the adhesive 7 on the IC chip 5, it is preferable to control the bonding area to 20% to 60% of the underside 5f of the IC chip 5. In other words, by setting the bonding area ratio to 20% or more, thermal resistance can be reduced, allowing heat generated during operation of the IC chip 5 to be efficiently dissipated via the adhesive 7. On the other hand, if the bonding area ratio is set to more than 60%, the adhesive 7 will spread excessively and come into contact with the bumps 8, increasing the risk of defects such as breakage occurring at the bumps 8. In other words, setting the bonding area ratio to 60% or less can suppress an increased risk of the adhesive 7 coming into contact with the bumps 8.

[0023] Substrate 23 has recess 2b. Recess 2b is a hole that penetrates substrate 23, and exposes upper surface 22f of substrate 22 and recess 2a at the bottom surface. As shown in Figures 2 and 3, recess 2a has an opening at the bottom surface of recess 2b.

[0024] An IC chip 5 is housed in the recess 2b. In other words, the IC chip 5 is flip-chip mounted on the upper surface 22f of the substrate 22 exposed at the bottom surface of the recess 2b. By being flip-chip mounted, the IC chip 5 is electrically connected to the electrodes 10 arranged on the upper surface 22f of the substrate 22 via the bumps 8. Metal bumps such as gold bumps and copper bumps can be used as the bumps 8. In this embodiment, the bumps 8 are an example of a bonding member.

[0025] Substrate 24 has recess 2c. Recess 2c is a hole that penetrates substrate 24, and exposes upper surface 23f of substrate 23 and recess 2b at the bottom surface. As shown in Figures 2 and 3, recess 2b has an opening at the bottom surface of recess 2c.

[0026] The recess 2c accommodates the vibration element 6. In other words, the vibration element 6 is mounted on the upper surface 23f of the substrate 23, which is exposed at the bottom of the recess 2c. By mounting the vibration element 6, the vibration element 6 is electrically connected to the electrode 11 arranged on the upper surface 23f of the substrate 23 via a bonding material 9. The bonding material 9 can be a conductive adhesive or a metal bump. In this embodiment, the upper surface 23f and / or the electrode 11 are an example of a mounting portion.

[0027] The electrode 11 is electrically connected to the electrode 10 via wiring and / or a through electrode (not shown). As a result, the vibration element 6 and the IC chip 5 are electrically connected via the electrode 10 and the electrode 11.

[0028] The lid 3 is bonded to the upper surface of the base 2 via a seal ring 4. The material of the lid 3 is not particularly limited, but is preferably a material with a linear expansion coefficient similar to that of the material of the base 2. For example, if the material of the base 2 is ceramic, an alloy such as Kovar is preferable. The seal ring 4 is, for example, a gasket made by die-cutting an Fe-Ni alloy or the like into a frame shape.

[0029] As described above, the vibration device 100 of this embodiment comprises an IC chip 5 as a semiconductor integrated circuit including a heat source circuit 51 that serves as a heat source, a vibration element 6, a base 2 as a substrate that houses the IC chip 5 and the vibration element 6, and an adhesive 7 arranged between the IC chip 5 and the base 2, and the base 2 has a recess 2b as a first recess that houses the IC chip 5 and a recess 2a as a second recess having an opening on the upper surface 22f of the substrate 22 that serves as the bottom surface of the recess 2b, and the adhesive 7 is arranged within the recess 2a in a planar view.

[0030] As described above, the resonator device 100 of this embodiment is configured to provide a recess 2a in the base 2 and place the adhesive 7 in the recess 2a, which makes it easier to control the spread of the adhesive 7 than in a configuration without the recess 2a. This prevents the adhesive 7 from coming into contact with the bumps 8 and causing defects such as breakage in the bumps 8 due to thermal stress caused by heat generation from the IC chip 5 or heat during reflow mounting. This makes it possible to realize a highly reliable resonator device 100.

[0031] Furthermore, in the resonation device 100 of this embodiment, the recess 2a allows the contact area between the adhesive 7 and the IC chip 5 to be easily controlled to a desired value, so that heat generated during operation of the IC chip 5 can be efficiently dissipated to the base 2. As a result, the temperature difference between the IC chip 5 and the resonator element 6 is reduced. Therefore, a resonation device 100 with excellent dynamic temperature characteristics can be realized.

[0032] In the resonation device 100 of this embodiment, the base 2 includes an electrode 10 arranged on the upper surface 22f of the substrate 22, which serves as the bottom surface of the recess 2b, and the IC chip 5 is electrically connected to the electrode 10 via bumps 8.

[0033] In this way, the electrode 10 is disposed in the recess 2b, and the adhesive 7 is disposed in the recess 2a. Therefore, the electrode 10 and the adhesive 7 are disposed on different surfaces, which reduces the risk of the adhesive 7 and the bump 8 coming into contact with each other.

[0034] In the resonation device 100 of this embodiment, the area of ​​the region where the IC chip 5 and the opening of the recess 2a overlap in plan view is 20% to 60% of the area of ​​the lower surface 5f of the IC chip 5, which is the surface on the recess 2a side.

[0035] In this way, the thermal resistance can be reduced by making the area where the IC chip 5 and the opening of the recess 2a overlap 20% or more of the area of ​​the lower surface 5f of the IC chip 5. Therefore, the heat generated during operation of the IC chip 5 can be efficiently dissipated to the base 2 via the adhesive 7. Furthermore, by making the area of ​​the region where the IC chip 5 and the opening of the recess 2a overlap 60% or less of the area of ​​the lower surface 5f of the IC chip 5, it is possible to reduce the risk of the adhesive 7 coming into contact with the bumps 8. Therefore, it is possible to realize a highly reliable resonation device 100.

[0036] In the resonator device 100 of this embodiment, the base 2 has a recess 2c on the bottom surface as a third recess having the opening of the recess 2b and the upper surface 23f of the substrate 23 as a mounting portion on which the resonator element 6 is mounted and / or the electrode 11. Therefore, the heat transferred from the IC chip 5 to the base 2 is more easily transferred to the vibration element 6, reducing the temperature difference between the IC chip 5 and the vibration element 6. Therefore, it is possible to realize a vibration device 100 with excellent dynamic temperature characteristics.

[0037] 2. Embodiment 2 Fig. 5 is a plan view of the resonation device 120 of the second embodiment, with the internal configuration indicated by dashed lines. Fig. 6 is a cross-sectional view of the resonation device 120 taken along line VI-VI in Fig. 5. In the description of the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

[0038] 5 and 6, the substrate 22 has a recess 22a, which corresponds to the recess 2a of the first embodiment. The recess 22a differs from the recess 2a of the first embodiment in that, in plan view, it has a portion 22b that is arranged outside the outer edge 5s of the IC chip 5. In this embodiment, the recess 22a is an example of a second recess.

[0039] The portion 22b of the recess 22a is a portion that does not overlap with the IC chip 5 in a plan view. The portion 22b of the recess 22a is used when applying the adhesive 7. In the second embodiment, since the recess 22a has the portion 22b, the adhesive 7 can be applied after the IC chip 5 is flip-chip mounted in the recess 22a. After the IC chip 5 is flip-chip mounted in the recess 22a, the adhesive 7 is applied from the portion 22b of the recess 22a so as to fill the space between the IC chip 5 and the recess 22a.

[0040] In the second embodiment, the IC chip 5 can be flip-chip mounted before the adhesive 7 is applied to the recess 22a, which reduces variations in load and ultrasonic waves during flip-chip mounting, thereby improving the reliability of flip-chip mounting.

[0041] As described above, in the resonation device 120 of this embodiment, the opening of the recess 22a serving as the second recess has the portion 22b arranged outside the outer edge 5s of the IC chip 5 serving as the semiconductor integrated circuit in a plan view. In the second embodiment, since the recess 22a has the portion 22b, the IC chip 5 can be flip-chip mounted before the adhesive 7 is applied to the recess 22a. This reduces load variations and ultrasonic wave variations during flip-chip mounting, improving the reliability of the flip-chip mounting. This allows for the realization of a highly reliable resonator device 120.

[0042] 3. Embodiment 3 Fig. 7 is a plan view of the resonation device 130 of the third embodiment, and the internal configuration is indicated by a dashed line. Fig. 8 is a cross-sectional view of the resonation device 130 taken along line VIII-VIII in Fig. 7. In the description of the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

[0043] 7 and 8, the substrate 22 has a recess 23a. The recess 23a has a configuration corresponding to the recess 2a of embodiment 1. In this embodiment, the recess 23a is an example of a second recess.

[0044] In a plan view, the recess 23a overlaps with the heat source circuit 51. More specifically, the recess 23a is arranged so as to overlap only with the heat source circuit 51. The recess 23a may overlap with circuits other than the heat source circuit 51, but in order to reduce the size of the recess 23a, it is preferable that the recess 23a be arranged so as to overlap only with the heat source circuit 51.

[0045] The adhesive 7 is placed in the recess 23a. In the third embodiment, the size of the recess 23a can be reduced, so the amount of adhesive 7 can be reduced. Therefore, degassing from the adhesive 7 is reduced, so deterioration of the characteristics of the vibration device 130 can be suppressed. Therefore, a high-quality vibration device 130 can be realized. Furthermore, since the recess 23a overlaps the heat source circuit 51, the heat from the heat source circuit 51 can be efficiently dissipated via the adhesive 7.

[0046] As described above, in the resonation device 130 of this embodiment, the recess 23a overlaps at least the heat source circuit 51 in plan view. Therefore, it is possible to efficiently dissipate heat from the heat source circuit 51. Furthermore, since the amount of adhesive 7 can be reduced, degassing from the adhesive 7 is reduced, and deterioration of the characteristics of the vibration device 130 can be suppressed.

[0047] Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the above-described embodiments. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above-described embodiments, and any configuration can be added. [Explanation of symbols]

[0048] 1...package, 2...base, 2a...recess, 22a...recess, 22b...portion, 23a...recess, 2b...recess, 2c...recess, 3...lid, 4...seal ring, 5...IC chip, 51...heat source circuit, 5f...bottom surface, 5s...outer edge, 6...vibration element, 7...adhesive, 8...bump, 9...bonding material, 10...electrode, 11...electrode, 21...substrate, 21f...top surface, 22...substrate, 22f...top surface, 23...substrate, 23f...top surface, 24...substrate, 100, 120, 130...vibration device, S...accommodation space.

Claims

1. a semiconductor integrated circuit including a heat source circuit that serves as a heat source; A vibration element; a substrate that accommodates the semiconductor integrated circuit and the vibration element; an adhesive disposed between the semiconductor integrated circuit and the substrate; The substrate is a first recess for accommodating the semiconductor integrated circuit; a second recess having an opening on a bottom surface of the first recess, the adhesive is disposed in the second recess in a plan view; Vibration device.

2. the substrate includes an electrode disposed on a bottom surface of the first recess; the semiconductor integrated circuit is electrically connected to the electrodes via a bonding member; The vibration device according to claim 1 .

3. The area of ​​the region where the semiconductor integrated circuit and the opening of the second recessed portion overlap in a plan view is the area of ​​the surface of the semiconductor integrated circuit on the second recess side is 20% or more and 60% or less. The vibration device according to claim 1 .

4. the opening of the second recess has a portion disposed outside an outer edge of the semiconductor integrated circuit in a plan view; The vibration device according to claim 1 .

5. In a plan view, the second recess overlaps at least the heat source circuit. The vibration device according to claim 1 .

6. the substrate has a third recess on a bottom surface, the third recess having an opening of the first recess and a mounting portion on which the vibration element is mounted; The vibration device according to claim 1 .

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