Motor control device and sheet conveying device

Abstract

To prevent a situation in which a control signal indicating drive validity continues to be output to a motor drive unit even when an output of a clock signal is stopped, current supply from the motor drive unit to a motor continues, and the motor continues to operate.SOLUTION: A motor control device 1 includes: a motor drive unit 5 that inputs a clock signal for driving a motor and drives the motor; an engine control unit 3 that outputs the clock signal; a main control unit 2 that outputs a determination signal indicating no output of the clock signal when the clock signal is input from the engine control unit 3 and an input of the clock signal is stopped; and a relay unit 4 that outputs a drive control signal indicating drive validity or drive invalidity of the motor to the motor drive unit 5, and outputs the drive control signal indicating drive invalidity of the motor to the motor drive unit 5 when a determination signal indicating no output of the clock signal is input from the main control unit 2 while the drive control signal indicating drive validity of the motor is output.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a motor control device that controls a motor and a paper transport device that includes the same. [Background technology]

[0002] For example, in an image forming device, a recording paper is transported by the driving force of a motor and an image is formed on the recording paper. However, if the operation of the motor's control circuit becomes abnormal, the motor may not operate normally, and this must be addressed.

[0003] In the image forming apparatus described in Patent Document 1, when the thermal shutdown circuit detects overheating of the composite IC, the fan is driven via the driver circuit regardless of whether the ASIC outputs a FANON signal. Furthermore, when the thermal shutdown circuit detects overheating of the composite IC, it disables the motor drive enable signal (Enable) input from the ASIC to the motor driver, as well as the paper feed solenoid ON signal and the registration solenoid ON signal input from the ASIC to the driver circuit timer circuit. This allows for the fan to be forcibly driven while suppressing any abnormalities in the composite IC. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-040169 Summary of the Invention [Problem to be solved by the invention]

[0005] Here, if the motor control device is configured to include an engine control unit that outputs a clock signal for driving the motor and a control signal indicating whether driving is enabled or disabled, and a motor drive unit that receives the clock signal and control signal from the engine control unit and controls the driving of the motor, if an abnormality occurs in the engine control unit and the output of the clock signal from the engine control unit is interrupted, but the engine control unit continues to output a control signal indicating driving is enabled to the motor drive unit, the motor drive unit may continue to supply current to the motor, causing the motor to continue operating.

[0006] In Patent Document 1, when the composite IC overheats, the fan is driven and the motor drive enable, paper feed solenoid ON signal, and registration solenoid ON signal are disabled to suppress heat generation from the composite IC. However, if the output of the clock signal as described above is interrupted but a control signal indicating drive enable continues to be output to the motor drive unit, the motor drive unit continues to supply current to the motor, and it is not possible to prevent the motor from continuing to operate.

[0007] Therefore, the present invention has been made in consideration of the above circumstances, and aims to prevent a situation in which, even when the output of the clock signal has been interrupted, a control signal indicating that drive is enabled continues to be output to the motor drive unit, causing the motor drive unit to continue supplying current to the motor, causing the motor to continue operating. [Means for solving the problem]

[0008] A motor control device according to one aspect of the present invention comprises a motor drive unit that receives a clock signal for driving a motor and drives the motor; an engine control unit that outputs the clock signal; a main control unit that receives the clock signal from the engine control unit and, when the input of the clock signal stops, outputs a determination signal indicating that the clock signal is not being output; and a relay unit that outputs a drive control signal indicating whether the motor is being driven or not to be driven to the motor drive unit, and, when a determination signal indicating that the clock signal is not being output is input from the main control unit while the drive control signal indicating that the motor is being driven to the motor drive unit, outputs a drive control signal indicating that the motor is being driven not to be driven to the motor drive unit.

[0009] In addition, a paper transport device according to one aspect of the present invention includes a motor control device according to the above-described one aspect of the present invention, the motor, and a transport unit that transports paper using the motor, wherein the engine control unit of the motor control device determines that a jam has occurred in the transport unit and stops outputting the clock signal, the clock signal is input from the engine control unit to the relay unit of the motor control device, and when the input of the clock signal is stopped, the relay unit outputs a drive control signal to the motor drive unit indicating that drive of the motor is disabled. [Effects of the Invention]

[0010] According to the present invention, when the output of the clock signal is interrupted, the control signal indicating that drive is enabled is not continuously output to the motor drive unit, thereby preventing a situation in which the motor drive unit continues to supply current to the motor, causing the motor to continue operating. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram showing the configuration of a motor control device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a circuit diagram showing a relay unit in the motor control device of the present embodiment. [Figure 3] 4 is a timing chart showing the operation of the motor control device of the present embodiment. [Figure 4] In the motor control device of this embodiment, (A) is a timing chart showing the operation when a jam occurs but there is no abnormality in the engine control unit, (B) is a timing chart showing the operation when a jam occurs but there is an abnormality in the engine control unit, and (C) is a timing chart showing the operation when there is an abnormality in the engine control unit but there is no jam. [Figure 5] 3 is a flowchart showing a control procedure of the motor control device of the present embodiment. [Figure 6] In the comparative examples, (A) is a timing chart showing the operation when there is no abnormality in the engine control unit and no jam, (B) is a timing chart showing the operation when there is no abnormality in the engine control unit and a jam occurs, (C) is a timing chart showing the operation when there is an abnormality in the engine control unit and a jam occurs, and (D) is a timing chart showing the operation when there is an abnormality in the engine control unit and no jam. DETAILED DESCRIPTION OF THE INVENTION

[0012] A motor control device according to one embodiment of the present invention will be described below with reference to the drawings. Fig. 1 is a block diagram showing the configuration of a motor control device according to one embodiment of the present invention. The motor control device of this embodiment is applied to, for example, an image forming apparatus that forms an image on recording paper, and controls a motor that transports the recording paper.

[0013] As shown in FIG. 1, the motor control device 1 includes a main control unit 2, an engine control unit 3, a relay unit 4, and a motor drive unit 5.

[0014] The engine control unit 3 is composed of, for example, a CPU (Central Processing Unit), outputs a CPU clock signal CLK1 to the main control unit 2 and relay unit 4, and also performs data communication with the motor drive unit 5 regarding drive control of a motor (not shown).

[0015] The main control unit 2 is composed of, for example, an ASIC (Application Specific Integrated Circuit), and sets the judgment signal SC to a high level before the motor starts transporting the recording paper, inputs the CPU clock signal CLK1 from the engine control unit 3, and when the input of the CPU clock signal CLK1 from the engine control unit 3 stops, outputs a low-level judgment signal SC to the relay unit 4, indicating that the CPU clock signal CLK1 is not being output.

[0016] The relay unit 4 is composed of an electric circuit, and when it receives the CPU clock signal CLK1 from the engine control unit 3, it generates a relay clock signal CLK2 synchronized with the CPU clock signal CLK1 and outputs it to the motor drive unit 5. The relay unit 4 also receives the determination signal SC from the main control unit 2, and when the determination signal SC is high level, indicating that the CPU clock signal CLK2 is being output, it outputs the relay clock signal CLK2 and a high level drive control signal ENA indicating that the motor drive is enabled to the motor drive unit 5, and when the determination signal SC is low level, indicating that the CPU clock signal CLK2 is not being output, it outputs a low level drive control signal ENA indicating that the motor drive is disabled to the motor drive unit 5.

[0017] The motor driving unit 5 is a driving circuit that controls the driving of the motor based on the relay clock signal CLK2 and the drive control signal ENA when it receives the relay clock signal CLK2 and a high-level drive control signal ENA indicating that the motor is enabled to drive from the relay unit 4, and stops the motor when it receives a low-level drive control signal ENA indicating that the motor is disabled to drive from the relay unit 4.

[0018] On the other hand, when a sensor (not shown) of the image forming apparatus detects a jam in the conveyance of the recording paper, the engine control unit 3 stops outputting the CPU clock signal CLK1.

[0019] When the input of the CPU clock signal CLK1 from the engine control unit 3 stops, the relay unit 4 does not output the relay clock signal CLK2 to the motor drive unit 5, but instead outputs a low-level drive control signal ENA to the motor drive unit 5, indicating that motor drive is disabled.

[0020] When the relay clock signal CLK2 is not input to the motor driving unit 5 and a low-level drive control signal ENA indicating that the motor drive is disabled is input from the relay unit 4, the motor driving unit 5 stops the motor.

[0021] Furthermore, if an abnormality occurs in the engine control unit 3, the output of the CPU clock signal CLK1 from the engine control unit 3 is stopped. The main control unit 2 outputs a low-level determination signal SC indicating that the CPU clock signal CLK2 is not being output. The relay unit 4 receives the low-level determination signal SC and outputs a low-level drive control signal ENA indicating that the motor drive is disabled to the motor drive unit 5.

[0022] The motor driving unit 5 receives the low level driving control signal ENA, which indicates that the driving of the motor is disabled, from the relay unit 4, and stops the motor at this time.

[0023] 2 is a circuit diagram showing the relay unit 4. As shown in FIG. The circuit includes an NPN transistor 11, a PNP transistor 12, a PNP transistor 13, an NPN transistor 14, and a PNP transistor 15.

[0024] The emitter of PNP transistor 13 and line 16 are connected to a terminal of DC constant voltage V2 via resistor R4. Line 16 is drawn from between the emitter of PNP transistor 13 and resistor R4 and connected to motor driver 5, and relay clock signal CLK2 is output from line 16 to motor driver 5. CPU clock signal CLK1 from engine control unit 3 is applied to the base of PNP transistor 13. When CPU clock signal CLK1 goes high, no current flows through the emitter of PNP transistor 13, turning PNP transistor 12 off and causing relay clock signal CLK2 on line 16 to go high. When CPU clock signal CLK1 goes low, current flows through the emitter of PNP transistor 13, turning PNP transistor 13 on and causing relay clock signal CLK2 on line 16 to go low. As a result, relay clock signal CLK2 synchronized with CPU clock signal CLK1 is output to motor driver 5 via line 16.

[0025] A DC constant voltage V1 is applied to the emitter of PNP transistor 12, and the base of PNP transistor 12 is connected to NPN transistor 11 via resistor R1. In addition, a determination signal SC from main control unit 2 is applied to the base of NPN transistor 11. When determination signal SC goes high, NPN transistor 11 is turned on, current flows to the emitter of PNP transistor 12, and PNP transistor 12 is turned on. When determination signal SC goes low, NPN transistor 11 is turned off, no current flows to the emitter of PNP transistor 12, and PNP transistor 12 is turned off.

[0026] The collector of PNP transistor 12 is connected to NPN transistor 14 via resistor element R2, and to PNP transistor 15 via resistor element R3. Line 17 is drawn from between resistor element R3 and the emitter of PNP transistor 15 and connected to motor drive unit 5, and a drive control signal ENA is output to motor drive unit 5 via line 17.

[0027] The CPU clock signal CLK1 is applied to the base of the NPN transistor 14. When the determination signal SC is high, the NPN transistor 11 is on, and the PNP transistor 12 is on as described above, the terminal of the DC constant voltage V1 is connected to the resistor element R2 through the PNP transistor 12. When the CPU clock signal CLK1 goes high in this state, the NPN transistor 14 turns on, causing current to flow from the DC constant voltage V1 through the resistor element R2 and the NPN transistor 14 to the capacitor C1, charging the capacitor C1. When the CPU clock signal CLK1 goes low, the NPN transistor 14 turns off, causing the capacitor C1 to discharge through the resistor element R5. Because the capacitance of the capacitor C1 and the resistance of the resistor element R5 are appropriately set, when the NPN transistor 14 is repeatedly turned on and off in synchronization with the CPU clock signal CLK1, the amount of charge of the capacitor C1 becomes greater than the amount of discharge, increasing the amount of charge on the capacitor C1.

[0028] Similarly, when the determination signal SC is at a high level, the NPN transistor 11 is on, and the PNP transistor 12 is on, the terminal of the DC constant voltage V1 is connected to the resistance element R3 through the PNP transistor 12, so that before the capacitor C1 is charged, current flows from the emitter of the PNP transistor 15 to the capacitor C1, the PNP transistor 15 is turned on, and the drive control signal ENA on the line 17 goes to a low level.

[0029] As described above, the NPN transistor 14 is repeatedly turned on and off in synchronization with the CPU clock signal CLK1, and as the charge amount of the capacitor C1 increases, current stops flowing to the emitter of the PNP transistor 15, the PNP transistor 15 turns off, and the drive control signal ENA on line 17 goes high.

[0030] Furthermore, when the CPU clock signal CLK1 is no longer input to the NPN transistor 14, the NPN transistor 14 remains off, the capacitor C1 is discharged, current flows from the emitter of the PNP transistor 15 to the capacitor C1, the PNP transistor 15 turns on, and the drive control signal ENA on the line 17 goes low.

[0031] On the other hand, when the determination signal SC is at a low level, the NPN transistor 11 is off, and the PNP transistor 12 is off as described above, the terminal of the DC constant voltage V1 is not connected to the resistor elements R2 and R3 through the PNP transistor 12, and the terminal of the DC constant voltage V1 is disconnected from the NPN transistor 14 and the PNP transistor 15. In this state, even if the NPN transistor 14 is turned on, no current flows from the terminal of the DC constant voltage V1 through the resistor element R2 and the NPN transistor 14 to the capacitor C1, discharging the capacitor C1. Also, no current flows to the emitter of the PNP transistor 15, turning the PNP transistor 15 off. Since the line 17 is grounded through the resistor element R6, the drive control signal ENA on the line 17 goes to a low level.

[0032] Therefore, relay unit 4 receives CPU clock signal CLK1 from engine control unit 3 and outputs relay clock signal CLK2 synchronized with CPU clock signal CLK1 to motor drive unit 5 via line 16. It also receives determination signal SC from main control unit 2, and when determination signal SC is high, it outputs a high-level drive control signal ENA indicating drive enable to motor drive unit 5 via line 17 in response to the input of CPU clock signal CLK1, and outputs a low-level drive control signal ENA indicating drive disable to motor drive unit 5 via line 17 in response to the stop of input of CPU clock signal CLK1. Furthermore, when determination signal SC is low, it outputs a low-level drive control signal ENA indicating drive disable to motor drive unit 5 via line 17.

[0033] Next, the operation of the motor control device 1 for transporting the recording paper on which an image is formed by a motor in the image forming apparatus will be described with reference to the timing chart shown in FIG.

[0034] At time t0, before the motor starts transporting the recording paper, the DC constant voltage V1 of the relay unit 4 is turned on, and then at time t1, the main control unit 2 sets the judgment signal SC to a high level, and then at time t2, the DC constant voltage V2 of the relay unit 4 is turned on.

[0035] The engine control unit 3 starts outputting the CPU clock signal CLK1 at time t3, just before the motor starts transporting the recording paper. The relay unit 4 outputs the relay clock signal CLK2, which is synchronized with the CPU clock signal CLK1, to the motor drive unit 5 via line 16.

[0036] At time t1, the determination signal SC goes high, turning on the NPN transistor 11 and PNP transistor 12 of the relay unit 4, and from time t3 onwards, the NPN transistor 14 of the relay unit 4 is repeatedly turned on and off, starting to charge the capacitor C1.

[0037] At time t4 when the CPU clock signal CLK1 and the relay clock signal CLK2 have stabilized, the charge amount of capacitor C1 in relay unit 4 increases, current stops flowing to the emitter of PNP transistor 15, PNP transistor 15 turns off, and a high-level drive control signal ENA indicating drive enable is output to motor drive unit 5 via line 17. At this time, as the current flowing to the emitter of PNP transistor 15 decreases, the level of the drive control signal ENA on line 17 gradually increases.

[0038] The motor drive unit 5 receives the relay clock signal CLK2 from time t3, and receives a high-level drive control signal ENA indicating that drive is enabled from time t4. Based on the relay clock signal CLK2 and the high-level drive control signal ENA, the motor drive unit 5 starts controlling the drive of the motor, causing the motor to start transporting the recording paper.

[0039] At time t5, when the motor finishes transporting the recording paper, the engine control unit 3 stops outputting the CPU clock signal CLK1. The relay unit 4 stops outputting the relay clock signal CLK2 to the motor drive unit 5. When the output of the CPU clock signal CLK1 stops, the NPN transistor 14 of the relay unit 4 turns off, the capacitor C1 discharges, the PNP transistor 15 turns on, and the drive control signal ENA on line 17 goes low.

[0040] From time t5, the motor driver 5 stops inputting the relay clock signal CLK2 and inputs a low level drive control signal ENA indicating that drive is disabled, thereby ending motor drive control and terminating the transport of the recording paper by the motor.

[0041] Thereafter, the motor drive control is performed in the same manner each time a recording sheet is transported.

[0042] Incidentally, when the motor is transporting recording paper, if an abnormality occurs in the engine control unit 3 and the output of the CPU clock signal CLK1 from the engine control unit 3 is interrupted, but the drive control signal ENA indicating that the motor is enabled continues to be input to the motor drive unit 5, current may continue to flow to the motor, causing the motor to continue operating. Also, a recording paper jam may occur.

[0043] However, in this embodiment, even if an abnormality or jam occurs in the engine control unit 3, the motor drive control by the motor drive unit 5 is stopped.

[0044] FIG. 4A is a timing chart showing the operation of the motor control device 1 when a jam occurs and there is no abnormality in the engine control unit 3.

[0045] At time t1, the main control unit 2 sets the judgment signal SC to high level, and at time t3, just before the motor starts to transport the recording paper, the engine control unit 3 starts outputting the CPU clock signal CLK1. The relay unit 4 outputs the relay clock signal CLK2, which is synchronized with the CPU clock signal CLK1, to the motor drive unit 5.

[0046] At time t4 when the CPU clock signal CLK1 and the relay clock signal CLK2 have stabilized, the charge amount of the capacitor C1 in the relay unit 4 increases, no current flows to the emitter of the PNP transistor 15, the PNP transistor 15 turns off, and a high-level drive control signal ENA indicating that drive is enabled is output to the motor drive unit 5 via line 17.

[0047] The motor driver 5 receives the relay clock signal CLK2 from time t3, and when the high level drive control signal ENA is received from time t4, it starts controlling the drive of the motor, causing the motor to start transporting the recording paper.

[0048] At time t11, before time t5 when the recording paper transport period ends, if a sensor (not shown) detects a recording paper jam, the engine control unit 3 stops outputting the CPU clock signal CLK1. The relay unit 4 stops outputting the relay clock signal CLK2 to the motor drive unit 5. From time t11, the capacitor C1 of the relay unit 4 is discharged without being charged, current flows to the emitter of the PNP transistor 15, turning the PNP transistor 15 on, and the drive control signal ENA on line 17 goes low, indicating that drive is disabled.

[0049] From time t11 onwards, the motor driver 5 stops inputting the relay clock signal CLK2 and inputs the low level drive control signal ENA, thereby ending the drive control of the motor and suspending the transport of the recording paper by the motor.

[0050] When a jam occurs, the engine control unit 3 stops outputting the CPU clock signal CLK1, the capacitor C1 in the relay unit 4 is discharged, the PNP transistor 15 is turned on, and the drive control signal ENA on line 17 goes low, indicating that drive is disabled. The motor drive unit 5 does not input the relay clock signal CLK2, but instead inputs a low-level drive control signal ENA, thereby terminating motor drive control and halting the motor's paper transport. This prevents the motor from continuing to operate.

[0051] FIG. 4B is a timing chart showing the operation of the motor control device 1 when an abnormality occurs in the engine control unit 3 and a jam occurs.

[0052] At time t1, the main control unit 2 sets the judgment signal SC to high level, and at time t3, just before the motor starts to transport the recording paper, the engine control unit 3 starts outputting the CPU clock signal CLK1. The relay unit 4 outputs the relay clock signal CLK2, which is synchronized with the CPU clock signal CLK1, to the motor drive unit 5.

[0053] At time t4 when the CPU clock signal CLK1 and the relay clock signal CLK2 have stabilized, the charge level of the capacitor C1 in the relay unit 4 increases, the PNP transistor 15 turns off, and a high-level drive control signal ENA indicating that drive is enabled is output to the motor drive unit 5 via line 17.

[0054] The motor driver 5 receives the relay clock signal CLK2 from time t3, and receives the high level drive control signal ENA from time t4, and starts controlling the drive of the motor, causing the motor to start transporting the recording paper.

[0055] At time t21, before time t5 when the recording paper transport period ends, an abnormality occurs in engine control unit 3, and the output of CPU clock signal CLK1 from engine control unit 3 stops. At this time, because there is an abnormality in engine control unit 3, CPU clock signal CLK1 is maintained at low or high level, and PNP transistor 15 is turned on or off. Relay clock signal CLK2 output from relay unit 4 is also maintained at low or high level.

[0056] Furthermore, at time t22, a sensor (not shown) detects a jam of recording paper, but since there is an abnormality in the engine control unit 3, the CPU clock signal CLK1 continues to be maintained at a low level or a high level even after time t22, and the PNP transistor 15 is turned on or off.

[0057] When the input of the CPU clock signal CLK1 from the engine control unit 3 stops at time t21, the main control unit 2 sets the determination signal SC to a low level at time t23. When the determination signal SC is low, the NPN transistor 11 is off, and the PNP transistor 12 is off as described above, there is a disconnection between the terminal of the DC constant voltage V1 and the NPN transistor 14 and the PNP transistor 15. In this state, no current flows from the terminal of the DC constant voltage V1 through the resistor element R3 and the NPN transistor 14 to the capacitor C1, so that the capacitor C1 is discharged without being charged. Also, no current flows to the emitter of the PNP transistor 15, so that the PNP transistor 15 changes from on or off to off. Since the line 17 is grounded through the resistor element R5, the drive control signal ENA on the line 17 goes to a low level indicating that drive is disabled.

[0058] At time t23, a low level drive control signal ENA is input to the motor drive unit 5, at which point the motor drive unit 5 ends the drive control of the motor and stops the transport of the recording paper by the motor.

[0059] When an abnormality occurs in the engine control unit 3 and a jam occurs, the CPU clock signal CLK1 output from the engine control unit 3 is maintained at a low or high level, and the PNP transistor 15 is turned on or off. Since the input of the CPU clock signal CLK1 has stopped, the main control unit 2 sets the determination signal SC to a low level. This disconnects the DC constant voltage V1 terminal from the NPN transistor 14 and the PNP transistor 15, preventing current from flowing through the emitter of the PNP transistor 15. The PNP transistor 15 then changes from on or off to off. Since line 17 is grounded through resistor R5, the drive control signal ENA on line 17 goes low, indicating that drive is disabled. The motor drive unit 5 inputs a low-level drive control signal ENA to terminate motor drive control and halt paper transport by the motor. This prevents the motor from overheating.

[0060] FIG. 4C is a timing chart showing the operation of the motor control device 1 when an abnormality occurs in the engine control unit 3 but no jam occurs.

[0061] At time t1, the main control unit 2 sets the judgment signal SC to high level, and at time t3, just before the motor starts to transport the recording paper, the engine control unit 3 starts outputting the CPU clock signal CLK1. The relay unit 4 outputs the relay clock signal CLK2, which is synchronized with the CPU clock signal CLK1, to the motor drive unit 5.

[0062] At time t4 when the CPU clock signal CLK1 and the relay clock signal CLK2 have stabilized, the charge level of the capacitor C1 in the relay unit 4 increases, the PNP transistor 15 turns off, and a high-level drive control signal ENA indicating that drive is enabled is output to the motor drive unit 5 via line 17.

[0063] When the relay clock signal CLK2 is input to the motor drive unit 5 from time t3 and the high-level drive control signal ENA is input from time t4, the motor drive unit 5 starts controlling the drive of the motor and causes the motor to start transporting the recording paper.

[0064] At time t31, before time t5 when the recording paper transport period ends, an abnormality occurs in engine control unit 3, and the output of CPU clock signal CLK1 from engine control unit 3 stops. At this time, because there is an abnormality in engine control unit 3, CPU clock signal CLK1 is maintained at low or high level, and PNP transistor 15 is turned on or off. Relay clock signal CLK2 output from relay unit 4 is also maintained at low or high level.

[0065] Without a sensor (not shown) detecting a jam of recording paper, the CPU clock signal CLK1 continues to be maintained at low or high level, and the PNP transistor 15 is turned on or off.

[0066] When the input of the CPU clock signal CLK1 from the engine control unit 3 stops at time t31, the main control unit 2 sets the determination signal SC to a low level at time t32. When the determination signal SC is low, the NPN transistor 11 is off, and the PNP transistor 12 is off as described above, there is a disconnection between the terminal of the DC constant voltage V1 and the NPN transistor 14 and the PNP transistor 15. In this state, no current flows from the terminal of the DC constant voltage V1 through the resistor element R3 and the NPN transistor 14 to the capacitor C1, so that the capacitor C1 is discharged without being charged. Also, no current flows to the emitter of the PNP transistor 15, so that the PNP transistor 15 changes from on or off to off. Since the line 17 is grounded through the resistor element R5, the drive control signal ENA on the line 17 goes to a low level indicating that drive is disabled.

[0067] When a low level drive control signal ENA is input to the motor drive unit 5 at time t32, the motor drive unit 5 ends the drive control of the motor and stops the transport of the recording paper by the motor.

[0068] When an abnormality in the engine control unit 3 occurs but no jam has occurred, the CPU clock signal CLK1 output from the engine control unit 3 remains low or high, and the PNP transistor 15 is turned on or off. Since the input of the CPU clock signal CLK1 has stopped, the main control unit 2 sets the determination signal SC to low. This disconnects the DC constant voltage V1 terminal from the NPN transistor 14 and the PNP transistor 15, preventing current from flowing through the emitter of the PNP transistor 15. The PNP transistor 15 then changes from on or off to off. Since line 17 is grounded through resistor R5, the drive control signal ENA on line 17 goes low, indicating that drive is disabled. The motor drive unit 5 inputs the low-level drive control signal ENA to terminate motor drive control and halt the motor's paper feed. This prevents the motor from continuing to operate.

[0069] Next, the motor control procedure performed by the motor control device 1 will be described with reference to the flowchart shown in FIG.

[0070] At time t0 before the motor starts transporting the recording paper, the DC constant voltage V1 is turned on (S101), and then at time t1 the main control unit 2 sets the judgment signal SC to a high level (S102), and then at time t2 the DC constant voltage V2 is turned on (S103).

[0071] The engine control unit 3 starts outputting the CPU clock signal CLK1 at time t31 just before the motor starts transporting the recording paper (S104). The relay unit 4 outputs the relay clock signal CLK2, which is synchronized with the CPU clock signal CLK1, to the motor drive unit 5 via line 16.

[0072] At time t4 when the CPU clock signal CLK1 and the relay clock signal CLK2 have stabilized, the charge amount of the capacitor C1 in the relay unit 4 increases, current stops flowing to the emitter of the PNP transistor 15, the PNP transistor 15 turns off, and a high-level drive control signal ENA indicating that drive is enabled is output to the motor drive unit 5 via line 17 (S105, S106).

[0073] When a high-level drive control signal ENA is input to the motor drive unit 5 from time t2 and a relay clock signal CLK2 is input from time t3, the motor drive unit 5 starts controlling the drive of the motor and causes the motor to start transporting the recording paper (S107).

[0074] If the engine control unit 3 is outputting the CPU clock signal CLK1 (S108 "Yes"), it determines whether a recording paper jam has been detected by a sensor (not shown) (S109). If a recording paper jam has not been detected (S109 "No"), the engine control unit 3 determines whether the motor has finished transporting the recording paper (S110), and if the transport of the recording paper has not finished (S110 "No"), it returns to S109.

[0075] When the motor finishes transporting the recording paper (S110 "Yes"), the engine control unit 3 stops outputting the CPU clock signal CLK1 at time t5, when the recording paper transport period ends, and ends the control procedure shown in Figure 5. When the output of the CPU clock signal CLK1 is stopped, the output of the relay clock signal CLK2 from the relay unit 4 is stopped, and the CPU clock signal CLK1 no longer charges the capacitor C1 of the relay unit 4, discharging the capacitor C1, turning on the PNP transistor 15, and the drive control signal ENA on line 17 goes low, indicating that drive is disabled.

[0076] When the relay clock signal CLK2 is no longer input to the motor driver 5 from time t5 and a low level drive control signal ENA is input, the motor driver 5 ends the drive control of the motor and stops the transport of the recording paper.

[0077] Furthermore, when a recording paper jam is detected (S109 "Yes"), the engine control unit 3 stops outputting the CPU clock signal CLK1. When the output of the CPU clock signal CLK1 is stopped, the output of the relay clock signal CLK2 from the relay unit 4 is stopped, and the capacitor C1 of the relay unit 4 is not charged by the CPU clock signal CLK1, so that the capacitor C1 is discharged, the PNP transistor 15 is turned on, and the drive control signal ENA on the line 17 goes low, indicating that drive is disabled (S111).

[0078] When the relay clock signal CLK2 is not input to the motor drive unit 5 and a low-level drive control signal ENA is input, the motor drive unit 5 ends the drive control of the motor and interrupts the transport of the recording paper by the motor.

[0079] At this time, the main control unit 2 causes, for example, a display unit (not shown) to display the occurrence of a jam (S112). The user looks at the display and resolves the jam. The engine control unit 3 determines whether the detection signal from the sensor indicates the occurrence of a jam (S113 "No"), and when the engine control unit 3 determines that the detection signal from the sensor does not indicate the occurrence of a jam (S113 "Yes"), the process from S109 is repeated.

[0080] Furthermore, if an abnormality occurs in the engine control unit 3 and there is no output of the CPU clock signal CLK1 from the engine control unit 3 (S108 "No"), the main control unit 2 determines that an abnormality has occurred in the engine control unit 3 when the input of the CPU clock signal CLK1 is stopped (S108 "No"), stops the power supply to the engine control unit 3, and sets the determination signal SC to low level (S115). When the determination signal SC is low level, the NPN transistor 11 is off, and the PNP transistor 12 is off as described above, the terminal of the DC constant voltage V1 is disconnected from the NPN transistor 14 and the PNP transistor 15. In this state, no current flows from the terminal of the DC constant voltage V1 through the resistor element R3 and the NPN transistor 14 to the capacitor C1, so the capacitor C1 is discharged without being charged, and no current flows to the emitter of the PNP transistor 15, so the PNP transistor 15 is turned off and the line 17 is grounded through the resistor element R5, so the drive control signal ENA on the line 17 goes to a low level indicating that drive is disabled (S116).

[0081] The motor drive unit 5 receives a low level drive control signal ENA, ends the drive control of the motor, and stops the transport of the recording paper by the motor.

[0082] The main control unit 2 displays, for example, the occurrence of an abnormality in the engine control unit 3 on a display unit (not shown) (S117). After this, the control procedure shown in Fig. 5 ends. The user sees the display and contacts, for example, a service technician.

[0083] As shown in the timing chart of FIG. 4(B), when an abnormality occurs in the engine control unit 3 and a jam occurs, the processes of S114 to S117 are performed. <Comparative Example>

[0084] 6(A) to 6(D) are timing charts showing the operation of a motor control device not according to this embodiment. This motor control device does not have a relay circuit such as relay unit 4, and controls the motor drive unit only by the engine control unit. In this motor control device, the engine control unit outputs a clock signal CLK and a drive control signal ENA to the motor drive unit.

[0085] FIG. 6A is a timing chart showing the operation of the motor control device when there is no abnormality in the engine control unit and no jam occurs.

[0086] At time t3, immediately before the motor starts to transport the recording paper, the engine control unit starts outputting the CPU clock signal CLK to the motor drive unit.

[0087] At time t4 when the CPU clock signal CLK stabilizes, the engine control unit outputs a high-level drive control signal ENA, which indicates that drive is enabled, to the motor drive unit.

[0088] The CPU clock signal CLK is input to the motor drive unit from time t3, and when a high-level drive control signal ENA is input from time t4, the motor drive unit starts controlling the drive of the motor, causing the motor to start transporting the recording paper.

[0089] At time t5 when the recording paper transport period ends, the engine control unit stops outputting the CPU clock signal CLK and outputs a low level drive control signal ENA indicating drive invalidity to the motor drive unit.

[0090] When the CPU clock signal CLK is not input to the motor drive unit and a low-level drive control signal ENA is input, the motor drive unit ends the drive control of the motor and stops the motor from transporting the recording paper.

[0091] In this way, when there is no abnormality in the engine control unit and no jam occurs, the conveyance of the recording paper by the motor starts and ends normally.

[0092] FIG. 6B is a timing chart showing the operation of the motor control device when a jam occurs and there is no abnormality in the engine control unit.

[0093] At time t3, the engine control unit starts outputting the CPU clock signal CLK to the motor drive unit.

[0094] At time t4 when the CPU clock signal CLK stabilizes, the engine control unit outputs a high-level drive control signal ENA, which indicates that drive is enabled, to the motor drive unit.

[0095] When the CPU clock signal CLK and a high-level drive control signal ENA are input to the motor drive unit, the motor drive unit starts controlling the drive of the motor, causing the motor to start transporting the recording paper.

[0096] When a recording paper jam is detected by a sensor (not shown) at time t41, before time t5 when the recording paper transport period ends, the engine control unit stops outputting the CPU clock signal CLK and outputs a low-level drive control signal ENA to the motor drive unit, indicating that drive is disabled.

[0097] When the CPU clock signal CLK is not input to the motor drive unit and a low-level drive control signal ENA is input, the motor drive unit ends the drive control of the motor and stops the motor from transporting the recording paper.

[0098] In this way, when a jam occurs even though there is no abnormality in the engine control unit, the engine control unit stops outputting the CPU clock signal CLK and outputs a low-level drive control signal ENA to the motor drive unit, which stops the motor from transporting the recording paper and prevents the motor from continuing to operate.

[0099] FIG. 6C is a timing chart showing the operation of the motor control device 1 when a jam occurs due to an abnormality in the engine control unit.

[0100] At time t3, the engine control unit 3 starts outputting the CPU clock signal CLK to the motor drive unit 5.

[0101] At time t4 when the CPU clock signal CLK stabilizes, the engine control unit outputs a high-level drive control signal ENA, which indicates that drive is enabled, to the motor drive unit.

[0102] When the CPU clock signal CLK and a high-level drive control signal ENA are input to the motor drive unit, the motor drive unit starts controlling the drive of the motor, causing the motor to start transporting the recording paper.

[0103] At time t51, before time t5 when the recording paper transport period ends, an abnormality occurs in the engine control unit, and the output of the CPU clock signal CLK from the engine control unit stops, but the high-level drive control signal ENA continues to be output from the engine control unit to the motor drive unit.

[0104] Although the CPU clock signal CLK is not input to the motor driver, the high-level drive control signal ENA continues to be input, so the motor driver continues to pass current to the motor, causing the motor to continue operating.

[0105] In this way, when a jam occurs due to an abnormality in the engine control unit, even if the output of the CPU clock signal CLK from the engine control unit is stopped, the engine control unit continues to output a high-level drive control signal ENA, so current continues to flow to the motor and the motor continues to operate.

[0106] FIG. 6D is a timing chart showing the operation of the motor control device when an abnormality occurs in the engine control unit but no jam occurs.

[0107] At time t3, the engine control unit starts outputting the CPU clock signal CLK to the motor drive unit.

[0108] At time t4 when the CPU clock signal CLK stabilizes, the engine control unit outputs a high-level drive control signal ENA, which indicates that drive is enabled, to the motor drive unit.

[0109] When the CPU clock signal CLK and a high-level drive control signal ENA are input to the motor drive unit, the motor drive unit starts controlling the drive of the motor, causing the motor to start transporting the recording paper.

[0110] At time t61, before time t5 when the recording paper transport period ends, an abnormality occurs in the engine control unit, and the output of the CPU clock signal CLK from the engine control unit stops. A high-level drive control signal ENA continues to be output from the engine control unit to the motor drive unit 5, without a recording paper jam being detected by a sensor (not shown).

[0111] Although the CPU clock signal CLK is not input to the motor driver, the high-level drive control signal ENA continues to be input, so the motor driver continues to pass current to the motor, causing the motor to continue operating.

[0112] In this way, when there is an abnormality in the engine control unit but no jam occurs, even if the output of the CPU clock signal CLK from the engine control unit stops, the engine control unit continues to output a high-level drive control signal ENA, so current continues to flow to the motor and the motor continues to operate.

[0113] In the above embodiment, the motor control device of the present invention is applied to a motor that transports recording paper in an image forming device, but it may also be applied to an image reading device that reads an image of a document to control a motor that transports the document.

[0114] Furthermore, the configurations and processes of the above-described embodiment explained using FIGS. 1 to 5 are merely examples of the present invention, and the present invention is not limited to these configurations and processes. [Explanation of symbols]

[0115] 1 Motor control device 2 Main control unit 3 Engine control unit 4 Relay section 5 Motor drive unit

Claims

1. a motor driving unit that receives a clock signal for driving the motor and drives the motor; an engine control unit that outputs the clock signal; a main control unit that receives the clock signal from the engine control unit and, when the input of the clock signal stops, outputs a determination signal indicating that the clock signal is not being output; a relay unit that outputs a drive control signal indicating whether the motor is enabled or disabled to the motor drive unit, and when a determination signal indicating that the clock signal is not being output is input from the main control unit while the drive control signal indicating the motor is enabled to the motor drive unit, outputs a drive control signal indicating that the motor is disabled to the motor drive unit.

2. the engine control unit determines the occurrence of a preset error and stops outputting the clock signal; The relay unit receives the clock signal from the engine control unit, The motor control device according to claim 1 , wherein the relay unit outputs a drive control signal indicating that driving of the motor is disabled to the motor drive unit when input of the clock signal is stopped.

3. The relay unit receives the clock signal from the engine control unit, The motor control device according to claim 1 , wherein the relay unit relays the clock signal and outputs it to the motor drive unit.

4. The motor control device according to claim 1 ; the motor; a conveying unit that conveys paper by the motor, the engine control unit of the motor control device determines that a jam has occurred in the conveyance unit and stops outputting the clock signal; the clock signal is input to the relay unit of the motor control device from the engine control unit, The relay unit outputs a drive control signal indicating that driving of the motor is disabled to the motor drive unit when the input of the clock signal is stopped.

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