Grid-side current harmonic suppression method and device for motor driving system without electrolytic capacitor

Abstract

The invention provides a grid-side current harmonic suppression method and device for a motor driving system without an electrolytic capacitor. The method comprises the following steps: determining first and second bus voltage harmonics based on bus voltage obtained by sampling and inverter switching frequency; correcting the bus voltage according to the first bus voltage harmonic wave and the second bus voltage harmonic wave so as to determine a reconstructed bus voltage; according to the second bus voltage harmonic, the reconstructed bus voltage, an inverter output three-phase duty ratio and a motor three-phase current, first and second network side current harmonic regulation and control voltages are determined based on a self-defined closed-loop controller; and adopting a motor alpha-axis correction voltage and a motor beta-axis correction voltage determined according to the first and second grid-side current harmonic regulation and control voltages to participate in motor SVPWM modulation to output the three-phase duty ratio of an inverter so as to suppress grid-side input current harmonics. According to the method and the device, factors such as motor operation conditions, bus voltage harmonic waves and digital control delay are comprehensively considered, the quality of grid-side input electric energy is improved, and disturbance to machine-side rotating speed and torque is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of current harmonic suppression, and more particularly, to a method and device for suppressing grid-side current harmonics of an electrolytic capacitor-free motor drive system. BACKGROUND

[0002] The electrolytic capacitor-free motor drive system uses a small-capacitance film capacitor instead of an electrolytic capacitor as a bus capacitor, which effectively improves the power density and reliability of the motor drive system and reduces the cost of the drive. However, the reduction of the capacitance of the bus capacitor also leads to an increase in bus voltage fluctuations and a serious coupling of grid-side input and motor-side output energy, making it difficult for the grid-side input current harmonics to meet the IEC61000-3-12 standard.

[0003] Current methods for suppressing grid-side current harmonics of electrolytic capacitor-free motor systems can be divided into hardware and software solutions. The hardware solution absorbs grid-side current harmonics by adding auxiliary circuits to improve the grid-side input power quality. However, this method requires additional power devices, increasing the cost of the drive and system losses. The software control solution changes the duty cycle output of the inverter by designing an inverter control algorithm, which effectively increases the grid-side input impedance of the motor drive system to suppress grid-side input current harmonics. Software control methods can be divided into two categories based on their physical meaning: grid-side current harmonic suppression methods based on virtual impedance remodeling and grid-side current harmonic suppression methods based on inductance current regulation.

[0004] Grid-side current harmonic suppression methods based on virtual impedance remodeling feed the harmonic information in the grid-side input power to the motor current loop output voltage to increase the equivalent input impedance of the motor system, thereby suppressing the grid-side input current harmonics. However, this method is usually open-loop controlled, and it is difficult to maintain optimal control when the motor operating conditions change. Grid-side current harmonic suppression methods based on inductance current regulation use the positive correlation between grid-side input current and inductance current harmonics to design an inductance current harmonic controller to suppress inductance current harmonics and improve grid-side input power quality. However, this control method does not take into account the influence of bus voltage harmonics and digital control delay of the motor control system, making it difficult to achieve optimal control. SUMMARY

[0005] To solve the technical problems of the existing software method for suppressing grid-side current harmonics of electrolytic capacitor-free motor systems, which either uses open-loop control and is difficult to maintain optimal control when the motor operating conditions change, or does not take into account the influence of bus voltage harmonics and digital control delay of the motor control system, making it difficult to achieve optimal control, the present application provides a method and device for suppressing grid-side current harmonics of an electrolytic capacitor-free motor drive system.

[0006] According to an aspect of the present application, the present application provides a method for suppressing grid-side current harmonics of a motor drive system without electrolytic capacitor, comprising:

[0007] determining a first bus voltage harmonic based on the sampled bus voltage;

[0008] acquiring a bus voltage harmonic intermediate variable required for correcting digital control delay according to the frequency of the first bus voltage harmonic and the inverter switching frequency;

[0009] calculating a second bus voltage harmonic required for correcting digital control delay according to the bus voltage harmonic intermediate variable;

[0010] correcting the bus voltage to determine a reconstructed bus voltage according to the first bus voltage harmonic and the second bus voltage harmonic;

[0011] determining a first grid-side current harmonic regulating voltage based on a self-defined closed-loop controller according to the second bus voltage harmonic;

[0012] determining a second grid-side current harmonic regulating voltage based on a self-defined closed-loop controller according to the reconstructed bus voltage, inverter output three-phase duty cycle and motor three-phase current;

[0013] determining an alpha-axis correction voltage and a beta-axis correction voltage of the motor according to the first grid-side current harmonic regulating voltage and the second grid-side current harmonic regulating voltage;

[0014] participating the alpha-axis correction voltage and the beta-axis correction voltage in motor SVPWM modulation to output inverter three-phase duty cycle to suppress grid-side input current harmonics.

[0015] According to another aspect of the present application, the present application provides a device for suppressing grid-side current harmonics of a motor drive system without electrolytic capacitor, comprising:

[0016] a first harmonic module for determining a first bus voltage harmonic based on the sampled bus voltage;

[0017] an intermediate variable module for acquiring a bus voltage harmonic intermediate variable required for correcting digital control delay according to the frequency of the first bus voltage harmonic and the inverter switching frequency;

[0018] a second harmonic module for calculating a second bus voltage harmonic required for correcting digital control delay according to the bus voltage harmonic intermediate variable;

[0019] a first voltage module for correcting the bus voltage to determine a reconstructed bus voltage according to the first bus voltage harmonic and the second bus voltage harmonic;

[0020] a second voltage module configured to determine a first grid-side current harmonic regulation voltage based on a self-defined closed-loop controller according to the second bus voltage harmonic;

[0021] a third voltage module configured to determine a second grid-side current harmonic regulation voltage based on a self-defined closed-loop controller according to the reconstructed bus voltage, inverter output three-phase duty cycle and motor three-phase current;

[0022] a fourth voltage module configured to determine an alpha-axis correction voltage of the motor and a beta-axis correction voltage of the motor according to the first grid-side current harmonic regulation voltage and the second grid-side current harmonic regulation voltage;

[0023] a harmonic suppression module configured to participate in motor SVPWM modulation to output inverter three-phase duty cycle with the alpha-axis correction voltage and the beta-axis correction voltage to suppress grid-side input current harmonic.

[0024] According to still another aspect of the present application, a computer readable storage medium is provided, which stores a computer program, the program being executed by a processor to implement the method according to any one of the above aspects of the present application.

[0025] According to still another aspect of the present application, an electronic device is provided, which comprises: a processor; a memory for storing executable instructions of the processor; and the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method according to any one of the above aspects of the present application.

[0026] The method and device for suppressing grid-side current harmonic of electrolytic capacitor-free motor drive system according to the present application comprises the following steps: determining a first bus voltage harmonic based on a sampled bus voltage; obtaining a bus voltage harmonic intermediate variable required for correcting digital control delay according to the frequency of the first bus voltage harmonic and the switching frequency of an inverter; calculating a second bus voltage harmonic required for correcting digital control delay according to the bus voltage harmonic intermediate variable; correcting the bus voltage to determine a reconstructed bus voltage according to the first bus voltage harmonic and the second bus voltage harmonic; determining a first grid-side current harmonic regulation voltage based on a self-defined closed-loop controller according to the second bus voltage harmonic; determining a second grid-side current harmonic regulation voltage based on a self-defined closed-loop controller according to the reconstructed bus voltage, inverter output three-phase duty cycle and motor three-phase current; determining an alpha-axis correction voltage of the motor and a beta-axis correction voltage of the motor according to the first grid-side current harmonic regulation voltage and the second grid-side current harmonic regulation voltage; participating in motor SVPWM modulation to output inverter three-phase duty cycle with the alpha-axis correction voltage and the beta-axis correction voltage to suppress grid-side input current harmonic. The method and device have the following advantages:

[0027] First, the main harmonic components in the bus voltage are corrected by using the periodic repetition characteristics of the bus voltage harmonics, and the digital control delay of the electrolytic capacitor-free motor drive system is compensated.

[0028] Second, the inductance current harmonic closed-loop control loop is constructed by using the positive correlation characteristics of the inductance current harmonic and the grid-side current harmonic, the grid-side input current harmonics under various motor operating conditions are effectively suppressed, and the robustness of the control strategy to the changes in the motor operating conditions is improved.

[0029] Third, the bus voltage harmonic resonance controller is designed, the bus voltage harmonics of the electrolytic capacitor-free motor drive system are effectively suppressed, and the bus voltage fluctuation is reduced.

[0030] Fourth, compared with the traditional control strategy, the grid-side input power quality is further improved by comprehensively considering the motor operating conditions, bus voltage harmonics, and digital control delay, and the disturbance to the motor-side speed and torque is reduced by designing the control voltage injection angle. BRIEF DESCRIPTION OF DRAWINGS

[0031] The exemplary embodiments of the present application can be more completely understood by reference to the following drawings:

[0032] Figure 1 The flowchart of the electrolytic capacitor-free motor drive system grid-side current harmonic suppression method according to the preferred embodiment of the present application;

[0033] Figure 2 The control block diagram of the electrolytic capacitor-free motor drive system grid-side current harmonic suppression method according to the preferred embodiment of the present application;

[0034] Figure 3 The analysis waveform schematic diagram of the grid-side current, bus voltage, motor operating frequency, and motor torque before applying the control under the condition that the motor operating frequency is 50Hz;

[0035] Figure 4 The analysis waveform schematic diagram of the grid-side current, bus voltage, motor operating frequency, and motor torque under the condition that the conventional inductance current control strategy is applied under the condition that the motor operating frequency is 50Hz;

[0036] Figure 5 The analysis waveform schematic diagram of the grid-side current, bus voltage, motor operating frequency, and motor torque of the electrolytic capacitor-free motor drive system grid-side current harmonic suppression method according to the preferred embodiment of the present application under the condition that the motor operating frequency is 50Hz;

[0037] Figure 6 The structure schematic diagram of the electrolytic capacitor-free motor drive system grid-side current harmonic suppression device according to the preferred embodiment of the present application;

[0038] Figure 7 Structure diagram of an electronic device according to a preferred embodiment of the present application. DETAILED DESCRIPTION

[0039] Reference will now be made to the drawings to describe the preferred embodiments of the present application in detail. The present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. Functional or operational descriptions can be understood as encompassing structural examples and structural or operational descriptions can be understood as encompassing functional examples. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0041] Exemplary method

[0042] Figure 1 Flow chart of a method for suppressing grid-side current harmonics of an electrolytic capacitor-less motor drive system according to a preferred embodiment of the present application. As shown in Figure 1 The method for suppressing grid-side current harmonics of an electrolytic capacitor-less motor drive system according to the preferred embodiment of the present application starts from step 101.

[0043] In step 101, a first bus voltage harmonic is determined based on a sampled bus voltage.

[0044] Preferably, determining the first bus voltage harmonic based on the sampled bus voltage means filtering the obtained frequency domain bus voltage with a band-pass filter to obtain a frequency domain first bus voltage harmonic, and the calculation formula is:

[0045] u dch (s) = u dc (s) * G BPF (s)

[0046] In the formula, u dc (s) is the frequency domain bus voltage, u dch (s) is the frequency domain first bus voltage harmonic, G BPF (s) is the band-pass filter transfer function, and s is the Laplace operator.

[0047] In step 102, according to the frequency of the first bus voltage harmonic and the inverter switching frequency, a bus voltage harmonic intermediate variable required for correcting the digital control delay is obtained.

[0048] Preferably, the intermediate bus voltage harmonic variable required for correcting the digital delay is obtained based on the frequency of the first bus voltage harmonic and the inverter switching frequency, including:

[0049] The harmonics of the first busbar in the frequency domain are u dc (s) is converted into discrete domain first bus voltage harmonic u using bilinear transformation. dc (z), its conversion formula is:

[0050]

[0051] In the formula, T s Let Z be the sampling period, and Z be the Z-transform operator.

[0052] The proportional value N is calculated based on the frequency of the first bus voltage harmonics and the inverter switching frequency. The calculation formula is as follows:

[0053]

[0054] In the formula, f h f is the frequency of the harmonic of the first bus voltage. s is the inverter switching frequency, and [] represents the integer operation;

[0055] The intermediate variable of the bus voltage harmonics required for correcting the digital delay is calculated based on the first bus voltage harmonic in the discrete domain and the aforementioned proportional value. The calculation formula is as follows:

[0056] u dchrel (z)=u dch (z) * Z -N+1

[0057] u dchre2 (z)=u dch (z) * Z -N+2

[0058] In the formula, u dchre1 (z) and u dchre2 (z) represents the intermediate variable of the discrete-domain bus voltage harmonics required to correct the digital delay.

[0059] In step 103, the second bus voltage harmonic required to correct the digital control delay is calculated based on the intermediate variable of the bus voltage harmonic.

[0060] Preferably, the second bus voltage harmonic required for correcting the digital control delay is calculated based on the intermediate variable of the bus voltage harmonic, and the calculation formula is as follows:

[0061]

[0062] wherein u dchav (z) is the discrete-domain second bus voltage harmonic required for correcting the digital control delay.

[0063] In step 104, the bus voltage is corrected according to the first bus voltage harmonic and the second bus voltage harmonic to determine a reconstructed bus voltage.

[0064] Preferably, correcting the bus voltage according to the first bus voltage harmonic and the second bus voltage harmonic to determine a reconstructed bus voltage comprises:

[0065] performing an inverse Z-transform on the discrete-domain second bus voltage harmonic u dchav (z) to obtain a frequency-domain second bus voltage harmonic u dchav (s).

[0066] correcting the frequency-domain bus voltage according to the frequency-domain first bus voltage harmonic and the frequency-domain second bus voltage harmonic to determine a frequency-domain reconstructed bus voltage, which is calculated by the formula:

[0067] u dcre (s) = u dc (s) - u dch (s) + u dchav (s).

[0068] wherein u dcre (s) is the frequency-domain reconstructed bus voltage.

[0069] In step 105, a first grid-side current harmonic regulating voltage is determined based on a custom closed-loop controller according to the second bus voltage harmonic.

[0070] Preferably, determining the first grid-side current harmonic regulating voltage based on the custom closed-loop controller according to the second bus voltage harmonic comprises:

[0071] setting a given reference value of the frequency-domain first bus voltage harmonic u dchref (s) to 0, and performing a difference operation between the given reference value u dchref (s) and a frequency-domain second bus voltage harmonic u dchav (s) to obtain a difference value as an input of the custom closed-loop controller, and then outputting a frequency-domain first grid-side current harmonic regulating voltage u dccom (s) by the custom closed-loop controller.

[0072] In step 106, a second grid-side current harmonic regulating voltage is determined based on a custom closed-loop controller according to the reconstructed bus voltage, an inverter output three-phase duty cycle, and a motor three-phase current.

[0073] Preferably, the second grid-side current harmonic regulation voltage is determined based on a self-defined closed-loop controller according to the reconstructed bus voltage, the inverter output three-phase duty ratio and the motor three-phase current, comprising:

[0074] The inductance current output by the grid-side three-phase uncontrolled rectifier bridge is calculated according to the reconstructed bus voltage, the inverter output three-phase duty ratio and the motor three-phase current;

[0075] The second grid-side current harmonic regulation voltage is determined based on a self-defined closed-loop controller according to the main harmonic component of the inductance current.

[0076] Preferably, the inductance current output by the grid-side three-phase uncontrolled rectifier bridge is calculated according to the reconstructed bus voltage, the inverter output three-phase duty ratio and the motor three-phase current, and the calculation formula is:

[0077] i L (s)=s*C dc *u dcre (s)+D a *i a (s)+D b *i b (s)+D c *i c (s)

[0078] In the formula, i L (s) is the frequency domain inductance current output by the grid-side three-phase uncontrolled rectifier bridge, C dc is the bus capacitance value, u dcre (s) is the frequency domain reconstructed bus voltage, i a (s), i b (s) and i c (s) are the motor frequency domain three-phase currents, D a , D b and D c are the inverter output three-phase duty ratios.

[0079] Preferably, the second grid-side current harmonic regulation voltage is determined based on a self-defined closed-loop controller according to the main harmonic component of the inductance current, comprising:

[0080] The main harmonic component i L (s) of the frequency domain inductance current i Lh (s) is obtained by filtering with a band-pass filter, and the calculation formula is:

[0081] i Lh (s)=i L (s) * G BPF (s)

[0082] A given reference value i Lref (s) is set to 0, and the given reference value i Lref (s) is subtracted from the main harmonic component i Lh (s) of the frequency-domain inductance current, and the difference is taken as an input of a self-defined closed-loop controller, and an output of the self-defined closed-loop controller is a second grid-side current harmonic regulation voltage u Lcom (s).

[0083] Preferably, the self-defined closed-loop controller is a quasi-proportional-resonant controller, and an expression of the quasi-proportional-resonant controller is as follows:

[0084]

[0085] wherein K RP , K RR , ω c and ω0 are a proportional coefficient, a resonant coefficient, a resonant bandwidth and a resonant center frequency of the quasi-proportional-resonant controller, respectively.

[0086] In the preferred embodiment, the same closed-loop controller is used to suppress the bus voltage harmonic and the inductance current harmonic, and only the values of parameters of the controller are different in specific use.

[0087] In step 107, an α-axis correction voltage of the motor and a β-axis correction voltage of the motor are determined according to the first grid-side current harmonic regulation voltage and the second grid-side current harmonic regulation voltage.

[0088] Preferably, the α-axis correction voltage of the motor and the β-axis correction voltage of the motor are determined according to the first grid-side current harmonic regulation voltage and the second grid-side current harmonic regulation voltage, and the method comprises:

[0089] The first grid-side current harmonic regulation voltage and the second grid-side current harmonic regulation voltage are summed to obtain a resultant damping voltage;

[0090] The resultant damping voltage is decomposed into a d-axis direction damping voltage of the motor and a q-axis direction damping voltage of the motor along a motor-side power direction;

[0091] The d-axis direction damping voltage is superimposed into a d-axis given voltage of the motor to obtain a corrected d-axis given voltage, and the q-axis direction damping voltage is superimposed into a q-axis given voltage of the motor to obtain a corrected q-axis given voltage;

[0092] The corrected d-axis given voltage and the corrected q-axis given voltage are subjected to inverse Park transformation to obtain the α-axis correction voltage of the motor and the β-axis correction voltage of the motor;

[0093] The alpha-axis correction voltage and the beta-axis correction voltage are used to participate in SVPWM modulation of the motor to output three-phase duty cycles of the inverter to suppress the grid-side input current harmonics.

[0094] Preferably, the synthetic damping voltage is decomposed into a motor d-axis direction damping voltage and a motor q-axis direction damping voltage along the grid-side power direction, comprising:

[0095] According to the synthetic damping voltage, a regulation voltage injection angle is determined based on a self-defined regulation voltage injection angle selection principle, and the regulation voltage injection angle selection principle expression is:

[0096]

[0097] In the formula, u com is the synthetic damping voltage, θ com is the regulation voltage injection angle, ω dc is the angular frequency of the first bus voltage harmonic, θ is the motor rotor electrical angle, u ref is the motor given voltage vector, u dref and u qref are the d-axis and q-axis given voltages output by the current loop PI regulator, respectively.

[0098] According to the synthetic damping voltage and the regulation voltage injection angle, a motor d-axis direction damping voltage u dcom and a motor q-axis direction damping voltage u qcom are determined, and the calculation formula is:

[0099] u dcom = u com * cosθ com

[0100] u qcom = u com * sinθ com

[0101] In the formula, u dcom and u qcom are the motor d-axis direction damping voltage and the motor q-axis direction damping voltage, respectively.

[0102] In the preferred embodiment, the derivation process of the regulation voltage injection angle selection principle is as follows:

[0103] First, the voltage model of the permanent magnet synchronous motor in the dq coordinate axis system is established in the frequency domain, and specifically, the expression of the voltage model in the dq coordinate axis system is:

[0104]

[0105] In the formula, R aL is the stator resistance of the motor. q L is the q-axis inductance of the motor. d For the d-axis inductance of the motor, ω e Let ψ be the electric angular frequency of the motor. f For motor stator flux linkage;

[0106] Then substitute the angular frequency ω of the harmonics in the first bus voltage. dc The relationship between the motor's dq-axis current and dq-axis voltage at the harmonic frequency of the bus voltage is obtained as follows:

[0107]

[0108] In the formula, G(jω) dc )for:

[0109]

[0110] In the formula, u1(jω) dc ) = ju d (jω dc )+u q (jω dc ).

[0111] Therefore, when u d (jω dc ) = ju q (jω dc At this time, the harmonic amplitude related to the harmonic frequency of the bus voltage in the motor's dq-axis current reaches its minimum value, thus the control voltage injection angle θ can be determined. com The selection principle is based on the expressions listed in this preferred embodiment.

[0112] In step 108, the α-axis correction voltage and β-axis correction voltage are used to participate in the motor SVPWM modulation output inverter three-phase duty cycle to suppress grid-side input current harmonics.

[0113] Figure 2 for Figure 2 This is a control block diagram of a method for suppressing harmonic current on the grid side of a capacitor-free motor drive system according to a preferred embodiment of the present invention. Figure 2 As shown, the overall control of the electrolytic capacitor-free motor drive system can be divided into two parts: vector control and grid-side current harmonic regulation voltage generation.

[0114] Firstly, the vector control part is based on i d The control is a dual closed-loop system with a zero-to-zero value, where the outer loop is the speed loop and the inner loop is the current loop. The speed loop input is the ideal setpoint speed. The actual rotational speed ω output by the speed observer e The difference, after passing through the speed loop PI controller, outputs the ideal given d-axis current. ideal given current q-axis current The difference between the ideal given dq-axis current and the actual dq-axis current obtained by sampling is input to the current loop, and then the ideal d-axis given voltage u is output by the current loop PI controller dref q-axis given voltage u qref The ideal dq-axis given voltage is superimposed with the grid-side current harmonic dq-axis regulation voltage u dcom u qcom After superimposition, the dq-axis modified given voltage u is obtained dref_re u qref_re After inverse Park transformation of the dq-axis modified given voltage, the αβ-axis modified given voltage u is obtained αref_re u βref_re The αβ-axis modified given voltage and the reconstructed bus voltage u are superimposed dcre The observer-observed rotor position angle jointly participates in space vector pulse width modulation, and outputs the machine-side inverter control duty cycle D a,b,c Finally, permanent magnet synchronous motor vector control is realized.

[0115] The grid-side current harmonic regulation voltage generation part first extracts the main harmonic components of the bus voltage u dc through a band-pass filter, and corrects the bus voltage harmonics affected by the digital control delay using the periodic repetition characteristics of the bus voltage harmonics. The reconstructed bus voltage u dcre is obtained by replacing the original sampled bus voltage harmonics with the corrected bus voltage harmonics, to compensate for the harmonic components introduced by the digital control delay of the drive system, and a bus voltage harmonic controller G PRV (s) is constructed using a resonant controller to obtain the bus voltage harmonic regulation voltage, i.e., the first grid-side current harmonic regulation voltage u dccom , to reduce the grid-side input current harmonics introduced by the bus voltage harmonics. The reconstructed bus voltage u dcre , the motor three-phase current i a b,c and the inverter output three-phase duty cycle D a b,c are used to calculate the inductance current i L , and a band-pass filter G BPF (s) is used to extract the main harmonic components, and a current resonant controller G PRC (s) is used to obtain the inductance current harmonic regulation voltage, i.e., the second grid-side current harmonic regulation voltage u Lcom . The first grid-side current harmonic regulation voltage u dccom and the second grid-side current harmonic regulation voltage u Lcom are superimposed to obtain the grid-side current harmonic regulation voltage u com . The regulation voltage injection angle θ comThe grid-side current harmonic regulation voltage is decomposed into dq-axis grid-side current harmonic regulation voltages according to the regulation voltage injection angle, and is superimposed into the dq-axis given voltage to realize grid-side current harmonic regulation.

[0116] Further, the preferred embodiment verifies the effectiveness of the proposed control strategy in the electrolytic capacitorless permanent magnet synchronous motor experimental platform. Considering the grid-side input power quality and the stability requirements of the drive system, the bus-side film capacitor capacitance is 30 μF, and the DC-side reactor inductance is 2.5 mH. The control algorithm is realized by the DSP28075 chip, and the PWM carrier frequency and the current and voltage sampling frequency are all set to 8 kHz. The main parameters of the experimental platform are shown in Table 1.

[0117] Table 1 Main parameters of the electrolytic capacitorless motor system experimental platform

[0118] Parameter name Parameter value Quadrature axis inductance (mH) 17.2 Stator resistance (Ω) 0.275 Direct axis inductance (mH) 7.5 Motor rated power (kW) 11 Direct current capacitance (μF) 30 Direct current reactor (mH) 0.3 Motor rated current (A) 22 Number of pole pairs 3 No-load back EMF (V) 220

[0119] The grid-side current harmonic suppression is carried out by using the main parameters of the experimental platform shown in Table 1 to obtain Figures 3 to 5 wherein, Figure 3 is the waveform diagram of the grid-side current, bus voltage, motor operating frequency and motor torque under the condition of applying the control before the motor operating frequency is 50 Hz, Figure 4 is the waveform diagram of the grid-side current, bus voltage, motor operating frequency and motor torque under the condition of applying the conventional inductance current control strategy before the motor operating frequency is 50 Hz, Figure 5 is the waveform diagram of the grid-side current, bus voltage, motor operating frequency and motor torque under the condition of applying the electrolytic capacitorless motor drive system grid-side current harmonic suppression method of the preferred embodiment of the present application before the motor operating frequency is 50 Hz, and Figures 3 to 5As shown, before the control is applied, the bus voltage fluctuation of the electrolytic capacitor-free motor drive system is 115.5V, and the grid-side input current THD is 62.1%. After the conventional inductance current control is applied, the bus voltage fluctuation is reduced from 115.5V to 82.6V, and the grid-side input current THD is reduced from 62.1% to 50.1%. After the grid-side current harmonic suppression strategy based on the bus voltage decoupling is applied, the bus voltage fluctuation is further reduced to 61.4V, and the grid-side current THD is further reduced to 35.6%. It can be known that the proposed control strategy can effectively further improve the grid-side power quality. At the same time, it can be known from the motor torque and operating frequency waveforms that, after the inductance current control is applied, the motor torque fluctuation is increased from 2.5N·m to 8.6N·m, and the speed fluctuation is increased from 0.62Hz to 0.72Hz. After the grid-side current harmonic suppression strategy based on the bus voltage decoupling is applied, the torque fluctuation is reduced to 7.3N·m, and the speed fluctuation is reduced to 0.63Hz. It can be known that by designing the regulation voltage injection angle, the interference of the injected regulation voltage on the motor side can be effectively reduced. In summary, the grid-side current harmonic suppression method of the electrolytic capacitor-free motor drive system according to the preferred embodiment can not only effectively reduce the grid-side input current distortion of the electrolytic capacitor-free motor drive system and suppress the bus voltage fluctuation, but also reduce the interference on the motor side compared with the traditional grid-side current harmonic control scheme.

[0120] Exemplary apparatus

[0121] Figure 6 The structure diagram of the electrolytic capacitor-free motor drive system grid-side current harmonic suppression device according to the preferred embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, the electrolytic capacitor-free motor drive system grid-side current harmonic suppression device 600 according to the preferred embodiment of the present application comprises: Figure 6

[0122] The first harmonic module 601 is configured to determine a first bus voltage harmonic based on the sampled bus voltage.

[0123] The intermediate variable module 602 is configured to obtain a bus voltage harmonic intermediate variable required for correcting the digital control delay according to the frequency of the first bus voltage harmonic and the inverter switching frequency.

[0124] The second harmonic module 603 is configured to calculate a second bus voltage harmonic required for correcting the digital control delay according to the bus voltage harmonic intermediate variable.

[0125] The first voltage module 604 is configured to correct the bus voltage to determine a reconstructed bus voltage according to the first bus voltage harmonic and the second bus voltage harmonic.

[0126] ​The second voltage module 605 is configured to determine a first grid-side current harmonic regulation voltage based on a self-defined closed-loop controller according to the second bus voltage harmonic;

[0127] The third voltage module 606 is configured to determine a second grid-side current harmonic regulation voltage based on a self-defined closed-loop controller according to the reconstructed bus voltage, inverter output three-phase duty ratio and motor three-phase current;

[0128] The fourth voltage module 607 is configured to determine an alpha-axis correction voltage and a beta-axis correction voltage of the motor according to the first grid-side current harmonic regulation voltage and the second grid-side current harmonic regulation voltage;

[0129] The harmonic suppression module 608 is configured to participate in motor SVPWM modulation output inverter three-phase duty ratio by using the alpha-axis correction voltage and the beta-axis correction voltage to suppress grid-side input current harmonic.

[0130] Preferably, the first harmonic module 601 determines the first bus voltage harmonic based on the sampled bus voltage, which means that a band-pass filter is used to filter the obtained frequency domain bus voltage to obtain the frequency domain first bus voltage harmonic, and the calculation formula is as follows:

[0131] u dch (s)=u dc (s) * G BPF (s)

[0132] In the formula, u dc (s) is the frequency domain bus voltage, u dch (s) is the frequency domain first bus voltage harmonic, G BPF (s) is the band-pass filter transfer function, and s is the Laplace operator.

[0133] Preferably, the intermediate variable module 602 obtains the bus voltage harmonic intermediate variable required for correction digital delay according to the frequency of the first bus voltage harmonic and the inverter switching frequency, and the intermediate variable includes:

[0134] The frequency domain first bus voltage harmonic u dc (s) is converted into the discrete domain first bus voltage harmonic u dc (z) by using bilinear transformation, and the conversion formula is as follows:

[0135]

[0136] In the formula, T s is the sampling period, and Z is the Z transform operator;

[0137] The proportional value N is calculated according to the frequency of the first bus voltage harmonic and the inverter switching frequency, and the calculation formula is as follows:

[0138]

[0139] In the formula, f h f is the frequency of the harmonic of the first bus voltage. s is the inverter switching frequency, and [] represents the integer operation;

[0140] The intermediate variable of the bus voltage harmonics required for correcting the digital delay is calculated based on the first bus voltage harmonic in the discrete domain and the aforementioned proportional value. The calculation formula is as follows:

[0141] u dchrel (z)=u dch (z) * Z -N+1

[0142] u dchre2 (z)=u dch (z) * Z -N+2

[0143] In the formula, u dchre1 (z) and u dchre2 (z) represents the intermediate variable of the discrete-domain bus voltage harmonics required to correct the digital delay.

[0144] Preferably, the second harmonic module 603 calculates the second bus voltage harmonic required to correct the digital control delay based on the intermediate variable of the bus voltage harmonic, and the calculation formula is as follows:

[0145]

[0146] In the formula, u dchav (z) represents the discrete-domain second bus voltage harmonics required to correct the digital control delay.

[0147] Preferably, the first voltage module 604 corrects the bus voltage based on the first bus voltage harmonic and the second bus voltage harmonic to determine the reconstructed bus voltage, including:

[0148] For the discrete domain second bus voltage harmonic u dchav (z) Perform the inverse Z-transform to obtain the frequency domain second bus voltage harmonic u. dchav (s);

[0149] The frequency domain bus voltage is determined by correcting the harmonics of the first and second frequency domain bus voltages. The calculation formula is as follows:

[0150] u dcre (s)=u dc (s)-u dch (s)+u dchav (s)

[0151] wherein u dcre (s) is the frequency domain reconstructed bus voltage.

[0152] Preferably, the second voltage module 605 determines the first grid-side current harmonic regulating voltage based on the self-defined closed-loop controller according to the second bus voltage harmonics, comprising:

[0153] The given reference value u dchref (s) of the frequency domain first bus voltage harmonic is set to 0, and the given reference value u dchref (s) is subtracted from the frequency domain second bus voltage harmonic u dchav (s) to obtain the difference value, and the difference value is taken as the input of the self-defined closed-loop controller, and the self-defined closed-loop controller outputs the frequency domain first grid-side current harmonic regulating voltage u dccom (s).

[0154] Preferably, the third voltage module 606 determines the second grid-side current harmonic regulating voltage based on the self-defined closed-loop controller according to the reconstructed bus voltage, the inverter output three-phase duty ratio and the motor three-phase current, comprising:

[0155] The inductance current output by the grid-side three-phase uncontrolled rectifier bridge is calculated according to the reconstructed bus voltage, the inverter output three-phase duty ratio and the motor three-phase current.

[0156] The second grid-side current harmonic regulating voltage is determined based on the self-defined closed-loop controller according to the main harmonic component of the inductance current.

[0157] Preferably, the third voltage module 606 calculates the inductance current output by the grid-side three-phase uncontrolled rectifier bridge according to the reconstructed bus voltage, the inverter output three-phase duty ratio and the motor three-phase current, and the calculation formula is:

[0158] i L (s) = s * C dc *u dcre (s) + D a *i a (s) + D b *i b (s) + D c *i c (s)

[0159] wherein i L (s) is the frequency domain inductance current output by the grid-side three-phase uncontrolled rectifier bridge, C dc is the bus capacitance value, u dcre (s) is the frequency domain reconstructed bus voltage, i a (s), i b (s) and i c(s) are the motor frequency-domain three-phase currents, D a , D b , and D c are the inverter output three-phase duty cycles.

[0160] Preferably, the third voltage module 606 determines the second grid-side current harmonic regulation voltage based on a self-defined closed-loop controller according to the main harmonic component of the inductor current, including:

[0161] The main harmonic component i L (s) of the frequency-domain inductor current i Lh (s) is obtained by filtering with a band-pass filter.

[0162] i Lh (s) = i L (s) * G BPF (s)

[0163] The given reference value i Lref (s) of the main harmonic component of the frequency-domain inductor current is set to 0, the difference between the given reference value i Lref (s) and the main harmonic component i Lh (s) of the frequency-domain inductor current is calculated, and the difference is taken as the input of the self-defined closed-loop controller, and the output of the self-defined closed-loop controller is the second grid-side current harmonic regulation voltage u Lcom (s).

[0164] Preferably, the self-defined closed-loop controller in the second voltage module 605 and the third voltage module 606 is a quasi-proportional resonant controller, and the expression is:

[0165]

[0166] In the formula, K RP , K RR , ω c , and ω0 are the proportional coefficient, resonant coefficient, resonant bandwidth, and resonant center frequency of the quasi-proportional resonant controller, respectively.

[0167] Preferably, the fourth voltage module 607 determines the α-axis correction voltage and the β-axis correction voltage of the motor according to the first grid-side current harmonic regulation voltage and the second grid-side current harmonic regulation voltage, including:

[0168] The first grid-side current harmonic regulation voltage and the second grid-side current harmonic regulation voltage are summed to obtain a synthesized damping voltage;

[0169] The synthesized damping voltage is decomposed into a motor d-axis direction damping voltage and a motor q-axis direction damping voltage along the motor-side power direction.

[0170] The d-axis direction damping voltage is superimposed into the motor d-axis given voltage to obtain a corrected d-axis given voltage, and the q-axis direction damping voltage is superimposed into the motor q-axis given voltage to obtain a corrected q-axis given voltage;

[0171] The corrected d-axis given voltage and the corrected q-axis given voltage are subjected to inverse Park transformation to obtain a motor α-axis corrected voltage and a motor β-axis corrected voltage;

[0172] The α-axis corrected voltage and the β-axis corrected voltage are used to participate in SVPWM modulation of the motor to output three-phase duty cycles of the inverter to suppress the grid-side input current harmonics.

[0173] Preferably, the fourth voltage module 607 decomposes the synthetic damping voltage into a motor d-axis direction damping voltage and a motor q-axis direction damping voltage along the machine-side power direction, comprising:

[0174] According to the synthetic damping voltage, a regulation voltage injection angle is determined based on a self-defined regulation voltage injection angle selection principle, and the regulation voltage injection angle selection principle expression is:

[0175]

[0176] In the formula, u com is the synthetic damping voltage, θ com is the regulation voltage injection angle, ω dc is the angular frequency of the first bus voltage harmonic, θ is the motor rotor electrical angle, u ref is the motor given voltage vector, u dref and u qref are the d-axis and q-axis given voltages output by the current loop PI regulator, respectively;

[0177] According to the synthetic damping voltage and the regulation voltage injection angle, a motor d-axis direction damping voltage u dcom and a motor q-axis direction damping voltage u qcom are determined, and the calculation formula is:

[0178] u dcom = u com * cosθ com

[0179] u qcom = u com * sinθ com

[0180] In the formula, u dcom and u qcom are the motor d-axis direction damping voltage and the motor q-axis direction damping voltage, respectively.

[0181] The no-electrolytic capacitor motor drive system grid-side current harmonic suppression device and the no-electrolytic capacitor motor drive system grid-side current harmonic suppression method according to the preferred embodiment of the present application comprehensively consider the motor operating condition, bus voltage harmonic, and digital control delay, and the steps of suppressing the grid-side input current harmonic are the same, and the technical effects achieved are the same, which will not be described here.

[0182] Exemplary electronic device

[0183] Figure 7 A structural schematic diagram of an electronic device according to the preferred embodiment of the present application is shown in FIG. 7. As shown in FIG. 7, the electronic device includes one or more processors 701 and a memory 702. Figure 7

[0184] The processor 701 can be a central processing unit (CPU) or other form of processing unit having data processing and / or instruction executing capabilities, and can control other components in the electronic device to perform desired functions.

[0185] The memory 702 can include one or more computer program products that can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory, for example, can include random access memory (RAM), cache memory, and / or the like. The non-volatile memory, for example, can include read-only memory (ROM), hard disk, flash memory, and / or the like. One or more computer program instructions can be stored on the computer-readable storage media, and the processor 701 can execute the program instructions to implement the no-electrolytic capacitor motor drive system grid-side current harmonic suppression method according to the disclosed embodiments described above and / or other desired functions. In one example, the electronic device can further include an input device 703 and an output device 704, which are interconnected through a bus system and / or other form of connection mechanism (not shown).

[0186] In addition, the input device 703 can further include, for example, a keyboard, a mouse, and / or the like.

[0187] The output device 704 can output various information to the outside. The output device 704 can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and / or the like.

[0188] Of course, in order to simplify, Figure 7 only some of the components in the electronic device related to the present disclosure are shown, and components such as buses, input / output interfaces, and / or the like are omitted. In addition, the electronic device can further include any other appropriate components according to specific application cases.​

[0189] Exemplary computer program product and computer readable storage medium

[0190] In addition to the above method and device, an embodiment of the present disclosure can also be a computer program product, which includes computer program instructions, which, when executed by a processor, cause the processor to perform the steps in the motor drive system grid-side current harmonic suppression method according to various embodiments of the present disclosure described in the above “Exemplary Method” section of the present specification.

[0191] The computer program product can be written in any combination of one or more programming languages, including an object-oriented programming language such as Java, C++, etc., and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote computing device or server.

[0192] In addition, an embodiment of the present disclosure can also be a computer readable storage medium, which stores computer program instructions, which, when executed by a processor, cause the processor to perform the steps in the motor drive system grid-side current harmonic suppression method according to various embodiments of the present disclosure described in the above “Exemplary Method” section of the present specification.

[0193] The computer readable storage medium can take any combination of one or more of the following readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium, for example, can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the above. More specific examples (a non-exhaustive list) of the readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0194] The above describes the basic principles of the present disclosure in conjunction with specific embodiments, but it should be noted that the advantages, benefits, effects and the like mentioned in the present disclosure are merely examples and are not limiting, and these advantages, benefits, effects and the like cannot be considered as necessary for each embodiment of the present disclosure. In addition, the above specific details of the disclosure are only for the purpose of example and for the purpose of understanding, and are not limiting, and the above details do not limit the present disclosure to be necessarily implemented with the above specific details.

[0195] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between each embodiment can be understood by referring to each other. For system embodiments, since they basically correspond to method embodiments, the description is relatively simple, and the relevant parts can be understood by referring to the part of the method embodiment.

[0196] The block diagrams of the devices, apparatuses, equipment, systems involved in the present disclosure are only exemplary examples and are not intended to require or imply the connection, arrangement, configuration shown in the block diagram. As those skilled in the art will recognize, these devices, apparatuses, equipment, systems can be connected, arranged, configured in any manner. Words such as "include", "contain", "have" and the like are open-ended words, which mean "including but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.

[0197] The devices and methods of the present disclosure can be implemented in many ways. For example, the devices and methods of the present disclosure can be implemented by software, hardware, firmware, or any combination of software, hardware, firmware. The above order of steps for the method is only for illustration, and the steps of the method of the present disclosure are not limited to the above specific description, unless otherwise specifically described. In addition, in some embodiments, the present disclosure can also be implemented as programs recorded in recording media, which include machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers the recording media storing the programs for executing the method according to the present disclosure.

[0198] It is also important to note that the devices, apparatuses and methods described in the disclosure can be embodied in a variety of other forms, including but not limited to oral, written, and / or visual forms. It is also noted that scripting languages can be used in the devices, apparatuses and methods described in the disclosure. It is also noted that the devices, apparatuses and methods described in the disclosure can be implemented in software and / or hardware. It is also noted that the devices, apparatuses and methods described in the disclosure can be implemented in a variety of ways, including as a computer program product, as a computer-implemented process, and / or as an apparatus. Furthermore, the described aspects can be implemented by hardware, software, firmware or any combination thereof. If implemented in software, the described aspects can be stored in or implemented with one or more computer-readable storage mediums. Any of the described aspects can also be embodied as computer-readable storage mediums containing instructions that, when executed by a processor, can cause the processor to carry out the described acts. The computer-readable storage mediums can include volatile or non-volatile storage mediums (e.g., removable storage mediums and / or non-removable storage mediums), which can be implemented in any method or technology for storage of information such as computer-readable instructions. The computer-readable storage mediums can also include transmission mediums, which can be implemented in any method or technology for transmission of information such as computer-readable instructions. The computer-readable storage mediums and / or transmission mediums can be one or more of, for example, volatile memory, non-volatile memory, removable storage mediums, non-removable storage mediums, and / or any combination thereof. The computer-readable storage mediums and / or transmission mediums can be included within a computer program product.

[0199] The above description has been presented for the purposes of illustration and description. Further, this description is not intended to limit embodiments of the disclosure to the forms disclosed herein. Although several example aspects and embodiments have been discussed, those skilled in the art will recognize certain variations, modifications, changes, additions, and sub-combinations thereof.

Claims

1. A method for suppressing harmonic current on the grid side of a capacitor-free motor drive system, characterized in that, The method includes: The first bus voltage harmonic is determined based on the bus voltage obtained from sampling. Based on the frequency of the first bus voltage harmonic and the inverter switching frequency, obtain the intermediate bus voltage harmonic variable required to correct the digital control delay. The second bus voltage harmonic required to correct the digital control delay is calculated based on the intermediate variable of the bus voltage harmonic. The bus voltage is corrected based on the first bus voltage harmonic and the second bus voltage harmonic to determine the reconstructed bus voltage; Based on the second bus voltage harmonics, the first grid-side current harmonic regulation voltage is determined using a custom closed-loop controller. Based on the reconstructed bus voltage, inverter output three-phase duty cycle and motor three-phase current, the second grid-side current harmonic regulation voltage is determined based on a custom closed-loop controller. The α-axis correction voltage and β-axis correction voltage of the motor are determined based on the first grid-side current harmonic control voltage and the second grid-side current harmonic control voltage. The α-axis correction voltage and β-axis correction voltage are used to participate in the SVPWM modulation output inverter of the motor to suppress the harmonics of the grid-side input current.

2. The method according to claim 1, characterized in that, Determining the first bus voltage harmonic based on the sampled bus voltage refers to filtering the acquired frequency domain bus voltage using a bandpass filter to obtain the first frequency domain bus voltage harmonic. The calculation formula is as follows: u dch (s)=u dc (s) * G BPF (s) In the formula, u dc (s) represents the frequency domain bus voltage, u dch (s) represents the harmonic of the first bus voltage in the frequency domain, G BPF (s) is the transfer function of the bandpass filter, and s is the Laplace operator.

3. The method according to claim 2, characterized in that, Based on the frequency of the first bus voltage harmonic and the inverter switching frequency, obtain the intermediate bus voltage harmonic variables required for correcting the digital delay, including: The harmonics of the first busbar in the frequency domain are u dc (s) is converted into discrete domain first bus voltage harmonic u using bilinear transformation. dc (z), its conversion formula is: In the formula, T s Let Z be the sampling period, and Z be the Z-transform operator; The proportional value N is calculated based on the frequency of the first bus voltage harmonics and the inverter switching frequency. The calculation formula is as follows: In the formula, f h f is the frequency of the harmonic of the first bus voltage. s is the inverter switching frequency, and [] represents the integer operation; The intermediate variable of the bus voltage harmonics required for correcting the digital delay is calculated based on the first bus voltage harmonic in the discrete domain and the aforementioned proportional value. The calculation formula is as follows: at dchrel (with)=u dch (With) * WITH -N+1 at dchre2 (with)=u dch (With) * WITH -N+2 In the formula, u dchre1 (z) and u dchre2 (z) represents the intermediate variable of the discrete-domain bus voltage harmonics required to correct the digital delay.

4. The method according to claim 3, characterized in that, The second bus voltage harmonic required for correcting the digital control delay is calculated based on the intermediate variable of the bus voltage harmonic. The calculation formula is as follows: In the formula, u dchav (z) represents the discrete-domain second bus voltage harmonics required to correct the digital control delay.

5. The method according to claim 4, characterized in that, Correcting the bus voltage based on the first bus voltage harmonic and the second bus voltage harmonic to determine the reconstructed bus voltage includes: For the discrete domain second bus voltage harmonic u dchav (z) Perform the inverse Z-transform to obtain the frequency domain second bus voltage harmonic u. dchav (s); The frequency domain bus voltage is determined by correcting the harmonics of the first and second frequency domain bus voltages. The calculation formula is as follows: in dcre (s)=in dc (with)-in dch (with)+in dchav (with) In the formula, u dcre (s) represents the frequency domain reconstructed bus voltage.

6. The method according to claim 5, characterized in that, Based on the second bus voltage harmonics, the first grid-side current harmonic regulation voltage is determined using a custom closed-loop controller, including: The given reference value u of the first bus voltage harmonic in the frequency domain dchref (s) is set to 0, so that the given reference value u dchref (s) and the harmonics of the second bus voltage in the frequency domain u dchav (s) Perform a difference operation, and use the difference between the two as the input of the custom closed-loop controller. Then, the custom closed-loop controller outputs the frequency domain first grid side current harmonic regulation voltage u. dccom (s).

7. The method according to claim 1, characterized in that, Based on the reconstructed bus voltage, inverter output three-phase duty cycle, and motor three-phase current, the second grid-side current harmonic regulation voltage is determined using a custom closed-loop controller, including: The inductor current output by the grid-side three-phase uncontrolled rectifier bridge is calculated based on the reconstructed bus voltage, the inverter output three-phase duty cycle, and the motor three-phase current. Based on the main harmonic components of the inductor current, the second grid-side current harmonic regulation voltage is determined using a custom closed-loop controller.

8. The method according to claim 7, characterized in that, The inductor current output by the grid-side three-phase uncontrolled rectifier bridge is calculated based on the reconstructed bus voltage, the inverter output three-phase duty cycle, and the motor three-phase current. The calculation formula is as follows: i L (s)=s*C dc *u dcre (s)+D a *i a (s)+D b *i b (s)+D c *i c (s) In the formula, i L (s) represents the frequency domain inductor current output by the grid-side three-phase uncontrolled rectifier bridge, C dc U is the capacitance value of the bus capacitor. dcre (s) represents the frequency domain reconstructed bus voltage, i a (s), i b (s) and i c (s) represent the three-phase currents in the frequency domain of the motor, D a D b and D c These represent the three-phase duty cycles of the inverter output.

9. The method according to claim 8, characterized in that, Based on the main harmonic components of the inductor current, the second grid-side current harmonic regulation voltage is determined using a custom closed-loop controller, including: Using a bandpass filter to filter the frequency domain inductor current i L (s) Filter to obtain its main harmonic components i Lh (s), its calculation formula is: i Lh (s)=i L (s) * G BPF (s) The given reference value i of the main harmonic components of the frequency domain inductor current. Lref (s) is set to 0, so that the given reference value i Lref (s) and the main harmonic components of the frequency domain inductor current i Lh (s) Perform a difference calculation, and use the difference between the two as the input to the custom closed-loop controller. Then, the custom closed-loop controller outputs the second grid-side current harmonic regulation voltage u. Lcom (s).

10. The method according to claim 7 or 9, characterized in that, The custom closed-loop controller is a quasi-proportional resonant controller, and its expression is: In the formula, K RP K RR ω c ω0 and ω0 are the proportional coefficient, resonant coefficient, resonant bandwidth and resonant center frequency of the quasi-proportional resonant controller, respectively.

11. The method according to claim 1, wherein determining the α-axis correction voltage and β-axis correction voltage of the motor based on the first grid-side current harmonic control voltage and the second grid-side current harmonic control voltage comprises: The first grid-side current harmonic control voltage and the second grid-side current harmonic control voltage are summed, and the sum is used as the composite damping voltage. The combined damping voltage is decomposed along the power direction on the machine side into damping voltage in the d-axis direction of the motor and damping voltage in the q-axis direction of the motor; The d-axis damping voltage is superimposed on the motor's d-axis given voltage to obtain the corrected d-axis given voltage, and the q-axis damping voltage is superimposed on the motor's q-axis given voltage to obtain the corrected q-axis given voltage; The corrected d-axis given voltage and the corrected q-axis given voltage are subjected to inverse Park transformation to obtain the corrected α-axis voltage and the corrected β-axis voltage of the motor. The α-axis and β-axis corrected voltages are used to participate in the SVPWM modulation of the motor to output the three-phase duty cycle of the inverter in order to suppress the harmonics of the grid-side input current.

12. The method according to claim 11, characterized in that, The combined damping voltage is decomposed along the power direction on the machine side into damping voltage in the d-axis direction of the motor and damping voltage in the q-axis direction of the motor, including: Based on the synthesized damping voltage, the control voltage injection angle is determined according to a custom control voltage injection angle selection principle. The expression for the control voltage injection angle selection principle is as follows: In the formula, u com To synthesize the damping voltage, θ com To control the voltage injection angle, ω dc Let θ be the angular frequency of the first bus voltage harmonic, and θ be the electrical angle of the motor rotor. ref A voltage vector is given to the motor, u dref with u qref These are the d-axis and q-axis setpoint voltages output from the current loop PI regulator, respectively. The damping voltage u in the d-axis direction of the motor is determined based on the synthesized damping voltage and the controlled voltage injection angle. dcom Damping voltage u along the q-axis of the motor qcom The calculation formula is as follows: in dcom =in com * cosθ com u qcom =u com * sinθ com In the formula, u dcom and u qcom These are the damping voltages along the d-axis and q-axis of the motor, respectively.

13. A grid-side current harmonic suppression device for a capacitorless motor drive system, characterized in that, The device includes: The first harmonic module is used to determine the first bus voltage harmonic based on the sampled bus voltage. The intermediate variable module is used to obtain the intermediate bus voltage harmonics required for correcting the digital control delay based on the frequency of the first bus voltage harmonics and the inverter switching frequency. The second harmonic module is used to calculate the second bus voltage harmonic required to correct the digital control delay based on the intermediate variable of the bus voltage harmonic. A first voltage module is used to correct the bus voltage based on the first bus voltage harmonic and the second bus voltage harmonic to determine the reconstructed bus voltage; The second voltage module is used to determine the first grid-side current harmonic regulation voltage based on the second bus voltage harmonic and a custom closed-loop controller. The third voltage module is used to determine the second grid-side current harmonic regulation voltage based on the reconstructed bus voltage, the inverter output three-phase duty cycle and the motor three-phase current, using a custom closed-loop controller. The fourth voltage module is used to determine the α-axis correction voltage and β-axis correction voltage of the motor based on the first grid-side current harmonic control voltage and the second grid-side current harmonic control voltage. The harmonic suppression module is used to participate in the SVPWM modulation of the motor output inverter's three-phase duty cycle by using the α-axis correction voltage and β-axis correction voltage to suppress grid-side input current harmonics.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the method as described in any one of claims 1-12.

15. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method described in any one of claims 1-12.

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