Photoelectric conversion device and equipment

Abstract

To provide a high-performance photoelectric conversion device.SOLUTION: A photoelectric conversion device including a plurality of substrates including a first substrate and a second substrate includes: a plurality of pixels each having a photoelectric conversion element for generating charge according to received light amount, a floating diffusion for outputting a signal according to the charge, a first source follower circuit for amplifying a signal output from the floating diffusion, and a first transistor for driving the first source follower circuit; a first holding circuit electrically connected to a gate electrode of the first transistor; a second source follower circuit for amplifying a signal output from the first source follower circuit; and a signal processing circuit for processing a signal output from the second source follower circuit. The photoelectric conversion elements are arranged on the first substrate, and the signal processing circuit is arranged on the second substrate.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and equipment. [Background technology]

[0002] Patent Document 1 proposes a solid-state imaging device with a so-called global shutter function that has a charge storage section that temporarily stores electric charges and transfers electric charges from photoelectric conversion elements to the charge storage section simultaneously for multiple pixels. The configuration of Patent Document 1 also includes a source follower circuit that amplifies signals output from the pixels and a current source that drives the source follower circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 215105 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the solid-state imaging device disclosed in Patent Document 1, fluctuations in the bias voltage supplied to the current source for driving the source follower circuit may cause a deterioration in the quality of the signal obtained via the source follower circuit.

[0005] An object of the present invention is to provide a photoelectric conversion device that does not experience or only experiences a small decrease in signal quality, that is, a high-performance device. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device having a plurality of substrates including a first substrate and a second substrate, the photoelectric conversion device having a plurality of pixels each including a photoelectric conversion element that generates a charge according to the amount of light received, a floating diffusion that outputs a signal according to the charge, a first source follower circuit that amplifies the signal output from the floating diffusion, and a first transistor for driving the first source follower circuit, a first holding circuit electrically connected to the gate electrode of the first transistor, a second source follower circuit that amplifies the signal output from the first source follower circuit, and a signal processing circuit that processes the signal output from the second source follower circuit, wherein the photoelectric conversion element is arranged on the first substrate and the signal processing circuit is arranged on the second substrate. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a high-performance photoelectric conversion device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 2] 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Figure 3] Schematic diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 4] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a modification of the first embodiment. [Figure 5] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a second embodiment. [Figure 6] Schematic diagram illustrating a photoelectric conversion device according to a second embodiment. [Figure 7] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a third embodiment. [Figure 8] FIG. 10 is a plan view illustrating a photoelectric conversion device according to a third embodiment. [Figure 9] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a fourth embodiment. [Figure 10]FIG. 10 is a plan view illustrating a photoelectric conversion device according to a fourth embodiment. [Figure 11] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a fifth embodiment. [Figure 12] FIG. 10 is a plan view illustrating a photoelectric conversion device according to a fifth embodiment. [Figure 13] Circuit diagram illustrating a photoelectric conversion device according to a sixth embodiment. [Figure 14] Circuit diagram illustrating a photoelectric conversion device according to a seventh embodiment. [Figure 15] Schematic diagram illustrating a photoelectric conversion device according to a seventh embodiment. [Figure 16] Circuit diagram illustrating a photoelectric conversion device according to an eighth embodiment. [Figure 17] Circuit diagram illustrating a photoelectric conversion device according to a ninth embodiment. [Figure 18] FIG. 13 is a plan view illustrating a photoelectric conversion device according to a ninth embodiment. [Figure 19] Circuit diagram illustrating a photoelectric conversion device according to a tenth embodiment. [Figure 20] FIG. 22 is a plan view illustrating a photoelectric conversion device according to a tenth embodiment. [Figure 21] Circuit diagram illustrating a photoelectric conversion device according to an eleventh embodiment. [Figure 22] Circuit diagram illustrating a photoelectric conversion device according to a twelfth embodiment. [Figure 23] 13A and 13B are schematic diagrams illustrating devices according to a thirteenth embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment will be described below with reference to the drawings. Note that the following embodiments do not limit the scope of the claimed invention. Although multiple features are described in the embodiments, not all of these features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar components are given the same reference numerals, and redundant description will be omitted. Also, in the following embodiments, an imaging sensor will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to an imaging sensor and can be applied to other examples of photoelectric conversion devices. Examples include an imaging device, a range finder (a device for measuring distance using focus detection or TOF (Time Of Flight)), and a photometric device (a device for measuring the amount of incident light).

[0010] In this specification, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) are used as necessary. The use of these terms is for the purpose of facilitating understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0011] In this specification, the phrase "electrically connecting component A and component B" does not necessarily mean that component A and component B are directly connected. For example, even if another component C is connected between component A and component B, it is acceptable as long as they are electrically connected.

[0012] In this specification, "plane" refers to a surface parallel to the main surface of a substrate. The main surface of a substrate may be the light incident surface of a substrate including a photoelectric conversion element, a surface on which multiple analog-digital conversion circuits are repeatedly arranged, or a bonding surface between substrates in a stacked photoelectric conversion device. Furthermore, "planar view" refers to a view from a direction perpendicular to the main surface of the substrate. Furthermore, "cross section" refers to a surface perpendicular to the light incident surface of a semiconductor layer. Furthermore, "cross section" refers to a view from a direction parallel to the main surface of the substrate.

[0013] Metallic components such as wiring and pads described herein may be composed of a single metal element or a mixture (alloy). For example, wiring described as copper wiring may be composed of copper alone or may be composed primarily of copper with other components. Furthermore, for example, pads connected to external terminals may be composed of aluminum alone or may be composed primarily of aluminum with other components. The copper wiring and aluminum pads shown here are merely examples and can be replaced with various metals. Furthermore, the wiring and pads shown here are merely examples of metallic components used in photoelectric conversion devices and may also be applied to other metallic components.

[0014] First Embodiment A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG.

[0015] FIG. 1 is an example of a block diagram of a photoelectric conversion device according to this embodiment.

[0016] 1 , the photoelectric conversion device includes a pixel array 1, an output line 4, a control line 5, a control circuit 6, a timing signal output circuit 7, an amplifier circuit 8, a signal processing circuit 9, and an output circuit 10. The photoelectric conversion device also includes a first bias output circuit 11, a second bias output circuit 12, a third bias output circuit 13, a first bias line 3, a second bias line 14, and a third bias line 15.

[0017] The pixel array 1 has a plurality of pixels 2 that perform photoelectric conversion, and the plurality of pixels 2 are arranged across a plurality of rows and a plurality of columns within the pixel array 1. Each of the plurality of pixels 2 includes a photoelectric conversion element that generates and accumulates an electric charge according to the amount of received light, and outputs a pixel signal according to the amount of incident light. Note that the pixel signal output from the pixel 2 is an analog signal.

[0018] In this specification, the horizontal direction in the drawings may be referred to as the row direction, and the vertical direction as the column direction. The number of rows and columns of the pixels 2 arranged in the pixel array 1 is not particularly limited. The pixels 2 may include effective pixels that output pixel signals according to the amount of incident light, as well as optical black pixels whose photoelectric conversion elements are shielded from light, dummy pixels that do not output signals, and the like.

[0019] Furthermore, a control line 5 is arranged in each row of the pixel array 1, extending in the row direction. Each of the control lines 5 is electrically connected to a corresponding one of the pixels 2 arranged in the row direction. One control line 5 commonly controls a plurality of pixels 2 arranged in one row. A control circuit 6 supplies control signals to the plurality of pixels 2 via the control lines 5.

[0020] The amplifier circuit 8 has a circuit for amplifying pixel signals output from the pixels 2 for each column in which multiple pixels 2 are arranged. Multiple pixels 2 arranged in a certain column are electrically connected to the same circuit that amplifies the pixel signals, and the pixel signals output from the pixels 2 are input to the amplifier circuit 8.

[0021] An output line 4 is arranged in the column direction for each column in which a plurality of pixels 2 are arranged. Each of the plurality of output lines 4 is electrically connected to a circuit included in an amplifier circuit 8 that amplifies the pixel signals arranged for each column. The amplifier circuit 8 is electrically connected to a signal processing circuit 9. The pixel signals output from the pixels 2 are amplified by the amplifier circuit 8 and input to the signal processing circuit 9. The signal processing circuit 9 performs signal processing such as analog-to-digital (AD) conversion on the pixel signals output from the amplifier circuit 8 for each column. The AD conversion method can be various AD conversion methods such as slope-type AD conversion, successive approximation AD conversion, and ΔΣ AD conversion. The number of output lines 4 arranged for each column is not limited to one, and may be multiple. In this case, multiple circuits that amplify pixel signals are provided for each column in correspondence with the multiple output lines 4 arranged for each column. When multiple output lines 4 are provided for one column, pixels 2 arranged in multiple rows can be read out at the same time, enabling high-speed pixel signal readout.

[0022] The output circuit 10 includes a buffer amplifier, a differential amplifier, etc., performs predetermined signal processing on the pixel signals output from the pixels 2, and outputs the processed pixel signals to the outside of the photoelectric conversion device. Examples of signal processing performed by the output circuit 10 include correction processing using correlated double sampling (CDS) and amplification processing.

[0023] The timing signal output circuit 7 supplies timing signals to the control circuit 6 and the output circuit 10. The timing signal may be generated by the timing signal output circuit 7, or may be generated by a circuit different from the timing signal output circuit 7.

[0024] The first bias output circuit 11 supplies a bias voltage to the pixel 2 via the first bias line 3 for operating the pixel 2. The second bias output circuit 12 supplies a bias voltage to the amplifier circuit 8 via the second bias line 14 for operating the amplifier circuit 8. The third bias output circuit 13 supplies a bias voltage to the signal processing circuit 9 via the third bias line 15 for driving the signal processing circuit 9. Note that the first bias output circuit 11, the second bias output circuit 12, and the third bias output circuit 13 may generate the bias voltages, or a circuit different from these bias output circuits may generate the bias voltages.

[0025] 1 shows an example in which one circuit block for reading out pixel signals is provided, including a signal processing circuit 9 and an output circuit 10. However, multiple circuit blocks for reading out pixel signals may be provided. For example, by providing two circuit blocks for reading out pixel signals and inputting pixel signals from pixels 2 arranged in even-numbered columns to one circuit block and from pixels 2 arranged in odd-numbered columns to the other circuit block, high-speed readout of pixel signals becomes possible.

[0026] 2 is an example of a circuit diagram of the pixel 2, amplifier circuit 8, and signal processing circuit 9 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0027] As shown in FIG. 2, the photoelectric conversion device includes two substrates: a first substrate 1000 and a second substrate 2000. The photoelectric conversion device has a three-dimensional structure formed by bonding these two substrates together. The first substrate 1000 and the second substrate 2000 are stacked, for example, by hybrid bonding. The first substrate 1000 is electrically connected to the second substrate 2000 via a first bonding portion HB1 provided on the first substrate 1000 and a second bonding portion HB2 provided on the second substrate 2000. The bonding of the substrates using the first bonding portion HB1 and the second bonding portion HB2 is not limited to hybrid bonding. The substrates may be bonded by other methods, and the first substrate 1000 and the second substrate 2000 may be electrically connected using conductive vias, bumps, or the like. In this embodiment, the pixels 2 and the first bias output circuit 11 are arranged on the first substrate 1000, and the amplifier circuit 8, the signal processing circuit 9, the output circuit 10, the second bias output circuit 12, and the third bias output circuit 13 are arranged on the second substrate 2000. Note that the first substrate 1000 and the second substrate 2000 may each be a semiconductor substrate such as a silicon substrate.

[0028] As shown in FIG. 2, the pixel 2 includes a photoelectric conversion circuit 100, a pixel amplifier circuit 200, and a pixel memory circuit 300. The photoelectric conversion circuit 100 also includes a first photoelectric conversion element PD1, a second photoelectric conversion element PD2, a first transfer transistor 101, a second transfer transistor 102, and a floating diffusion 106. Hereinafter, in this specification, the floating diffusion 106 may be referred to as FD106 (FD stands for Floating Diffusion). The FD106 may also be referred to as a floating diffusion region 106. The photoelectric conversion circuit 100 also includes a first reset transistor 103 for resetting the FD106, a first amplifier transistor 104 for amplifying a signal, and a first selection transistor 105. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 are electrically connected to a first reference voltage line GND1, and a reference voltage is supplied thereto. The first reset transistor 103 and the first amplification transistor 104 are electrically connected to a first power supply voltage line VDD1, and a power supply voltage is supplied to the first reset transistor 103 and the first amplification transistor 104. The number of photoelectric conversion elements included in the photoelectric conversion circuit 100 may be one, or may be three or more.

[0029] The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 are, for example, photodiodes. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 are not limited to photodiodes and may be, for example, photoelectric conversion films. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 receive light incident on the pixel 2, generate charges according to the amount of the incident light, and accumulate the charges. The first reset transistor 103 is driven by a control signal RES1. When the first reset transistor 103 is turned on, the FD106 is reset to a voltage based on the power supply voltage. When the first reset transistor 103 is turned off, the reset of the FD106 is released. The first transfer transistor 101 is driven by a control signal TX1. When the first transfer transistor 101 is turned on, the charges generated in the first photoelectric conversion element PD1 are transferred to the FD106. The FD106 temporarily holds the charges input from the first photoelectric conversion element PD1 and functions as a charge-voltage converter that converts the held charges into a voltage signal. The first amplification transistor 104 amplifies the voltage signal (pixel signal) obtained by the FD 106. The first selection transistor 105 is driven by a control signal SEL1 to connect the first amplification transistor 104 to the pixel amplification circuit 200 and output the pixel signal amplified by the first amplification transistor 104 to the pixel amplification circuit 200. The second photoelectric conversion element PD2 and the second transfer transistor 102 are driven in the same way as the first photoelectric conversion element PD1 and the first transfer transistor 101.

[0030] 2 is merely an example, and the photoelectric conversion circuit 100 may further include transistors having predetermined functions. For example, a transistor that changes the capacitance value of the FD 106 or a transistor that drains charge from the first photoelectric conversion element PD1 may be further provided. Alternatively, the photoelectric conversion circuit 100 may be configured not to include the first selection transistor 105, but rather to change the selected / non-selected state of the photoelectric conversion circuit 100 depending on the voltage input from the first reset transistor 103 to the FD 106.

[0031] The pixel amplifier circuit 200 has a first bias control circuit 201, a first cascode transistor 202, a first transistor 203, and a first holding circuit 204. The first cascode transistor 202 and the first transistor 203 included in the pixel amplifier circuit 200 operate based on control signals supplied by the control circuit 6. The first transistor 203 functions as a current source and supplies a current to the first amplifier transistor 104. The first amplifier transistor 104, the first cascode transistor 202, and the first transistor 203 function as a source follower circuit (first source follower circuit), and an amplified pixel signal is output from the photoelectric conversion circuit 100. Note that even if the first cascode transistor 202 is not provided, the first amplifier transistor 104 and the first transistor 203 function as a source follower circuit.

[0032] The first bias output circuit 11 outputs a first bias voltage VG1 and supplies it to the gate electrode of the first cascode transistor 202. The first bias output circuit 11 also outputs a second bias voltage VB1 and supplies it to the gate electrode of the first transistor 203 via the first bias line 3 and the first bias control circuit 201.

[0033] A first holding circuit 204 is electrically connected to the gate electrode of the first transistor 203. The first holding circuit 204 includes a capacitive element (first capacitive element) and functions as a sample-and-hold circuit. The first bias control circuit 201 controls the electrical connection between the first bias line 3 and the gate electrode of the first transistor 203 and the first holding circuit 204. In other words, it can be said that the first bias control circuit 201 controls the second bias voltage VB1. The capacitance value of the capacitive element included in the first holding circuit 204 is preferably 1 fF to 100 fF. More preferably, the capacitance value of the capacitive element included in the first holding circuit 204 is preferably 10 fF to 50 fF. In this embodiment, a first holding circuit 204 is provided corresponding to each of the multiple pixels 2.

[0034] During the period when the first reset transistor 103 is off, at least one of the first transfer transistor 101 and the second transfer transistor 102 operates, and the photoelectric conversion circuit 100 outputs a pixel signal. At this timing, the voltage of the source electrode of the first selection transistor 105, which is the readout node for the pixel signal, fluctuates, causing the voltage of the first bias line 3 to fluctuate due to capacitive coupling. At this time, the first bias line 3 is electrically connected to the gate electrode of the first transistor 203. Due to the influence of the voltage fluctuation of the first bias line 3, the second bias voltage VB1 supplied to the gate electrode of the first transistor 203 varies for each of the multiple pixels 2, degrading the quality of the signal obtained from the photoelectric conversion device. Furthermore, the image quality of an image using the signal obtained from the photoelectric conversion device is degraded.

[0035] Therefore, in this embodiment, during a period when the first reset transistor 103 is on, the first bias control circuit 201 controls a sampling operation to electrically connect the first bias line 3 to the gate electrode of the first transistor 203 and the first holding circuit 204. Note that during a period when the first reset transistor 103 is on, voltage fluctuations at the source electrode of the first selection transistor 105 are smaller than during an operation period of at least one of the first transfer transistor 101 and the second transfer transistor 102. During a period when the first reset transistor 103 is off, at least one of the first transfer transistor 101 and the second transfer transistor 102 operates, and the photoelectric conversion circuit 100 outputs a pixel signal. At this timing, the first bias control circuit 201 controls a hold operation to disconnect the electrical connection between the first bias line 3 and the gate electrode of the first transistor 203 and the first holding circuit 204. This suppresses fluctuations in the second bias voltage VB1 caused by voltage fluctuations on the first bias line 3, thereby suppressing variations in pixel signals output from multiple pixels 2. That is, the quality of the signal obtained from the photoelectric conversion device is improved. Furthermore, by suppressing the variation in the signals output from the plurality of pixels 2, deterioration of the image quality of the image using the signals obtained from the photoelectric conversion device is reduced.

[0036] The pixel memory circuit 300 includes an N signal transistor 301, a first S signal transistor 302, a second S signal transistor 303, an N signal memory circuit 304, a first S signal memory circuit 305, and a second S signal memory circuit 306. The pixel memory circuit 300 further includes a second reset transistor 307, a second amplification transistor 308, and a second selection transistor 309. The pixel memory circuit 300 functions as a circuit for holding the pixel signal amplified by the pixel amplifier circuit 200. Here, the N signal is a reset level signal for the photoelectric conversion circuit 100, and the S signal is a photoelectric conversion signal from the photoelectric conversion circuit 100. Each transistor included in the pixel memory circuit 300 operates based on a control signal supplied by the control circuit 6.

[0037] The N signal memory circuit 304, the first S signal memory circuit 305, and the second S signal memory circuit 306 each include a capacitive element (third capacitive element). The capacitance value of the capacitive element included in each of the N signal memory circuit 304, the first S signal memory circuit 305, and the second S signal memory circuit 306 is preferably 100 fF to 800 fF. More preferably, the capacitance value of the capacitive element included in each of the N signal memory circuit 304, the first S signal memory circuit 305, and the second S signal memory circuit 306 is preferably 200 fF to 600 fF. If the capacitance value of the capacitive element included in each of the N signal memory circuit 304, the first S signal memory circuit 305, and the second S signal memory circuit 306 is small, there is a possibility that the held signals will leak. Therefore, by making the capacitance value of each of the above-mentioned capacitive elements (third capacitive elements) larger than the capacitance value of the capacitive element (first capacitive element) included in the first holding circuit 204, it is possible to suppress leakage of the held signal and improve the quality of the signal obtained from the photoelectric conversion device. Furthermore, deterioration in the image quality of an image using the signal obtained from the photoelectric conversion device is reduced.

[0038] Each transistor included in pixel 2 may be an N-type MOS transistor or a P-type MOS transistor. In this embodiment, a case will be described in which, of the electron-hole pairs generated in the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 by incident light, electrons are used as signal charges. When electrons are used as charges, each transistor included in pixel 2 may be configured as an N-type MOS transistor. However, the charges are not limited to electrons, and holes may also be used as charges. When holes are used as charges, each transistor included in pixel 2 may be configured as a P-type MOS transistor different from that described in this embodiment.

[0039] The amplifier circuit 8 has a second bias control circuit 401, a second cascode transistor 402, a second transistor 403, and a second holding circuit 404. Each transistor included in the amplifier circuit 8 operates based on a control signal supplied by the control circuit 6. The second transistor 403 functions as a current source and supplies a current to the second amplifier transistor 308. The second amplifier transistor 308, the second cascode transistor 402, and the second transistor 403 function as a source follower circuit (second source follower circuit), and an amplified pixel signal is output from the pixel memory circuit 300. Note that even if the second cascode transistor 402 is not provided, the second amplifier transistor 308 and the second transistor 403 function as a source follower circuit.

[0040] The second bias output circuit 12 outputs a third bias voltage VG2 and supplies it to the gate electrode of the second cascode transistor 402. The second bias output circuit 12 also outputs a fourth bias voltage VB2 and supplies it to the gate electrode of the second transistor 403 via the second bias line 14 and the second bias control circuit 401.

[0041] A second holding circuit 404 is electrically connected to the gate electrode of the second transistor 403. The second holding circuit 404 includes a capacitive element (second capacitive element) and functions as a sample-and-hold circuit. The second bias control circuit 401 controls the electrical connection between the second bias line 14 and the gate electrode of the second transistor 403 and the second holding circuit 404. In other words, it can be said that the second bias control circuit 401 controls the fourth bias voltage VB2. The capacitance value of the capacitive element included in the second holding circuit 404 is preferably 100 fF to 800 fF. More preferably, the capacitance value of the capacitive element included in the second holding circuit 404 is preferably 200 fF to 600 fF.

[0042] While the first holding circuit 204 is provided corresponding to each of the plurality of pixels 2, the second holding circuit 404 is provided corresponding to the output line 4 to which the plurality of pixels 2 provided for each column are electrically connected. Therefore, by making the capacitance value of the capacitive element (second capacitive element) included in the second holding circuit 404 larger than the capacitance value of the capacitive element (first capacitive element) included in the first holding circuit 204, it is possible to suppress the characteristic variation for each column in which the pixels 2 are arranged.

[0043] While the second reset transistor 307 is off, the pixel signal held in at least one of the N signal memory circuit 304, the first S signal memory circuit 305, and the second S signal memory circuit 306 is output. At this timing, the voltage of the source electrode of the second selection transistor 309 fluctuates, causing the voltage of the second bias line 14 to fluctuate due to capacitive coupling. At this time, the second bias line 14 is electrically connected to the gate electrode of the second transistor 403. Due to the influence of the voltage fluctuation of the second bias line 14, the fourth bias voltage VB2 supplied to the gate electrode of the second transistor 403 varies among the multiple output lines 4, degrading the quality of the signal obtained from the photoelectric conversion device. Furthermore, the image quality of the image using the signal obtained from the photoelectric conversion device is degraded.

[0044] Therefore, in this embodiment, while the second reset transistor 307 is on, a sampling operation is performed under the control of the second bias control circuit 401 to electrically connect the second bias line 14 to the gate electrode of the second transistor 403 and the second holding circuit 404. While the second reset transistor 307 is on, voltage fluctuations at the source electrode of the second selection transistor 309 are smaller than during periods when pixel signals are output from at least one of the N signal memory circuit 304, the first S signal memory circuit 305, and the second S signal memory circuit 306. Then, while the second reset transistor 307 is off, the pixel signal held in at least one of the N signal memory circuit 304, the first S signal memory circuit 305, and the second S signal memory circuit 306 is output. At this timing, a hold operation is performed under the control of the second bias control circuit 401 to electrically disconnect the second bias line 14 from the gate electrode of the second transistor 403 and the second holding circuit 404. This suppresses fluctuations in the fourth bias voltage VB2 caused by voltage fluctuations on the second bias line 14, thereby suppressing variations in pixel signals output from pixels arranged in different columns. That is, the quality of signals obtained from the photoelectric conversion device is improved. Furthermore, suppressing variations in pixel signals output from pixels arranged in different columns reduces degradation in image quality of images using signals obtained from the photoelectric conversion device.

[0045] The signal processing circuit 9 has a plurality of AD conversion circuits (analog-to-digital conversion circuits) 500 corresponding to each column on which a plurality of pixels 2 are arranged. The third bias output circuit 13 outputs a bias voltage for operating the AD conversion circuits 500. The bias voltage output from the third bias output circuit 13 is supplied to the AD conversion circuits 500 via a third bias line 15.

[0046] A first power supply voltage line VDD1, a second power supply voltage line VDD2, and a third power supply voltage line VDD3 are arranged to supply power supply voltages to the pixels 2, the amplifier circuit 8, and the signal processing circuit 9. A first reference voltage line GND1, a second reference voltage line GND2, and a third reference voltage line GND3 are arranged to supply reference voltages to the pixels 2, the amplifier circuit 8, and the signal processing circuit 9. The first power supply voltage line VDD1, the second power supply voltage line VDD2, and the third power supply voltage line VDD3 may or may not be electrically connected to each other. The first reference voltage line GND1, the second reference voltage line GND2, and the third reference voltage line GND3 may or may not be electrically connected to each other.

[0047] FIG. 3 is a schematic diagram of an example of a photoelectric conversion device according to this embodiment. FIG. 3(a) is a perspective view of the photoelectric conversion device as viewed from the light incident surface side of the first substrate 1000. FIG. 3(b) is a plan view of the first substrate 1000 as viewed from the light incident surface of the first substrate 1000. FIG. 3(c) is a plan view of the second substrate 2000 as viewed from the light incident surface of the first substrate 1000 (second substrate 2000). As shown in FIG. 3(a), the photoelectric conversion device has a configuration in which multiple substrates including the first substrate 1000 and the second substrate 2000 are stacked.

[0048] As shown in FIG. 3(b), the first holding circuit 204 (first capacitance element) and the first junction HB1 are arranged corresponding to each of the plurality of pixels 2. Each of the plurality of pixels 2 is electrically connected to the second substrate 2000 via each of the plurality of first junctions HB1. In a plan view, at least a portion of each first junction HB1 overlaps with at least a portion of each pixel 2 corresponding to the first junction HB1. The arrangement of the first holding circuit 204 and the first junction HB1 is not limited to that shown in FIG. 3(b). Although FIG. 3(b) does not show components included in the pixel 2 other than the first holding circuit 204, these components may be arranged in the pixel 2.

[0049] As shown in FIG. 3(c), the second junctions HB2 are arranged corresponding to each of the plurality of pixels 2. Each of the plurality of amplifier circuits 8 is electrically connected to the first substrate 1000 via each of the plurality of second junctions HB2. In a plan view, at least a portion of each second junction HB2 overlaps with at least a portion of each first junction HB1 corresponding to each second junction HB2. The arrangement of the second junctions HB2 is not limited to that shown in FIG. 3(c). Although FIG. 3(c) does not show components included in the amplifier circuit 8, these components may be arranged within the amplifier circuit 8.

[0050] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0051] A photoelectric conversion device according to a modified example of the first embodiment of the present invention will be described with reference to Fig. 4. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0052] The modified example of the first embodiment differs from the first embodiment in that a single photoelectric conversion element is arranged instead of multiple ones. Fig. 4 is an example of a circuit diagram of the pixel 2, amplifier circuit 8, and signal processing circuit 9 of the photoelectric conversion device according to this modified example.

[0053] 4, the photoelectric conversion circuit 100 included in the pixel 2 has a first photoelectric conversion element PD1 and a first transfer transistor 101. The pixel memory circuit 300 included in the pixel 2 has an N signal transistor 301, a first S signal transistor 302, an N signal memory circuit 304, and a first S signal memory circuit 305. The first holding circuit 204 of the pixel amplifier circuit 200 included in the pixel 2 includes a first capacitance element, similar to the first embodiment.

[0054] In this modification, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0055] Second Embodiment A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Figures 5 and 6. Note that components similar to those in the first embodiment are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0056] This embodiment differs from the first embodiment in that a first holding circuit 204 including a first capacitance element is arranged on a second substrate 2000. Fig. 5 is an example of a circuit diagram of the pixel 2, amplifier circuit 8, and signal processing circuit 9 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0057] As shown in FIG. 5 , the first substrate 1000 is electrically connected to the second substrate 2000 via a third joint HB3 provided on the first substrate 1000 and a fourth joint HB4 provided on the second substrate 2000. The bonding of the substrates using the third joint HB3 and the fourth joint HB4 is not limited to hybrid bonding. The substrates may be bonded by other methods, and the first substrate 1000 and the second substrate 2000 may be electrically connected using conductive vias or bumps. In this embodiment, the first holding circuit 204 is disposed on the second substrate 2000, not on the first substrate 1000. The first holding circuit 204 is connected to a fourth reference voltage line GND4, and a reference voltage is supplied to the first holding circuit 204. The first reference voltage line GND1, the second reference voltage line GND2, the third reference voltage line GND3, and the fourth reference voltage line GND4 may or may not be electrically connected to each other.

[0058] 6A and 6B are schematic diagrams of an example of a photoelectric conversion device according to this embodiment, and Fig. 6A is a plan view of the first substrate 1000 as viewed from the light incident surface of the first substrate 1000. Fig. 6B is a plan view of the second substrate 2000 as viewed from the light incident surface of the first substrate 1000 (second substrate 2000).

[0059] As shown in FIG. 6(a), a first junction HB1, which is bonded to a second junction HB2 (described later), and a third junction HB3, which is bonded to a fourth junction HB4 (described later), are disposed corresponding to each of the plurality of pixels 2. Each of the plurality of pixels 2 is electrically connected to the second substrate 2000 via each of the plurality of first junctions HB1 and each of the plurality of third junctions HB3. In a plan view, at least a portion of each first junction HB1 overlaps with at least a portion of each pixel 2 corresponding to the first junction HB1. In a plan view, at least a portion of each third junction HB3 overlaps with at least a portion of each pixel 2 corresponding to the third junction HB3. The arrangement of the first junction HB1 and the third junction HB3 is not limited to that shown in FIG. 6(a). Although FIG. 6(a) does not illustrate components included in the pixel 2, these components may be disposed within the pixel 2.

[0060] As shown in FIG. 6(b), the first holding circuit 204, the second junction HB2, and the fourth junction HB4 are arranged corresponding to each of the multiple pixels 2. Each of the multiple amplifier circuits 8 is electrically connected to the first substrate 1000 via each of the multiple second junctions HB2 and each of the multiple fourth junctions HB4. In a plan view, at least a portion of each second junction HB2 overlaps with at least a portion of each first junction HB1 corresponding to each second junction HB2. In a plan view, at least a portion of each fourth junction HB4 overlaps with at least a portion of each third junction HB3 corresponding to each fourth junction HB4. The arrangement of the first holding circuit 204, the second junction HB2, and the fourth junction HB4 is not limited to that shown in FIG. 6(b). Although FIG. 6(b) does not illustrate components included in the amplifier circuit 8, these components may be arranged within the amplifier circuit 8.

[0061] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0062] Furthermore, in this embodiment, the first holding circuit 204 is disposed on the second substrate 2000, so that the area of ​​the pixel array 1 disposed on the first substrate 1000 can be increased compared to the first embodiment. This makes it possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device.

[0063] Third Embodiment A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Figures 7 and 8. Note that components similar to those in the first and second embodiments are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0064] This embodiment differs from the first and second embodiments in that the first holding circuit 204 is shared by two pixels 2. Fig. 7 is an example of a circuit diagram of the pixel 2, amplifier circuit 8, and signal processing circuit 9 of the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0065] FIG. 7 shows two columns of pixels 2 arranged in the same row (a first pixel 2-1 arranged in the first column and a second pixel 2-2 arranged in the second column). FIG. 7 also shows two columns of amplifier circuits 8 arranged in the same row (a first amplifier circuit 8-1 arranged in the first column and a second amplifier circuit 8-2 arranged in the second column). FIG. 7 also shows two columns of AD conversion circuits 500 arranged in the same row (a first AD conversion circuit 500-1 arranged in the first column and a second AD conversion circuit 500-2 arranged in the second column). In order to distinguish between the components arranged in the first and second columns, identification numbers (1, 2) are added to the end of the reference numerals of the components. Hereinafter, when it is necessary to distinguish between components arranged in different columns, an identification number is added to the end of the reference numeral of the component. However, when it is not necessary to distinguish between components arranged in different columns, the identification number at the end of the reference numeral of the component may be omitted.

[0066] 7, the first pixel 2-1 and the second pixel 2-2 share the first holding circuit 204. Note that the first column and the second column may be adjacent columns.

[0067] FIG. 8 is an example of a plan view of a pixel 2 included in the photoelectric conversion device according to this embodiment.

[0068] As shown in FIG. 8 , the first holding circuit 204 is arranged between the first pixel 2-1 and the second pixel 2-2 in a planar view. Specifically, the first holding circuit 204 may be arranged between the first photoelectric conversion element PD1-1 and the first photoelectric conversion element PD1-2 in a planar view. Specifically, the first holding circuit 204 may be arranged between the second photoelectric conversion element PD2-1 and the second photoelectric conversion element PD2-2 in a planar view. Specifically, the first holding circuit 204 may be arranged between the first transfer transistor 101-1 and the first transfer transistor 101-2 in a planar view. Specifically, the first holding circuit 204 may be arranged between the second transfer transistor 102-1 and the second transfer transistor 102-2 in a planar view. Specifically, the first holding circuit 204 may be arranged between the first reset transistor 103-1 and the first reset transistor 103-2 in a planar view. Specifically, in a plan view, the first holding circuit 204 may be arranged between the first amplification transistor 104-1 and the first amplification transistor 104-2. Specifically, in a plan view, the first holding circuit 204 may be arranged between the first selection transistor 105-1 and the first selection transistor 105-2. Specifically, in a plan view, the first holding circuit 204 may be arranged between the first bias control circuit 201-1 and the first bias control circuit 201-2. Specifically, in a plan view, the first holding circuit 204 may be arranged between the first cascode transistor 202-1 and the first cascode transistor 202-2. Specifically, in a plan view, the first holding circuit 204 may be arranged between the first transistor 203-1 and the first transistor 203-2. Specifically, in a plan view, the first holding circuit 204 may be arranged between the pixel memory circuit 300-1 and the pixel memory circuit 300-2. In addition, in plan view, the first holding circuit 204 may be disposed between the first joint HB1-1 and the first joint HB1-2.

[0069] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0070] Furthermore, in this embodiment, by sharing the first holding circuit 204 between two pixels 2, it is possible to increase the area of ​​at least one of the photoelectric conversion circuit 100 and the pixel memory circuit 300 arranged on the first substrate 1000. When the area of ​​the photoelectric conversion circuit 100 is increased, it is possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device. Furthermore, when the area of ​​the pixel memory circuit 300 is increased, it is possible to reduce leakage from a capacitive element included in the pixel memory circuit 300, thereby improving the performance of the photoelectric conversion device.

[0071] In this embodiment, multiple pixels 2 arranged in two columns share one first holding circuit 204, but multiple pixels 2 arranged in three or more columns may also share one first holding circuit 204.

[0072] Note that the first holding circuit 204 may be shared by two rows of pixels 2 (first and second rows) arranged in the same column, rather than by two columns of pixels 2 arranged in the same row. In this case, the two rows of pixels 2 arranged in the same column are electrically connected to one amplifier circuit 8 and one AD conversion circuit 500. In this case, the first and second rows may be adjacent rows.

[0073] Fourth Embodiment A photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to Figures 9 and 10. Note that components similar to those in the first to third embodiments are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0074] This embodiment differs from the first to third embodiments in that the first holding circuit 204 is shared by four pixels 2. Fig. 9 is an example of a circuit diagram of the pixels 2, amplifier circuits 8, and signal processing circuits 9 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0075] FIG. 9 shows a first pixel 2-1 arranged in the first row and first column, a second pixel 2-2 arranged in the first row and second column, a third pixel 2-3 arranged in the second row and first column, and a fourth pixel 2-4 arranged in the second row and second column. FIG. 9 also shows a first amplifier circuit 8-1 arranged in the first column and a second amplifier circuit 8-2 arranged in the second column. FIG. 9 also shows a first AD conversion circuit 500-1 arranged in the first column and a second AD conversion circuit 500-2 arranged in the second column. Note that, to distinguish the components arranged in the first row and first column, the first row and second column, the second row and first column, and the second row and second column from one another, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals of the components. Hereinafter, when it is necessary to distinguish components arranged in different rows and columns from one another, identification numbers are added to the end of the reference numerals of the components. However, when it is not necessary to distinguish between elements arranged in different rows and columns, the identification number at the end of the element reference number may be omitted.

[0076] 9, the first pixel 2-1, the second pixel 2-2, the third pixel 2-3, and the fourth pixel 2-4 share the first holding circuit 204. Note that the first column and the second column may be adjacent columns, and the first row and the second row may be adjacent rows.

[0077] FIG. 10 is an example of a plan view of a pixel 2 included in the photoelectric conversion device according to this embodiment.

[0078] 10 , in a plan view, the first holding circuit 204 is arranged in a region surrounded by the first pixel 2-1, the second pixel 2-2, the third pixel 2-3, and the fourth pixel 2-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first photoelectric conversion element PD1-1, the first photoelectric conversion element PD1-2, the first photoelectric conversion element PD1-3, and the first photoelectric conversion element PD1-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the second photoelectric conversion element PD2-1, the second photoelectric conversion element PD2-2, the second photoelectric conversion element PD2-3, and the second photoelectric conversion element PD2-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first transfer transistor 101-1, the first transfer transistor 101-2, the first transfer transistor 101-3, and the first transfer transistor 101-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the second transfer transistor 102-1, the second transfer transistor 102-2, the second transfer transistor 102-3, and the second transfer transistor 102-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first reset transistor 103-1, the first reset transistor 103-2, the first reset transistor 103-3, and the first reset transistor 103-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first amplification transistor 104-1, the first amplification transistor 104-2, the first amplification transistor 104-3, and the first amplification transistor 104-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first selection transistor 105-1, the first selection transistor 105-2, the first selection transistor 105-3, and the first selection transistor 105-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first bias control circuit 201-1, the first bias control circuit 201-2, the first bias control circuit 201-3, and the first bias control circuit 201-4.Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first cascode transistor 202-1, the first cascode transistor 202-2, the first cascode transistor 202-3, and the first cascode transistor 202-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first transistor 203-1, the first transistor 203-2, the first transistor 203-3, and the first transistor 203-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the pixel memory circuit 300-1, the pixel memory circuit 300-2, the pixel memory circuit 300-3, and the pixel memory circuit 300-4. Furthermore, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first junction HB1-1, the first junction HB1-2, the first junction HB1-3, and the first junction HB1-4.

[0079] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0080] Furthermore, in this embodiment, by sharing the first holding circuit 204 among four pixels 2, it is possible to increase the area of ​​at least one of the photoelectric conversion circuit 100 and the pixel memory circuit 300 arranged on the first substrate 1000. When the area of ​​the photoelectric conversion circuit 100 is increased, it is possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device. Furthermore, when the area of ​​the pixel memory circuit 300 is increased, it is possible to reduce leakage from a capacitive element included in the pixel memory circuit 300, thereby improving the performance of the photoelectric conversion device.

[0081] In this embodiment, a plurality of pixels 2 arranged in two rows and two columns share one first holding circuit 204, but a plurality of pixels 2 arranged in a matrix of more than two rows and two columns may share one first holding circuit 204. A matrix of more than two rows and two columns means, for example, two rows and three columns, three rows and two columns, or three rows and three columns.

[0082] Fifth Embodiment A photoelectric conversion device according to a fifth embodiment of the present invention will be described with reference to Figures 11 and 12. Note that the same components as those in the first to fourth embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0083] This embodiment is a combination of the second and third embodiments.

[0084] 11 is an example of a circuit diagram of the pixel 2, amplifier circuit 8, and signal processing circuit 9 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0085] 11, the first holding circuit 204 is disposed on the second substrate 2000. The first pixel 2-1 and the second pixel 2-2 share the first holding circuit 204.

[0086] FIG. 12 is an example of a plan view of the amplifier circuit 8 included in the photoelectric conversion device according to this embodiment.

[0087] As shown in FIG. 12 , in a plan view, the first holding circuit 204 is arranged between the amplifier circuit 8 corresponding to the first pixel 2-1 and the amplifier circuit 8 corresponding to the second pixel 2-2. Specifically, in a plan view, the first holding circuit 204 may be arranged between the second bias control circuit 401-1 and the second bias control circuit 401-2. Specifically, in a plan view, the first holding circuit 204 may be arranged between the second cascode transistor 402-1 and the second cascode transistor 402-2. Specifically, in a plan view, the first holding circuit 204 may be arranged between the second transistor 403-1 and the second transistor 403-2. Specifically, in a plan view, the first holding circuit 204 may be arranged between the second holding circuit 404-1 and the second holding circuit 404-2. Furthermore, in a plan view, the first holding circuit 204 may be arranged between the AD conversion circuit 500-1 and the AD conversion circuit 500-2. In addition, in plan view, the first holding circuit 204 may be disposed between the second joint HB2-1 and the second joint HB2-2.

[0088] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0089] Furthermore, in this embodiment, the area of ​​the pixel array 1 arranged on the first substrate 1000 can be expanded by arranging the first holding circuit 204 on the second substrate 2000. This makes it possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device.

[0090] Furthermore, in this embodiment, by sharing the first holding circuit 204 between two pixels 2, it is possible to increase the area of ​​at least one of the photoelectric conversion circuit 100 and the pixel memory circuit 300 arranged on the first substrate 1000. When the area of ​​the photoelectric conversion circuit 100 is increased, it is possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device. Furthermore, when the area of ​​the pixel memory circuit 300 is increased, it is possible to reduce leakage from a capacitive element included in the pixel memory circuit 300, thereby improving the performance of the photoelectric conversion device.

[0091] Sixth Embodiment A photoelectric conversion device according to the sixth embodiment of the present invention will be described with reference to Fig. 13. Note that the same components as those in the first to fifth embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0092] This embodiment is a combination of the second and fourth embodiments.

[0093] 13 is an example of a circuit diagram of the pixel 2, amplifier circuit 8, and signal processing circuit 9 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0094] 13, the first holding circuit 204 is disposed on the second substrate 2000. The first pixel 2-1, the second pixel 2-2, the third pixel 2-3, and the fourth pixel 2-4 share the first holding circuit 204.

[0095] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0096] Furthermore, in this embodiment, the area of ​​the pixel array 1 arranged on the first substrate 1000 can be expanded by arranging the first holding circuit 204 on the second substrate 2000. This makes it possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device.

[0097] Furthermore, in this embodiment, by sharing the first holding circuit 204 among four pixels 2, it is possible to increase the area of ​​at least one of the photoelectric conversion circuit 100 and the pixel memory circuit 300 arranged on the first substrate 1000. When the area of ​​the photoelectric conversion circuit 100 is increased, it is possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device. Furthermore, when the area of ​​the pixel memory circuit 300 is increased, it is possible to reduce leakage from a capacitive element included in the pixel memory circuit 300, thereby improving the performance of the photoelectric conversion device.

[0098] Seventh Embodiment A photoelectric conversion device according to the seventh embodiment of the present invention will be described with reference to Figures 14 and 15. Note that the same components as those in the first to sixth embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0099] This embodiment differs from the first to sixth embodiments in that it has a third substrate 3000 in addition to a first substrate 1000 and a second substrate 2000. Fig. 14 is an example of a circuit diagram of the pixels 2, amplifier circuits 8, and signal processing circuits 9 of the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0100] As shown in FIG. 14 , the photovoltaic device includes three substrates: a first substrate 1000, a second substrate 2000, and a third substrate 3000. The photovoltaic device has a three-dimensional structure formed by bonding these three substrates together. The first substrate 1000 and the third substrate 3000 are stacked, for example, by hybrid bonding. The first substrate 1000 is electrically connected to the third substrate 3000 via a fifth bonding portion HB5 provided on the first substrate 1000 and a sixth bonding portion HB6 provided on the third substrate 3000. The bonding of the substrates using the fifth bonding portion HB5, the sixth bonding portion HB6, and the like is not limited to hybrid bonding. The substrates may be bonded by other methods, and the first substrate 1000 and the third substrate 3000 may be electrically connected using conductive vias, bumps, or the like. In this embodiment, a pixel 2A, which is a part of the pixel 2, is arranged on a first substrate 1000, and an amplifier circuit 8, a signal processing circuit 9, an output circuit 10, a second bias output circuit 12, and a third bias output circuit 13 are arranged on a second substrate 2000. A first bias output circuit 11 and a pixel 2B, which is another part of the pixel 2, are arranged on a third substrate 3000. Note that the first substrate 1000, the second substrate 2000, and the third substrate 3000 may each be a semiconductor substrate such as a silicon substrate.

[0101] Fig. 15 is a schematic diagram of an example of a photoelectric conversion device according to this embodiment. Fig. 15 is a perspective view of the photoelectric conversion device as viewed from the light incident surface side of the first substrate 1000. As shown in Fig. 15, the photoelectric conversion device has a configuration in which multiple substrates including a first substrate 1000, a second substrate 2000, and a third substrate 3000 are stacked.

[0102] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0103] Furthermore, in this embodiment, pixel 2 is divided into pixel 2A and pixel 2B, and each pixel is arranged on a different substrate, thereby enabling the areas of photoelectric conversion circuit 100 and pixel memory circuit 300 to be increased. By increasing the area of ​​photoelectric conversion circuit 100, it becomes possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device. Furthermore, by increasing the area of ​​pixel memory circuit 300, it becomes possible to reduce leakage from a capacitive element included in pixel memory circuit 300, thereby improving the performance of the photoelectric conversion device.

[0104] Eighth Embodiment A photoelectric conversion device according to an eighth embodiment of the present invention will be described with reference to Fig. 16. Note that components similar to those in the first to seventh embodiments are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0105] This embodiment is a combination of the second and seventh embodiments.

[0106] 16 is an example of a circuit diagram of the pixel 2, amplifier circuit 8, and signal processing circuit 9 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0107] 16, the first holding circuit 204 is arranged on the second substrate 2000. In addition, a pixel 2A, which is a part of the pixel 2, is arranged on the first substrate 1000. In addition, a first bias output circuit 11 and a pixel 2B, which is another part of the pixel 2, are arranged on the third substrate 3000.

[0108] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0109] Furthermore, in this embodiment, pixel 2 is divided into pixel 2A and pixel 2B, and each pixel is arranged on a different substrate, thereby enabling the areas of photoelectric conversion circuit 100 and pixel memory circuit 300 to be increased. By increasing the area of ​​photoelectric conversion circuit 100, it becomes possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device. Furthermore, by increasing the area of ​​pixel memory circuit 300, it becomes possible to reduce leakage from a capacitive element included in pixel memory circuit 300, thereby improving the performance of the photoelectric conversion device.

[0110] Furthermore, in this embodiment, the area of ​​the pixel memory circuit 300 arranged on the third substrate 3000 can be expanded by arranging the first holding circuit 204 on the second substrate 2000. This makes it possible to reduce leakage from the capacitive elements included in the pixel memory circuit 300, improving the performance of the photoelectric conversion device.

[0111] Ninth Embodiment A photoelectric conversion device according to a ninth embodiment of the present invention will be described with reference to Figures 17 and 18. Note that the same components as those in the first to eighth embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0112] This embodiment is a combination of the third and seventh embodiments.

[0113] 17 is an example of a circuit diagram of the pixel 2, amplifier circuit 8, and signal processing circuit 9 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0114] 17, the first pixel 2-1 and the second pixel 2-2 share the first holding circuit 204. In addition, pixels 2A-1 and 2A-2, which are part of the pixel 2, are arranged on the first substrate 1000. In addition, the first bias output circuit 11 and pixels 2B-1 and 2B-2, which are other parts of the pixel 2, are arranged on the third substrate 3000.

[0115] FIG. 18 is an example of a plan view of a pixel 2B included in the photoelectric conversion device according to this embodiment.

[0116] 18 , the first holding circuit 204 is arranged between the first pixel 2B-1 and the second pixel 2B-2 in a planar view. Specifically, the first holding circuit 204 may be arranged between the first bias control circuit 201-1 and the first bias control circuit 201-2 in a planar view. Specifically, the first holding circuit 204 may be arranged between the first cascode transistor 202-1 and the first cascode transistor 202-2 in a planar view. Specifically, the first holding circuit 204 may be arranged between the first transistor 203-1 and the first transistor 203-2 in a planar view. Specifically, the first holding circuit 204 may be arranged between the pixel memory circuit 300-1 and the pixel memory circuit 300-2 in a planar view. Furthermore, the first holding circuit 204 may be arranged between the first junction HB1-1 and the first junction HB1-2 in a planar view. In addition, in plan view, the first holding circuit 204 may be disposed between the sixth joint HB6-1 and the sixth joint HB6-2.

[0117] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0118] Furthermore, in this embodiment, pixel 2 is divided into pixel 2A and pixel 2B, and each pixel is arranged on a different substrate, thereby enabling the areas of photoelectric conversion circuit 100 and pixel memory circuit 300 to be increased. By increasing the area of ​​photoelectric conversion circuit 100, it becomes possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device. Furthermore, by increasing the area of ​​pixel memory circuit 300, it becomes possible to reduce leakage from a capacitive element included in pixel memory circuit 300, thereby improving the performance of the photoelectric conversion device.

[0119] Furthermore, in this embodiment, the area of ​​the pixel memory circuit 300 arranged on the third substrate 3000 can be expanded by sharing the first holding circuit 204 between two pixels 2. This makes it possible to reduce leakage from the capacitive element included in the pixel memory circuit 300, improving the performance of the photoelectric conversion device.

[0120] Tenth Embodiment A photoelectric conversion device according to a tenth embodiment of the present invention will be described with reference to Figures 19 and 20. Note that the same components as those in the first to ninth embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0121] This embodiment is a combination of the fourth and seventh embodiments.

[0122] 19 is an example of a circuit diagram of the pixel 2, amplifier circuit 8, and signal processing circuit 9 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0123] 19, the first pixel 2-1, the second pixel 2-2, the third pixel 2-3, and the fourth pixel 2-4 share the first holding circuit 204. Pixels 2A-1, 2A-2, 2A-3, and 2A-4, which are part of the pixel 2, are arranged on the first substrate 1000. Pixels 2B-1, 2B-2, 2B-3, and 2B-4, which are another part of the pixel 2, are arranged on the third substrate 3000.

[0124] FIG. 20 is an example of a plan view of a pixel 2B included in the photoelectric conversion device according to this embodiment.

[0125] 20 , in a plan view, the first holding circuit 204 is arranged in a region surrounded by the first pixel 2B-1, the second pixel 2B-2, the third pixel 2B-3, and the fourth pixel 2B-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first bias control circuit 201-1, the first bias control circuit 201-2, the first bias control circuit 201-3, and the first bias control circuit 201-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first cascode transistor 202-1, the first cascode transistor 202-2, the first cascode transistor 202-3, and the first cascode transistor 202-4. Specifically, in a plan view, the first holding circuit 204 may be arranged in a region surrounded by the first transistor 203-1, the first transistor 203-2, the first transistor 203-3, and the first transistor 203-4. Specifically, in a plan view, the first retaining circuit 204 may be arranged in a region surrounded by the pixel memory circuit 300-1, the pixel memory circuit 300-2, the pixel memory circuit 300-3, and the pixel memory circuit 300-4. Also, in a plan view, the first retaining circuit 204 may be arranged in a region surrounded by the first junction HB1-1, the first junction HB1-2, the first junction HB1-3, and the first junction HB1-4. Also, in a plan view, the first retaining circuit 204 may be arranged in a region surrounded by the sixth junction HB6-1, the sixth junction HB6-2, the sixth junction HB6-3, and the sixth junction HB6-4.

[0126] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0127] Furthermore, in this embodiment, pixel 2 is divided into pixel 2A and pixel 2B, and each pixel is arranged on a different substrate, thereby enabling the areas of photoelectric conversion circuit 100 and pixel memory circuit 300 to be increased. By increasing the area of ​​photoelectric conversion circuit 100, it becomes possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device. Furthermore, by increasing the area of ​​pixel memory circuit 300, it becomes possible to reduce leakage from a capacitive element included in pixel memory circuit 300, thereby improving the performance of the photoelectric conversion device.

[0128] Furthermore, in this embodiment, the area of ​​the pixel memory circuit 300 arranged on the third substrate 3000 can be expanded by sharing the first holding circuit 204 among four pixels 2. This makes it possible to reduce leakage from the capacitive element included in the pixel memory circuit 300, improving the performance of the photoelectric conversion device.

[0129] Eleventh Embodiment A photoelectric conversion device according to an eleventh embodiment of the present invention will be described with reference to Fig. 21. Note that components similar to those in the first to tenth embodiments are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0130] This embodiment is a combination of the fifth and seventh embodiments.

[0131] 21 is an example of a circuit diagram of the pixel 2, amplifier circuit 8, and signal processing circuit 9 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0132] 21 , the first holding circuit 204 is arranged on the second substrate 2000. The first pixel 2-1 and the second pixel 2-2 share the first holding circuit 204. The first substrate 1000 has a pixel 2A, which is a part of the pixel 2, arranged thereon, and the third substrate 3000 has a pixel 2B, which is another part of the pixel 2, and a first bias output circuit 11 arranged thereon.

[0133] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0134] Furthermore, in this embodiment, pixel 2 is divided into pixel 2A and pixel 2B, and each pixel is arranged on a different substrate, thereby enabling the areas of photoelectric conversion circuit 100 and pixel memory circuit 300 to be increased. By increasing the area of ​​photoelectric conversion circuit 100, it becomes possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device. Furthermore, by increasing the area of ​​pixel memory circuit 300, it becomes possible to reduce leakage from a capacitive element included in pixel memory circuit 300, thereby improving the performance of the photoelectric conversion device.

[0135] Furthermore, in this embodiment, the area of ​​the pixel memory circuit 300 arranged on the third substrate 3000 can be expanded by arranging the first holding circuit 204 on the second substrate 2000. This makes it possible to reduce leakage from the capacitive elements included in the pixel memory circuit 300, improving the performance of the photoelectric conversion device.

[0136] Furthermore, in this embodiment, the area of ​​the pixel memory circuit 300 arranged on the third substrate 3000 can be expanded by sharing the first holding circuit 204 between two pixels 2. This makes it possible to reduce leakage from the capacitive element included in the pixel memory circuit 300, improving the performance of the photoelectric conversion device.

[0137] Twelfth Embodiment A photoelectric conversion device according to the twelfth embodiment of the present invention will be described with reference to Fig. 22. Note that the same components as those in the first to eleventh embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0138] This embodiment is a combination of the sixth and seventh embodiments.

[0139] 22 is an example of a circuit diagram of the pixel 2, amplifier circuit 8, and signal processing circuit 9 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0140] 22, the first holding circuit 204 is arranged on the second substrate 2000. The first pixel 2-1, the second pixel 2-2, the third pixel 2-3, and the fourth pixel 2-4 share the first holding circuit 204. The pixel 2A, which is a part of the pixel 2, is arranged on the first substrate 1000, and the pixel 2B, which is another part of the pixel 2, and the first bias output circuit 11 are arranged on the third substrate 3000.

[0141] In this embodiment, the quality of the signal output from the photoelectric conversion device is improved by providing a first holding circuit 204 that performs a sample-and-hold operation to the gate electrode of the first transistor 203. Furthermore, degradation of the image quality of an image using a signal obtained from the photoelectric conversion device is reduced.

[0142] Furthermore, in this embodiment, pixel 2 is divided into pixel 2A and pixel 2B, and each pixel is arranged on a different substrate, thereby enabling the areas of photoelectric conversion circuit 100 and pixel memory circuit 300 to be increased. By increasing the area of ​​photoelectric conversion circuit 100, it becomes possible to improve the utilization efficiency of incident light, thereby improving the performance of the photoelectric conversion device. Furthermore, by increasing the area of ​​pixel memory circuit 300, it becomes possible to reduce leakage from a capacitive element included in pixel memory circuit 300, thereby improving the performance of the photoelectric conversion device.

[0143] Furthermore, in this embodiment, the area of ​​the pixel memory circuit 300 arranged on the third substrate 3000 can be expanded by arranging the first holding circuit 204 on the second substrate 2000. This makes it possible to reduce leakage from the capacitive elements included in the pixel memory circuit 300, improving the performance of the photoelectric conversion device.

[0144] Furthermore, in this embodiment, the area of ​​the pixel memory circuit 300 arranged on the third substrate 3000 can be expanded by sharing the first holding circuit 204 among four pixels 2. This makes it possible to reduce leakage from the capacitive element included in the pixel memory circuit 300, improving the performance of the photoelectric conversion device.

[0145] Thirteenth Embodiment The thirteenth embodiment is applicable to any of the first to twelfth embodiments. FIG. 23(a) is a schematic diagram illustrating an apparatus 9191 including a semiconductor device 930 according to this embodiment. The photoelectric conversion device according to any of the above-described embodiments can be used for the semiconductor device 930. The apparatus 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 may include a semiconductor device 910. The semiconductor device 930 may include, in addition to the semiconductor device 910, a package 920 that houses the semiconductor device 910. The package 920 may include a base to which the semiconductor device 910 is fixed and a lid such as glass that faces the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0146] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0147] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0148] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0149] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0150] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft (drone, aircraft). The mechanical device 990 in the transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0151] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0152] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0153] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 23(b) and 23(c).

[0154] FIG. 23(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 80 includes a photoelectric conversion device 800. The photoelectric conversion device 800 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 80 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 800, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 80. Here, the photoelectric conversion system 80 may include an optical system (not shown) that guides light to the photoelectric conversion device 800, such as a lens, shutter, or mirror. Furthermore, multiple photoelectric conversion units that are approximately conjugate with the pupil of the optical system may be arranged in pixels of the photoelectric conversion device 800. For example, the multiple photoelectric conversion units that are approximately conjugate with the pupil are arranged corresponding to one microlens. The photoelectric conversion units receive light beams that have passed through different positions of the pupil of the optical system, and the photoelectric conversion device 800 outputs image data corresponding to the light beams that have passed through the different positions. The parallax acquisition unit 802 may then calculate parallax using the output image data. The photoelectric conversion system 80 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. The distance information includes information about the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may use any of this distance information to determine the possibility of a collision. The distance information may be acquired using ToF (Time of Flight). The distance information acquisition means may be implemented by dedicated hardware or a software module. Furthermore, it may be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like, or may be realized by a combination of these.

[0155] The photoelectric conversion system 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 80 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0156] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 80. Fig. 23(c) shows the photoelectric conversion system 80 when imaging the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 80 or the photoelectric conversion device 800. This configuration can further improve the accuracy of distance measurement.

[0157] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as autonomous driving control to follow other vehicles and autonomous driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system 80 can be applied not only to automobiles and other vehicles, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generator that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generator can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, an aircraft's propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0158] As used herein, expressions such as "A or B," "at least one of A and B," "at least one of A or / and B," "one or more of A or / and B," and the like, include all possible combinations of the listed items unless expressly defined otherwise. That is, the above expressions are understood to disclose all cases, including cases containing at least one A, cases containing at least one B, and cases containing both at least one A and at least one B. This applies equally to combinations of three or more elements.

[0159] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0160] The disclosure of this embodiment includes the following configurations.

[0161] (Configuration 1) A photoelectric conversion device having a plurality of substrates including a first substrate and a second substrate, the photoelectric conversion device having a plurality of pixels each including a photoelectric conversion element that generates a charge according to the amount of light received, a floating diffusion that outputs a signal according to the charge, a first source follower circuit that amplifies the signal output from the floating diffusion, and a first transistor for driving the first source follower circuit, a first holding circuit electrically connected to the gate electrode of the first transistor, a second source follower circuit that amplifies the signal output from the first source follower circuit, and a signal processing circuit that processes the signal output from the second source follower circuit, wherein the photoelectric conversion element is arranged on the first substrate and the signal processing circuit is arranged on the second substrate.

[0162] (Configuration 2) The photoelectric conversion device according to Configuration 1, further comprising: a second transistor for driving the second source follower circuit; and a second holding circuit electrically connected to a gate electrode of the second transistor, wherein the capacitance value of the first capacitance element included in the first holding circuit is smaller than the capacitance value of the second capacitance element included in the second holding circuit.

[0163] (Configuration 3) The photoelectric conversion device according to configuration 1 or 2, wherein each of the plurality of pixels includes a memory circuit that holds the signal output from the first source follower circuit, and a capacitance value of a first capacitance element included in the first holding circuit is smaller than a capacitance value of a third capacitance element included in the memory circuit.

[0164] (Configuration 4) A photoelectric conversion device described in any one of configurations 1 to 3, characterized in that it comprises a bias output circuit that supplies a bias voltage to the gate electrode of the first transistor, and a bias control circuit that controls the connection relationship between the gate electrode and the bias output circuit, and the bias output circuit is electrically connected to the first holding circuit via the bias control circuit.

[0165] (Configuration 5) A photoelectric conversion device described in any one of configurations 1 to 4, characterized in that at the timing when the floating diffusion outputs a signal according to the charge, the bias control circuit electrically disconnects the gate electrode and the bias output circuit.

[0166] (Structure 6) The photoelectric conversion device described in any one of structures 1 to 5, characterized in that the plurality of pixels have a first pixel and a second pixel, and the first holding circuit is electrically connected to the gate electrode of the first transistor included in the first pixel and the gate electrode of the first transistor included in the second pixel.

[0167] (Configuration 7) The photoelectric conversion device according to any one of configurations 1 to 6, wherein the first pixel and the second pixel are adjacent to each other.

[0168] (Configuration 8) The photoelectric conversion device according to any one of configurations 1 to 7, wherein the first holding circuit is disposed between the first pixel and the second pixel in plan view.

[0169] (Structure 9) A photoelectric conversion device described in any one of structures 1 to 8, characterized in that, in a planar view, the first holding circuit is arranged between the photoelectric conversion element of the first pixel and the photoelectric conversion element of the second pixel.

[0170] (Structure 10) A photoelectric conversion device described in any one of structures 1 to 9, characterized in that it has a first bonding portion and a second bonding portion that bond the first substrate to a substrate different from the first substrate, and the first holding circuit is arranged between the first bonding portion that overlaps the first pixel and the second bonding portion that overlaps the second pixel in a planar view.

[0171] (Configuration 11) The photoelectric conversion device described in any one of configurations 1 to 10, characterized in that the plurality of pixels have a third pixel and a fourth pixel, the first pixel and the second pixel are arranged in a first row, the third pixel and the fourth pixel are arranged in a second row, the first pixel and the third pixel are arranged in a first column, and the second pixel and the fourth pixel are arranged in a second column, and the first holding circuit is electrically connected to the gate electrode of the first transistor included in the third pixel and the gate electrode of the first transistor included in the fourth pixel.

[0172] (Structure 12) A photoelectric conversion device described in any one of structures 1 to 11, characterized in that, in a planar view, the first holding circuit is arranged in an area surrounded by the first pixel, the second pixel, the third pixel, and the fourth pixel.

[0173] (Structure 13) The photoelectric conversion device described in any one of structures 1 to 12, characterized in that, in a planar view, the first holding circuit is arranged in an area surrounded by the photoelectric conversion element of the first pixel, the photoelectric conversion element of the second pixel, the photoelectric conversion element of the third pixel, and the photoelectric conversion element of the fourth pixel.

[0174] (Structure 14) A photoelectric conversion device described in any one of structures 1 to 13, characterized in that it has a first bonding portion, a second bonding portion, a third bonding portion, and a fourth bonding portion that bond the first substrate to a substrate different from the first substrate, and the first holding circuit is arranged in an area surrounded, in a planar view, by the first bonding portion that overlaps the first pixel, the second bonding portion that overlaps the second pixel, the third bonding portion that overlaps the third pixel, and the fourth bonding portion that overlaps the fourth pixel.

[0175] (Configuration 15) A photoelectric conversion device described in any one of configurations 1 to 14, characterized in that it has a plurality of the first holding circuits, and each of the plurality of first holding circuits is electrically connected to the gate electrode of the first transistor included in each of the plurality of pixels.

[0176] (Configuration 16) A photoelectric conversion device described in any one of configurations 1 to 15, characterized in that it has a second transistor for driving the second source follower circuit and a second holding circuit electrically connected to the gate electrode of the second transistor, and the first holding circuit and the second holding circuit are arranged on different substrates.

[0177] (Configuration 17) The photoelectric conversion device according to any one of configurations 1 to 16, wherein the first holding circuit is disposed on the first substrate, and the second holding circuit is disposed on the second substrate.

[0178] (Configuration 18) A photoelectric conversion device described in any one of configurations 1 to 17, characterized in that it has a second transistor for driving the second source follower circuit and a second holding circuit electrically connected to the gate electrode of the second transistor, and the first holding circuit and the second holding circuit are arranged on the same substrate.

[0179] (Configuration 19) The photoelectric conversion device according to any one of configurations 1 to 18, wherein the first holding circuit and the second holding circuit are disposed on the second substrate.

[0180] (Structure 20) A photoelectric conversion device described in any one of structures 1 to 19, characterized in that it includes a third substrate on which the first transistor is arranged, and the first substrate, the third substrate, and the second substrate are bonded in that order.

[0181] (Configuration 21) The photoelectric conversion device according to any one of configurations 1 to 20, wherein the signal processing circuit has an analog-to-digital conversion circuit.

[0182] (Configuration 22) The photoelectric conversion device according to any one of configurations 1 to 21, wherein the first transistor and the first holding circuit are supplied with a reference voltage from a common reference voltage line.

[0183] (Configuration 23) The photoelectric conversion device according to any one of configurations 1 to 22, wherein the first transistor and the first holding circuit are supplied with reference voltages from different reference voltage lines.

[0184] (Configuration 24) An apparatus comprising a photoelectric conversion device according to any one of configurations 1 to 23, further comprising at least one of an optical device that guides light to the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes signals output from the photoelectric conversion device, a display device that displays information obtained by the photoelectric conversion device, a memory device that stores information obtained by the photoelectric conversion device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. [Explanation of symbols]

[0185] PD1 First photoelectric conversion element 9 Signal Processing Circuit 104 first amplifying transistor 106 Floating Diffusion 203 First Transistor 204 1st holding circuit 308 First Amplifying Transistor 403 Second Transistor 1000 First board 2000 Second board

Claims

1. A photoelectric conversion device including a plurality of substrates including a first substrate and a second substrate, a plurality of pixels each including a photoelectric conversion element that generates a charge according to an amount of received light, a floating diffusion that outputs a signal according to the charge, a first source follower circuit that amplifies the signal output from the floating diffusion, and a first transistor for driving the first source follower circuit; a first holding circuit electrically connected to the gate electrode of the first transistor; a second source follower circuit that amplifies the signal output from the first source follower circuit; a signal processing circuit that processes a signal output from the second source follower circuit; and the photoelectric conversion element is disposed on the first substrate; The signal processing circuit is disposed on the second substrate. A photoelectric conversion device characterized by:

2. 2. The photoelectric conversion device according to claim 1, further comprising: a second transistor for driving the second source follower circuit; and a second holding circuit electrically connected to a gate electrode of the second transistor, wherein a capacitance value of a first capacitive element included in the first holding circuit is smaller than a capacitance value of a second capacitive element included in the second holding circuit.

3. 2. The photoelectric conversion device according to claim 1, wherein each of the plurality of pixels includes a memory circuit that holds the signal output from the first source follower circuit, and a capacitance value of a first capacitance element included in the first holding circuit is smaller than a capacitance value of a third capacitance element included in the memory circuit.

4. 2. The photoelectric conversion device according to claim 1, further comprising: a bias output circuit that supplies a bias voltage to the gate electrode of the first transistor; and a bias control circuit that controls a connection relationship between the gate electrode and the bias output circuit, wherein the bias output circuit is electrically connected to the first holding circuit via the bias control circuit.

5. 5. The photoelectric conversion device according to claim 4, wherein the bias control circuit electrically separates the gate electrode and the bias output circuit at a timing when the floating diffusion outputs a signal in accordance with the charge.

6. 2. The photoelectric conversion device according to claim 1, wherein the plurality of pixels include a first pixel and a second pixel, and the first holding circuit is electrically connected to the gate electrode of the first transistor included in the first pixel and the gate electrode of the first transistor included in the second pixel.

7. The photoelectric conversion device according to claim 6 , wherein the first pixel and the second pixel are adjacent to each other.

8. 7. The photoelectric conversion device according to claim 6, wherein the first holding circuit is disposed between the first pixel and the second pixel in a plan view.

9. 9. The photoelectric conversion device according to claim 8, wherein the first holding circuit is disposed between the photoelectric conversion element of the first pixel and the photoelectric conversion element of the second pixel in a plan view.

10. 9. The photoelectric conversion device according to claim 8, further comprising a first bonding portion and a second bonding portion that bond the first substrate to a substrate different from the first substrate, and wherein, in a planar view, the first holding circuit is arranged between the first bonding portion that overlaps the first pixel and the second bonding portion that overlaps the second pixel.

11. 7. The photoelectric conversion device according to claim 6, wherein the plurality of pixels include a third pixel and a fourth pixel, the first pixel and the second pixel are arranged in a first row, the third pixel and the fourth pixel are arranged in a second row, the first pixel and the third pixel are arranged in a first column, and the second pixel and the fourth pixel are arranged in a second column, and the first holding circuit is electrically connected to the gate electrode of the first transistor included in the third pixel and the gate electrode of the first transistor included in the fourth pixel.

12. 12. The photoelectric conversion device according to claim 11, wherein the first holding circuit is arranged in an area surrounded by the first pixel, the second pixel, the third pixel, and the fourth pixel in a planar view.

13. The photoelectric conversion device described in claim 12, characterized in that, in a planar view, the first holding circuit is arranged in an area surrounded by the photoelectric conversion element of the first pixel, the photoelectric conversion element of the second pixel, the photoelectric conversion element of the third pixel, and the photoelectric conversion element of the fourth pixel.

14. 13. The photoelectric conversion device according to claim 12, further comprising a first bonding portion, a second bonding portion, a third bonding portion, and a fourth bonding portion that bond the first substrate to a substrate different from the first substrate, and wherein, in a planar view, the first holding circuit is arranged in an area surrounded by the first bonding portion that overlaps the first pixel, the second bonding portion that overlaps the second pixel, the third bonding portion that overlaps the third pixel, and the fourth bonding portion that overlaps the fourth pixel.

15. 2. The photoelectric conversion device according to claim 1, further comprising a plurality of the first holding circuits, each of the plurality of first holding circuits being electrically connected to the gate electrode of the first transistor included in each of the plurality of pixels.

16. 2. The photoelectric conversion device according to claim 1, further comprising: a second transistor for driving the second source follower circuit; and a second holding circuit electrically connected to a gate electrode of the second transistor, wherein the first holding circuit and the second holding circuit are arranged on different substrates.

17. 17. The photoelectric conversion device according to claim 16, wherein the first holding circuit is disposed on the first substrate, and the second holding circuit is disposed on the second substrate.

18. 2. The photoelectric conversion device according to claim 1, further comprising: a second transistor for driving the second source follower circuit; and a second holding circuit electrically connected to a gate electrode of the second transistor, wherein the first holding circuit and the second holding circuit are arranged on the same substrate.

19. 19. The photoelectric conversion device according to claim 18, wherein the first holding circuit and the second holding circuit are disposed on the second substrate.

20. 2. The photoelectric conversion device according to claim 1, further comprising a third substrate on which the first transistor is disposed, the first substrate, the third substrate, and the second substrate being bonded in this order.

21. 2. The photoelectric conversion device according to claim 1, wherein the signal processing circuit includes an analog-to-digital conversion circuit.

22. 2. The photoelectric conversion device according to claim 1, wherein the first transistor and the first holding circuit are each supplied with a reference voltage from a common reference voltage line.

23. 2. The photoelectric conversion device according to claim 1, wherein the first transistor and the first holding circuit are supplied with reference voltages from different reference voltage lines.

24. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 23, an optical device that guides light to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

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