Image sensor

Abstract

To provide an image sensor in which the noise is reduced and the trans-conductance is high.SOLUTION: An image sensor of the present invention includes a substrate including a pixel region that is defined by a pixel separation part, a first active region and an element separation part provided in the pixel region, and a source follower gate electrode on the pixel region. The first active region has a fin-shaped cross section. The source follower gate electrode covers at least a part of an upper surface of the first active region and a side surface of the first active region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an image sensor, and more particularly to an image sensor having improved electrical and optical characteristics. [Background technology]

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors can be classified into charge coupled device (CCD) type and complementary metal oxide semiconductor (CMOS) type.

[0003] CMOS image sensors are abbreviated as CIS (CMOS image sensor). The CIS includes a plurality of pixels arranged two-dimensionally. Each pixel includes a photodiode (PD). The photodiode serves to convert incident light into an electrical signal.

[0004] Image sensors are constantly improving, and further improvements in electrical and optical characteristics are a challenge. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 10,199,423 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in view of the above-mentioned problems with conventional image sensors, and an object of the present invention is to provide an image sensor with reduced noise and high transconductance. [Means for solving the problem]

[0007] In order to achieve the above object, an image sensor according to the present invention includes a substrate including a pixel region defined by a pixel isolation portion, a first active region and an isolation portion provided in the pixel region, and a source follower gate electrode on the pixel region, wherein the first active region has a fin-shaped cross section, and the source follower gate electrode covers an upper surface of the first active region and at least a portion of a side surface of the first active region.

[0008] According to another embodiment of the present invention, an image sensor includes a substrate including a pixel region defined by a pixel isolation portion, a first active region and a device isolation portion provided in the pixel region, the first active region being defined by the device isolation portion, and a source follower gate electrode on the pixel region, the source follower gate electrode including a first region and a second region connected to the first region, the first region being provided on the first active region, and a lower portion of the second region penetrating a portion of the device isolation portion.

[0009] According to another embodiment of the present invention, an image sensor includes a substrate including a first pixel group and a second pixel group adjacent to each other in a first direction, each of the first and second pixel groups including first to fourth pixels arranged clockwise, a pixel separator disposed within the substrate and separating the first to fourth pixels included in each of the first and second pixel groups, first to fourth transfer gate electrodes disposed corresponding to the first to fourth pixels in each of the first and second pixel groups, respectively, the first pixel of the first pixel group and the third pixel and the fourth pixel of the second pixel group each including a source follower gate electrode, the source follower gate electrode including a first region on the substrate and a second region and a third region connected to the first region, and a lower surface of the second region and the third region being lower than a lower surface of the first region. [Effects of the Invention]

[0010] In the image sensor according to the present invention, the active region of the image sensor has a fin-shaped cross section, and the source follower gate electrode covers at least a part of the top surface and side surface of the active region. This increases the channel length and source follower gate area in the active region, resulting in an increase in the amount of current and a reduction in noise when the source follower transistor operates, thereby improving the electrical and optical characteristics of the image sensor. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged view of a CU1 portion of FIG. [Figure 3A] 3 is a cross-sectional view taken along line XX' in FIG. 2 for illustrating a schematic configuration of an image sensor according to an embodiment of the present invention. FIG. [Figure 3B] 3 is a cross-sectional view taken along line YY' in FIG. 2 for illustrating a schematic configuration of an image sensor according to an embodiment of the present invention. FIG. [Figure 3C] 3 is a cross-sectional view taken along line ZZ' in FIG. 2 for explaining a schematic configuration of an image sensor according to an embodiment of the present invention. FIG. [Figure 4A] FIG. 3B is an enlarged view of a portion CU2 in FIG. 3A. [Figure 4B] FIG. 3C is an enlarged view of a portion CU3 in FIG. 3B. [Figure 5A] 3 is a cross-sectional view illustrating a manufacturing process of an image sensor according to an embodiment of the present invention, which corresponds to a cross-section taken along line XX' in FIG. 2. FIG. [Figure 5B] 3 is a cross-sectional view illustrating a manufacturing process of an image sensor according to an embodiment of the present invention, which corresponds to a cross-section taken along line YY' in FIG. 2. FIG. [Figure 6A]3 is a cross-sectional view illustrating a manufacturing process of an image sensor according to an embodiment of the present invention, which corresponds to a cross-section taken along line XX' in FIG. 2. FIG. [Figure 6B] 3 is a cross-sectional view illustrating a manufacturing process of an image sensor according to an embodiment of the present invention, which corresponds to a cross-section taken along line YY' in FIG. 2. FIG. [Figure 6C] 6B is a cross-sectional view illustrating a manufacturing process of an image sensor according to an embodiment of the present invention, and is an enlarged view of a portion CU4 of FIG. 6A. [Figure 6D] 6B is a cross-sectional view illustrating a manufacturing process of an image sensor according to an embodiment of the present invention, and is an enlarged view of a portion CU5 in FIG. 6B. [Figure 7A] 3 is a cross-sectional view illustrating a manufacturing process of an image sensor according to an embodiment of the present invention, which corresponds to a cross-section taken along line XX' in FIG. 2. FIG. [Figure 7B] 3 is a cross-sectional view illustrating a manufacturing process of an image sensor according to an embodiment of the present invention, which corresponds to a cross-section taken along line YY' in FIG. 2. FIG. [Figure 7C] 7B is a cross-sectional view illustrating a manufacturing process of an image sensor according to an embodiment of the present invention, and is an enlarged view of a portion CU6 in FIG. 7A. [Figure 7D] 7B is a cross-sectional view illustrating a manufacturing process of an image sensor according to an embodiment of the present invention, and is an enlarged view of a portion CU7 in FIG. 7B. [Figure 8] 1 is a plan view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 9] 1 is a cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] Next, specific examples of embodiments of the image sensor according to the present invention will be described with reference to the drawings.

[0013] FIG. 1 is a plan view showing a schematic configuration of an image sensor according to an embodiment of the present invention, FIG. 2 is an enlarged view of a CU1 portion of FIG. 1, and FIGS. 3A, 3B, and 3C are cross-sectional views taken along lines XX', YY', and ZZ' of FIG. 2, respectively, for explaining the schematic configuration of an image sensor according to an embodiment of the present invention.

[0014] 1, 2, and 3A to 3C, an image sensor 1 according to an embodiment of the present invention includes a substrate 2. The substrate 2 includes a substrate 2a. The substrate 2 includes a first surface 2a and a second surface 2b facing each other. Light enters the substrate 2 through the second surface 2b. The substrate 2 may be a single crystal wafer or epitaxial layer containing silicon and / or germanium, or an SOI (Silicon on Insulator) substrate. The substrate 2 includes a first active region ACT1 and a second active region ACT2 defined by an element isolation portion STI, which will be described later.

[0015] In this specification, the first direction D1 is defined as a direction parallel to the first surface 2a of the substrate 2. The second direction D2 is defined as a direction parallel to the first surface 2a of the substrate 2 and perpendicular to the first direction D1. The third direction D3 is defined as a direction perpendicular to the first surface 2a of the substrate 2. The fourth direction D4 is parallel to the first surface 2a of the substrate 2 and is defined as one direction between the first direction D1 and the second direction D2. The fifth direction D5 is defined as a direction that is parallel to the first surface 2a of the substrate 2 and perpendicular to the fourth direction D4.

[0016] The substrate 2 includes a plurality of pixels (PX1 to PX8) arranged two-dimensionally along a first direction D1 and a second direction D2. Specifically, the image sensor 1 according to the embodiment of the present invention includes a first pixel group GRP1 and a second pixel group GRP2 on a substrate 2. The first pixel group GRP1 and the second pixel group GRP2 are adjacent to each other in the second direction D2. The first pixel group GRP1 includes first to fourth pixels (PX1 to PX4) arranged clockwise. The second pixel group GRP2 includes fifth to eighth pixels (PX5 to PX8) arranged clockwise. At this time, the first pixel PX1 is adjacent to the eighth pixel PX8 in the second direction D2. The second pixel PX2 is adjacent to the seventh pixel PX7 in the second direction D2.

[0017] A first source follower gate electrode SF1 is disposed on the first active region ACT1 of the first pixel PX1. A first reset gate electrode RG1 is disposed on the first active region ACT1 of the second pixel PX2. The second reset gate electrode RG2 is disposed on the first active region ACT1 of the third pixel PX3. It is possible that the gate electrode is not disposed on the first active region ACT1 of the fourth pixel PX4. The ground region GND is disposed in the fourth pixel PX4. A select gate electrode SEL is disposed on the first active region ACT1 of the fifth pixel PX5. The ground region GND is disposed in the fifth pixel PX5. The third reset gate electrode RG3 is disposed on the first active region ACT1 of the sixth pixel PX6. A second source follower gate electrode SF2 is disposed on the first active region ACT1 of the seventh pixel PX7. A third source follower gate electrode SF3 is disposed on the first active region ACT1 of the eighth pixel PX8.

[0018] The first to fourth pixels (PX1 to PX4) each include first to fourth transmission gate electrodes (TG1 to TG4) and first to fourth floating diffusion regions (FD1 to FD4) arranged on the second active region ACT2. A first common floating diffusion region FDC1 is disposed in the center of the first pixel group GRP1. The first common floating diffusion region FDC1 is electrically connected to the first to fourth floating diffusion regions (FD1 to FD4). The fifth to eighth pixels (PX5 to PX8) each include fifth to eighth transmission gate electrodes (TG5 to TG8) and fifth to eighth floating diffusion regions (FD5 to FD8) arranged on the second active region ACT2. A second common floating diffusion region FDC2 is disposed in the center of the second pixel group GRP2. The second common floating diffusion region FDC2 is electrically connected to the fifth to eighth floating diffusion regions (FD5 to FD8).

[0019] Referring to FIG. 2, the first active region ACT1 is disposed in a shape surrounding the second active region ACT2. At this time, the first active region ACT1 has at least one or more depressions (EP1, EP2) in plan view. Specifically, the first active region ACT1 includes a first depressed portion EP1 and a second depressed portion EP2. A plurality of first recesses EP1 are arranged on the inner sidewall ACT1n of the first active region ACT1. The second depressed portion EP2 is disposed on the outer side wall ACT1m of the first active region ACT1. The first recess EP1 is provided closer to the second active region ACT2 than the second recess EP2. The second depressed portion EP2 is provided closer to the side wall DTIs of the pixel isolation portion DTI than the first depressed portion EP1.

[0020] Referring again to FIGS. 2, 3A, and 3B, the substrate 2 is doped with a first impurity and has a first conductivity type. The first impurity may be, for example, boron. The first conductivity type may be, for example, P-type. A pixel separating portion DTI is disposed within the substrate 2, separating the first to eighth pixels (PX1 to PX8) from each other. The pixel isolation part DTI includes an isolation conductive pattern 10, an isolation insulating pattern 12, and a buried insulating pattern 14.

[0021] The isolated conductive pattern 10 is disposed at a distance from the substrate 2 . The separated conductive pattern 10 may comprise a conductive material having a different refractive index than the substrate 2 . The isolated conductive pattern 10 may include, for example, polysilicon or metal doped with impurities. The isolated insulating pattern 12 is interposed between the isolated conductive pattern 10 and the substrate 2 . A buried insulating pattern 14 is disposed below the isolated conductive pattern 10 . The isolated insulating pattern 12 and the buried insulating pattern 14 may include an insulating material having a refractive index different from that of the substrate 2 . As an example, each of the isolated insulating pattern 12 and the buried insulating pattern 14 includes silicon oxide.

[0022] The pixel separating portion DTI penetrates the substrate 2. The width of the pixel isolation portion DTI becomes narrower from the first surface 2a toward the second surface 2b. A negative bias voltage is applied to the isolated conductive pattern 10 . The isolated conductive pattern 10 serves as a common bias line. Therefore, it is possible to capture holes present on the surface of the substrate 2 in contact with the pixel separating portion DTI, thereby improving the dark current characteristics.

[0023] The side surface ground region GNL is disposed in the substrate 2 so as to be adjacent to the side wall DTIs of the pixel isolation portion DTI. The sidewalls DTIs of the pixel isolation portion DTI correspond to the outer sidewalls of the isolation insulating pattern 12. The side ground region GNL is formed by being doped with the same first impurity as the impurity doped into the substrate 2, and has a higher doping concentration than the impurity doped into the substrate 2. The element isolation STI is disposed adjacent to the first surface 2 a of the substrate 2 . The isolation region STI may be formed of a single layer or a multi-layer structure of at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The element isolation portion STI is provided on the sidewalls DTIs of the pixel isolation portion DTI.

[0024] The photoelectric conversion unit PD is disposed in the substrate 2 . A well region PW is disposed between the photoelectric conversion portion PD and the first surface 2a. For example, the well region PW is doped with a first impurity and has a first conductivity type. The first impurity is, for example, boron. The first conductivity type is, for example, a P type. The concentration of the first impurity doped into the well region PW is equal to or greater than the concentration of the impurity doped into the substrate 2 . The photoelectric conversion unit PD is doped with a second impurity opposite to the first impurity and has a second conductivity type. The second impurity is, for example, phosphorus or arsenic. The second conductivity type is, for example, N type. The N-type region of the photoelectric conversion unit PD forms a PN junction with the P-type region of the surrounding substrate 2 and / or well region PW to form a photodiode, and when light is incident, electron-hole pairs are generated by the PN junction.

[0025] A first source follower gate electrode SF1 is provided on the first active region ACT1 and the element isolation part STI of the first pixel PX1. The first source follower gate electrode SF1 includes polysilicon doped with impurities. The first source follower gate electrode SF1 will be described in detail later with reference to FIGS. 4A and 4B.

[0026] Referring to FIG. 2, a first transmission gate electrode TG1 is disposed on the second active region ACT2. A first contact CT1 is provided on the first transmission gate electrode TG1. Although not shown in the figure, a part of the first transmission gate electrode TG1 penetrates the substrate 2. Referring to FIGS. 2 and 3C, a first source / drain pattern SD1 and a second source / drain pattern SD2 are provided on a first active region ACT1. The first source / drain pattern SD1 and the second source / drain pattern SD2 are provided adjacent to the first surface 2a of the substrate 2 and are spaced apart from each other in a fourth direction D4. A first source follower gate electrode SF1 is provided between the first source / drain pattern SD1 and the second source / drain pattern SD2. The first source follower gate electrode SF1, the first source / drain pattern SD1, and the second source / drain pattern SD2 constitute one transistor.

[0027] First to third interlayer insulating films (ILD1, ILD2, ILD3) and a passivation film PL are laminated in this order on the first surface 2a of the substrate 2. Each of the first to third interlayer insulating films (ILD1, ILD2, ILD3) may have a single film or multi-film structure made of at least one of silicon oxide, silicon nitride, silicon oxynitride, and porous insulating material, for example. The passivation film PL includes, for example, silicon nitride. The second contact CT2 and the third contact CT3 penetrate the first interlayer insulating film ILD1. The second contact CT2 and the third contact CT3 contact the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The fourth contact CT4 is provided on the first source follower gate electrode SF4 through the first interlayer insulating film ILD1.

[0028] A first metal wiring M1 and a second metal wiring M2 are provided in a second interlayer dielectric film ILD2 and a third interlayer dielectric film ILD3, respectively. The first to fourth contacts (CT1 to CT4), the first metal wiring M1, and the second metal wiring M2 include a conductive material such as a metal. A fixed charge film 40 is disposed on the second surface 2b of the substrate 20. The fixed charge film 40 and the second surface 2b are in contact with each other. The fixed charge film 40 is formed of a metal oxide film or a metal fluoride film containing oxygen or fluorine in an amount less than the stoichiometric ratio. As a result, the fixed charge film 40 has a negative fixed charge.

[0029] The fixed charge film 40 is formed of a metal oxide or a metal fluoride containing at least one metal selected from the group including hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanides. Holes accumulate around the fixed charge film 40 . Therefore, the occurrence of dark current and white spots can be effectively reduced. Preferably, the fixed charge film 40 may include at least one of aluminum oxide and hafnium oxide. An anti-reflection film 42 is disposed on the fixed charge film 40 .

[0030] The anti-reflective coating 42 includes, for example, silicon nitride. On the anti-reflection coating 42 a grid 45 is provided. The grid 45 includes a first material pattern 44 and a second material pattern 46 . The first material pattern 44 and the second material pattern 46 expose the anti-reflection film 42 on the photoelectric conversion unit PD. The first material pattern 44 is a material that does not transmit light, such as titanium. The sidewalls of the second material pattern 46 are aligned with the sidewalls of the first material pattern 44 . The first material pattern 44 and the second material pattern 46 can prevent crosstalk between adjacent pixels. The second material pattern 46 includes an organic material. The second material pattern 46 has, as an example, a refractive index of about 1.3 or less.

[0031] On the anti-reflection film 42, a first color filter CF1 is disposed. The first color filter CF1 includes a photoresist material doped with a dye or pigment. A single first color filter CF1 is disposed on the first pixel group GRP1. That is, the first to fourth pixels (PX1 to PX4) of the first pixel group GRP1 are covered with the first color filter CF1 of the same color. Although not shown in the drawing, a color filter of a second color different from the first color is disposed on the second pixel group GRP2. A microlens ML is disposed on the first color filter CF1. The ends of the microlenses ML are in contact with each other and connected.

[0032] FIG. 4A is an enlarged view of a portion CU2 in FIG. 3A, and FIG. 4B is an enlarged view of a portion CU3 in FIG. 3B. Specifically, FIGS. 4A and 4B are diagrams illustrating the cross-sectional shapes of the source follower gate electrode taken along lines XX' and YY' in FIG. 2, respectively.

[0033] Referring to FIGS. 2, 4A, and 4B, the first active region ACT1 has a fin-shaped cross section. At this time, the first source follower gate electrode SF1 covers at least a part of the upper surface ACT1a of the first active region ACT1 and the side surface ACT1s of the first active region ACT1. The level of the upper surface ACT1a of the first active region ACT1 is higher than the level of the lower surface of the first source follower gate electrode SF1. Specifically, the first source follower gate electrode SF1 has a first region RE1, a second region RE2 connected to the first region RE1, and a third region RE3. The third region RE3 is provided so as to be spaced apart from the second region RE2 via the first region RE1. The second region RE2 and the third region RE3 are integrally connected to the first region RE1 and function as a source follower gate electrode.

[0034] The first region RE1 is provided on the first active region ACT1. The lower portions of the second region RE2 and the third region RE3 penetrate a part of the element isolation part STI. The length PET that the second region RE2 and the third region RE3 penetrate through the element isolation part STI may be 70 nm to 100 nm. As a result, the levels of the lower surface RE2b of the second region RE2 and the lower surface RE3b of the third region RE3 are lower than the level of the lower surface RE1b of the first region RE1. That is, the height of the second region RE2 and the third region RE3 in the third direction D3 is greater than the height of the first region RE1 in the third direction D3. The first region RE1 has a first width W1 in the second direction D2. The second region RE2 has a second width W2 in the second direction D2. The third region RE3 has a third width W3 in the second direction D2. As an example, the size of the first width W1 may be 100 nm to 120 nm. The size of the second width W2 may be 70 nm to 100 nm. The third width W3 may be 20 nm to 30 nm.

[0035] A gate insulating pattern GI is provided below the first source follower gate electrode SF1. The first region RE1 is provided on the first active region ACT1, and the second region RE2 and the third region RE3 are provided on the element isolation portion STI, so that a portion of the gate insulation pattern GI contacts the substrate 2 and the remaining portion contacts the element isolation portion STI. The gate insulating pattern GI may include at least one of silicon oxide and silicon nitride.

[0036] The active region of the source follower gate electrode of the image sensor according to the embodiment of the present invention has a fin-shaped cross section, and the source follower gate electrode covers at least a portion of the top surface and side surfaces of the active region. This increases the length of the channel in the active region and the source follower gate area. As a result, when the source follower transistor operates, the amount of current increases and the transconductance improves. In addition, the linearity of the voltage-current graph of the image sensor is improved, and noise such as random noise and random telegraphy signal can be reduced.

[0037] 5A, 5B, 6A, 6B, 6C, 6D, 7A, 7B, 7C, and 7D are cross-sectional views illustrating a manufacturing process of an image sensor according to an embodiment of the present invention. Specifically, Figures 5A, 6A, and 7A are cross-sectional views corresponding to the cross section cut along line X-X' in Figure 2, Figures 5B, 6B, and 7B are cross-sectional views corresponding to the cross section cut along line Y-Y' in Figure 2, Figures 6C and 6D are enlarged views of the CU4 and CU5 portions of Figures 6A and 6B, respectively, and Figures 7C and 7D are enlarged views of the CU6 and CU7 portions of Figures 7A and 7B, respectively.

[0038] Referring to Figures 5A and 5B, a substrate 2 is provided having a first surface 2a and a second surface 2b opposite to each other. The substrate 2 has a first conductivity type (for example, P type). An element isolation STI is formed on the first surface 2 a of the substrate 2 . The element isolation portion STI is formed, for example, through an STI (Shallow Trench Isolation) process.

[0039] An element isolation portion STI and a pixel isolation portion DTI penetrating the substrate 2 are formed. The pixel isolation part DTI includes an isolation conductive pattern 10, an isolation insulating pattern 12, and a buried insulating pattern 14. The element isolation portion STI defines a first active region ACT1 and a second active region ACT2. A well region PW and a photoelectric conversion unit PD are formed in a substrate 2. Forming the well region PW includes implanting a first impurity into the substrate 2 . Forming the photoelectric conversion portion PD includes implanting a second impurity, which is different from the first impurity, into the substrate 2.

[0040] 6A, 6B, 6C, and 6D, a mask pattern MP is disposed on the first surface 2a of the substrate 2. The mask pattern MP includes an opening OP. A recess portion RES is formed in the opening OP. The recess portion RES defines a region in which the first source follower gate electrode SF1 described with reference to FIGS. 2, 3A, and 3B is to be formed. Using the mask pattern MP as an etching mask, the substrate 2, that is, a part of the first active region ACT1 and a part of the element isolation part STI are etched. Using the mask pattern MP, a part of the substrate 2 and a part of the element isolation part STI are etched, thereby forming a recess part RES. Due to the formation of the recess portion RES, the upper portion of the first active region ACT1 has a fin-shaped cross section. Thereafter, the mask pattern MP is removed.

[0041] 7A, 7B, 7C, and 7D, a gate insulation pattern GI and a first source follower gate electrode SF1 are sequentially formed on the isolation portion STI and the first active pattern ACT1. Forming the first source follower gate electrode SF1 includes filling the recess RES on the element isolation part STI and forming a metal layer on the first active pattern ACT1, and patterning the metal layer to form a metal pattern. At this time, the metal pattern formed on the first active pattern ACT1 corresponds to the first region RE1 of the first source follower gate electrode SF1 described with reference to FIG. 4A. The metal pattern formed on the element isolation part STI corresponds to the second region RE2 and the third region RE3.

[0042] Then, referring to FIGS. 2, 3A, and 3B, a first floating diffusion region FD1 is formed on the second active region ACT2. The first floating diffusion region FD1 is formed by doping the substrate 2 with a second impurity different from the first impurity. On the first surface 2a of the substrate 2, first to third interlayer insulating films (ILD1 to ILD3) and a passivation film PL are formed in this order. At this time, the first to fourth contacts (CT1 to CT4) are formed to penetrate the first interlayer insulating film ILD1, and the first metal wiring ML1 and the second metal wiring ML2 are provided in the second interlayer insulating film ILD2 and the third interlayer insulating film ILD3, respectively.

[0043] On the second surface 2b of the substrate 2, a fixed charge film 40 and an anti-reflection film 42 are formed in this order. Thereafter, a first material pattern 44 and a second material pattern 46 are sequentially formed on the anti-reflection film 42 . The first color filter CF1 is formed on the anti-reflection film 42. The first color filter CF1 is formed so as to overlap the photoelectric conversion unit PD in the third direction D3. Thereafter, the microlenses ML are formed on the first color filters CF1, thereby completing the image sensor shown in FIGS. 2, 3A, and 3B.

[0044] FIG. 8 is a plan view showing a schematic configuration of an image sensor according to an embodiment of the present invention. Explanations that overlap with those in FIG. 1 will be omitted. Referring to Figure 8, in a plan view, the shape of the first reset gate electrode RG1 on the second pixel PX2 included in the first pixel group GRP1 and the shape of the second reset gate electrode RG2 on the third pixel PX3 are substantially identical to the rotated shape of the first source follower gate electrode SF1 on the first pixel PX1.

[0045] As an example, the shape of the first reset gate electrode RG1 on the second pixel PX2 included in the first pixel group GRP1 is substantially the same as the shape of the first source follower gate electrode SF1 on the first pixel PX1 rotated 90 degrees clockwise in a planar view. As an example, the shape of the second reset gate electrode RG2 on the third pixel PX3 included in the first pixel group GRP1 is substantially the same as the shape of the first source follower gate electrode SF1 on the first pixel PX1 rotated 180 degrees clockwise in a planar view. The cross-sectional shapes of the first reset gate electrode RG1 and the second reset gate electrode RG2 are substantially the same as the cross-sectional shape of the first source follower gate electrode SF1 described with reference to FIGS. 3A and 3B.

[0046] In plan view, the shape of the third reset gate electrode RG3 on the sixth pixel PX6 included in the second pixel group GRP2 is also substantially the same as the rotated shape of the first source follower gate electrode SF1 on the first pixel PX1. As an example, the shape of the third reset gate electrode RG3 on the sixth pixel PX6 included in the second pixel group GRP2 is substantially the same as the shape of the first source follower gate electrode SF1 on the first pixel PX1 rotated 90 degrees clockwise in a planar view. The cross-sectional shape of the third reset gate electrode RG3 is substantially the same as the cross-sectional shape of the first source follower gate electrode SF1. In plan view, the shape of the select gate electrode SEL on the fifth pixel PX5 included in the second pixel group GRP2 is also substantially the same as the shape of the first source follower gate electrode SF1 on the first pixel PX1. The cross-sectional shape of the select gate electrode SEL is substantially the same as the cross-sectional shape of the first source follower gate electrode SF1.

[0047] FIG. 9 is a cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. Referring to FIG. 9, an image sensor 1 according to an embodiment of the present invention includes a pixel array area APS, a substrate 2 having an optical black area OB and a pad area PR, a wiring layer 200 on a first surface 2a of the substrate 2, and a base substrate 400 on the wiring layer 200.

[0048] The pixel array region APS includes the first to eighth pixels (PX1 to PX8) described with reference to FIGS. The wiring layer 200 includes an upper wiring layer 221 and a lower wiring layer 223 . In the optical black area OB, a first connecting structure 50, a first conductive pad 81, and a bulk color filter 90 are provided. The first connection structure 50 includes a first through conductive pattern 51 , an insulating pattern 53 , and a first capping pattern 55 . A first through conductive pattern 51 is provided on the second surface 2 b of the substrate 2 . The first through conductive pattern 51 conformally covers the inner walls of the third trench TR3 and the fourth trench TR4. The first through conductive pattern 51 penetrates the photoelectric conversion layer 150 and the upper wiring layer 221 to connect the photoelectric conversion layer 150 and the wiring layer 200 . The first through conductive pattern 51 contacts the wiring in the lower wiring layer 223 .

[0049] The first conductive pad 81 is electrically connected to the separated conductive pattern 10 of the pixel separating part DTI in FIG. 3A. The first through conductive pattern 51 blocks light incident into the optical black area OB. The first through conductive pattern 51 is made of a conductive material. The first through conductive pattern 51 may include, for example, titanium or tungsten. A first conductive pad 81 is provided inside the third trench TR3 and fills the remaining portion of the third trench TR3. The first conductive pad 81 includes a metal material such as aluminum. A negative bias voltage can be applied to the isolated conductive pattern 10 through the first conductive pad 81 . Therefore, the problems of white spots and dark current in the image sensor 1 can be prevented / reduced.

[0050] The insulating pattern 53 fills the remaining portion of the fourth trench TR4 except for the first through conductive pattern 51. The insulating pattern 53 passes through the photoelectric conversion layer 150 and the wiring layer 200 entirely or partially. The first capping pattern 55 is provided on the insulating pattern 53 . A bulk color filter 90 is provided on the first conductive pads 81 , the first through conductive patterns 51 and the first capping patterns 55 . The bulk color filter 90 covers the first conductive pads 81 , the first through conductive patterns 51 , and the first capping patterns 55 . A first protective film 71 is provided on the bulk color filter 90 to seal the bulk color filter 90 .

[0051] A plurality of pixels PX are also arranged in the optical black area OB, and the first reference photoelectric conversion unit PD' and the second reference area 111 are arranged in the pixels PX. The first reference photoelectric conversion unit PD' provides a first reference charge amount generated in a state where light is blocked. The first reference charge amount is a relative reference value when calculating the charge amount generated from the pixel PX. The second reference region 111 provides a second reference charge amount that is generated in the absence of the photoelectric conversion unit PD. The second reference charge amount is used as information for removing process noise. In the pad region PR, a second connection structure 60, a second conductive pad 83, and a second protective film 73 are provided on the substrate 2. The second connection structure 60 includes a second through conductive pattern 61 , an insulating pattern 63 , and a second capping pattern 65 .

[0052] The second through conductive pattern 61 conformally covers the inner walls of the fifth trench TR5 and the sixth trench TR6. The second through conductive pattern 61 penetrates the photoelectric conversion layer 150 and the upper wiring layer 221 to connect the photoelectric conversion layer 150 and the wiring layer 200 . The second through conductive pattern 61 contacts the wiring in the lower wiring layer 223 . The second through conductive pattern 61 is electrically connected to the wiring in the wiring layer 200. The second through conductive pattern 61 may include a metal material, for example, titanium or tungsten. A second conductive pad 83 is provided inside the fifth trench TR5 and fills the remaining portion of the fifth trench TR5.

[0053] The second conductive pad 83 includes a metal material such as aluminum. The second conductive pad 83 serves as an electrical connection path between the image sensor 1 and an external device. An insulating pattern 63 fills the remaining part of the sixth trench TR6. The insulating pattern 63 passes through the photoelectric conversion layer 150 and the wiring layer 200 entirely or partially. A second capping pattern 65 is provided on the insulating pattern 63 . The second protective film 73 covers a part of the second through conductive pattern 61 and the second capping pattern 65 . Although not shown in the drawings, according to one embodiment of the present invention, the first connection structure 50 and the pad region PR may not be provided. In this case, the second conductive pads 83 are provided in the lower wiring layer 223, and the photoelectric conversion layer 150 and the wiring layer 200 are electrically connected through bonding between metal pads or the like.

[0054] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0055] 2 boards 10 Separate conductive pattern 12 Separation insulating pattern 14 Buried insulating pattern 40 Fixed charge membrane 42 Anti-reflection coating 44 First Material Pattern 45 grid 46 Second Material Pattern ACT1, ACT2 (1st, 2nd) active region CF1 First color filter CT1~CT4 (1st~4th) contacts DTI pixel separation section EP1, EP2 (first and second) depressions FD1 to FD8 (1st to 8th) floating diffusion regions FDC1, FDC2 (1st, 2nd) 1 common floating diffusion region GNL side ground area GRP1, GRP2 (1st, 2nd) pixel groups ILD1, ILD2, ILD3 (1st to 3rd) interlayer insulating films M1, M2 (1st, 2nd) metal wiring ML Micro Lens PD photoelectric conversion unit PL passivation film PW well region PX1 to PX8 (1st to 8th) pixels RE1 1st area RE2 2nd area RG1, RG2, RG3 (first to third) reset gate electrodes SD1, SD2 (first, second) source / drain patterns SEL Select gate electrode SF1 to SF4 (1st to 4th) source follower gate electrodes STI element isolation section TG1 to TG8 (1st to 8th) transmission gate electrodes

Claims

1. a substrate including a pixel region defined by a pixel separator; a first active region and an isolation portion provided in the pixel region; a source follower gate electrode on the pixel region, the first active region has a fin-shaped cross section; The image sensor, wherein the source follower gate electrode covers an upper surface of the first active region and at least a portion of a side surface of the first active region.

2. a gate insulating pattern provided between the source follower gate electrode and the substrate; a portion of the gate insulating pattern contacting the substrate; The image sensor of claim 1 , wherein a remaining portion of the gate insulating pattern contacts the device isolation portion.

3. 2. The image sensor of claim 1, wherein the level of an upper surface of the first active region is higher than the level of a lower surface of the source follower gate electrode.

4. The image sensor of claim 1 , wherein the first active region has at least one recess.

5. the substrate further includes a second active region defined by the isolation portion; a transmission gate electrode on the second active region; the first active region surrounds the second active region; The image sensor of claim 1 , wherein the first active region includes at least one recess.

6. The recessed portion includes a first recessed portion and a second recessed portion, the first recess is disposed on an inner sidewall of the first active region; The image sensor of claim 5 , wherein the second recessed portion is disposed on an outer wall of the first active region.

7. The image sensor of claim 6 , wherein the first recess is closer to the second active region than the second recess.

8. The image sensor of claim 6 , wherein the second recess is closer to a sidewall of the pixel separating portion than the first recess.

9. The image sensor of claim 5 , wherein the substrate further comprises a floating diffusion region on the second active region.

10. 4. The image sensor of claim 3, wherein the source follower gate electrode comprises polysilicon doped with impurities.

Images