Power semiconductor element

Abstract

To provide a power semiconductor element with improved electric characteristics.SOLUTION: A power semiconductor element in an embodiment of the present invention can include a substrate of a first conductivity type, a drift layer of the first conductivity type on the substrate, a well region of a second conductivity type extending from an upper surface of the drift layer and disposed in the drift layer, a source region of the first conductivity type extending from the upper surface of the well region and disposed in the well region, an insulating liner on the drift layer, a gate structure on the insulating liner, a first gate bus line on the gate structure, a second gate bus line disposed on the first gate bus line and including a first part that overlaps with the first gate bus line and a second part that extends to the first part, a conductive terminal disposed on the second part of the second gate bus line, and a drain electrode on a lower surface of the substrate.SELECTED DRAWING: Figure 1a

Description

[Technical Field]

[0001] The present invention relates to a power semiconductor device, and more particularly to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) power semiconductor device. [Background technology]

[0002] Power semiconductor devices are semiconductor devices that operate in high voltage and high current environments and are used in fields that require high power switching, such as power conversion, power converters, and inverters. Power semiconductor devices are basically required to withstand high voltages, and recently, high-speed switching operations have also been required. As a result, research is being conducted into power semiconductor devices using SiC, which has superior withstand voltage characteristics compared to silicon (Si). Summary of the Invention [Problem to be solved by the invention]

[0003] One of the technical objects to be achieved by the present invention is to provide a power semiconductor device having improved electrical characteristics.

[0004] However, the object of the present invention is not limited to the above object, and can be variously expanded within the scope of the idea and scope of the present invention. [Means for solving the problem]

[0005] A power semiconductor device according to an embodiment of the present invention may include a substrate of a first conductivity type, a drift layer of the first conductivity type on the substrate, a well region of a second conductivity type extending from an upper surface of the drift layer and disposed in the drift layer, a source region of the first conductivity type extending from an upper surface of the well region and disposed in the well region, an insulating liner on the drift layer, a gate structure on the insulating liner, a first gate bus line on the gate structure, a second gate bus line disposed on the first gate bus line and including a first portion overlapping the first gate bus line and a second portion extending to the first portion, a conductive terminal disposed on the second portion of the second gate bus line, and a drain electrode on a lower surface of the substrate.

[0006] A power semiconductor device according to an embodiment of the present invention may include a substrate of a first conductivity type, a drift layer of the first conductivity type on the substrate, a well region of a second conductivity type on the drift layer, a source region of the first conductivity type on the well region, a gate structure disposed on the drift layer and including first and second body portions spaced apart from each other in a first direction and a finger portion connecting the first body portion and the second body portion, a first gate bus line overlapping the first and second body portions, a second gate bus line disposed on the first gate bus line and including a first portion overlapping the first gate bus line in a direction perpendicular to an upper surface of the substrate and a second portion extending from the first portion but not overlapping the first gate bus line, a conductive terminal disposed on the second portion of the second gate bus line, and a drain electrode on a lower surface of the substrate.

[0007] A power semiconductor device according to an embodiment of the present invention may include a substrate of a first conductivity type, a drift layer of the first conductivity type on the substrate, a well region of a second conductivity type extending from an upper surface of the drift layer and disposed in the drift layer, a source region of the first conductivity type extending from an upper surface of the well region and disposed in the well region, an insulating liner on the drift layer, a gate structure disposed on the insulating liner and including a cell region and a dummy region, a first gate bus line overlapping the dummy region of the gate structure in a vertical direction perpendicular to an upper surface of the substrate, a second gate bus line including a first portion overlapping the first gate bus line in the vertical direction and a second portion extending from the first portion and overlapping the cell region of the gate structure, a conductive terminal disposed on the second portion of the second gate bus line, and a drain electrode on a lower surface of the substrate. [Effects of the Invention]

[0008] A power semiconductor device according to an embodiment of the present invention includes a first gate bus line connected to a gate structure and a second gate bus line overlapping a cell region and connected to the first gate bus line and a conductive terminal to which an external voltage is applied, thereby securing a cell region and providing a power semiconductor device with improved electrical characteristics.

[0009] However, the effects of the present invention are not limited to the above-mentioned effects, and can be variously expanded within the scope of the present invention. [Brief explanation of the drawings]

[0010] [Figure 1a] 1 is a schematic plan view of a partial configuration of a power semiconductor device according to an embodiment of the present invention; [Figure 1b] 1 is a schematic plan view of a partial configuration of a power semiconductor device according to an embodiment of the present invention; [Figure 1c] 1 is a schematic plan view of a partial configuration of a power semiconductor device according to an embodiment of the present invention; [Figure 2a]1b is a cross-sectional view of an embodiment of the power semiconductor device taken along line II' of FIG. 1a. [Figure 2b] 1b is a cross-sectional view of the power semiconductor device of FIG. 1a taken along line II-II' according to an embodiment; [Figure 3a] 1b is a cross-sectional view showing another embodiment of the power semiconductor device taken along line II' of FIG. 1a. [Figure 3b] 1b is a cross-sectional view showing another embodiment of the power semiconductor device taken along line II-II' of FIG. 1a. [Figure 4a] FIG. 10 is a schematic plan view of a partial configuration of a power semiconductor device according to another embodiment of the present invention. [Figure 4b] FIG. 10 is a schematic plan view of a partial configuration of a power semiconductor device according to another embodiment of the present invention. [Figure 5a] 4b is a cross-sectional view showing another embodiment of the power semiconductor device taken along line III-III' of FIG. 4a. [Figure 5b] 4b is a cross-sectional view showing another embodiment of the power semiconductor device taken along line IV-IV' of FIG. 4a. [Figure 6] FIG. 10 is a schematic plan view of a partial configuration of a power semiconductor device according to another embodiment of the present invention. [Figure 7] 7 is a cross-sectional view showing another embodiment of the power semiconductor device taken along line VV' of FIG. 6. FIG. [Figure 8a] FIG. 10 is a schematic plan view of a partial configuration of a power semiconductor device according to another embodiment of the present invention. [Figure 8b] FIG. 10 is a schematic plan view of a partial configuration of a power semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The same reference numerals are used to designate the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0012] 1a to 1c are schematic plan views of a portion of a configuration of a power semiconductor device according to an embodiment of the present invention, FIG. 2a is a cross-sectional view showing one embodiment of the power semiconductor device taken along line II' of FIG. 1a, and FIG. 2b is a cross-sectional view showing one embodiment of the power semiconductor device taken along line II-II' of FIG. 1a.

[0013] FIG. 1a is a schematic plan view of a gate structure 130 of a power semiconductor device 100 according to an embodiment of the present invention, FIG. 1b is a schematic plan view of a first gate bus line 155 and a first source electrode 150 of the power semiconductor device 100 according to an embodiment of the present invention, and FIG. 1c is a schematic plan view of a second gate bus line 165 and a second source electrode 160 of the power semiconductor device 100 according to an embodiment of the present invention.

[0014] 1a to 2b, the power semiconductor device 100 may include a substrate 101, a drift layer 103 on the substrate 101, well regions 105 extending from an upper surface of the drift layer 103, source regions 107 extending from an upper surface of the well regions 105 in each of the well regions 105, well contact regions 109 on one side of the source regions 107, gate structures 130 on the drift layer 103, an insulating liner 122 between the gate structures 130 and the well regions 105, a dielectric layer 125 covering the gate structures 130, a first source electrode 150 and a first gate bus line 155 covering the dielectric layer 125, a second source electrode 160 arranged on a portion of the first source electrode 150, a second gate bus line 165 arranged on the first gate bus line 155 and extending onto the first source electrode 150, and a drain electrode 180 on the lower surface of the substrate 101. In one example, the power semiconductor device 100 may further include a first insulating pattern ILD1 arranged between the first source electrode 150 and the first gate bus line 155 and a second insulating pattern ILD2 arranged between the second source electrode 160 and the second gate bus line 165.

[0015] The substrate 101 may have a top surface extending in a first direction (X-direction) and a second direction (Y-direction). The substrate 101 may include a semiconductor material, such as SiC. However, in some embodiments, the substrate 101 may include a Group IV semiconductor material, such as Si or Ge, or a compound semiconductor material, such as GaN, SiGe, GaAs, InAs, or InP.

[0016] The substrate 101 may be provided as a bulk wafer or an epitaxial layer. The substrate 101 may include first conductivity type impurities, thereby having the first conductivity type. In some embodiments, the first conductivity type may be, for example, N-type, and the first conductivity type impurities may be N-type impurities such as nitrogen (N) and / or phosphorus (P). In some embodiments, the first conductivity type may be, for example, P-type, and the first conductivity type impurities may be P-type impurities such as aluminum (Al). Hereinafter, unless otherwise specified, the power semiconductor device 100 will be described based on the case where it includes an N-type MOSFET. However, the power semiconductor device 100 may include a P-type MOSFET, in which the first conductivity type is P-type.

[0017] The drift layer 103 may be disposed on the substrate 101. The drift layer 103 may include a semiconductor material. The drift layer 103 may be an epitaxial layer grown on the substrate 101. The drift layer 103 may include first conductivity type impurities, thereby having the first conductivity type. The concentration of the first conductivity type impurities in the drift layer 103 may be lower than the concentration of the first conductivity type impurities in the substrate 101. In the embodiment, the first conductivity type impurities in the substrate 101 and the drift layer 103 may be the same or different from each other.

[0018] The well regions 105 may be disposed at a predetermined depth from the top surface of the drift layer 103 and may be spaced apart from each other in a horizontal direction, e.g., a first direction (X direction). The well regions 105 may include a semiconductor material, e.g., SiC. The well regions 105 may be regions having a second conductivity type and may include second conductivity type impurities. The second conductivity type may be, e.g., P type, and the second conductivity type impurities may be, e.g., P type impurities such as aluminum (Al). In some embodiments, the well regions 105 may include multiple regions having different doping concentrations.

[0019] The source region 107 may be disposed in each of the well regions 105 and may be disposed at a predetermined depth from the top surface of the well region 105. The thickness of the source region 107 may be smaller than the thickness of the well region 105. The source region 107 may include a semiconductor material, such as SiC. The concentration of the first conductive type impurity in the source region 107 may be higher than the concentration of the first conductive type impurity in the drift layer 103, but is not limited to this.

[0020] The well contact region 109 may be disposed on one side of the well region 105 together with at least a portion of the source region 109. The well contact region 109 may be disposed between the well region 105 and the first source electrode 150 so that a voltage may be applied to the well region 105 from the first source electrode 150. In one example, the relative depths of the well contact region 109 and the source region 107 may vary. The well contact region 109 may include a semiconductor material, for example, SiC. The well contact region 109 may be a region having the second conductivity type and may include the second conductivity type impurities described above. The concentration of the second conductivity type impurities in the well contact region 109 may be higher than the concentration of the second conductivity type impurities in the well region 105.

[0021] The gate structure 130 may be disposed on the insulating liner 122 of the drift layer 103, and may be disposed on one end of the source region 107 and on the well region 105 outside the source region 107. The gate structure 130 may be disposed to overlap a portion of the source region 107 and a portion of the well region 105 in the third direction (Z direction). The gate structure 130 may be separated from the source region 107, the well region 105, and the drift layer 103 by the insulating liner 122.

[0022] The gate structure 130 may include body portions 135 extending in a first direction (X direction), and finger portions 131 and 132 disposed between and connecting the body portions 135 .

[0023] The body portion 135 may include first and second body portions 135a and 135b extending in a first direction (X direction) and spaced apart in a second direction (Y direction). The finger portions 131 and 132 may be a plurality of gate electrodes extending from the first and second body portions 135a and 135b in the second direction (Y direction) and spaced apart from each other in the first direction (X direction). The finger portions 131 and 132 may include a first finger portion 131 overlapping a portion of a first gate bus line 155 (described below) in the third direction (Z direction) and a second finger portion 132 overlapping a first source electrode 150 in the third direction (Z direction). The first finger portion 131 may be a gate electrode disposed outermost between the first and second body portions 135a and 135b and extending in the second direction (Y direction). In one example, the first finger portion 131 is shown as having one gate electrode disposed between the first body portion 135a and the second body portion 135b, but is not limited to this and may include two or more gate electrodes. The second finger portion 132 is shown as having thirteen gate electrodes disposed between the first body portion 135a and the second body portion 135b, but is not limited to this and may include more or less than thirteen gate electrodes.

[0024] The first finger portion 131 may include first electrode portions 131_1 and 131_3 overlapping the first gate bus line 155 and a second electrode portion 131_2 disposed between the first electrode portions 131_1 and 131_3 and overlapping the first source electrode 150. In one example, the first electrode portions 131_1 and 131_3 of the first finger portion 131 may include a 1-1 electrode portion 131_1 at one end of the first finger portion 131 extending from the first body portion 135a and a 1-2 electrode portion 131_3 at the other end of the first finger portion 131 extending from the second body portion 135b. In this specification, the first finger portion 131 may be referred to as a first gate electrode.

[0025] The gate structure 130 may include a cell region R1 and dummy regions R2a and R2b. In one example, the cell region R1 of the gate structure 130 may be a region overlapping a first source electrode 150 (described later) in the third direction (Z direction). The dummy regions R2a and R2b of the gate structure 130 may be a region overlapping a first gate bus line 155 (described later) in the third direction (Z direction).

[0026] The cell region R1 of the gate structure 130 may include the second electrode portion 131_2 of the first finger portion 131 and the second finger portion 132. The dummy regions R2a and R2b of the gate structure 130 may include the first and second body portions 135a and 135b and the first electrode portions 131_1 and 131_3 of the first finger portion 131.

[0027] The gate structure 130 may include a conductive material, such as a semiconductor material such as doped polycrystalline silicon, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo). In an embodiment, the gate structure 130 may be comprised of two or more multi-layers.

[0028] The insulating liner 122 may be disposed on the lower surface of the gate structure 130. The insulating liner 122 may extend over the source region 107, the well region 105 outside the source region 107, and the drift layer 103. The insulating liner 122 may be disposed between the source region 107, the well region 105, and the drift layer 103 and the gate structure 130. The insulating liner 122 may function as a gate insulating layer of the gate structure 130.

[0029] The insulating liner 122 may include an insulating material. For example, the insulating liner 122 may include an oxide, a nitride, or a high-k material. The high-k material may refer to a dielectric material having a higher dielectric constant than silicon oxide (SiO2). Examples of the high-k material include aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and praseodymium oxide (Pr2O3).

[0030] The dielectric layer 125 may cover portions of the gate structure 130 and the insulating liner 122 and may be disposed to expose portions of the source region 107. The dielectric layer 125 may cover the side and top surfaces of the gate structure 130. The dielectric layer 125 may include an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0031] A first gate bus line 155 and a first source electrode 150 may be disposed on the gate structure 130. In one example, the first gate bus line 155 may be disposed on the first and second body portions 135a and 135b of the gate structure 130 and the first electrode portions 131_1 and 131_3 of the first finger portion 131 extending from the first and second body portions 135a and 135b. The first source electrode 150 may be disposed on the second finger portion 132 of the gate structure 130 and the second electrode portion 131_2 of the first finger portion 131.

[0032] The first gate bus line 155 may be in contact with the dielectric layer 125 covering the first and second body portions 135a and 135b of the gate structure 130 and a portion of the first finger portion 131. In one example, the first gate bus line 155 may include two gate bus lines. In one example, the first gate bus line 155 may include a 1-1 gate bus line 155a overlapping the first body portion 135a and a 1-2 gate bus line 155b overlapping the second body portion 135b. In one example, the 1-1 gate bus line 155a and the 1-2 gate bus line 155b may be spaced apart from each other in the second direction (Y direction). The 1-1 gate bus line 155a and the 1-2 gate bus line 155b may be symmetrical in the second direction (Y direction) with respect to the first source electrode 150.

[0033] The 1-1 gate bus line 155a may include a 1-1 extending portion 155a_1 overlapping the first body portion 135a and extending in the first direction (X direction) and a 1-1 bent portion 155a_2 extending from the 1-1 extending portion 155a_1 and disposed on one end of the first finger portion 131. In one example, the 1-2 gate bus line 155b may include a 1-2 extending portion 155b_1 overlapping the second body portion 135b and extending in the first direction (X direction) and a 1-2 bent portion 155b_2 extending from the 1-2 extending portion 155b_1 and disposed on the other end of the first finger portion 131. In one example, the 1-1 extension portion 155a_1 and the 1-2 extension portion 155b_1 may be referred to as a third portion in this specification, and the 1-1 bent portion 155a_2 and the 1-2 bent portion 155b_2 may be referred to as a fourth portion.

[0034] The first gate bus line 155 may be connected to the gate structure 130 by penetrating the dielectric layer 125 in at least one region. In one example, the first gate bus line 155 may be connected to the gate structure 130 by penetrating the dielectric layer 125 covering the first finger portion 131. For example, the 1-1 gate bus line 155a and the 1-2 gate bus line 155b may be connected to the gate structure 130 (or the first finger portion 131) by penetrating the dielectric layer 125 covering one end and the other end of the first finger portion 131, respectively.

[0035] The first source electrode 150 may be disposed on a portion of the gate structure 130. In one example, the first source electrode 150 may be disposed on the dielectric layer 125 covering the second electrode portion 131_2 of the first finger portion 131 and the second finger portion 132. The first source electrode 150 may include a 1-1 source electrode 150_1 disposed on the second finger portion 132 and a 1-2 source electrode 150_2 extending from the 1-1 source electrode 150_1 and disposed on the second electrode portion 131_2 of the first finger portion 131.

[0036] A metal-semiconductor compound layer 152 may be disposed at the interface where the first source electrode 150 and the source region 107 contact each other. The metal-semiconductor compound layer 152 may include a metal element and a semiconductor element, and may include, for example, at least one of TiSi, CoSi, MoSi, LaSi, NiSi, TaSi, or WSi.

[0037] The upper surface of the first gate bus line 155 may be disposed at substantially the same level as the upper surface of the first source electrode 150 .

[0038] The first gate bus line 155 does not overlap with the first source electrode 150 in the vertical direction (Z direction), and the first source electrode 150 may be disposed between the 1-1 and 1-2 gate bus lines 155a and 155b. A first insulating pattern ILD1 may be disposed between the first gate bus line 155 and the first source electrode 150. The first gate bus line 155 may not be electrically connected to the first source electrode 150 by the first insulating pattern ILD1.

[0039] The first insulation pattern ILD1 may cover upper surfaces of the first gate bus line 155 and the first source electrode 150 and fill a space between the first gate bus line 155 and the first source electrode 150. The upper surface of the first insulation pattern ILD1 may be disposed at a higher level than the upper surfaces of the first gate bus line 155 and the first source electrode 150.

[0040] A second source electrode 160 and a second gate bus line 165 may be disposed on the first source electrode 150 and the first gate bus line 155. In one example, the second source electrode 160 and the second gate bus line 165 may be disposed on a first insulating pattern ILD1 disposed on the first source electrode 150 and the first gate bus line 155. The second source electrode 160 and the second gate bus line 165 may be in contact with the first insulating pattern ILD1 covering the upper surfaces of the first source electrode 150 and the first gate bus line 155.

[0041] The second gate bus line 165 may include first portions 165_1, 165_2, 165_4, and 165_5 overlapping the first gate bus line 155, and a second portion 165_3 extending from the first portions 165_1, 165_2, 165_4, and 165_5 to connect the first portions 165_1, 165_2, 165_4, and 165_5. In one example, the second gate bus line 165 may be an integrated electrode structure. That is, the first portions 165_1, 165_2, 165_4, and 165_5 and the second portion 165_3 may be a single electrode structure. In one example, the first portions 165_1, 165_2, 165_4, and 165_5 may include 1-1 portions 165_1 and 165_2 overlapping with the 1-1 gate bus line 155a of the first gate bus line 155 and 1-2 portions 165_4 and 165_5 overlapping with the 1-2 gate bus line 155b. In one example, the second portion 165_3 may overlap with the first source electrode 150. In one example, the first portions 165_1, 165_2, 165_4, and 165_5 of the second gate bus line 165 may overlap with the first and second body portions 135a and 135b and parts of the first finger portion 131 of the gate structure 130 in the vertical direction (Z direction). In one example, the first portions 165_1, 165_2, 165_4, and 165_5 of the second gate bus line 165 may overlap the dummy regions R2a and R2b of the gate structure 130.

[0042] The second gate bus line 165 may be connected vertically to the first gate bus line 155 by passing through the first insulation pattern ILD1 in at least one region. In one example, the second gate bus line 165 may be connected to the first-1 gate bus line 155a by passing through the first insulation pattern ILD1 at the first-1 portions 165_1 and 165_2. For example, the second gate bus line 165 may be connected to the first-1 gate bus line 155a by passing through the first insulation pattern ILD1 disposed below the first-1 portion 165_2. In one example, the second gate bus line 165 may be connected to the first-2 gate bus line 155b by passing through the first insulation pattern ILD1 at the first-2 portions 165_4 and 165_5. For example, the second gate bus line 165 may be connected to the first-2 gate bus line 155b by passing through the first insulating pattern ILD1 disposed under the first-2 portion 165_4.

[0043] The second portion 165_3 of the second gate bus line 165 extends from the first portions 165_1, 165_2, 165_4, and 165_5 and may overlap the first source electrode 150 in the vertical direction (Z direction). The second portion 165_3 of the second gate bus line 165 is a region where a conductive terminal 170 (described later) is disposed and may be a gate pad region for the gate structure 130. In one example, the second portion 165_3 of the second gate bus line 165 may overlap the second portion 131_2 of the first finger portion 131 of the gate structure 130 and a part of the second finger portion 132 adjacent to the first finger portion 131 in the vertical direction (Z direction). The second portion 165_3 of the second gate bus line 165 may overlap the cell region R1 of the gate structure 130.

[0044] The conductive terminal 170 and the first and second gate bus lines 155 and 165 are electrically connected to the gate structure 130 and may be a gate wiring structure for connecting the gate structure 130 to the outside. The conductive terminal 170 may be disposed on the second portion 165_3 of the second gate bus line 165. In one example, the second portion 165_3 of the second gate bus line 165 may overlap the conductive terminal 170 in the vertical direction (Z direction). In one example, the conductive terminal 170 may overlap at least a portion of the finger portions 131 and 132 of the gate structure 130 in the third direction (Z direction). The conductive terminal 170 may have an upper surface on which a pad metal layer or a wire structure (not shown) is disposed, and may be electrically connected to the pad metal layer or the wire structure to apply an electrical signal. In another example, the conductive terminal 170 may be a gate wire or a wire pad to which the gate wire is connected. In one example, the second portion 165_3 of the second gate bus line 165 may extend to and be electrically connected to a lower portion of the conductive terminal 170. The shape of the conductive terminal 170 may be rectangular, circular, oval, or the like in a plan view.

[0045] The second source electrode 160 may be disposed on the first insulating pattern ILD1 covering the first source electrode 150. The second source electrode 160 may overlap the first source electrode 150 in the vertical direction (Z direction). In one example, the area of ​​the second source electrode 160 on a plane may be smaller than the area of ​​the first source electrode 150 on a plane.

[0046] At least one region of the second source electrode 160 may be vertically connected to the first source electrode 150 through the first insulating pattern ILD1.

[0047] The second source electrode 160 may include a 2-1 source electrode 160_3 and 2-2 source electrodes 160_1 and 160_2 extending from the 2-1 source electrode 160_3 and disposed between the first portions 165_1 and 165_5 and the second portion 165_3 of the second gate bus line 165. The 2-2 source electrodes 160_1 and 160_2 may include a 2-2a source electrode 160_1 disposed between the 1-1 portion 165_1 and the second portion 165_3 and a 2-2b source electrode 160_2 disposed between the 1-2 portion 165_5 and the second portion 165_3. The 2-2a source electrode 160_1 and the 2-2b source electrode 160_2 may be spaced apart in the second direction (Y direction) across the second portion 165_3 of the second gate bus line 165.

[0048] The second gate bus line 165 may be arranged parallel to the second source electrode 160 in the horizontal direction without overlapping with the second gate bus line 165 in the vertical direction (Z direction). A second insulating pattern ILD2 may be arranged between the second gate bus line 165 and the second source electrode 160. The second gate bus line 165 may not be electrically connected to the second source electrode 160 by the second insulating pattern ILD2.

[0049] The second insulating pattern ILD2 may fill a space between the second gate bus line 165 and the second source electrode 160. The top surface of the second insulating pattern ILD2 may be disposed at the same level as the top surfaces of the second gate bus line 165 and the second source electrode 160.

[0050] The first and source electrodes 150, 160 may include at least one of a metal material, such as nickel (Ni), aluminum (Al), titanium (Ti), silver (Ag), vanadium (V), tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), and ruthenium (Ru).

[0051] The first and second gate bus lines 155 and 165 may include a conductive material, such as a metal material, such as at least one of titanium nitride (TiN), titanium (Ti), titanium carbide (TiC), tantalum nitride (TaN), tungsten nitride (WN), aluminum (Al), tungsten (W), and molybdenum (Mo).

[0052] The drain electrode 180 may be disposed on the lower surface of the substrate 101 and electrically connected to the substrate 101. The drain electrode 180 may include at least one of a metal material, such as nickel (Ni), aluminum (Al), titanium (Ti), silver (Ag), vanadium (V), and tungsten (W). In some embodiments, the drain electrode 180 may also include a metal-semiconductor compound layer similar to the metal-semiconductor compound layer 152.

[0053] The power semiconductor device according to the embodiment of the present invention may include a first gate bus line 155 connected to the gate structure 130, and a second gate bus line 165 connected to the first gate bus line 155 and the conductive terminal 170 and overlapping the first source electrode 150 (or the cell region R1). As a result, the cell region R1 is secured, and a power semiconductor device with improved electrical characteristics may be provided.

[0054] Figure 3a is a cross-sectional view showing another embodiment of the power semiconductor element of Figure 1a taken along line II', and Figure 3b is a cross-sectional view showing another embodiment of the power semiconductor element of Figure 1a taken along line II-II'.

[0055] 3a and 3b, in the power semiconductor device 100t, the remaining configuration, excluding the gate structure 130t in the gate trench GT, the gate insulating film 123, and the well contact region 109, may be the same as or correspond to the configuration shown in Figures 2a and 2b. Of the configuration, excluding the gate structure 130t in the gate trench GT, the gate insulating film 123, and the well contact region 109, duplicated descriptions of the same or corresponding components as the configuration shown in Figures 2a and 2b will be omitted.

[0056] The well contact region 109 may be disposed on the well region 105 between adjacent source regions 107. The well contact region 109 may be disposed between the well region 105 and the first source electrode 150 so that a voltage may be applied to the well region 105 from the first and second source electrodes 150 and 160. The well contact region 109 may include a semiconductor material, such as SiC. The well contact region 109 may be a region having a second conductivity type and may include the above-described second conductivity type impurities. The concentration of the second conductivity type impurities in the well contact region 109 may be higher than the concentration of the second conductivity type impurities in the well region 105.

[0057] The gate trench GT may extend from an upper surface of the source region 107 through the source region 107 and the well region 105 into the drift layer 103. The gate trench GT may completely pass through the well region 105, and a lower end of the gate trench GT may be located in the drift layer 103. However, the length by which the gate trench GT extends into the drift layer 103 may be changed according to various embodiments. In one example, the lower end of the gate trench GT may be located on an upper surface of the drift layer 103.

[0058] The gate trench GT may include sidewalls extending in the third direction (Z direction) and in contact with the source region 107, the well region 105, and the drift layer 103, and a bottom surface extending from the sidewalls and in contact with the drift layer 103. In another example, the gate trench GT may include sidewalls in contact with the source region 107 and the well region 105, and a bottom surface extending from the sidewalls and in contact with the well region 105.

[0059] The gate trench GT may have a shape with corners without being bent. The angle between the sidewall and the bottom surface of the gate trench GT may be a right angle. In one example, the sidewall of the gate trench GT may have a vertically extending side surface, and the width of the gate trench GT may be substantially constant. However, this is not limited thereto. In another example, the angle between the sidewall and the bottom surface of the gate trench GT may be an obtuse angle. In this case, the sidewall of the gate trench GT may have a sloping side surface. The width of the gate trench GT may decrease toward the bottom of the gate trench GT. In one example, the bottom surface of the gate trench GT may extend substantially linearly in the first direction (X direction). However, this is not limited thereto, and the shape of the gate trench GT may be modified in various ways.

[0060] The gate structures 130t may be disposed in the gate trenches GT. The gate structures 130t may be disposed on the gate insulating film 123 in the gate trenches GT. In one example, the gate structures 130t may overlap the gate insulating film 123, the drift layer 103, the well region 105, and the source region 107 in the horizontal direction. The lower surfaces of the gate structures 130t may be located in the drift layer 103. The lower surfaces of the gate structures 130t may be located at a lower level than the lower surface of the well region 105, and the upper surfaces of the gate structures 130t may be located at the same level as the upper surfaces of the source regions 107. However, without being limited thereto, the upper surfaces of the gate structures 130t may be located at a lower level than the upper surfaces of the source regions 107.

[0061] The gate structure 130t may include a side surface having a shape corresponding to the sidewall of the gate trench GT, an upper surface extending from the side surface to contact the dielectric layer 125′, and a lower surface to contact the gate insulating film 123. In one example, the side surface of the gate structure 130t may be perpendicular to the substrate 101. However, this is not limiting. The side surface of the gate structure 130t may be inclined with respect to the substrate 101.

[0062] The gate insulating film 123 may be disposed in the gate trench GT. The gate insulating film 123 may cover the side and bottom surfaces of the gate structure 130t. In one example, the gate insulating film 123 may be disposed between the source region 107, the well contact region 109, the well region 105, and the drift layer 103 and the gate structure 130t. The gate insulating film 123 may include an insulating material. The insulating material may include an oxide or a nitride. The gate insulating film 123 may be composed of a plurality of insulating layers.

[0063] 4a to 4b are schematic plan views of a partial configuration of a power semiconductor element according to another embodiment of the present invention, FIG. 5a is a cross-sectional view showing another embodiment of the power semiconductor element of FIG. 4a taken along line III-III', and FIG. 5b is a cross-sectional view showing another embodiment of the power semiconductor element of FIG. 4a taken along line IV-IV'.

[0064] 4a is a schematic plan view of a gate structure 130' of a power semiconductor device 100a according to another embodiment of the present invention, and FIG. 4b is a schematic plan view of a first gate bus line 155' and a first source electrode 150' of the power semiconductor device 100a according to another embodiment of the present invention. The second gate bus line 165 and the second source electrode 160 of the power semiconductor device 100 of FIG. 1c can be similarly applied to the power semiconductor device 100a.

[0065] 4a to 5b, in the power semiconductor device 100a, the remaining components, excluding the gate structure 130′, the first gate bus line 155′, and the first source electrode 150′, may be the same as or correspond to the components shown in Figures 2a and 2b. Duplicate descriptions of components that are the same as or correspond to the components shown in Figures 2a and 2b will be omitted.

[0066] 4a to 5b, the power semiconductor device 100a may include a substrate 101, a drift layer 103 on the substrate 101, well regions 105 extending from an upper surface of the drift layer 103, source regions 107 extending from an upper surface of each of the well regions 105, a gate structure 130′ on the drift layer 103, an insulating liner 122 between the gate structure 130′ and the well region 105, a dielectric layer 125 covering the gate structure 130′, a first source electrode 150′ and a first gate bus line 155′ covering the dielectric layer 125, a second source electrode 160 arranged on a portion of the first source electrode 150′, a second gate bus line 165 arranged on the first gate bus line 155′ and extending onto the first source electrode 150′, and a drain electrode 180 on the lower surface of the substrate 101. In one example, the power semiconductor device 100a may further include a first insulating pattern ILD1 arranged between the first source electrode 150′ and the first gate bus line 155′ and a second insulating pattern ILD2 arranged between the second source electrode 160 and the second gate bus line 165.

[0067] The gate structure 130' may include body portions 135 extending in a first direction (X direction) and finger portions 132 disposed between and connecting the body portions 135.

[0068] The body portion 135 may include first and second body portions 135a and 135b extending in a first direction (X direction) and spaced apart in a second direction (Y direction). The finger portions 132 may be a plurality of gate electrodes extending from the first and second body portions 135a and 135b in the second direction (Y direction) and spaced apart from each other in the first direction (X direction).

[0069] The gate structure 130' may include a cell region R3 and dummy regions R4a and R4b. In one example, the cell region R3 of the gate structure 130' may be a region overlapping a first source electrode 150' (described later) in the third direction (Z direction). The dummy regions R4a and R4b of the gate structure 130' may be a region overlapping a first gate bus line 155' (described later) in the third direction (Z direction).

[0070] A first gate bus line 155' and a first source electrode 150' may be disposed on the gate structure 130'. In one example, the first gate bus line 155' may be disposed on the body portion 135 of the first gate structure 130'. The first gate bus line 155' may be in contact with the dielectric layer 125 covering the body portion 135 of the first gate structure 130'.

[0071] The first gate bus line 155' may include a 1-1 gate bus line 155a' overlapping the first body portion 135a and a 1-2 gate bus line 155b' overlapping the second body portion 135b. In one example, the 1-1 and 1-2 gate bus lines 155a' and 155b' may be spaced apart from each other in the second direction (Y direction) and have a bar shape extending in the first direction (X direction). That is, the dummy regions R4a and R4b of the gate structure 130' may have a bar shape corresponding to the 1-1 and 1-2 gate bus lines 155a' and 155b'.

[0072] The first gate bus line 155' may be connected to the gate structure 130' by passing through the dielectric layer 125 covering the first and second body portions 135a and 135b. In one example, the 1-1 gate bus line 155a' may be connected to the gate structure 130' by passing through the dielectric layer 125 covering the first body portion 135a. For example, the 1-2 gate bus line 155b' may be connected to the gate structure 130' by passing through the dielectric layer 125 covering the second body portion 135b.

[0073] The first source electrode 150′ may overlap the finger portion 132 of the gate structure 130′ in the vertical direction (Z direction). That is, the cell region R3 of the gate structure 130′ may have a rectangular shape corresponding to the shape of the first source electrode 150′.

[0074] The top surface of the first gate bus line 155' may be disposed at substantially the same level as the top surface of the first source electrode 150'.

[0075] The first gate bus line 155' may not overlap with the first source electrode 150' in the third direction (Z direction) and the first direction (X direction). The first-1 gate bus line 155a' and the first-2 gate bus line 155b' may be spaced apart in the second direction (Y direction) with the first source electrode 150' sandwiched therebetween. In one example, the first-1 gate bus line 155a', the first source electrode 150', and the first-2 gate bus line 155b' may be spaced apart in sequence in the second direction (Y direction). In one example, a first insulation pattern ILD1 may be disposed in a space between the first gate bus line 155' and the first source electrode 150' and on the first gate bus line 155' and the first source electrode 150'.

[0076] The second source electrode 160 and the second gate bus line 165 may be disposed on the first source electrode 150' and the first gate bus line 155'. In one example, the second source electrode 160 and the second gate bus line 165 may be disposed on a first insulating pattern ILD1 disposed on the first source electrode 150' and the first gate bus line 155'. The second source electrode 160 and the second gate bus line 165 may be in contact with the first insulating pattern ILD1 covering the top surfaces of the first source electrode 150' and the first gate bus line 155'.

[0077] The second gate bus line 165 may include first portions 165_1 and 165_5 overlapping the first gate bus line 155' and second portions 165_2, 165_3, and 165_4 extending from the first portions 165_1 and 165_5 to connect the first portions 165_1 and 165_5. The first portions 165_1 and 165_5 of the second gate bus line 165 may include a 1-1 portion 165_1 overlapping the 1-1 gate bus line 155a' and a 1-2 portion 165_5 overlapping the 1-2 gate bus line 155b'. In one example, the second portions 165_2, 165_3, and 165_4 may overlap the first source electrode 150'. In one example, the first portions 165_1 and 165_5 may overlap the first and second body portions 135a and 135b of the gate structure 130'. The second portions 165_2, 165_3, and 165_4 may overlap the finger portions 132 of the gate structure 130'. In one example, the first portions 165_1 and 165_5 of the second gate bus line 165 may overlap the dummy regions R4a and R4b of the gate structure 130'. The second portions 165_2, 165_3, and 165_4 of the second gate bus line 165 may overlap the cell region R3 of the gate structure 130'.

[0078] The second gate bus line 165 may be connected to the first gate bus line 155a' by passing through the first insulating pattern ILD1 at the first-1 portion 165_1, and may be connected to the first-2 gate bus line 155b' by passing through the first insulating pattern ILD1 at the first-2 portion 165_5.

[0079] The second portions 165_2, 165_3, and 165_4 of the second gate bus line 165 extend from the first portions 165_1 and 165_5 and may overlap the first source electrode 150′ in the vertical direction (Z direction). The second portions 165_2, 165_3, and 165_4 may overlap a part of the finger portion 132 in the vertical direction (Z direction).

[0080] A conductive terminal 170 may be disposed on the second portion 165_3 of the second gate bus line 165. In one example, the second portion 165_3 of the second gate bus line 165 may overlap the conductive terminal 170 in the vertical direction (Z direction).

[0081] The second source electrode 160 may be disposed on the first insulating pattern ILD1 covering the first source electrode 150′. The second source electrode 160 may overlap the first source electrode 150′ in the vertical direction (Z direction). In one example, the planar area of ​​the second source electrode 160 may be smaller than the planar area of ​​the first source electrode 150′. The second source electrode 160 may overlap a portion of the finger portion 132 of the gate structure 130′. In one example, the second source electrode 160 may be connected to the first source electrode 150′ by passing through the first insulating pattern ILD1 covering the first source electrode 150′.

[0082] The power semiconductor device 100a according to an embodiment of the present invention may include a first gate bus line 155' connected to the gate structure 130', and a second gate bus line 165 connected to the first gate bus line 155' and the conductive terminal 170 and overlapping the first source electrode 150' (or cell region R3). This ensures the cell region R3, thereby providing a power semiconductor device with improved electrical characteristics.

[0083] FIG. 6 is a schematic plan view of a partial configuration of a power semiconductor device according to another embodiment of the present invention, and FIG. 7 is a cross-sectional view showing another embodiment of the power semiconductor device taken along line V-V' of FIG. 6.

[0084] FIG. 6 is a schematic plan view of a gate structure 130', a first gate bus line 155_b, and a first source electrode 150' of a power semiconductor device 100b according to another embodiment of the present invention.

[0085] 6 and 7, in the power semiconductor device 100b, the configuration other than the first gate bus line 155_b and the first insulation pattern ILD1′ may be the same as or correspond to the configuration shown in Figures 5a and 5b, and redundant descriptions of the components that are the same as or correspond to the configuration shown in Figures 5a and 5b will be omitted.

[0086] 6 and 7, the power semiconductor device 100b may include a substrate 101, a drift layer 103 on the substrate 101, a well region 105 extending from the upper surface of the drift layer 103, a source region 107 extending from the upper surface of the well region 105 in each of the well regions 105, a gate structure 130′ on the drift layer 103, an insulating liner 122 between the gate structure 130′ and the well region 105, a dielectric layer 125 covering the gate structure 130′, a first source electrode 150′ and a first gate bus line 155_b covering the dielectric layer 125, a second source electrode 160 arranged on a portion of the first source electrode 150′, a second gate bus line 165 arranged on the first gate bus line 155_b and extending onto the first source electrode 150′, and a drain electrode 180 on the lower surface of the substrate 101. In one example, the power semiconductor device 100b may further include a first insulation pattern ILD1′ disposed between the first source electrode 150′ and the first gate bus line 155_b and a second insulation pattern ILD2 disposed between the second source electrode 160 and the second gate bus line 165. The second gate bus line 165 and the second source electrode 160 of the power semiconductor device 100 of FIG. 1c may be applied to the power semiconductor device 100b.

[0087] The first gate bus line 155_b may include a 1-1 gate bus line pattern 155a_b overlapping the first body portion 135a and a 1-2 gate bus line pattern 155b_b overlapping the second body portion 135b. In one example, the 1-1 gate bus line pattern 155a_b and the 1-2 gate bus line pattern 155b_b may be spaced apart from each other in the second direction (Y direction). The 1-1 gate bus line pattern 155a_b and the 1-2 gate bus line pattern 155b_b may each include electrode patterns spaced apart from each other in the first direction (X direction). In one example, the 1-1 gate bus line pattern 155a_b may include electrode patterns 155a_b1, 155a_b2, 155a_b3, and 155a_b4 spaced apart from each other in the first direction (X direction). The first-second gate bus line pattern 155b_b may also include electrode patterns spaced apart in the first direction (X direction) similarly to the first gate bus line pattern 155a_b.

[0088] The electrode patterns included in each of the first-1 gate bus line pattern 155a_b and the first-2 gate bus line pattern 155b_b may be spaced apart from each other in the first direction (X direction) by a first insulation pattern ILD1'. Finger portions 132 may branch from the electrode patterns included in each of the first-1 gate bus line pattern 155a_b and the first-2 gate bus line pattern 155b_b and extend in the second direction (Y direction). In one example, the first insulation pattern ILD1' may be arranged between the electrode patterns 155a_b1, 155a_b2, 155a_b3, and 155a_b4 of the first-1 gate bus line pattern 155a_b. For example, a 1-1 insulation pattern ILD1a may be arranged between the 1-1 electrode pattern 155a_b1 and the 1-2 electrode pattern 155a_b2, a 1-2 insulation pattern ILD1b may be arranged between the 1-2 electrode pattern 155a_b2 and the 1-3 electrode pattern 155a_b3, a 1-3 insulation pattern ILD1c may be arranged between the 1-3 electrode pattern 155a_b3 and the 1-4 electrode pattern 155a_b4, and a 1-4 electrode pattern 155a_b4 may be arranged between the 1-3 insulation pattern ILD1c and the 1-4 insulation pattern ILD1d.

[0089] The first insulating pattern ILD1' may expose upper surfaces of the electrode patterns of the 1-1 gate bus line pattern 155a_b and the 1-2 gate bus line pattern 155b_b. In one example, upper surfaces of the electrode patterns 155a_b1, 155a_b2, 155a_b3, and 155a_b4 of the 1-1 gate bus line pattern 155a_b may be exposed by the first insulating pattern ILD1'.

[0090] The second gate bus line 165 may contact the upper surfaces of the electrode patterns of the 1-1 gate bus line pattern 155a_b and the 1-2 gate bus line pattern 155b_b exposed by the first insulation pattern ILD1'. In one example, the 1-1 portion 165_1 of the second gate bus line 165 may contact the upper surfaces of the electrode patterns 155a_b1, 155a_b2, 155a_b3, and 155a_b4 of the 1-1 gate bus line pattern 155a_b. The 1-2 portion 165_5 of the second gate bus line 165 may contact the upper surface of the electrode pattern of the 1-2 gate bus line 155b_b.

[0091] The electrode patterns 155a_b1, 155a_b2, 155a_b3, and 155a_b4 of the 1-1 gate bus line pattern 155a_b may be connected to the gate structure 130' by penetrating the dielectric layer 125 covering the first body portion 135a of the gate structure 130'.

[0092] In another embodiment, the 1-1 extension portion 155a_1 and the 1-2 extension portion 155b_1 of the first gate bus line 155 of the power semiconductor device 100 of FIG. 1b may also include electrode patterns spaced apart in the first direction (X direction).

[0093] In the power semiconductor device 100b, the phenomenon of a relatively large voltage drop occurring in an area far from the gate pad (e.g., the conductive terminal 170 in FIG. 5b) is improved, thereby improving the uniformity of the voltage drop. That is, in the power semiconductor device 100b, the uniformity of the voltage applied to the gate electrode 130′ via the conductive terminal 170 can be improved.

[0094] 8a and 8b are schematic plan views of a partial configuration of a power semiconductor device according to another embodiment of the present invention.

[0095] FIG. 8a is a schematic plan view of a gate structure 130, a first gate bus line 155″, and a first source electrode 150″ of a power semiconductor device 100c according to another embodiment of the present invention, and FIG. 8b is a schematic plan view of a second gate bus line 165″ and a second source electrode 160″ of a power semiconductor device 100c according to another embodiment of the present invention.

[0096] 8a and 8b, in the power semiconductor device 100c, the remaining configurations except for the first gate bus line 155", the first source electrode 150", the second gate bus line 165", and the second source electrode 160" may be the same as or correspond to the configurations shown in FIGS. 2a and 2b. Duplicate descriptions of components that are the same as or correspond to the configurations shown in FIGS. 2a and 2b will be omitted.

[0097] The first gate bus line 155'' and the second gate bus line 165'' of the power semiconductor device 100c according to the embodiment may have a cross-sectional area that gradually changes in the first direction (X direction) that is the extension direction.

[0098] The first gate bus line 155" may include a 1-1 gate bus line 155c and a 1-2 gate bus line 155d spaced apart from the 1-1 gate bus line 155c in the second direction (Y direction). In one example, the 1-1 gate bus line 155c overlaps the first body portion 135a of the gate structure 130 and includes a 1-1 extension portion 155c_1 and a 1-2 extension portion 155c_2 that extend in the first direction (X direction). The first-second gate bus line 155d may include a first-first bent portion 155c_2 extending from the first main body portion 135b of the gate structure 130 and disposed on one end of the first finger portion 131. The first-second gate bus line 155d may include a first-second extending portion 155d_1 overlapping the second main body portion 135b of the gate structure 130 and extending in the first direction (X direction), and a first-second bent portion 155d_2 extending from the first-second extending portion 155d_1 and disposed on the other end of the first finger portion 131.

[0099] The cross-sectional area of ​​each of the first-first extension portion 155c_1 of the first-first gate bus line 155c and the first-second extension portion 155d_1 of the first-second gate bus line 155d may increase as the electrical path from the gate pad (e.g., the conductive terminal 170 in FIG. 2b) becomes longer. Unless otherwise specified in this specification, "cross-sectional area" refers to the area of ​​a cross section perpendicular to the extension direction. The cross-sectional area, e.g., width, of each of the first-first extension portion 155c_1 and the first-second extension portion 155d_1 may increase as they become farther away from the conductive terminal 170 disposed on the second portion 165c_3 of the second gate bus line 165c. The width of each of the first-first extension portion 155c_1 and the first-second extension portion 155d_1 may gradually increase in the first direction (X direction), which is the extension direction. The widths of the 1-1 extension portion 155c_1 and the 1-2 extension portion 155d_1 may increase continuously or linearly, but are not limited thereto, and the widths of the 1-1 extension portion 155c_1 and the 1-2 extension portion 155d_1 may increase discontinuously or non-linearly.

[0100] Each of the 1-1 extension portion 155c_1 and the 1-2 extension portion 155d_1 may gradually increase in width from a second width W2 to a third width W3 in the second direction (Y direction).

[0101] The first-first bending portion 155c_2 of the first-first gate bus line 155c and the first-second bending portion 155d_2 of the first-second gate bus line 155d may each have a constant cross-sectional area along the second direction (Y direction). That is, the first-first bending portion 155c_2 and the first-second bending portion 155d_2 may each have a constant first width W1 along the second direction (Y direction). However, the present invention is not limited thereto, and the cross-sectional area of ​​the first-first bending portion 155c_2 and the first-second bending portion 155d_2 may increase as the distance from the conductive terminal 170 increases along the second direction (Y direction). That is, the first-first bending portion 155c_2 and the first-second bending portion 155d_2 may each have a narrower width at a portion spaced a first distance from the conductive terminal 170 than at a portion spaced a second distance greater than the first distance.

[0102] The first source electrode 150″ may be disposed on a portion of the gate structure 130. In one example, the first source electrode 150″ may be disposed on a portion of the first finger portion 131 and the second finger portion 132. The first source electrode 150″ may include a 1-1 source electrode 150_1″ disposed on the second finger portion 132 and a 1-2 source electrode 150_2″ extending from the 1-1 source electrode 150_1″ and disposed on a portion of the first finger portion 131.

[0103] The width of the 1-1 source electrode 150_1" may gradually decrease along the first direction (X direction), which is the extension direction. The 1-1 source electrode 150_1" may have a fourth width W4 at a portion spaced a first distance from the conductive terminal 170, and a fifth width W5 smaller than the fourth width W4 at a portion spaced a second distance greater than the first distance.

[0104] The width of the 1-1 source electrode 150_1" may decrease continuously or linearly. However, without being limited thereto, the width of the 1-1 source electrode 150_1" may decrease discontinuously or non-linearly. In one example, the width of the 1-1 source electrode 150_1" may decrease along the first direction (X direction) which is the extension direction, in response to the increase in each width of the 1-1 extension portion 155c_1 and the 1-2 extension portion 155d_1 along the first direction (X direction).

[0105] A second source electrode 160" and a second gate bus line 165" may be disposed on the first source electrode 150" and the first gate bus line 155".

[0106] The second gate bus line 165'' may include first portions 165_1'', 165_2'', 165_4'', 165_5'' overlapping the first gate bus line 155'', and a second portion 165_3'' extending from the first portions 165_1'', 165_2'', 165_4'', 165_5'' and connecting the first portions 165_1'', 165_2'', 165_4'', 165_5''.

[0107] The shapes of the first portions 165_1", 165_2", 165_4", and 165_5" of the second gate bus line 165" may correspond to the shape of the first gate bus line 155". The 1-1 portions 165_1", 165_2" may overlap with the 1-1 gate bus line 155c. The 1-2 portions 165_4", 165_5" may overlap with the 1-2 gate bus line 155d.

[0108] The cross-sectional area of ​​each of the first-1 portion 165_1″ and the first-2 portion 165_5″ overlapping with the first-1 extension portion 155c_1 and the first-2 extension portion 155d_1 of the first gate bus line 155″ may increase, for example, the width, as it moves away from the conductive terminal 170. In one example, each of the first-1 portion 165_1″ and the first-2 portion 165_5″ may gradually increase from the second width W2′ to the third width W3′ in the second direction.

[0109] Each of the 1-1 portion 165_2″ and the 1-2 portion 165_4″ overlapping with the 1-1 bending portion 155c_2 and the 1-2 bending portion 155d_2 of the first gate bus line 155″ may have a constant cross-sectional area along the second direction (Y direction). That is, each of the 1-1 portion 165_2″ and the 1-2 portion 165_4″ may have a constant first width W1′ along the second direction (Y direction). However, without being limited thereto, each of the 1-1 portion 165_2″ and the 1-2 portion 165_4″ may have an increased cross-sectional area as it moves away from the conductive terminal 170 along the second direction (Y direction).

[0110] A second portion 165_3'' of the second gate bus line 165'' may extend from the first portions 165_1'', 165_2'', 165_4'', and 165_5'' to overlap the first source electrode 150''.

[0111] The second source electrode 160" may be disposed on the first insulating pattern ILD1 covering the first source electrode 150". The second source electrode 160" may overlap the first source electrode 150" in the third direction (Z direction).

[0112] The second source electrode 160″ may include a second-first source electrode 160_3″ and second-second source electrodes 160_1″ and 160_2″ extending from the second-first source electrode 160_3″ and disposed between the first portion 165_1″ and 165_5″ and the second portion 165_3″ of the second gate bus line 165″. The second-second source electrodes 160_1″ and 160_2″ may include a first portion 165_1″ and a second portion 165_3″. The second gate bus line 165" may include a 2-2a source electrode 160_1" disposed between the first portion 165_5" and the second portion 165_3" and a 2-2b source electrode 160_2" disposed between the first portion 165_5" and the second portion 165_3". In one example, the 2-2a source electrode 160_1" and the 2-2b source electrode 160_2" may be spaced apart in the second direction (Y direction) across the second portion 165_3" of the second gate bus line 165".

[0113] The cross-sectional area of ​​each of the 2-2a source electrode 160_1" and the 2-2b source electrode 160_2" may decrease as it moves away from the conductive terminal 170. Each of the 2-2a source electrode 160_1" and the 2-2b source electrode 160_2" may have a 4-1 width W4a at a first portion spaced a first distance from the conductive terminal 170, and a 4-2 width W4b smaller than the 4-1 width W4a at a portion spaced a second distance greater than the first distance.

[0114] The 2-1 source electrode 160_3" may have a shape corresponding to the overlapping 1-1 source electrode 150_1". In one example, the width of the 2-1 source electrode 160_3" may gradually decrease along the first direction (X direction) in which it extends. The 2-1 source electrode 160_3" may have a fifth width W5' at a portion spaced a first distance from the conductive terminal 170, and may have a sixth width W6' smaller than the fifth width W5' at a portion spaced a second distance greater than the first distance.

[0115] The power semiconductor device 100c according to an embodiment of the present invention may include first and second gate bus lines 155", 165", whose widths increase as the distance from the conductive terminal 170 increases. That is, one region of the first and second gate bus lines 155", 165" that is relatively close to the conductive terminal 170 may have a high resistance, while another region of the first and second gate bus lines 155", 165" that is relatively far away from the conductive terminal 170 may have a low resistance. As a result, the phenomenon of a large voltage drop occurring in a region that is relatively far away from the conductive terminal 170 in the power semiconductor device 100c may be improved, thereby improving the uniformity of the voltage drop.

[0116] Although the present invention has been described above with reference to the embodiments thereof, it will be understood by those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit and scope of the present invention as defined in the claims. [Explanation of symbols]

[0117] 101 Substrate 103 Drift Layer 105 well area 107 Source Area 122 Insulating liner 130 Gate Structure 150 first source electrode 160 second source electrode ILD1 First insulation pattern ILD2 Second insulation pattern 155 First Gate Bus Line 165 Second Gate Bus Line 170 Gate Pad 180 drain electrode

Claims

1. a substrate of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type extending from an upper surface of the drift layer and disposed within the drift layer; a source region of the first conductivity type extending from an upper surface of the well region and disposed within the well region; an insulating liner on the drift layer; a gate structure on the insulating liner; a first gate bus line on the gate structure; a second gate bus line disposed on the first gate bus line and including a first portion overlapping the first gate bus line and a second portion extending to the first portion; a conductive terminal disposed on the second portion of the second gate bus line; A power semiconductor device including a drain electrode on a lower surface of the substrate.

2. The power semiconductor device according to claim 1 , wherein the conductive terminal does not overlap the first gate bus line in a direction perpendicular to the upper surface of the substrate.

3. a dielectric layer covering the gate structure; a first source electrode disposed on the dielectric layer and in contact with the source region; 2. The power semiconductor device according to claim 1, wherein the second portion of the second gate bus line overlaps with the first source electrode in a direction perpendicular to the upper surface of the substrate.

4. 4. The power semiconductor device according to claim 3, wherein an upper surface of the first gate bus line is disposed at the same level as an upper surface of the first source electrode.

5. The power semiconductor device according to claim 3 , further comprising a first insulating pattern disposed between the first gate bus line and the first source electrode.

6. The power semiconductor device according to claim 3 , further comprising a second source electrode disposed on and connected to the first source electrode.

7. 7. The power semiconductor device according to claim 6, wherein an upper surface of the second gate bus line is disposed at the same level as an upper surface of the second source electrode.

8. The power semiconductor device according to claim 6 , further comprising a second insulating pattern disposed between the second gate bus line and the second source electrode.

9. the gate structure includes a first body portion and a second body portion spaced apart from each other and extending in a first direction, and a finger portion connecting the first body portion and the second body portion; 2. The power semiconductor device according to claim 1, wherein, in a vertical direction perpendicular to the upper surface of the substrate, the first portions of the first gate bus line and the second gate bus line overlap with the first body portion and the second body portion, and the second portion of the second gate bus line overlaps with the finger portion.

10. the first gate bus line includes a third portion that overlaps the first body portion and the second body portion in the vertical direction and extends in the first direction, and a fourth portion that extends from the third portion and extends in a second direction that intersects with the first direction; 10. The power semiconductor device according to claim 9, wherein the fourth portion of the first gate bus line overlaps a part of the first gate electrode of the finger portion in the vertical direction.

11. 11. The power semiconductor device according to claim 10, wherein the second portion of the second gate bus line overlaps with a remaining portion of the first gate electrode of the finger portion in the vertical direction.

12. The power semiconductor device of claim 9 , wherein the first gate bus line has a bar shape extending in the first direction.

13. the first gate bus lines include electrode patterns spaced apart from each other in the first direction and connected to the second gate bus lines; The power semiconductor device according to claim 9 , further comprising a first insulating pattern disposed between the electrode patterns.

14. The power semiconductor device of claim 9 , wherein the conductive terminal overlaps the finger portion of the gate structure in the vertical direction.

15. 10. The power semiconductor device according to claim 9, wherein the second gate bus line contacts the first gate bus line disposed on the first and second body portions or the finger portions.

16. 2. The power semiconductor device according to claim 1, wherein the first portions of the first gate bus line and the second gate bus line have cross-sectional areas that gradually change in one direction that is the extension direction.

17. a substrate of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type on the drift layer; a source region of the first conductivity type on the well region; a gate structure disposed on the drift layer, the gate structure including first and second body portions spaced apart from each other in a first direction, and a finger portion connecting the first body portion and the second body portion; a first gate bus line overlapping the first and second body portions; a second gate bus line disposed on the first gate bus line, the second gate bus line including a first portion overlapping the first gate bus line in a vertical direction perpendicular to the upper surface of the substrate, and a second portion extending from the first portion but not overlapping the first gate bus line; a conductive terminal disposed on the second portion of the second gate bus line; A power semiconductor device including a drain electrode on a lower surface of the substrate.

18. The power semiconductor device of claim 17 , wherein the gate structure is disposed in a gate trench that penetrates the source region and the well region.

19. a dielectric layer covering the gate structure; a first source electrode disposed on the dielectric layer and in contact with the source region; a second source electrode disposed on the first source electrode and overlapping a portion of the first source electrode in the vertical direction; 18. The power semiconductor device of claim 17, wherein the second portion of the second gate bus line overlaps with a remainder of the first source electrode.

20. a substrate of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type extending from an upper surface of the drift layer and disposed within the drift layer; a source region of the first conductivity type extending from an upper surface of the well region and disposed within the well region; an insulating liner on the drift layer; a gate structure disposed on the insulating liner, the gate structure including a cell region and a dummy region; a first gate bus line overlapping the dummy region of the gate structure in a vertical direction perpendicular to the upper surface of the substrate; a second gate bus line including a first portion overlapping the first gate bus line in the vertical direction and a second portion extending from the first portion to overlap a cell region of the gate structure; a conductive terminal disposed on the second portion of the second gate bus line; A power semiconductor device including a drain electrode on a lower surface of the substrate.

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