Wireless Power Transmission

Abstract

The power receiver 105 communicates with the power transmitter 101 using load modulated data symbols modulated by a chip sequence, the chip sequence being divided into load time intervals with different modulation loads. The power transmitter 101 comprises a receiver 207 including a load measurer 209 for determining measured load values ​​of the power transmission signal for the load time intervals. A chip determination circuit 211 determines a received chip sequence from the measured load values, the received chip sequence including a sequence of chip values. Each chip value is determined according to a difference between the measured load values ​​for at least two modulated load time intervals of a chip. The storage unit 215 stores a set of chip sequences, each chip sequence being linked to a data symbol. The detector 213 detects the received data symbol value according to a correlation between the received chip sequence and a chip sequence of the set of chip sequences.

Description

[Technical field]

[0001] The present invention relates to wireless power transfer, and in particular, but not exclusively, to communication in power transfer systems such as the Qi wireless power transfer standard. [Background technology]

[0002] Most current electrical products require a dedicated electrical contact to be powered from an external source. However, this tends to be impractical, requiring the user to physically insert a connector or otherwise establish physical electrical contact. Typically, power requirements also vary widely, and currently most devices are provided with a dedicated power source, resulting in a typical user having a number of different power sources, each dedicated to a particular device. However, while the use of an internal battery may avoid the need for a wired connection to the power source during use, this only provides a partial solution, as the battery requires recharging (or replacement). Also, using a battery may substantially increase the weight and potential cost and size of the device.

[0003] To provide a significantly improved user experience, it is proposed to use a wireless power source where power is inductively transferred from a transmitter coil in the power transmitting device to a receiver coil in the individual devices.

[0004] Power transfer via magnetic induction is a well-known concept and is mostly applied in transformers with tight coupling between the primary transmitter inductor / coil and the secondary receiver coil. By separating the primary transmitter coil and the secondary receiver coil between the two devices, wireless power transfer between them becomes possible based on the principle of loosely coupled transformers.

[0005] Such a configuration allows for wireless power transmission to a device without the need for wires or physical electrical connections. Indeed, a device can simply be placed adjacent to or on the transmitter coil for external recharging or powering. For example, the power transmitter can be configured to have a horizontal surface onto which a device can simply be placed to provide power.

[0006] Moreover, such wireless power transmission configurations can be advantageously designed so that the power transmitter can be used with a range of power receiving devices. In particular, a wireless power transmission approach known as the Qi standard has been defined and is currently being further developed. This approach allows power transmitter devices that meet the Qi standard to be used with power receiver devices that meet the Qi standard without having to be from the same manufacturer or exclusive to each other. The Qi standard further includes several features to allow the operation to be adapted to a specific power receiving device (e.g., depending on a specific power drain).

[0007] The Qi standard has been developed by the Wireless Power Consortium and further information can be found, for example, on its website http: / / www.wirelesspowerconsortium.com / index.html, in particular the defined specifications.

[0008] To support efficient wireless power transmission, wireless power transmission systems, such as Qi-based systems, utilize substantial communication between the power transmitter and the power receiver. Initially, Qi only supported communication from the power receiver to the power transmitter using load modulation of the power transmission signal. Thus, early Qi devices only supported one-way communication from the power receiver to the power transmitter.

[0009] However, the development of standards has introduced bidirectional communication, and many functions are supported by communication exchanges between the power receiver and the power transmitter. In many systems, communication from the power transmitter to the power receiver is achieved by modulating the power transmission signal.

[0010] Some systems have proposed using separate, dedicated communication capabilities, such as, for example, Bluetooth or NFC (near field communication) based communication. However, while such approaches tend to provide efficient operation in many scenarios, they are also associated with several drawbacks, including the need for dedicated, complex communication circuitry and potentially reducing the confidence that the power transmitter is communicating with the power receiver that is actually being powered. Also, backward compatibility with, for example, Qi-based devices, can be problematic for newer devices based on separate communication.

[0011] However, communicating using load modulation of a power transmission signal that transmits power to a power receiver tends to have several associated drawbacks. For example, load modulation tends to introduce some electrical noise, including both noise into the device's signal and radiated electromagnetic noise. Load modulation can increase electromagnetic interference to other devices, and maintaining sufficient or optimal electromagnetic compatibility has proven difficult.

[0012] It has also been found in practice that load modulation can introduce undesirable spurious oscillations into the drive and power transfer signals. Another drawback is that load modulation of the power transfer signal can result in acoustic noise. Such noise can result from the effect of the variations on the electromagnetic fields caused by the load modulation on the mechanical elements, which in particular can cause the mechanical elements to move and vibrate, potentially generating acoustic noise.

[0013] In some cases, for example, the load modulation communication used in early versions of the Qi standard may not be completely reliable and may in some cases result in some bit errors. For example, high levels of noise may result in bit errors and / or may require an increase in modulation depth which may result in increased electrical or acoustic noise resulting from the load modulation.

[0014] In some methods, it may be desirable to maintain backward compatibility or change to a different communication approach that reduces the amount of changes required to existing designs and approaches, but this is a major challenge that often makes it unattractive.

[0015] Therefore, improved approaches would be advantageous, particularly approaches that enable increased flexibility, reduced cost, reduced complexity, improved power transfer operation, increased reliability, reduced communication errors, improved backward compatibility, improved electromagnetic compatibility, reduced electrical and / or acoustic noise, improved communications, and / or improved performance. Summary of the Invention [Problem to be solved by the invention]

[0016] Accordingly, the Invention seeks to preferably mitigate, reduce or eliminate one or more of the above mentioned disadvantages singly or in any combination. [Means for solving the problem]

[0017] According to one aspect of the invention, there is provided a power transmitter for wirelessly supplying power to a power receiver via an electromagnetic power transmission signal, the power transmitter comprising: an output circuit including a transmitter coil configured to generate a power transmission signal in response to a drive signal applied to the output circuit; a driver configured to generate the drive signal; and a receiver configured to receive load modulated data symbols modulated by a chip sequence, each chip of the chip sequence having a duration divided into a plurality of duty time intervals, a modulated load of the load modulation being different for successive time intervals of the plurality of duty time intervals, and a modulated load pattern formed by the modulated load of the plurality of duty time intervals being different for different chip values ​​of each chip, the receiver comprising: a load measurer configured to measure a load of the power transmission signal to determine a measured load value during a duty time interval; and a chip determination circuit configured to determine a received chip sequence from the measured load value, the received chip sequence comprising a sequence of chip values, The method comprises a chip determination circuit, in which each chip value is determined in response to a difference between measured load values ​​during at least two modulation load time intervals of a chip, a storage unit configured to store a set of chip sequences, each chip sequence being linked to a data symbol, and a detector configured to detect a received data symbol value in response to a correlation between a received chip sequence and a chip sequence of the set of chip sequences.

[0018] The present invention may in many embodiments enable improved performance, and in particular may in many embodiments enable improved communication between a power receiver and a power transmitter, which may in many embodiments enable improved power transfer.

[0019] This approach can enable improved communication and, in many embodiments, can allow for improved tradeoffs between different parameters and operating characteristics. This approach can, for example, allow for reduced modulation depth to be used while still allowing reliable communication. This approach can reduce electrical noise and / or electromagnetic interference, allowing for improved electromagnetic compatibility. This approach can often reduce or prevent acoustic noise. Additionally, the approach can provide advantageous backward compatibility, allowing for relatively easy modification of existing approaches, such as those used by the Qi standard. This approach can often reuse many features from such existing approaches. This approach can provide very efficient performance while allowing for low complexity implementation. This communication approach can be particularly advantageous for use in power transfer systems, as bandwidth considerations may be less important in such systems.

[0020] This approach can enable improved tradeoffs between various parameters, including computational resource requirements, data detection accuracy, bit error rate, data rate, etc., in many scenarios.

[0021] This approach, in many embodiments, allows for improved and / or facilitated detection of load modulation data in a power transmitter. It can reduce or eliminate in many scenarios the need to determine an average or nominal load reference level to detect modulation load levels and variations. For example, in many embodiments, chip values ​​can be determined considering only the modulation load values ​​within the chip itself.

[0022] In many scenarios, the load modulation of the individual chips can not only indicate the chip value but also provide a reference load value for the determination of the chip value.

[0023] In many scenarios, reduced sensitivity to time variations, noise, distortion, etc. is achieved for the communication of data from a power receiver to a power transmitter.

[0024] A chip sequence is a sequence / pattern of chip values. Each of these modulation load values ​​can be constant within a load time interval. The chip sequences for different data symbols have different sequences / patterns of chip values.

[0025] In many embodiments, the length of the chip sequence is greater than or equal to 10 chips and less than or equal to 1024 chips.

[0026] The measured load value may be a sample of a signal indicative of the load of the power transmission signal. The measured load value may be a sample of a parameter of the drive signal.

[0027] The load measurer may be configured to determine one measured load value for each load time interval.

[0028] The load measurer may be configured to measure the loading / loading of the power transmission signal (particularly by the power receiver) to determine a measured load value for a load time interval.

[0029] Each chip in the chip sequence can be represented by a modulated load pattern, with different chip values ​​being represented by different modulated load patterns, each modulated load pattern being formed by a sequence of load time intervals, with the modulated load value being constant within each load time interval and varying between different time intervals.

[0030] Each chip of the chip sequence is divided into at least two duty time intervals having different modulation loads, the pattern of the different modulation loads being different for different chip values.

[0031] In accordance with an optional feature of the invention, each chip of the chip sequence is divided into two duty time intervals having different modulation duties.

[0032] This may allow for improved performance and / or accelerated operation and / or reduced complexity.

[0033] In accordance with an optional feature of the invention, each chip of the chip sequence is divided into at least three duty time intervals having different modulation duties.

[0034] This may allow for improved performance and / or accelerated operation and / or reduced complexity.

[0035] In some embodiments, each chip of the chip sequence is divided into three or more duty time intervals, with adjacent duty time intervals of the chip having different modulation duty.

[0036] According to an optional feature of the invention, the load measurement device is configured to synchronize measurements of the load of the power transmission signal to cycles of the power transmission signal.

[0037] This may allow for improved performance and / or accelerated operation and / or reduced complexity, which may in particular allow for improved and / or facilitated determination of appropriate load values ​​for data symbol detection.

[0038] In accordance with an optional feature of the invention, each duty time interval has a duration of one cycle of the power transfer signal.

[0039] This may allow for improved performance and / or accelerated operation and / or reduced complexity, which in many scenarios allows for increased data rates.

[0040] In accordance with an optional feature of the invention, each load time interval has a duration of multiple cycles of the power transfer signal.

[0041] This may allow for improved performance and / or expedited operation and / or reduced complexity, which in some embodiments may provide reduced sensitivity to synchronization errors.

[0042] In accordance with an optional feature of the invention, the load measurer is configured to perform a single load measurement per load time interval.

[0043] This may allow for improved performance and / or accelerated operation and / or reduced complexity.

[0044] According to an optional feature of the invention, the chip determiner is configured to determine a binary chip value for each chip as a function of the sign of the difference between the measured load values ​​during two modulated load time intervals for a chip.

[0045] This may allow for improved performance and / or accelerated operation and / or reduced complexity.

[0046] According to an optional feature of the invention, the chip determiner is configured to determine the received chip sequence to include a soft-decision chip value in response to a magnitude of a difference between the measured loading values ​​between two modulation loading time intervals for a chip, and the detector is configured to perform a correlation with a chip sequence from the set of chip sequences in response to the soft-decision chip value. This may allow for improved performance and / or accelerated operation and / or reduced complexity.

[0047] In accordance with an optional feature of the invention, the pattern of different modulation loads is a pattern of binary modulation load values.

[0048] This may allow for improved performance and / or accelerated operation and / or reduced complexity.

[0049] According to one aspect of the present invention, a power receiver for wirelessly receiving power from a power transmitter via an electromagnetic power transmission signal is provided, the power receiver comprising: a receiver coil configured to extract power from the power transmission signal; and a transmitter configured to transmit data symbols to the power transmitter by load modulating the power transmission signal, where each data symbol is modulated by a sequence of modulation load values ​​corresponding to a chip sequence of a set of chip sequences, where the chip sequences of the set of chip sequences are linked to different data symbol values, the transmitter configured to modulate the power transmission signal by dividing a duration of each chip of the chip sequence into a plurality of load time intervals, where the modulation load of the load modulation is different for consecutive time intervals of the plurality of load time intervals; and a modulation load pattern formed by the modulation load of the plurality of load time intervals is different for different chip values ​​of each chip.

[0050] According to an optional feature of the invention, the transmitter is configured to synchronize at least two duty time intervals to a cycle of the power transmission signal.

[0051] According to one aspect of the invention, there is provided a method of operating a power transmitter for wirelessly supplying power to a power receiver via an electromagnetic power transmission signal, the power transmitter comprising: an output circuit including a transmitter coil configured to generate a power transmission signal in response to a drive signal applied to the output circuit; a driver configured to generate the drive signal; and a receiver configured to receive load modulated data symbols modulated by a chip sequence, each chip of the chip sequence having a duration divided into a plurality of duty time intervals, a modulated load of the load modulation being different for successive time intervals of the plurality of duty time intervals, and a modulated load pattern formed by the modulated load of the plurality of duty time intervals being different for different chip values ​​of each chip, the method comprising the steps of: the receiver measuring a load of the power transmission signal to determine measured load values ​​for a duty time interval; determining a received chip sequence from the measured load values, the received chip sequence comprising a sequence of chip values, each chip value being determined in response to a difference between the measured load values ​​of at least two modulated duty time intervals of a chip; and storing a set of chip sequences, each chip sequence being linked to a data symbol. Detecting a received data symbol value in response to a correlation between the received loading chip sequence and a chip sequence from the set of chip sequences.

[0052] According to one aspect of the present invention, there is provided a method of operating a power receiver for wirelessly receiving power from a power transmitter via an electromagnetic power transmission signal, the method comprising the steps of: an input circuit having a receiver coil extracting power from the power transmission signal; and load modulating the power transmission signal to transmit data symbols to the power transmitter, each data symbol being modulated by a sequence of modulation load values ​​corresponding to a chip sequence of a set of chip sequences, and each chip sequence of the set of chip sequences being linked to a different data symbol value, the step of transmitting the data symbols comprising modulating the power transmission signal by dividing a duration of each chip of the chip sequence into a plurality of load time intervals, the modulation load of the load modulation being different in successive time intervals of the plurality of load time intervals, and a modulation load pattern formed by the modulation load of the plurality of load time intervals being different for different chip values ​​of each chip.

[0053] These and other aspects, features and advantages of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. [Brief description of the drawings]

[0054] Embodiments of the present invention will now be described, by way of example only, with reference to the drawings in which: [Figure 1] FIG. 1 illustrates example elements of a power transfer system according to some embodiments of the present invention. [Diagram 2] 1 illustrates example elements of a power transmitter according to some embodiments of the present invention. [Diagram 3] FIG. 2 illustrates an example of a half-bridge inverter for a power transmitter. [Figure 4] FIG. 1 illustrates an example of a full bridge inverter for a power transmitter. [Diagram 5] 1 illustrates example elements of a power receiver according to some embodiments of the present invention. [Figure 6] FIG. 13 is a diagram showing an example of a chip sequence. [Figure 7]FIG. 1 is a diagram showing an example of load communication in a wireless power transmission system. [Figure 8] 11A and 11B are diagrams showing examples of simulation results of load modulation communication in a wireless power transmission system. [Figure 9] 1 illustrates an example of load communication in a wireless power transfer system according to some embodiments of the present invention. [Figure 10] 11A and 11B are diagrams showing examples of simulation results of load modulation communication in a wireless power transmission system. [Figure 11] 11A-11C show example simulation results of load modulation communication in a wireless power transfer system according to some embodiments of the present invention. [Figure 12] 11A and 11B are diagrams showing examples of simulation results of load modulation communication in a wireless power transmission system. [Figure 13] 11A-11C show example simulation results of load modulation communication in a wireless power transfer system according to some embodiments of the present invention. [Figure 14] 11A and 11B are diagrams showing examples of simulation results of load modulation communication in a wireless power transmission system. [Figure 15] 11A-11C show example simulation results of load modulation communication in a wireless power transfer system according to some embodiments of the present invention. [Figure 16] 11A and 11B are diagrams showing examples of simulation results of load modulation communication in a wireless power transmission system. [Figure 17] 11A-11C show examples of simulation results of load modulation communication in some implementations of a wireless power transfer system of the present invention. [Figure 18] 1A-1C illustrate examples of load communication in some implementations of a wireless power transfer system of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0055] The following description focuses on embodiments of the invention applicable to high power wireless power transfer systems utilizing power transfer approaches as known from the Qi or Ki standards, however, it will be appreciated that the invention is not limited to this application and can be applied to many other wireless power transfer systems.

[0056] 1 illustrates an example of a power transfer system according to some embodiments of the present invention. The power transfer system includes a power transmitter 101 including (or coupled to) a transmitter coil / inductor 103. The system further includes a power receiver 105 including (or coupled to) a receiver coil / inductor 107.

[0057] The system provides an inductive electromagnetic power transmission signal capable of inductively transmitting power from a power transmitter 101 to a power receiver 105. Specifically, the power transmitter 101 generates an electromagnetic signal, which is propagated as a magnetic flux by a transmitter coil or inductor 103. The power transmission signal can typically have a frequency between about 20 kHz and about 500 kHz, and in many practical systems can be about 120-150 kHz. The transmitter coil 103 and the receiver coil 107 are loosely coupled, and thus the receiver coil 107 picks up (at least a portion of) the power transmission signal from the power transmitter 101. Thus, power is transmitted from the power transmitter 101 to the power receiver 105 via wireless inductive coupling from the transmitter coil 103 to the receiver coil 107. The term power transmission signal is primarily used to refer to the induction signal / magnetic field (magnetic flux signal) between the transmitter coil 103 and the receiving coil 107, but it will be understood that equivalently it can also be considered and used to refer to an electrical signal supplied to the transmitter coil 103 or picked up by the receiving coil 107.

[0058] In an embodiment, power receiver 105 is specifically a power receiver that receives power via receiver coil 107. However, in other embodiments, power receiver 105 may include a metallic element, such as a metallic heating element, where the power transmission signal directly induces eddy currents that result in direct heating of the element.

[0059] The operation of the power transmitter 101 and the power receiver 105 will be described below with particular reference to an embodiment generally in accordance with the Qi specification (except for any modifications or extensions thereto described (or entailed) herein).

[0060] Many wireless power transfer systems utilize resonant power transfer, where the transmitter coil 103 is part of a resonant circuit, and typically the receiver coil 107 is also part of the resonant circuit. In many embodiments, the resonant circuit may be a series resonant circuit, such that the transmitter coil 103 and the receiver coil 107 may be coupled in series with corresponding resonant capacitors. The use of a resonant circuit tends to provide more efficient power transfer.

[0061] Typically, wireless power transfer systems use a power control loop to steer the system towards a suitable operating point. This power control loop varies the amount of power transmitted from the power transmitter to the power receiver. The received power (or voltage or current) can be measured and, depending on the set power value, an error signal can be generated. The power receiver feeds this error signal to the power control function of the power transmitter, which reduces this static error, ideally to zero.

[0062] FIG. 2 shows elements of the power transmitter 101 of FIG. 1 in more detail.

[0063] The power transmitter 101 includes a driver 201 capable of generating a drive signal that is provided to a power transmitter coil 103, which in return generates an electromagnetic power transmission signal, thereby providing power transmission to a power receiver 105. The transmitter coil 103 is part of an output resonant circuit that includes the transmitter coil 103 and a capacitor 203. In this example, the output resonant circuit is a series resonant circuit, although it will be appreciated that in other embodiments the output resonant circuit can be a parallel resonant circuit. It will be appreciated that any suitable resonant circuit may be used, including those that use multiple inductors and / or capacitors.

[0064] The driver 201 generates the current and voltage that are supplied to the output resonant circuit and thus to the transmitter coil 103. The driver 201 is a drive circuit, typically in the form of an inverter, that generates an AC signal from a DC voltage. The output of the driver 201 is typically a switched bridge that generates the drive signal by appropriate switching of the switches of the switched bridge. Figure 3 shows a half-bridge switched bridge / inverter. Switches S1 and S2 are controlled so that they are never closed at the same time. Alternately, S1 is closed while S2 is open and S2 is closed while S1 is open. The switches are opened and closed at a desired frequency, thereby generating an AC signal at the output. Typically, the output of the inverter is connected to the transmitter inductor via a resonant capacitor. Figure 4 shows a full-bridge switched bridge / inverter. Switches S1 and S2 are controlled so that they are never closed at the same time. Switches S3 and S4 are controlled so that they are never closed at the same time. Alternately, switches S1 and S4 are closed while S2 and S3 are open, and switches S2 and S3 are closed while S1 and S4 are open, thereby producing a square wave signal at the output. The switches are opened and closed at the desired frequency.

[0065] The power transmitter 101 further includes a power transmitter controller 205 configured to control the operation of the power transmitter 101 according to a desired operating principle. In particular, the power transmitter 101 may include many of the functions necessary to perform power control according to the Qi standard.

[0066] The power transmitter controller 205 is particularly configured to control the generation of the drive signal by the driver 201 and is in particular able to control the power level of the drive signal and thus the level of the generated power transmission signal. The power transmitter controller 205 comprises a power loop controller that controls the power level of the power transmission signal in response to power control messages received from the power receiver 105 during the power transfer phase.

[0067] FIG. 5 illustrates some example elements of the power receiver 105.

[0068] In this example, the receiver coil 107 is coupled to the power receiver controller 501 via a capacitor 503 that forms an input resonant circuit with the receiver coil 107. Thus, the power transfer can be a resonant power transfer between the resonant circuits. In other embodiments, only one or neither of the power receiver and power transmitter can utilize a resonant circuit for power transfer.

[0069] The power receiver controller 501 couples the receiver coil 107 to the load 505 via a switch 507. The power receiver controller 501 includes a power control path that converts the power extracted by the receiver coil 107 to a supply suitable for the load 505. In some embodiments, the power receiver controller 501 can provide a direct power path that simply connects the input resonant circuit to the switch 507 or the load 505, i.e., the power path of the power receiver controller 501 can be implemented simply by two wires. In other embodiments, the power path can include, for example, a rectifier and possibly a smoothing capacitor to provide a DC voltage. In still other embodiments, the power path can include more complex functions such as, for example, a voltage control circuit, an impedance matching circuit, a current control circuit, etc. Similarly, it will be appreciated that the switch 507 may only be present in some embodiments and that in some embodiments the load 505 can be permanently coupled to the input resonant circuit.

[0070] Additionally, the power receiver controller 501 may include various power receiver controller functions required to perform power transfer, particularly functions required to perform power transfer according to the Qi standard.

[0071] The power receiver 105 is configured to transmit data to the power transmitter 101. Such data may include, among other things, a power control loop error message used to implement a feedback power loop for controlling the power level of the power transmission signal during power transmission, as known to those skilled in the art. The power receiver is capable, in many embodiments, of transmitting a variety of different messages that serve different purposes, as known to those skilled in the art. For example, a variety of different messages, such as those specified in the Qi standard, may be transmitted. A message may include one or more data bits / symbols.

[0072] The power receiver is configured to transmit a message to the power transmitter using load modulation.

[0073] As is well known to those skilled in the art, for load modulation, changes in the load of the power transmission signal can be introduced by the power receiver, where the changes depend on the data values ​​to be transmitted, and these changes can be detected by the power transmitter to decode the data from the power receiver.

[0074] Load modulation can be used as a method for the power receiver to communicate control messages or other data to the power transmitter, for example according to the Qi wireless power standard.

[0075] Typically, there are two main ways to perform load modulation: either directly modifying the resistive load / power extraction of the input circuit, and / or detuning the resonance of the input circuit, for example by modifying the reactive load of the input circuit (typically by switching a capacitor in / out in line with the data to be transmitted). A similar approach can be used by the power receiver to load modulate the power transmission signal.

[0076] Correspondingly, in the power transmitter, a detection approach such as that known for the Qi standard system can be used to detect load variations. For example, a direct measurement of the power level or current amplitude of the drive signal can be used as an indicator of the load and therefore the load modulation variations introduced by the power receiver, as known to those skilled in the art.

[0077] The power receiver 105 comprises a data transmitter 509 configured to transmit data to the power transmitter 101 by load modulating the power transmission signal. For example, the data transmitter 509 can be configured to switch in / out a communication capacitor that is placed in parallel with the power receiver controller 501 or the resonant capacitor 503 and can thereby vary the resonant frequency and the loading of the power transmission signal.

[0078] The data transmitter 509 may be coupled to the power receiver controller 501 and may be configured to receive data from the power receiver controller 501 for transmission to the power transmitter.

[0079] For example, the data transmitter 509 may receive power error control data from the power receiver controller 501 and transmit corresponding power error control messages to the power transmitter 101 using load modulation. In operation, the system is typically configured to control the drive signal such that the power transmission signal achieves appropriate operating parameters / characteristics and the power transmission operates at an appropriate operating point. To do so, the power transmitter is configured to control parameters of the drive signal using a power control loop in which the power characteristics of the power transmission signal / drive signal are controlled in response to power control error messages received from the power receiver.

[0080] The data transmitter 509 is configured to transmit data symbols by load modulating a power transmission signal with a sequence of modulation load values ​​corresponding to the chip sequence.

[0081] In this approach, load modulation is used, but each symbol is represented by a chip sequence containing multiple chips, typically a sequence containing 10 to 1023 chips. Thus, rather than simply varying the load according to each symbol or bit, the data transmitter 509 is configured to transmit a given symbol (typically a bit) by a series of load changes and variations, where the changes and variations are different for each symbol. Specifically, a chip sequence can be defined for each symbol, and when transmitting a given symbol, the data transmitter 509 can read the chip sequence for that particular symbol and proceed to load modulate the power transmission signal according to the chip sequence for that symbol.

[0082] Similarly, as will be described in more detail below, the power transmitter can detect load modulation by considering the entire chip sequence, and in particular can attempt to determine the received symbol as the symbol whose measured load variation chip pattern most closely matches the chip sequence pattern of that symbol.

[0083] Such an approach in particular allows the modulation depth, i.e. the magnitude of the load fluctuations, to be significantly reduced, which can, for example, reduce electromagnetic noise and interference, reduce acoustic noise, and reduce spurious vibrations. It can also result in many embodiments in an improved signal-to-noise ratio, resulting in, for example, significantly improved and more reliable communications, often with a lower bit error rate. Thus, an overall improved power transfer can be achieved.

[0084] FIG. 6 shows some examples of two possible chip sequences. Each chip sequence consists of a sequence of chips. Typically, the set of chip values ​​is two, corresponding to a binary chip sequence. The symbol time is then divided into a number of chip intervals, and the chip sequences of chips are different for different data symbols. Typically, each sequence contains at least 10 chips, and often contains significantly more. In many embodiments, each chip sequence can have a length of 2N-1, where N is an integer typically equal to or greater than 4.

[0085] Each of the stored chip sequences is assigned to one symbol. Thus, each possible data symbol value that needs to be transmitted to the power transmitter can have a linked / associated chip sequence. For example, if only two data symbols are possible, i.e., binary communication is implemented, the set of chip sequences can include only two chip sequences.

[0086] When the power receiver wishes to transmit a data symbol, that value is provided from the power receiver controller 501 to the data transmitter 509, which proceeds to determine the chip sequence that is linked to the data symbol value to be transmitted.

[0087] The data transmitter 509 is configured to modulate the chip sequence on the power transmission signal. Specifically, the modulation load can be switched on and off (on / off) along the chip, i.e., the load can be changed according to the modulation load value of the chip sequence. The modulation load can be a part of the load of the power transmission signal that is due to the (load) modulation. The modulation load can be a part of the load of the power transmission signal that is fluctuating / variable due to the (load) modulation. In many scenarios, there may be other variations in the load of the power transmission signal, including both intended variations (e.g., variations in the extracted power for the final load) and unintended variations (e.g., changes in the position of metal (e.g., power receiver) in the vicinity of the power transmitter).

[0088] The chip sequence is selected from a set of chip sequences, and in this example the data transmitter 509 stores a set of such chip sequences, with each chip sequence linked to a data symbol value. Typically, the set of chip sequences includes a chip sequence for each possible data symbol value. For example, if binary communication is used, the first set of chip sequences may include only two chip sequences. It will be appreciated that the data transmitter 509 may store the chip sequences in any suitable form and need not store a complete sequence for each possible data symbol. For example, one or more chip sequences may be represented by a relationship to another chip sequence. For example, in the case of binary communication, the data transmitter 509 may store only a single chip sequence that corresponds to one of the binary data values. The chip sequence for the other binary data value may be given as the inverse of the stored bit sequence, and thus may be represented by the same stored bit sequence. Thus, in many cases a set of chip sequences will utilize complementary inverse chip sequences for pairs of data symbols, and thus only half of the chip sequences used will typically be explicitly stored in the data transmitter 509, with the remaining chip sequences automatically and implicitly stored as their inverses.

[0089] The chip sequences in a set are typically the same length.

[0090] Load modulation can provide advantageous operation in many systems and applications, and tends to provide reliable, low-complexity operation suitable for power transmission systems in which a power transmission signal is generated for the purpose of transmitting power. Reusing the power transmission signal as a communications carrier typically reduces complexity and requires less circuitry, thereby reducing cost. The Qi standard was originally implemented using unidirectional communication from the power receiver to the power transmitter by using load modulation with a modulation symbol shape that allows easy distinction between binary data values.

[0091] However, load modulation, as used, for example, in the Qi system, may also have some associated drawbacks, which may relate to issues such as electromagnetic compatibility, communication quality (bit error rate), and audible noise.

[0092] Load modulation can generate additional components in the electromagnetic spectrum, causing additional electromagnetic interference and electrical noise. It has also been found that in many cases the changes in the electromagnetic field caused by load modulation can cause mechanical forces and movements that result in audible noise. It has also been found that strong load modulation can disrupt the energy balance in wireless power systems and result in spurious oscillations in the communication carrier spectrum. In the presence of spurious oscillations, wireless power transmitters are often unable to properly demodulate the signal and therefore must interrupt the power supply to maintain safe operation.

[0093] This problem tends to get worse for higher power transmission levels. Indeed, as the power level of the power transmission signal increases, the load change due to the load modulation is typically required to increase as well. Typically, the load modulation is required to be a suitable percentage of the power level of the power transmission signal, or the maximum power level. For example, the load modulation caused by the load modulation may be required to have a magnitude of, for example, about 1% or more of the typical load of the power receiver (i.e., the load change of the receiver coil caused by the load modulation may be required to be 1% or more of the total load of the receiver coil 107). Qi was originally introduced for low power applications, less than about 5W. At such low power levels, the impact of the drawbacks of load modulation are relatively manageable or practically insignificant. However, the maximum power level of Qi has now been increased to a maximum of 15W, and work is underway to further increase this to a maximum level of 45W. However, at such power levels the drawbacks mentioned above tend to become more pronounced, and these may be a major obstacle to further development of the Qi specification.

[0094] The systems of Figures 1, 2 and 5 may utilize an approach that may address one or more of the problems associated with load modulation in many situations. Load modulation is used, but each symbol is represented by a chip sequence including multiple chips, typically by a sequence including 15 to 127 chips. Thus, rather than simply varying the load according to each symbol or bit, the data transmitter 509 is configured to transmit a given symbol (typically a bit) through a series of load changes and variations, where the changes and variations are different for each symbol. Specifically, a chip sequence may be defined for each symbol, and when transmitting a given symbol, the data transmitter 509 may read the chip sequence for that particular symbol and proceed to load modulate the power transmission signal according to the chip sequence for that symbol.

[0095] The power transmitter can detect load modulation by considering the entire sequence; specifically, the power transmitter can attempt to determine the received symbol as the symbol for which the detected load variation pattern most closely matches the chip sequence pattern of that symbol.

[0096] Such an approach in particular allows the modulation depth, i.e. the magnitude of the load fluctuations, to be significantly reduced, which may, for example, reduce electromagnetic noise and interference, reduce acoustic noise, and reduce spurious vibrations. It may also result in many embodiments in an improved signal-to-noise ratio, resulting in, for example, significantly improved and more reliable communications, often with a lower bit error rate. Thus, an overall improved power transfer may be achieved.

[0097] In many embodiments, binary communication may be used, where only two data symbol values ​​are possible (corresponding to a "0" or a "1" bit value). In such cases, one bit value may be represented by a given chip sequence, and the other bit value may be associated with the inverse bit sequence, i.e., the bit sequence resulting from changing each chip value to its opposite value. Thus, the two bit sequences are typically complementary, one resulting from multiplying the other by -1 (chip values ​​are represented by +1 and -1).

[0098] A particular advantage in such a case is that demodulation is particularly easy since a single correlation can be used to distinguish between bit values, since the magnitude of the correlation is the same for the chip sequence, but the sign of the correlation value is opposite.

[0099] The following description focuses on such binary communications, although it will be understood that the invention is not limited to only binary communications.

[0100] The data transmitter 509 can then be configured to receive, typically from the power receiver controller 501, data symbols to be transmitted to the power transmitter, determine a corresponding chip sequence, and proceed to load modulate the power transmission signal with this chip sequence. Typically, the data symbols are binary, but in some cases higher order modulation symbols may be used (i.e., having more than two possible values). In some cases, such higher order data symbols may correspond to combinations of the received data bits. For example, two bits can be combined into a single quaternary data symbol. Such combinations may be possible both when those data bits are related and, for example, when they are completely independent.

[0101] A longer chip sequence may provide improved noise suppression, etc., but may also result in a reduced data rate since the symbol time will increase for a given chip rate. Increasing the chip sequence length also increases the complexity and resource demands, especially at the receiver where correlation with longer sequences may require a significant number of calculations. A typical suitable value is N=5, which is a chip length of 31 chips.

[0102] Each chip sequence is assigned to one data symbol. Thus, each possible data symbol value that needs to be transmitted to the power transmitter can have a linked / associated chip sequence. For example, if only two data symbols are possible, i.e., if binary communication is implemented, the set of chip sequences can only include two chip sequences. In this case, the chip sequences may be inverses of each other as mentioned above, specifically, one may result from the multiplication of the other by -1.

[0103] The first set of chip sequences may include more than one chip sequence for a given data symbol, i.e., multiple sequences may be linked to the same data symbol (e.g., chip sequences having different lengths). Typically, however, each chip sequence is linked to one data symbol, and one data symbol is linked to only one chip sequence in the first set of chip sequences.

[0104] It will be appreciated that such a binary approach, in which two inverse chip sequences are used, is equivalent to considering two possible binary values ​​as being modulated by the same chip sequence, but with data symbols having opposite data values ​​(e.g., +1 and -1).

[0105] The power transmitter 101 of FIG. 2 comprises a receiver 207 configured to receive load modulated data symbols transmitted by the power receiver 105 using load modulation of the power transmission signal.

[0106] The receiver 207 includes a load measurer 209 configured to measure the loading of the power transmission signal to determine a measured load value of the power transmission signal. The measured load value may be indicative of the loading of the power transmission signal by the power receiver and thus the modulation load applied to the power transmission signal by the power receiver 105.

[0107] The load measurer 209 is coupled to a chip determination circuit 211 configured to determine the received chip sequence from the measured load values. The received chip sequence can specifically be a sequence of binary chip values ​​corresponding to estimated chip values ​​derived from the load measurements. The received chip sequence can in some embodiments be soft decision values ​​indicating not only the chip data values ​​but also the reliability of the chip data values. Thus, the received chip sequence is determined from the load variation determined by measuring the load of the power transmission signal.

[0108] The chip decision circuit 211 is coupled to a detector 213 to which the received chip sequence is fed. The detector 213 is coupled to a storage unit 215 that stores a set of chip sequences that specifically correspond to the chip sequences stored and used by the data transmitter 509 of the power receiver. Thus, the storage unit 215 stores chip sequences of the set of chip sequences, and the power receiver and the power transmitter therefore store local replicas of the same chip sequences, which are linked to the same data symbols. The power transmitter 101 contains a local representation of the chip sequence used by the power receiver. The power receiver and the power transmitter store the corresponding links between the reference chip sequences and the data symbols.

[0109] In this example, the storage unit 215 may only store a single data symbol chip sequence, i.e., the data symbol chip sequence used to modulate the binary data symbol (so that the single stored data symbol chip sequence is equal to the chip sequence representing one binary data value and the inverse (typically sign-reversed) chip sequence represents the other binary data value).

[0110] The detector 213 is configured to determine the data symbols received from the power receiver in response to a correlation between the stored chip sequence (of the set of chip sequences) and the received chip sequence. Specifically, in some embodiments, the load detector 213 can correlate the determined received chip sequence provided by the detector 213 with all the stored data symbol chip sequences of the set of chip sequences to determine a correlation value for each. In cases where some sequences are inverse to each other, such as the binary case described above, only one correlation can be performed, and the sign of the correlation value reflects the correlation with the two possible chip sequences.

[0111] Thus, detector 213 may correlate the received chip sequence with a reference chip sequence to determine a correlation value indicating how closely they match.

[0112] The detector 213 can then determine the data symbol as the data symbol linked to the chip sequence whose associated correlation value is sufficiently high above a given threshold. The threshold can in many embodiments be an adaptive threshold, e.g., the threshold can be set depending on the correlation value with other symbols. As a specific example, the threshold is set as the value of the next highest correlation value (e.g., a minimum threshold is applied), so that the data symbol is selected as the data symbol with the highest correlation value (e.g., above the minimum threshold).

[0113] Thus, the power receiver can transmit data to the power transmitter using load modulation with a relatively long chip sequence per data symbol, and the power transmitter can be configured to receive this communication. This approach can provide significantly improved communication and operation in many embodiments. In particular, significantly improved communication performance and reliability, in particular the symbol signal to noise ratio, can be significantly increased. This can allow the modulation depth, specifically the modulation load variation on the power transmission signal level / power transmission level, to be significantly reduced. In fact, in many cases the modulation depth can be reduced by a factor of 10, 100 or more. This can reduce and mitigate many of the drawbacks of using load modulation, for example reducing electromagnetic interference, reducing electrical noise, reducing mechanical noise, and preventing or mitigating spurious vibrations.

[0114] For example, using chip rates corresponding to the bit rates used in Qi (up to 2 kBps communication rates), the improvement in the signal-to-noise ratio can be increased by an amount corresponding to the sequence length. For example, using a bit length of 63 or 127 can increase the symbol energy-to-noise ratio by a corresponding amount while maintaining the same bit error rate, allowing the modulation depth to be reduced by a factor of 63 or 127, respectively.

[0115] A drawback of such an approach is that the effective communication rate is reduced. For example, using sequence lengths of 63 or 127 may reduce the effective baud rate to 30.7 or 15.7 bps, respectively. To address this, the chip time interval duration may be reduced. This reduction is an appropriate trade-off between the desired communication rate and bit error performance and may be selected for a particular application and implementation. Increasing the chip rate results in a corresponding increase, potentially significantly, in the required bandwidth and frequency spectrum of the load modulation. However, it is a particular advantage of the current approach that communications in wireless power transfer systems are typically not bandwidth limited or sensitive to the bandwidth of the communications, and therefore such additional bandwidth may typically be available without impacting other functions or performance.

[0116] However, while the described approach can provide favorable operation and performance in many scenarios and embodiments, it also poses some challenges. One challenge is how to accurately detect the chip value in the power transmitter. Typically, the load variation caused by load modulation is relatively small, which makes it difficult to accurately detect the chip value.

[0117] An approach that can be used to detect the chip value is to compare the measured load value to a threshold value. For example, the load measurer 209 can be configured to measure the load once per chip value, i.e., the load measurement can be a load measurement sample generated at one sample per chip.

[0118] For example, the load value (e.g., current and / or power) of the drive signal can be measured and sampled at time intervals corresponding to the chip interval during the time that a message is (expected to be) received from the power receiver, and the received chip sequence is thus generated from the sampling of the output circuit's signal.

[0119] However, since specific operating conditions tend to vary widely, a fixed, predetermined threshold is typically not feasible. Rather, appropriate thresholds can be determined based on signal conditions, and in particular, thresholds can be derived to correspond to average modulation load levels.

[0120] Figure 7 shows an example of how the power transfer signal is load modulated by the chips of the chip sequence. In this example, the modulation is synchronized to the power transfer signal at a rate of one chip per two power signal cycles. The arrows in Figure 7 indicate the times when the load of the power transfer signal is measured / sampled. The sampling is synchronized with the power transfer signal, producing one sample for each chip.

[0121] To determine the (binary) tip value, the sampled load value is compared to an average level 701. In a specific example, the load of the power transmission signal is determined as the peak cycle value of the measured signal (which may specifically be the current, voltage, phase or power of the power transmission signal) and the sampling is synchronized with the peak of the power transmission signal. Furthermore, the average level 701 of the peak cycle value is first determined and then the tip value is determined based on whether the measured sample value is above or below the average level 701.

[0122] However, while such an approach may provide a very useful communication link in many circumstances, it may be sensitive to noise, errors, etc., which may sometimes result in undesirably high bit error rates. In particular, in the approach described with reference to FIG. 7, it is important to determine the average level with high accuracy. Deviations and errors may have a significant effect not only on the individual chip values, but also on the correlation results used to determine the data symbols themselves. This may result in greatly reduced peak values, strong side lobes to the peaks, or even peaks with opposite signs, etc. This may therefore result in significant bit errors.

[0123] Figure 8 shows an example of a simulation result of such an approach. The top chart shows the sampled signal (sampled peak value of the power transmission signal) when three data symbols (two "0"s and one "1") are modulated onto the power transmission signal using a chip sequence of order 5. The bottom chart shows the output of the correlation to the chip sequence to determine the average level using a simple exponential moving average (EMA) filter. Strong side lobes can be clearly observed, which have the opposite sign to the main correlation peak, thereby potentially resulting in bit errors. The presence or absence of such side lobes strongly depends on the EMA filtering parameters, and the artifacts become more noticeable if the weight of past samples in the filtering is reduced.

[0124] However, the systems of Figures 1, 2 and 5 use a different approach, and in particular an approach that may typically provide improved performance and / or facilitated operation.

[0125] Rather than requiring an accurate average level determination, this approach effectively embeds the reference levels into the modulation format itself.

[0126] In this approach, each chip is divided into two (or more) duty time intervals with different modulation loads. Thus, each chip can include at least two duty time intervals with different modulation loads, and thus each chip is represented by at least two different modulation loads, specifically, each chip is represented by a different pattern of modulation loads for at least two duty time intervals. Furthermore, the pattern of different modulation loads is specific to a given chip value. Thus, different chip values ​​are linked to different patterns of load modulation.

[0127] In this approach, each chip of the chip sequence has a duration divided into multiple time intervals (also called load time intervals), and in many embodiments has two time intervals. The modulation load (value) varies between successive time intervals, so that the modulation load (value) is different in different time intervals. The modulation load (value) can be constant within each load time interval. In many cases, the time intervals can be considered to be defined by the time points at which the modulation load changes. Thus, the duration of a chip spans the time of at least two different modulation loads (values). Rather than corresponding to a single constant modulation load value, the chip duration spans at least two different modulation load values. Thus, rather than a constant modulation load, a pattern of modulation loads exists within each chip duration. The modulation load pattern depends on the chip value, and different chip values ​​are linked to different modulation load patterns.

[0128] Each chip of the chip sequence is represented by a modulated load pattern, different chip values ​​are represented by different modulated load patterns, and each modulated load pattern is formed by a series of load time intervals, and the modulated load value is constant within each load time interval and varies between different / consecutive time intervals. In many embodiments, the system may use a binary modulated load, i.e., the modulated load applied by the power receiver may have one of two possible load values. Such an approach is advantageous by allowing for low complexity implementation and easy operation. It typically facilitates load modulation operation for both transmit and receive functions, which tends to lead to efficient performance and reliable communication.

[0129] As an example, the data transmitter 509 can typically control the switching of modulation load components, such as capacitors or resistors, and therefore can apply different modulation loads.

[0130] Thus, in many embodiments, binary load modulation can be used. Furthermore, in many embodiments, the chip time interval can be divided into two load time intervals, with one binary load value being applied in one load time interval and the other load value being applied in the other load time interval. The two binary chip values ​​can then be determined to correspond to two possible patterns / orders of the two modulation loads assigned to the two load time intervals. Specifically, in some embodiments, each transmitted chip can be divided into two halves to have opposite modulation loads in each of those halves, with these orders (i.e., which modulation load is assigned to the first half) depending on the binary chip value.

[0131] An example of this is shown in Figure 9, where the top signal 901 shows a chip sequence and the middle signal 903 shows the variation of modulation load values. As shown, each chip is divided into two load time intervals, one with a high modulation load and one with a low modulation load. Whether the first load time interval of a given chip is a high or low modulation load depends on the chip value.

[0132] Specifically, signal 901 indicates the chips in the sequence, and signal 903 indicates the modulation load switching by the data transmitter 509, i.e., the modulation load level within the load time interval. In this example, for a "1" chip, the data transmitter 509 switches the modulation load off (or low) in the first half and on (or high) in the second half. Conversely, for a "0" chip, the data transmitter 509 switches the modulation load on (or high) in the first half and off (or low) in the second half.

[0133] In this approach, the power transmitter is configured to determine the data symbol by considering the relative load variation within the chip. Specifically, the load measurer 209 is configured to measure the load of the power transmission signal to determine a measured load value during a load time interval. A measured load value / sample can be determined for each load time interval.

[0134] The chip determination circuit 211 is configured to determine an individual chip value in response to a difference between the measured load values ​​for at least two modulated load time intervals of an individual chip.

[0135] Specifically, the tip determination circuit 211 is configured to determine a difference between two load time intervals, e.g., a load value of a first load time interval can be subtracted from a load value of a second load time interval, and depending on the result, the tip determination circuit 211 can proceed to determine a tip value as a function of the difference.

[0136] In Fig. 9, signal 905 represents a measurement of the drive signal / power transfer signal. Thus, each chip consists of a duty time interval with a high signal level (high modulation load) and a duty time interval with a low signal level (low modulation load), the order of which depends on the chip value. In this example, an increased signal level (the level of the second duty time interval is higher than the level of the first duty time interval) is decoded as a chip value of "1" and a decreased signal level (the level of the first duty time interval is higher than the level of the second duty time interval) is decoded as a chip value of "0".

[0137] The amplitude / level of the drive signal / power transfer signal in the first half of the chip (first load time interval) can serve as a reference level for measurements made in the second half of the chip (second load time interval), and vice versa. Thus, the reference for individual chip load modulation determination is embedded directly within the modulation format. Thus, chip value determination can be made without the need for average or reference levels to be estimated or determined. Rather, local, intra-chip relative measurements and comparisons can be used to determine chip values.

[0138] The chip value is then used to generate a received chip sequence, which is compared to the chip sequence by detector 213 to determine the data symbol value.

[0139] In particular, a load value indicative of the received chip sequence can be fed to the correlation detector 213, the load value being the difference between the (peak) values ​​of the drive signal / power transfer signal measured in each of the two halves of the chip. Such a procedure can eliminate the need to find the average level, and therefore any optimization of filtering parameters, etc. Another advantage is that the proposed approach is insensitive to slow or even fast variations in the power signal.

[0140] This approach can provide substantially improved performance and more reliable data communication. As an example, Fig. 10 illustrates the power transmission signal fluctuations due to load modulation and noise, as well as respective examples of correlation values ​​resulting from the approach according to Fig. 7 (using a simple EMA filter). Fig. 11 shows the corresponding results of the approach according to Fig. 9. As can be seen, the correlation peak in the latter case is clearly and significantly more pronounced. The embedded data uses a 5th order sequence with a modulation depth of 1%.

[0141] Figures 12 and 13 correspond to the examples of Figures 10 and 11, respectively, but for the case where small oscillating noise components are superimposed on the power transmission signal. The period of the oscillations is approximately half the bit length. While the approach using a simple EMA filter is highly affected by these oscillating components, the performance of the proposed new method is not affected at all.

[0142] Figures 14 and 15 correspond to the examples of Figures 10 and 11, respectively, but with a step in the carrier signal / power transmission signal. Clearly, reliable demodulation is not possible using simple EMA filtering techniques. However, demodulation with the approach of Figure 9 has little effect.

[0143] Figures 16 and 17 correspond to the examples of Figures 10 and 11, respectively, but for situations where the carrier signal / power transmission signal is subject to strong noise, strong vibrations and steep steps. The data is embedded using a 7th order sequence with a modulation depth of 1%. Demodulation is not possible using simple EMA filtering. However, using the approach of Figure 9 demodulation can be achieved with high reliability.

[0144] In many embodiments, the tip determiner circuit 211 can be configured to determine the tip value as a binary tip value. Specifically, the tip determiner circuit 211 can be configured to select the binary tip value to correspond to the sign of the difference between the load values / measurements in the load time interval of the tip. For example, if the signal peak sample is higher in the first load time interval than in the second load time interval, the tip value can be determined as "1", while if the signal peak sample is lower in the first load time interval than in the second load time interval, the tip value can be determined as "0" (or vice versa). In many embodiments, the tip determiner circuit 211 can determine the difference between the load values ​​in the load time interval and set the binary value to correspond to its sign.

[0145] Such an approach can provide a low-complexity yet accurate determination of the received chip sequence and is suitable for low-complexity correlation, for example, it can enable binary correlation operations that are significantly less complex and resource demanding because multiplications can be replaced by simple binary operations (e.g., simple binary XOR operations).

[0146] In some embodiments, the chip determiner circuit 211 can be configured to determine the received chip sequence to include soft-decision chip values. Rather than a simple binary value, the generated chip value can also indicate the reliability or reliability level of the chip value.

[0147] For example, in addition to the sign, the magnitude of the difference can be considered. For example, for a given nominal in the absence of noise, a nominal magnitude of the difference can be determined (or a nominal difference can be determined, for example, by averaging / down filtering multiple, typically many, chip differences). The deviation of a particular chip difference relative to this difference can then indicate the probability that the decision is the correct value. However, in most embodiments, the magnitude of the difference simply indicates confidence or reliability: the larger the measured difference, the more likely the sign is correct, i.e., the larger the magnitude of the difference, the more reliable the chip value.

[0148] The correlation with a chip sequence of the set of chip sequences may be performed in response to the soft decision chip values, specifically, the correlation may be performed using the soft decision values.

[0149] For example, in some embodiments, the correlation may be performed as a binary exclusive-or operation between the stored binary chip sequence and the received chip sequence formed by the determined difference sign, with the result of each exclusive-or operation being weighted (e.g., multiplied) by the magnitude of the difference (e.g., relative to a nominal difference) prior to summing the results. As another example, the stored chip sequence may be represented by chip values ​​of +1 and -1, and these values ​​may be directly multiplied by the corresponding chip load difference (corresponding to the received chip sequence). The correlation may then be determined by summing the multiplication results.

[0150] While such an approach may require more complex computations, it may provide improved performance in many embodiments and scenarios, and in particular may enable more accurate data symbol detection.

[0151] As in the above example, the chip time interval can typically be synchronized with the cycle of the power transmission signal. Similarly, the load time interval can typically be synchronized with the cycle of the power transmission signal. In many embodiments, the system can be configured to synchronize the load modulation communication (particularly the chip time interval and the load time interval) with the power transmission signal / drive signal.

[0152] In many embodiments, the data transmitter 509 can be specifically configured to synchronize the load modulation of the chip sequence and the duty time interval to the power transmission signal. The power transmission signal typically has an operating frequency in the range of 10 kHz to 500 kHz, and for Qi, is often around 100 kHz. The data transmitter 509 can adapt the timing of the chip time interval and the duty time interval to be synchronized to the oscillation and period of the power transmission signal. For example, in many embodiments, the data transmitter 509 can use chip durations / time intervals and / or duty time intervals (durations) that are multiples of the power transmission signal period. Thus, each duty time interval can have a duration that is a multiple of the period of the power transmission signal, i.e., the duration of the duty time interval can be N*T, where N is an integer and T is the duration of the period of the power transmission signal / drive signal.

[0153] In many embodiments, the data transmitter 509 not only synchronizes the duration of the duty time interval to the duration of the period of the power transmission signal, but also aligns the start and / or stop timing of the duty time interval to the timing of the power transmission signal. In particular, the transition times between modulation levels of the duty time interval can be synchronized to occur at the zero crossings of the power transmission signal or, for example, at a fixed offset relative to the zero crossings of the power transmission signal. It will be appreciated that the synchronization can be based on the timing of a signal induced in the receiver coil 107 by the power transmission signal.

[0154] Similarly, the power transmitter may be configured to generate the received chip sequence from samples / measurements of the load of the power transmission signal / drive signal (possibly after matched filtering has been applied).

[0155] The load measurement device 209 can sample signals of the output circuit corresponding to the power transmission signal, specifically the current and / or power of the drive signal, the relative phase between the current and voltage of the drive signal, the current through the transmitter coil 103, etc. The load modulation receiver 207 can then generate the received chip sequence from the difference between such load measurements at a given sampling time belonging to different load time intervals of a given chip.

[0156] In many embodiments, the load measurer 209 is configured to synchronize sampling to the power transfer signal, and specifically this may be achieved by synchronizing it to the drive signal.

[0157] In many embodiments, the synchronization may be sampling such that, for example, one sample is taken every duty time interval (possibly after matched filtering). In particular, if the duration of the duty time interval is equal to N times the period of the power transmission signal, the sampling can also be synchronized to be once every N times. Thus, in many embodiments, the synchronization can be such that the sampling rate is equal to the duty time interval frequency of the load modulation.

[0158] In some embodiments, sampling can be a two-stage process in which some samples are generated at a higher frequency and then decimated to a given sample rate. For example, for a load time interval duration of 10 times the period of the power transmission signal, the sampler can take one sample per period. The averaging filter can then sum the last 10 samples, i.e., it can be a square window FIR filter that sums the 10 most recent samples (with equal weights). The output of the sampling is then the sampled output of this filter, specifically the output every 10 periods, consistent with the filter being the sum of 10 periods within a single chip. Thus, sampling at synchronized instants can be effectively achieved by appropriately synchronized decimation at the output of the filter.

[0159] However, in most embodiments, only a single sample / measurement is performed per load time interval. In such situations, the timing of the samples can be synchronized to occur at the peak of the cycle of the signal / parameter being measured for each sample. If the load time interval and the samples are synchronized to the power transfer signal cycle, this can be accomplished by simply sampling / measuring at the center time of the load time interval.

[0160] In many embodiments, the operating frequency of the drive signal and the power transmission signal can be an integer multiple of the sampling rate of the sampling of the signal of the output circuit and / or an integer multiple of the load time interval and chip frequency of the load modulation. The multiple may specifically be 1. Indeed, in many embodiments, the integer multiple is advantageously relatively low to allow for efficient communication and higher data rates. In many embodiments, the integer is advantageously no more than 1, 3, 5, 10 or 20.

[0161] Synchronization of the load modulation to the power transmission signal may, in many practical implementations, allow a reduction in the amount of sampling that the power transmitter must perform, thus allowing an increase in the chip rate and / or bit rate. In the extreme case where the chip frequency is the same as the power transmission signal frequency, the power receiver may vary the load according to the chip sequence every cycle of the power transmission signal, and may vary the load every half cycle of the power transmission signal for two load time intervals. Alternatively, the power receiver may vary the load according to the chip sequence every N cycles of the power signal, reducing the chip frequency by a factor of N.

[0162] Synchronous modulation facilitates modulation detection at the power transmitter side by allowing it to apply synchronous sampling techniques and correlating the detected signal with the post-step modulation sequence. This approach can be significantly easier to implement while typically achieving efficient communication.

[0163] The length of the chip sequence can be selected to suit the particular preferences and requirements of an individual embodiment, and can be selected to provide a suitable compromise between communication reliability and performance (e.g., bit rate), data rate, bandwidth, modulation depth, associated drawbacks, etc. In most embodiments, lengths of 8 chips or more and / or 128 chips or less provide suitable and advantageous performance, particularly for wireless power transfer systems such as the Qi system.

[0164] In many embodiments, the first set of chip sequences may include only two chip sequences, in such an example, each symbol may be represented by one or the other chip sequence depending on the symbol value, and thus each symbol may be a binary symbol (bit) and the communication may be a binary communication.

[0165] In some embodiments, the first set of chip sequences can include more than two chip sequences, allowing more than two different symbol values. For example, in some embodiments, the first set of chip sequences can include three chip sequences, allowing, for example, three different symbol values ​​for each symbol communicated by the chip sequences. In other embodiments, more sequences can be included, allowing each chip sequence / data symbol to represent more data values, thereby increasing the effective bit rate. Such an approach is particularly suitable for longer chip sequences where a larger difference in correlation values ​​between chip sequences is feasible.

[0166] For example, for a chip length of 31 bits, 2147483648 different sequences are possible, and the system can select two of these sequences that have high autocorrelation and low cross-correlation. Typically, these sequences can be selected as the sequence with the highest autocorrelation and the binary inverse chip sequence with the lowest cross-correlation (normalized cross-correlation is -1 using the binary values ​​of -1 and 1). These two sequences can then be used for binary communication that allows high reliability, since the correlation performed by the load modulation receiver 207 produces significantly different correlation values ​​for the two possible chip sequences being received.

[0167] The particular sequences and patterns used may depend on the preferences and requirements of individual implementations. Typically, the sequences are selected to provide good correlation properties, specifically, the set of chip sequences is selected to consist of sequences with high autocorrelation and low cross-correlation values. In many embodiments, the chip sequences may be selected as maximum length sequences. For example, in many embodiments, the chip sequences may be selected as maximum length sequences generated from a polynomial, the order of the polynomial being selected by the power receiver according to the desired / selected modulation depth and the desired communication rate. In particular, pseudo-noise sequences developed for and used in direct sequence spread spectrum communication and code division multiple access systems tend to be well suited to the described approach.

[0168] As mentioned above, the set of sequences may include mirror image or inverted chip sequences, i.e., for a given binary chip sequence, the set of chip sequences may also include chip sequences in which all chips have complementary values. For example, if the load values ​​are represented by 1 and -1, the set of chip sequences may also include, for each chip sequence, a chip sequence resulting from multiplication by -1 (equivalent to a swap between 0 and 1 for all chips for chip sequences represented by values ​​of 1 and 0). Indeed, in some embodiments, the set of chip sequences may include only a chip sequence and its inverted chip sequence. It will be appreciated that in such embodiments, only a single representation needs to be stored to represent the pair of chip sequence and inverted chip sequence.

[0169] Such an approach is particularly suitable for many applications and may result in good performance and low complexity. For example, a single correlation between the received chip sequence and the reference chip sequence can provide correlation values ​​for both the reference chip sequence and the inverse chip sequence. Indeed, in the absence of noise, the correlation value of one of the reference chip sequences is +1, and the correlation value of the inverse reference chip sequence is -1. Thus, a single correlation value applicable to two symbol values / sequences can be determined and can be directly used to select between the two symbols.

[0170] It will be appreciated that the approach of using an inverted reference chip sequence can be considered equivalent to multiplying the binary data symbols with a single reference chip sequence (using values ​​of 1 and -1 to represent binary values).

[0171] As a specific example, the system may employ the following approach.

[0172] The power receiver significantly reduces the depth of load modulation, resulting in no spurious vibrations and reduced electrical and acoustic noise.

[0173] The power receiver encodes the individual bits as a direct (eg, pseudorandom) chip sequence that has a steep autocorrelation function.

[0174] The power receiver operates the load (typically by changing the load or detuning a resonant circuit) in synchronization with the power transmission signal (eg, a transition every power signal cycle or every multiple power signal cycles).

[0175] The power transmitter measures the load change, for example, by measuring the power transmitter coil voltage or coil current at a sampling time synchronized to the power transmission signal (e.g., one sample per power signal cycle, multiple samples per power signal cycle, or one sample per multiple power signal cycles).

[0176] The power transmitter determines the received chip sequence based on the load change between load time intervals within each chip.

[0177] The power transmitter decodes the data by correlating the received chip sequence with the stored chip sequences to find the matching chip sequence, and thus the data symbol value.

[0178] The chip sequence and the number of power signal cycles per symbol are known in advance by the power receiver and the power transmitter.

[0179] In the described example, each chip is divided into two load time intervals with different modulation loads. This allows for efficient operation with improved performance. In particular, it allows for low complexity and low resource usage while still providing significantly improved performance in many embodiments.

[0180] However, in some embodiments, each chip may be divided into three or more duty time intervals with different modulation duty.

[0181] For example, in some embodiments, each chip can be divided into three load time intervals, where the load level in the first load time interval is a reference level. The load in the second load time interval is higher than the reference level for the first binary chip value, and the load in the third load time interval is lower than the reference level. For other binary values, the load is lower than the reference level in the second load time interval and higher than the reference level in the third load time interval. Then, the chip determination circuit 211 can determine the (e.g., binary) chip value by detecting whether there are two load changes and in which direction they are changing in each load time interval. Such an approach allows for improved chip value determination in different scenarios. For example, it can reduce sensitivity to the direction of the load change.

[0182] In other embodiments, more load time intervals with different load values ​​can be used to represent non-binary chips, for example having three load time intervals allows four different chip values.

[0183] In many embodiments, each duty time interval can have the duration of a single cycle of the power transfer signal, which is advantageous in many embodiments because it can, for example, reduce the minimum time required per chip, thereby allowing higher data rates or, for example, longer chip sequences to be used.

[0184] However, in some embodiments, each load time interval can have a duration of multiple cycles of the power transmission signal. In some embodiments, each load time interval can have a duration of 2, 3, 5, 10 or more cycles of the power transmission signal. This is advantageous in many scenarios, for example, by facilitating or improving the measurement process. For example, while synchronization to the sample peak value of the power transmission signal / drive signal is relatively easy to achieve, synchronization between the set of cycles corresponding to each load time interval and the chip can be difficult. For example, the alignment between the cycle peaks and the load time intervals of the individual chips can be disrupted, resulting in the power transmitter assigning the load measurements to the wrong load time interval / chip.

[0185] For example, in many embodiments, the determination of the next power transfer signal cycle can be determined by detecting zero crossings of the power transfer signal. However, due to noise, etc., false additional zero crossings may be detected or zero crossings may not be found. If each load time interval has a duration of one power transfer signal cycle, this may result in misalignment between the cycle / measurement and the load time intervals of the individual chips, resulting in detection errors.

[0186] However, by having a duty time interval that is the duration of multiple cycles of the power transfer signal, such errors are mitigated.

[0187] To increase the robustness of this approach, the number of power transmission signal cycles per chip / duty time interval can be increased (at the expense of bit rate). This makes the communication more resilient to the power receiver making mistakes in detecting the start of the power cycle and aligning the measurement with the duty time interval. An example of the approach where each duty time interval has a duration of four power transmission signal cycles is shown in FIG. 18. In FIG. 18, the first row shows the situation where the alignment between the power cycle and the duty time interval is correct. In the middle row there is one cycle offset in one direction and in the lower row there is one cycle offset in the other direction. Even with such an offset in the alignment, the measurement will still likely be aligned with the correct duty time interval and therefore will not result in a detection error.

[0188] A modulated load may be a load component of a power transmission signal / drive signal load that is caused / dependent / varying due to load modulation.

[0189] It will be appreciated that for clarity, the above description has described embodiments of the invention with reference to different functional circuits, units and processors. However, it will be apparent that any suitable distribution of functionality between different functional circuits, units or processors may be used without departing from the invention. For example, functionality shown to be performed by separate processors or controllers may be performed by the same processor or controller. Thus, references to specific functional units or circuits should not be regarded as indicative of a strict logical or physical structure or organization, but merely as references to suitable means for providing the described functionality.

[0190] The invention may be implemented in any suitable form including hardware, software, firmware or any combination of these. The invention may optionally be implemented at least partly as computer software running on one or more data processors and / or digital signal processors. Elements and components of embodiments of the invention may be physically, functionally and logically implemented in any suitable way. Indeed functionality may be implemented in a single unit, in multiple units or as part of other functional units. Thus, the invention may be implemented in a single unit or may be physically and functionally distributed between different units, circuits and processors.

[0191] Although the present invention has been described in relation to several embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present invention is limited only by the appended claims. Moreover, although certain features may appear to be described in relation to a particular embodiment, those skilled in the art will recognize that various features of the described embodiments may be combined in accordance with the present invention. In the claims, the term "comprising" does not exclude the presence of other elements or steps.

[0192] Furthermore, although individually recited, a plurality of means, elements, circuits or method steps may be implemented by, for example, a single circuit, unit or processor. Moreover, although individual features may be included in different claims, these may in some cases be advantageously combined and the inclusion in different claims does not imply that the combination of features is not feasible and / or advantageous. Moreover, the inclusion of a feature in one category of claims does not imply a limitation to this category, but rather indicates that the feature is equally applicable to other claim categories, as appropriate. The inclusion of a feature in a dependent claim of an independent claim does not imply a limitation to this independent claim, but rather indicates that the feature is equally applicable to other independent claims, as appropriate. Moreover, the order of features in the claims does not imply a particular order in which the features must be operated, and in particular the order of individual steps in a method claim does not imply that the steps must be performed in this order. Rather, the steps may be performed in any suitable order. Moreover, a reference to the singular does not exclude a plurality. Thus, references to "a", "an", "first", "second", etc. do not exclude a plurality. Reference signs in the claims are provided merely as a clarifying example and shall not be construed as limiting the scope of the claims in any way.

[0193] In general, an example approach is illustrated by the following embodiment.

[0194] A power transmitter (101) for wirelessly supplying power to a power receiver (105) via an electromagnetic power transmission signal, said power transmitter (101) comprising an output circuit (203, 103) including a transmitter coil (103) configured to generate said power transmission signal in response to a drive signal applied to said output circuit (203, 103), a driver (201) configured to generate said drive signal, and a receiver (207) configured to receive load modulated data symbols modulated by a chip sequence, each chip of the chip sequence being divided into at least two load time intervals having different modulation loads, the pattern of the different modulation loads being different for different chip values, said receiver (207) measuring the load of the power transmission signal. the load measurer (209) configured to determine a measured load value of a load time interval from the measured load value; a chip determiner circuit (211) configured to determine a received chip sequence from the measured load values, the received chip sequence comprising a sequence of chip values, each chip value being determined in response to a difference between the measured load values ​​of at least two modulated load time intervals of the chip; a memory unit (215) configured to store a set of chip sequences, each chip sequence being linked to a data symbol; and a detector (213) configured to detect a received data symbol value in response to a correlation between the received chip sequence and a chip sequence of the set of chip sequences.

[0195] A power transmitter (101) for wirelessly providing power to a power receiver (105) via an electromagnetic power transmission signal, said power transmitter (101) comprising: an output circuit (203, 103) having a transmitter coil (103) configured to generate said power transmission signal in response to a drive signal applied to said output circuit (203, 103); a driver (201) configured to generate said drive signal; and a receiver (207) configured to receive load modulated data symbols modulated by a chip sequence, each chip of the chip sequence being represented by a modulated load pattern, different chip values ​​being represented by different modulated load patterns, each modulated load pattern being formed by a sequence of load time intervals, the modulated load value being constant within each load time interval and varying between different time intervals, said receiver (207) comprising: a load meter (209) configured to measure the load of the power transmission signal to determine a measured load value for the load time interval; a chip determiner circuit (211) configured to determine a received chip sequence from measured load values, the received chip sequence comprising a sequence of chip values, each chip value being determined in response to a difference between the measured load values ​​for at least two modulated load time intervals of the chip; a memory unit (215) configured to store a set of chip sequences, each chip sequence being linked to a data symbol; and a detector (213) configured to detect a received data symbol value in response to a correlation between the received chip sequence and a chip sequence of the set of chip sequences.

[0196] A power receiver (105) for wirelessly receiving power from a power transmitter (101) via an electromagnetic power transmission signal, the power receiver (105) comprising: an input circuit (107, 503) having a receiver coil (107) configured to extract power from the power transmission signal; and a transmitter (509) configured to transmit data symbols to the power transmitter by load modulating the power transmission signal, each data symbol being modulated by a sequence of modulation load values ​​corresponding to a chip sequence of a set of chip sequences, the chip sequences of the set of chip sequences being linked to different data symbol values, the transmitter configured to modulate the power transmission signal by dividing each chip of the chip sequence into at least two load time intervals having different modulation loads.

[0197] A power receiver (105) for wirelessly receiving power from a power transmitter (101) via a power transmission signal, the power receiver comprising: an input circuit (107, 503) having a receiver coil (107) configured to extract power from the power transmission signal; and a transmitter (509) configured to transmit data symbols to the power transmitter by load modulating the power transmission signal, each data symbol being modulated by a sequence of modulation load values ​​corresponding to a chip sequence of a set of chip sequences, each sequence of the set of chip sequences being linked to a different data symbol value, the transmitter configured to modulate the power transmission signal by representing each chip of the chip sequence with a modulation load pattern, different chip values ​​being represented by different modulation load patterns, each modulation load pattern being formed by a sequence of loading time intervals, the modulation load value being constant within each loading time interval and varying between different time intervals.

Claims

1. A power transmitter that wirelessly supplies power to a power receiver via an electromagnetic power transmission signal, comprising: an output circuit having a transmitter coil configured to generate the power transfer signal in response to a drive signal applied to the output circuit; A driver configured to generate the drive signal; a receiver configured to receive load modulated data symbols modulated by a chip sequence, each chip of the chip sequence having a duration that is divided into a plurality of load time intervals, a modulation load of the load modulation being different in successive time intervals of the plurality of load time intervals, and a modulation load pattern formed by the modulation loads of the plurality of load time intervals being different for different chip values ​​of each chip; and wherein the receiver comprises: a load measurer configured to measure a load on the power transmission signal to determine a measured load value during a load time interval; a tip determiner circuit configured to determine a received tip sequence from the measured load values, the received tip sequence having a sequence of tip values, each tip value being determined as a function of a difference between the measured load values ​​during at least two load time intervals of a tip; a memory configured to store a set of chip sequences, each chip sequence linked to a data symbol; a detector configured to detect received data symbol values ​​as a function of a correlation between the received chip sequence and a chip sequence of the set of chip sequences; A power transmitter comprising:

2. 2. The power transmitter of claim 1, wherein each chip of the chip sequence is divided into two duty time intervals having different modulation duty.

3. 10. The power transmitter of claim 1, wherein each chip of the chip sequence is divided into three or more duty time intervals having different modulation duty.

4. 4. A power transmitter according to claim 1, wherein the load measurement device is configured to synchronize a measurement of the load of the power transmission signal to a cycle of the power transmission signal.

5. 5. The power transmitter of claim 4, wherein each duty time interval has a duration of one cycle of the power energy signal.

6. The power transmitter of claim 4 , wherein each duty time interval has a duration of multiple cycles of the power transmission signal.

7. 7. A power transmitter according to claim 1, wherein the load measurer is configured to perform one load measurement per load time interval.

8. 8. A power transmitter as claimed in claim 1, wherein the tip determiner circuit is configured to determine a binary tip value of a tip as a function of the sign of the difference between measured load values ​​of two load time intervals of that tip.

9. 8. A power transmitter according to claim 1, wherein the chip determiner circuit is configured to determine the received chip sequence to include a soft decision chip value depending on the magnitude of a difference between measured load values ​​of two load time intervals of a chip, and the detector is configured to perform the correlation with a chip sequence from the set of chip sequences depending on the soft decision chip value.

10. 10. A power transmitter as claimed in any preceding claim, wherein the pattern of different modulation loads is a pattern of binary modulation load values.

11. A power receiver that wirelessly receives power from a power transmitter via an electromagnetic power transmission signal, comprising: an input circuit having a receiver coil configured to extract power from the power transmission signal; a transmitter configured to transmit data symbols to the power transmitter by load modulating the power transmission signal, each data symbol being modulated by a sequence of modulation load values ​​corresponding to a chip sequence of a set of chip sequences, and each chip sequence of the set of chip sequences being linked to a different data symbol value; wherein the transmitter is configured to modulate the power transmission signal by dividing a duration of each chip of a chip sequence into a plurality of duty time intervals, a modulation load of the load modulation being different in successive time intervals of the plurality of duty time intervals, and a modulation load pattern formed by the modulation loads of the plurality of duty time intervals being different for different chip values ​​of each chip.

12. The power receiver of claim 11 , wherein the transmitter is configured to synchronize the at least two duty time intervals to a cycle of the power transmission signal.

13. A wireless power transmission system comprising: a power transmitter according to any one of claims 1 to 10; and a power receiver according to claim 11 or 12.

14. 1. A method of operating a power transmitter that wirelessly provides power to a power receiver via an electromagnetic power transmission signal, the method comprising: an output circuit having a transmitter coil configured to generate the power transfer signal in response to a drive signal applied to the output circuit; A driver configured to generate the drive signal; a receiver configured to receive load modulated data symbols modulated by a chip sequence, each chip of the chip sequence having a duration that is divided into a plurality of load time intervals, a modulation load of the load modulation being different in successive time intervals of the plurality of load time intervals, and a modulation load pattern formed by the modulation loads of the plurality of load time intervals being different for different chip values ​​of each chip; The method comprises the steps of: measuring a load on the power transmission signal to determine a measured load value during a load time interval; determining a received chip sequence from the measured load values, the received chip sequence having a sequence of chip values, each chip value being determined as a function of a difference between the measured load values ​​during at least two load time intervals of a chip; a discard pool for storing a set of chip sequences, each chip sequence being linked to a data symbol; detecting received data symbol values ​​as a function of correlation between the received chip sequence and a chip sequence of the set of chip sequences; A method for performing.

15. 1. A method of operating a power receiver that wirelessly receives power from a power transmitter via an electromagnetic power transmission signal, the method comprising: an input circuit having a receiver coil configured to extract power from the power transmission signal; transmitting data symbols to the power transmitter by load modulating the power transmission signal, where each data symbol is modulated by a sequence of modulation load values ​​corresponding to a chip sequence of a set of chip sequences, and the chip sequences of the set of chip sequences are linked to different data symbol values; wherein transmitting the data symbols includes modulating the power transmission signal by dividing a duration of each chip of a chip sequence into a plurality of duty time intervals, a modulation load of the load modulation being different in successive time intervals of the plurality of duty time intervals, and a modulation load pattern formed by the modulation loads of the plurality of duty time intervals being different for different chip values ​​of each chip.

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