Integration of a timing controller with spread spectrum video signal transmission.

Abstract

The timing controller of the display set is integrated with the encoder for carrying analog signals between the display controller and the source driver of the display panel. The timing controller and the integrated encoder are in an integrated circuit and are part of a chipset. The integrated circuit is located immediately after the SoC of the display set or is integrated in the SoC. The video signal sent to the timing controller chip is unpacked into sample values ​​and arranged into vectors of samples (one vector per encoder). Each vector is converted to analog and encoded, and the analog levels are sent to the source driver, which decodes it into analog samples. Alternatively, each digital vector is encoded and then converted to analog. A line buffer uses memory to present pixel row information to the encoder. A mobile phone has a TCON integrated with a SSVT transmitter.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 300,975 (HYFYP013P), filed January 19, 2022, U.S. Provisional Patent Application No. 63 / 317,746 (Docket No. HYFYP013P2), filed March 8, 2022, and U.S. Provisional Patent Application No. 63 / 391,226 (Docket No. HYFYP013P3), filed July 21, 2022, which are incorporated by reference in their entireties.

[0002] This application is also incorporated by reference into U.S. Patent Application No. 15 / 925,123, filed March 19, 2018 (Docket No. HYFYP001), U.S. Patent Application No. 16 / 494,901, filed September 17, 2019 (Docket No. HYFYP002), U.S. Patent Application No. 17 / 879,499, filed August 2, 2022 (Docket No. HYFYP003), U.S. Patent Application No. 17 / 686,790, filed March 4, 2022 (Docket No. HYFYP004AX1), U.S. Patent Application No. 17 / 887,849, filed August 15, 2022 (Docket No. HYFYP004AX2), and U.S. Patent Application No. 17 / 887,849, filed August 15, 2022 (Docket No. HYFYP004AX3). No. HYFYP006), U.S. Provisional Patent Application No. 63 / 398,460, filed on August 16, 2022 (Docket No. HYFYP008P), U.S. Provisional Patent Application No. 17 / 900,570, filed on August 31, 2022 (Docket No. HYFYP009), and U.S. Provisional Patent Application No. 63 / 346,064, filed on May 26, 2022 (Docket No. HYFYP014P2).

[0003] The present invention relates generally to displaying images on a display panel of a display set. More specifically, the present invention relates to a timing controller integrated with an encoder that encodes digital signals into analog signals for display. [Background technology]

[0004] Image sensors, display panels and video processors are constantly racing to achieve larger formats, greater color depth, higher frame rates and higher resolution. Local site video transport involves performance scaling bottlenecks that throttle throughput, compromising performance while consuming more cost and power. Eliminating these bottlenecks could provide benefits.

[0005] For example, as display resolutions increase, the data rate at which video information is transferred from a video source to a display screen has increased exponentially, from 3Gbps for Full HD ten years ago to 160Gbps for new 8K screens. Typically, a display with a 4K display resolution requires approximately 20Gbps of bandwidth at 60Hz, while at 120Hz it requires 40Gbps. An 8K display requires 80Gbps at 60Hz and 160Gbps at 120Hz.

[0006] Currently, traditional column (or source) drivers rely on wiring looms in display sets that can limit scaling to larger formats as well as higher frame rates for many reasons. One of the reasons is that the area and volume required for complex wiring looms become too large, which means that the size and cost of the printed circuitry implementing the wiring loom exceeds practical limits. In addition, the DACs in source drivers are limited to 8-bit resolution, and any increase would result in excessive data rates and too much power consumption. These limitations force architectural discontinuities in the display set industry, increasing costs and risks.

[0007] Until now, data has been transferred digitally using a variation of Low-Voltage Differential Signaling (LVDS) data transfer, using a bit rate of 16 Gbps per signal pair (depending on the architecture), by paralleling pairs to achieve the required total bit rate. This digital information then needs to be converted on the fly to analog pixel information using D / A conversion in the display's source driver.

[0008] Today, most source driver D / A converters require 8 bits, but soon D / A conversion may require 10 or even 12 bits, and it will be very difficult to maintain a sufficiently high data rate. Therefore, the display must clock the digital data in a very short time, which makes the transmission of the digital signal unstable. Another problem with the limitations of existing digital transport is that not all 12, 10 or 8 bits per sample can be conveyed within the display panel, i.e., modern in-display compression methods can only convey 6 bits per sample, limiting the color depth of the display.

[0009] Accordingly, new devices and techniques are desirable to eliminate the need for D / A conversion in the display's source driver, to increase bandwidth, and to utilize analog video signals generated within the display unit. Summary of the Invention [Means for solving the problem]

[0010] To achieve the above, according to the object of the present invention, the timing controller of the display set is integrated with an SSVT transmitter having at least one encoder to enable the transport of analog signals between the display controller of the display set and the source driver of the display panel.

[0011] It has been found that the digital representation of the brightness levels of pixels (e.g. 8-bit or 10-bit numbers), especially during video transport, is a poor representation of the video data, whereas analog voltages representing those brightness levels are a better representation and have a much better resolution. Therefore, the present invention proposes to transport video data in the analog domain within a display set using voltages representing the brightness levels of pixels.

[0012] The advantages of the present invention include reduced power consumption. In the prior art, power consumption significantly limits display performance, but by using the present invention, the display electronics consume less power. The embodiments of the present invention described below can be scaled to arbitrarily large formats and frame rates, reducing power consumption in driving the panel by 50% and providing noise rejection by more than 10 times. Furthermore, some embodiments provide noise immunity and EM stealth in that the EMI / RFI emissions of the display set will be well below the mandated limits. Furthermore, the transmission range of the new analog signal can be much larger than that of conventional Ethernet or HDBaseT signals. While conventional carriers use expensive mixed signal processing for high speed digital circuits, embodiments of the present invention utilize mature analog processing for greater flexibility and lower manufacturing costs. Furthermore, the size of the wiring loom is reduced, requiring less space at the edge area of ​​the display panel.

[0013] Furthermore, by using spread spectrum video transport (SSVT) for data transfer between a display controller in a display set and the source driver of the display panel, the silicon area associated with video transport and therefore the chip cost can be reduced by up to one-third for a 4K 60Hz panel and up to one-tenth for an 8K 120Hz panel.

[0014] In a particular embodiment, the SSVT transmitter (and its encoder) and the integrated timing controller are in a single integrated circuit. The main advantage of this integration is that the digital video transfer is on-chip, resulting in no disruption to the digital signal transmission from the TCON to the encoder. It also provides power and cost advantages. Another advantage is a smaller area of ​​the combined chip due to pin savings and component sharing. In a variant, the transmitter, TCON and SoC are all in an integrated circuit. Integrating the SSVT transmitter with the TCON also aligns with the existing industry practice where the TCON has an integrated digital video transport (such as CEDS). In another particular embodiment, the SSVT transmitter and timing controller chip (or transmitter, TCON and SoC) are part of a display panel driver chipset, with one or more other semiconductor chips receiving the SSVT signals and implementing the source driver of the display.

[0015] The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0016] [Figure 1] 1 illustrates prior art delivery of digital signals to a display panel in a conventional display set. [Diagram 2] 1 shows the delivery of an analog video signal to a display panel by using encoding immediately after the SoC of the display set. [Diagram 3] FIG. 11 is a diagram of one possible arrangement implemented by the distributor to construct the four vectors V0, V1, V2, V3 as shown. [Figure 4] 1 shows in more detail the SSVT transmitter integrated with the analogue encoder. [Figure 5A] 5 illustrates the line buffer controller, distributor, clock domain crossing, DAC and encoder of FIG. 4 in more detail. [Figure 5B]1 illustrates a particular embodiment of an encoder for encoding analog values. [Figure 6] 1 shows the SSVT transmitter integrated with the digital encoder in more detail. [Figure 7] 1 is an example showing how an analog voltage value is coded in an encoder and then transmitted over an electromagnetic path. [Figure 8] This section describes coding techniques that can be applied to digital values. [Figure 9] 1 shows a simulation of a SSVT waveform transmitted over an EM path. [Figure 10] 1 illustrates the delivery of analog video signals to a display panel by using coding integrated with the display set's SoC. [Figure 11] An 8K display set with an integrated SSVT transmitter and timing controller is shown. [Figure 12] An 8K display set with an integrated SSVT transmitter, timing controller and SoC is shown. [Figure 13] 1 illustrates one particular embodiment of an integrated module using digital encoding. [Figure 14A] 14 shows one possible implementation of the distributor of FIG. 13 in more detail. [Figure 14B] 14 shows another possible implementation of the splitter of FIG. 13 in more detail. [Figure 15] 1 illustrates a particular embodiment of an integrated module using analog coding. [Figure 16] 14 shows one of the digital encoders from FIG. 13 in more detail. [Figure 17] 16 shows one of the analog encoders from FIG. 15 in more detail. [Figure 18] An 8K120 display set with an integrated SSVT transmitter, timing controller and SoC is shown. [Figure 19] 1 shows a display source driver. [Figure 20]1 shows a diagram of the decoding unit of the source driver in more detail. [Figure 21] 1 illustrates an alternative embodiment for implementing an array of source drivers. [Figure 22] FIG. 22 is a block diagram of one of the decoders from FIG. 21. [Figure 23] 22 is a block diagram of the collector from FIG. 21 showing the relay bank from FIG. 20 in more detail. [Figure 24] FIG. 2 is a logic diagram of one of the four decoders. [Diagram 25] FIG. 2 is a diagram of an exemplary decoder track circuit as shown. [Figure 26] 4 illustrates decoding of an analog input level that has been encoded using the encoder. [Figure 27A] The use of an analogue encoder and a corresponding analogue decoder is shown. [Figure 27B] The use of a digital encoder and a corresponding analog decoder is shown. [Figure 27C] The use of a digital decoder to decode an encoded analog signal that arrives over an electromagnetic path in a transmission medium is shown. [Figure 28] FIG. 1 is a block diagram for carrying video samples using SSVT in a mobile phone. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In a video system, conversion of incident light into a signal is typically performed by a source assembly or a graphics processing unit (GPU), where the conversion determines the format of the payload that is carried over one or more electromagnetic paths from the source assembly to a sink assembly, which may be a display or video processor that receives the format and converts the received payload into a signal used by a suitable output device to generate emitted light suitable for human viewing.

[0018] We know that digitization of video signals is done at the signal source of the system (usually in the GPU) and then the digital signal is transferred, usually using a combination of high performance wiring systems, to the display driver where it is converted back to analog again and loaded onto the display pixels. Thus, the only purpose of digitization is to transfer data from the video source to the display pixels. Therefore, we realize that it is much more beneficial to avoid digitization all together (to the extent possible) and transfer analog data directly from the video source (or from the display controller) to the display driver. This can be done using our novel encoding, which results in accurate analog voltages that are decoded again in the source driver. The decoded analog data is a high bit depth approximation of each sample without the need to exactly reproduce a certain number of bit positions. This means that the sample rate is at least 10 times lower than in the digital transfer case, leaving more bandwidth for expansion.

[0019] Furthermore, it is recognized that it is much easier to do the D / A conversion (if necessary) in that less power is required than at the end where the display panel is driven, where a lot of power is required. So instead of carrying the digital signal all the way from the video source (or from the display controller) to where the analog signal needs to be generated, we carry the analog signal to the display panel using a much lower sample rate than would normally be required by digitization. This means that instead of having to send gigabits per second over many lines, we can get away with only a few megas of analog samples per second, thus reducing the bandwidth of the channel that needs to be used. Furthermore, while in prior art digital transport every bit takes up almost half an inch of the signal line, by carrying analog data the amount of available space is increased by a factor of ten, which means additional bandwidth is available. And yet the bits in the digital data must be well defined. This definition is quite sensitive to errors and noise, and the high and low points need to be very precisely detectable, whereas the proposed analog transport is much less sensitive. This means that the cables (eg those running from one side of the display set to the other) do not have to be of high quality.

[0020] The present invention is particularly applicable to high resolution and high dynamic range displays used in computer systems, televisions, monitors, gaming displays, home theater displays, retail signage, outdoor signage, and the like.

[0021] (Digital Carrier) 1 shows the prior art delivery 10 of digital signals to a display panel in a conventional display set. For purposes of this disclosure, "display panel" refers to the internal portion of the display set that implements the pixels that generate light for viewing, while "display set" refers to the entire (usually) rectangular enclosure that includes the display panel, panel assembly, frame, drivers, cabling, and associated electronic controls for receiving, transporting, and displaying video images.

[0022] A digital video signal 62 is shown input to the display set via an HDMI connector (or via LVDS, HDBaseT, MIPI, IP video, etc.) into the display set's System on Chip (SoC) 63. The SoC 63 performs functions such as display controller, decompression, and output of a video signal 64 to a conventional TCON (timing controller) 50. The timing controller then conveys a digital signal 66 to the display panel 30. (Digital conveyance could also use MLVDS, DDI, etc.) The display panel 30 includes any number of DACs (digital-to-analog converters) within the display panel's column drivers 68, which convert the digital signals to analog signals for input to the display panel's pixels. High-speed shift registers 70 pass the digital signals from column driver to column driver using a "cascade" technique. Also shown are timing and framing signals 72 output by the timing controller 50, which provide timing and framing for the gate drivers 74.

[0023] In addition to the above drawbacks, this digital transport in conventional display sets raises concerns about high EMI / RFI due to the reliance on high speed digital circuits, which must be realized using relatively expensive integrated circuit processes. Furthermore, for example, 8K V-by-One HS requires 48 wire pairs at 3.5Gbps. Also, high speed bit-serial interfaces have synchronization issues.

[0024] It has been found that performing digital to analog conversion of digital video signals as close as possible to the SoC not only eliminates the need for DACs in the column drivers of the display panel, but also eliminates the disadvantages mentioned above and also realizes the advantages of carrying analog signals instead of digital signals within the display set.

[0025] (Analog transport within the display set) FIG. 2 shows the delivery 100 of an analog video signal to a display panel 130 by using conversion and encoding immediately after the SoC 163 of the display set 120. In this embodiment, the conversion and encoding of the digital video signal to an analog SSVT signal 167 is performed within the display set itself, thus improving display connectivity. The input of a digital video signal 162 is shown via an HDMI connector (or via LVDS, HDBaseT, MIPI, IP video, etc.) into a system-on-chip 163 that performs functions such as display controller, decompression, brightness, contrast, overlay, etc. The modified digital video signal 164 is then delivered to an integrated SSVT transmitter and timing controller 150 using LVDS, V-by-one, etc. In this embodiment, the timing controller is integrated with the transmitter, both implemented in one circuit, preferably in one integrated circuit on a semiconductor chip. The display panel 130 can be a display panel of any size. Note that the transmitter and timing controller chip 150 is located immediately behind the SoC chip 163, thus making the transmission of digital signals (at this point) easier. Preferably, the chip 150 is located within about 10 cm of the SoC chip. In one embodiment, the chip 150 is located within about 5 cm of the SoC, and in another embodiment, within about 2 cm. The physical characteristics of LVDS limit the maximum communication distance between chips to a few inches. The advantages of integration also include the SoC being integrated with the TCON. Thus, another embodiment discussed below is one in which the SSVT distributor, encoder, and line driver are integrated with the SoC and the TCON.

[0026] In one embodiment, the transmitter and timing controller chip 150 is one of two semiconductor chips in a display panel driver chipset; the other semiconductor chip (the "SSVT source driver" chip) receives the signal 167 and incorporates the source driver 169. Depending on the size of the display panel, there may be more than one SSVT source driver chip. Typically, the distance between chip 150 and source driver 169 ranges from about 5 cm to about 1.5 m, depending on the panel size.

[0027] The transmitter 150 converts the received digital video signal into a spread spectrum video carrier (SSVT) signal 167, which is carried to the display panel 130. Preferably, the signal 167 is delivered to the source driver 169 using a differential pair of wires (e.g., one or two pairs per source driver). The display panel 130 has a corresponding SSVT decoder (typically in each source driver 169) that decodes each analog SSVT signal into the analog signal expected by the display panel. Note that no DAC (digital-to-analog converter) is required in either the display panel or the source driver. A timing signal 171 controls the gate driver 174 to enable the correct lines of the display in synchronization with the source driver 169. In one particular embodiment, a novel source driver 169 is implemented as described herein and in the above-mentioned U.S. patent application Ser. No. 17 / 900,570 (HYFYP009).

[0028] Advantageously, by using SSVT signals instead of digital transport within the display, EMI / RFI emissions are well below mandated limits, with an 8K display requiring only 24 wire pairs at 680 Mbps. In contrast, conventional transport of digital video signals from a system-on-chip (SoC) (for example) within a display set to a display panel must be implemented in a high resolution and therefore relatively expensive IC process, and thus EMI / RFI emissions due to reliance on high speed digital circuits are a concern, with an 8K display requiring 48 wire pairs at 3.5 Gbps.

[0029] Even if the input signal 162 is not SSVT (i.e., a digital video signal), there is a significant advantage to using SSVT signals inside the display set. In the prior art display set, the HDMI signal is decompressed to obtain complete full bit rate digital data that must then be transferred from the receiving end of the display set to all places in the display set. Those connections can be quite long in a 64 or 80 inch display set. That is, the digital data must be transferred from one side of the set where the timing controller is located to the other side where the final display source driver is located. Therefore, there is an advantage to converting the digital signal to SSVT internally at or near the SoC, and then transmitting the SSVT signal to all places in the display set where the source driver is located. In particular, the distance of the digital transmission is shorter and the distance of the SSVT transmission is longer, which can reduce the cost and complexity of the digital transmission implementation while increasing the flexibility of the system integration.

[0030] 10 shows the delivery 100' of an analog video signal to a display panel 130 by using conversion and encoding integrated with a SoC 140' of a display set 120. In this embodiment, the conversion and encoding of a digital video signal 162 to an analog SSVT signal 167 is performed in a single chip 140' with the SSVT transmitter and timing controller integrated in the SoC 140'.

[0031] A digital video signal 162 is shown input into the display set 120 via an HDMI connector (or via LVDS, HDBaseT, MIPI, IP video, etc.), which is then sent (162') internally to the SoC 140'. The system-on-chip (SoC) 140' performs its traditional functions such as display controller, decompression, brightness, contrast, overlay, etc., and also functions as a timing controller and SSVT transmitter. After the SoC performs its traditional functions, the modified digital video signal (not shown) is delivered to the SSVT transmitter and timing controller integrated therein using a suitable protocol such as LVDS, V-by-one, etc. In this embodiment, both the timing controller and the SSVT transmitter are integrated with the SoC, and all three are implemented in a single circuit, preferably in one integrated circuit on a semiconductor chip.

[0032] For the SoC 140' to perform the encoding, one or more corresponding semiconductor chips ("SSVT source driver" chips) receive signals 167 and incorporate source drivers 169. Depending on the size of the display panel, there may be more than one SSVT source driver chip. Typically, the distance between the chip 140' and the column driver 169 ranges from about 5 cm to about 1.5 m, depending on the panel size.

[0033] An SSVT transmitter in chip 140' converts the modified digital video signal into a spread spectrum video carrier (SSVT) signal 167, which is carried to the display panel 130. Preferably, the signal 167 is delivered to the source driver 169 using a differential pair of wires (e.g., one or two pairs per source driver). The display panel 130 has a corresponding SSVT decoder (typically in each column driver 169) that decodes the analog SSVT signal into the analog signal expected by the display panel. Note that no DAC (digital-to-analog converter) is required, either in the display panel or in the source driver. Timing signal 171 controls gate drivers 174 to enable the correct lines of the display in sync with the source driver 169.

[0034] The integrated SoC chip 140' can be implemented as described herein, i.e., as shown in Figures 4 or 6, but keep in mind that the SSVT transmitter, timing controller and SoC functions are all integrated on the same chip. This embodiment of Figure 10 has the same advantages as those listed above with respect to Figure 2. In addition, integrating the SSVT transmitter and timing controller with the SoC chip itself provides further advantages such as reduced chip count, reduced complexity, reduced area required and reduced power required.

[0035] (SSVT Analog Encoder and Timing Controller) Figure 4 shows the SSVT transmitter and timing controller 150 in more detail. The SSVT transmitter and timing controller 150 is connected to the display source driver 169 via a transmission medium as shown in Figure 2. First, the distribution and encoding are described, and then details regarding the timing controller are described. Further details are shown in Figure 5A.

[0036] Briefly, a stream of input digital video samples is received at chip 150, and the input digital video samples are (1) iteratively distributed by assigning the input video samples to encoder input vectors (four in this example) according to a predefined sequence, and (2) coded using encoder 42 to generate a number of composite analog EM signals 260. The analog EM signals are then (3) transmitted over a transmission medium to one or more corresponding chips incorporating source drivers. At the receiving end, (4) the input analog EM signals are decoded using a corresponding decoder to reconstruct the samples into output vectors, and then (5) the output vectors are assembled by assigning the reconstructed video samples from the output vectors to an output stream using the inverse of the predefined sequence. As a result, an original stream of time-series video samples, including color and pixel-related information, is conveyed from the video source to the video sink.

[0037] Signal 164 is typically an LVDS digital signal from the SoC where pixel values ​​come in row-major order through a sequential video frame. More than one (e.g., two, four, etc.) pixel values ​​may arrive at a time; that is, they are serial in the sense that groups of pixels are sent sequentially from one side of a line to the other. Unpacker 26 unpacks (or exposes) these serial pixel values ​​into parallel RGB values. The number of output sample values ​​S for each set of pixel samples is determined by the color space applied by the video source. For RGB, S=3, and for YCbCr 4:2:2, S=2. In other situations, each sample set has only one sample value S or more than three. Unpacker 26 also unpacks framing information from digital signal 164 in the form of framing flags 27 (shown in FIG. 5A) that come along with the pixel values. Essentially, the framing flags indicate the location of the pixel within a particular video frame. That is, the framing flags mark the start of a line, the end of a line, the active video section, the horizontal and vertical blanking sections, etc., as is known in the art. The framing flags 27 inform the gate drivers which line is currently being sent to the display panel and also control the timing of the gate driver operation. The framing flags are input to a line buffer 290, which is described in more detail below in Figure 5A.

[0038] The distributor 40 of block 220 (shown in detail in FIG. 5A ) is arranged to receive pixel color information (e.g., R, G, B values) exposed in the input sample set. The distributor 40 takes the exposed color information and constructs a number of encoder input vectors according to a predefined arrangement. In the embodiment shown, there are four encoder input vectors (V0, V1, V2, V3), one for each of the four EM paths on the transmission medium. In various embodiments, the transmission medium may be a cable, such as an HDMI or optical fiber, or wireless. One of the number of encoders 42 is assigned to one of the four vectors V0, V1, V2, V3, respectively. Each encoder 42 is responsible for encoding the sample values ​​contained in the corresponding encoder input vector and for generating an EM signal that is transmitted in one of the parallel paths on the transmission medium.

[0039] In this particular embodiment shown, there are four EM paths, with each encoder 42 generating an EM signal for each of the four paths, respectively, but it should be understood that the invention should in no way be limited to four paths, and the number of paths on the transmission medium can vary from one to two or more.

[0040] At the receiving side, an SSVT receiver (not shown) is provided. The function of the SSVT receiver is complementary to the SSVT transmitter and timing controller 150 at the transmitting side. That is, the SSVT receiver (a) receives sequences of EM signals from multiple EM paths of the transmission medium, (b) decodes each sequence by applying SSVT demodulation to reconstruct the video samples of multiple output vectors, and (c) collects samples from multiple output vectors using the same arrangement used to distribute the input samples to the input vectors at the transmitting side. More specifically, the output vectors are relocated to the spatially correct positions on the output pins of the source driver toward the display panel. The collected output samples are then converted to a format suitable for display by the video sink for display in a time-shift mode.

[0041] As described herein, modulation and demodulation can be performed in the analog or digital domain, as illustrated in Figures 7-9 below. As described in more detail below, a stream of input sample sets is distributed at a first clock rate (pixel clock or "pix-clk") to generate encoder input vectors according to a predefined sequence. Modulation is then applied to each of the encoder input vectors to generate an encoded EM signal for each encoder input vector. The EM signals are then transmitted in parallel on a carrier at a second clock rate (SSVT clock or "SSVT_clk"). Applying spreading (SSDS) to each sample of the encoder input vector provides electrical resiliency, but at the expense of bandwidth per sample. However, by modulating with a mutually orthogonal code set and transmitting all of the resulting EM signals simultaneously, some or all of the lost bandwidth is recovered.

[0042] As mentioned above, the modified digital video signal 164 arrives from the SoC 163 via LVDS pairs (for example). Typically, the number of pairs is implementation specific and depends on the data rate per pair as well as the panel resolution, frame rate, bandwidth, etc. Digital signal processing (DSP) is performed in function block 210 and includes frame-by-frame inversion and other processing (gamma correction, LCD drive optimization, gamma correction, LCD drive optimization, HDR implementation, compensation for specific EM path electrical characteristics, etc.). Gamma correction converts samples from a linear color space to a non-linear color space to make the best use of the physical luminosity characteristics of the individual display. Gamma correction is a fundamental requirement for high quality systems. Compensation for EM path characteristics includes any signal processing function that pre-corrects the measured parameters of the EM path circuit elements.

[0043] After DSP and gamma correction 210, the digital video signal is passed internally to block 220 (214), which includes line buffers (and line buffer controllers), lane distribution (via distributor 40), clock domain crossing, and generation of gate driver control signals 171. Line buffer memory 230 temporarily stores rows of pixel information before distribution to the encoder. Typically, pixel information for a row of a display panel arrives sequentially from the SoC, and in order for the gate driver to be able to simultaneously display the row of pixel information, the source driver 169 must simultaneously prepare the pixel voltages for the entire row. Thus, line buffer memory 230 stores the row of pixel information as it arrives sequentially from the SoC. Once the entire row of pixel information is stored, it is available to block 220 for later conversion, encoding, transport, and display on the appropriate row of the display panel. Moreover, in a display panel, only half of a pixel row may be enabled by the gate driver at a given time, and thus information for half the row must be sent to the source driver and then the other half. A line buffer memory helps facilitate this: for example, a line is stored in the line buffer memory, and then half is extracted and transmitted while a new line is stored. Depending on the particular implementation, the line buffer memory 230 may be within the integrated circuit 150 or may be external.

[0044] The digital video samples are then converted using an intermediate frequency DAC 240 and then analog coded using any number of SSVT encoders 42. The number of encoders corresponds to the number of EM signals (EM paths) desired to be used on the transmission medium, as described in more detail below. Each analog signal 260 is then sent to a source driver 169 for decoding to the voltage levels expected by the display panel 130.

[0045] 3, there is shown a diagram of one possible arrangement that may be implemented by distributor 40 to construct four vectors V0, V1, V2, V3. Each of the vectors contains N samples of exposed color information. The exposed RGB samples from sample set 164 in this example are assigned from left to right to vectors V0, V1, V2, V3. In other words, the "R", "G", "B" values ​​of the leftmost sample and the "R" signal of the next sample set are assigned to vector V0, the next (from left to right) "G", "B", "R" and the "G" value of the next sample are assigned to vector V1, the next (from left to right) "B", "R", "G" and "B" values ​​are assigned to V2, and the next (from left to right) "R", "G", "R" and "R" values ​​are assigned to vector V3. At which point the fourth vector V3 has been assigned its signal, and the above process is repeated until each of the four vectors V0, V1, V2, V3 has N samples.

[0046] In various embodiments, the number of N samples can vary widely. As an example, consider an embodiment with N=60. In this case, the total number of N samples contained in the four vectors V0, V1, V2 and V3 is 240 (60×4=240). The four encoder input vectors V0, V1, V2 and V3, when fully constructed, contain 22 (240 / 3=80) distinct sets of samples (where S=3). In other words: Vector V0 is the sample P0, N0~P0, N N-1 Includes; Vector V1 is the sample P1, N0~P1, N N-1 Includes; Vector V2 is sample P2, N0~P2, N N-1 including; and Vector V3 is sample P3, N0~P3, N N-1 Includes.

[0047] It should be understood that the above examples are merely illustrative and therefore should not be construed as limiting. The number of samples N may be approximately 60. It should also be understood that the exposed color information of each set of samples may be any color information (e.g., Y, C, Cr, Cb, etc.) and is not limited to RGB. The number of EM paths on the transmission medium may also vary widely. Thus, the number of vectors V and the number of encoders 42 may also vary widely from just one to any number greater than one. It should also be understood that any ordering scheme used to construct the vectors may be used, limited only by the need to use the ordering scheme used at the transmitting end at the receiving end.

[0048] (Integrated SSVT transmitter and timing controller) 5A illustrates in more detail the line buffer and its controller 290, line buffer memory 230, distributor 40, clock domain crossing 180, DAC 62, and encoder 42 of FIG. 4. The distributor 40 may include an assembly bank 50, a relay bank 52, a presentation bank 54, and a frame controller 56. The encoder block 60 includes a bank of digital-to-analog converters (DACs) 62 and four encoders 42, one for each EM path on the transmission medium.

[0049] The distributor 40 is arranged to receive exposed color information (e.g., RGB) from the line buffer controller 290, which in turn receives this information from the unpacker 26 (after DSP and gamma correction). In response, the assembly bank 50 constructs four vectors V0, V1, V2, V3 from the exposed color information (e.g., RGB) for an input stream of sample sets. Once the sample sets are received, they are stored in the assembly bank 50 according to a predefined sequence. Again, the distributor 40 may use any number of different sequences in constructing the vectors, each containing N samples.

[0050] The relay bank 52 facilitates the crossing of N samples of each of the four vectors V0, V1, V2, V3 from a first clock frequency (or pixel clock domain) used by the unpacker 26 to a second clock frequency (or SSVT clock domain) used for encoding and transmission of the resulting EM signal over the transmission medium. As previously discussed in the example above with N=60 and S=3, the four encoder input vectors V0, V1, V2, V3 contain samples representing just 80 sets of RGB samples.

[0051] Boundary 180 indicates the clock domain crossing between the pixel clock domain and the SSVT clock domain. The pixel clock domain clocks in pixel values ​​to the left of boundary 180, and the SSVT clock domain clocks out sample values ​​to the DACs and encoders. Essentially, the pixel clock allows the signals in the relay bank 52 to remain stable long enough for the presentation bank 54 to sample those signals in the SSVT clock domain. The controller 56 uses the pixel clock in the relay bank and the SSVT clock in the presentation bank.

[0052] In various embodiments, the pixel clock frequency can be faster, slower, or the same as the SSVT clock frequency. The first clock frequency f_pix is ​​determined by the video format selected by any suitable video source. The second clock frequency f_ssvt is a function of f_pix, the number of EM paths P of the transmission medium, the number of samples S in each set of input / output samples, and the SSVT transformation parameters N (the number of input / output vector locations) and L (the length of each SSDS code), where f_ssvt=(f_pix * S * L) / (P * In this configuration, the input clock (pix_clk) oscillates at one rate and the SSVT clock (ssvt_clk) oscillates at a different rate. These clock rates may or may not be the same.

[0053] The presentation bank 54 presents N samples (from 0 to N-1) of each of the four encoder input vectors V0, V1, V2, V3 to the encoder block 60. Typically, the N input samples (individual color components) are assigned to an input vector, and then the encoder performs a forward transform (modulation) while the next input vector is prepared.

[0054] The controller 56 controls the operation and timing of the assembly bank 50, the relay bank 52, and the presentation bank 54. In particular, the controller is responsible for defining the ordering and number of samples N used in constructing the four encoder input vectors V0, V1, V2, V3. The controller 56 is also responsible for coordinating the clock domain crossing from the first clock frequency to the second clock frequency as performed by the relay bank 52. Furthermore, the controller 56 is responsible for coordinating the timing of when the presentation bank 54 presents the N samples (0 to N-1) of each of the four encoder input vectors V0, V1, V2, V3 to the encoder block 60. The controller 56 may also include an ordering controller that controls the distribution of RGB samples to locations within the encoder input vectors.

[0055] Within the encoder block 60, a number of digital-to-analog converters (DACs) 62 are provided, each of which has a P * N samples (P0 to P3, N0 to N N-1The DACs 62 are arranged to receive one of the signal pairs (up to 100 kHz) at once. Each DAC 62 converts its received sample from the digital domain to a differential pair of voltage signals with a magnitude proportional to its input digital value. In one embodiment, the output of the DACs 62 ranges from a maximum voltage to a minimum voltage. In this example, there is one DAC per signal pair (i.e., there are N slow DACs per encoder, with each DAC output presenting one sample to the encoder over the entire encoding interval). This configuration also allows for the use of one DAC per encoder (and therefore drive levels to the wire pairs at F_ssvt) and multiplexing of samples to one DAC. Such multiplexing requires a fast and accurate DAC to perform N conversions within one SSVT clock cycle.

[0056] The four encoders 42 are provided with four encoder input vectors V0, V1, V2, V3, respectively. Each encoder 42 receives a differential pair of signals for each of the N samples (0 to N-1) for that encoder input vector, modulates each of the N differential pairs of voltage signals using a unique orthogonal code as discussed herein, accumulates the modulation values, and then generates a differential EM signal that is the accumulated modulated sample values. Since there are four encoders 42 in this example, there are four EM signals (signal 0 to signal 3) that are transmitted simultaneously over the transmission medium. Modulation and coding are discussed in more detail in Figures 7 and 8 below.

[0057] The sequencer circuit 65 coordinates the timing of the operation of the DAC 62 and the encoder 42. The sequencer circuit 65 is responsible for controlling the clocking of the DAC 62 and the encoder 42. As will be explained in more detail below, the sequencer circuit 65 is also responsible for generating two clock phase signals “clk1” and “clk2” that are responsible for controlling the operation of the encoder 42.

[0058] As previously mentioned, the line buffer controller 290 coordinates the storage and retrieval of pixel values ​​to and from the line buffer memory 230. The line buffer controller stores a row of pixels for display in the line buffer memory and then retrieves the row to the line buffer when the row is complete so that the pixel values ​​for that row can be simultaneously sent (via distributors, encoders, EM paths, etc.) to the display source driver for display. The line buffer memory 230 may be a memory implemented within the SSVT transmitter and timing controller chip 150 or may be a memory separate from the chip 150.

[0059] As mentioned above, the framing flags 27 come from the unpacker 26 and are input to the line buffer controller 290, which uses these flags to know where the pixels are in the line so that they can be stored and then placed into the correct encoder. After the framing flags are output from the line buffer controller (usually with a delay), they are input to the gate driver controller 280, which generates a number of gate driver control signals 171 for controlling the timing of the gate drivers. These signals 171 include at least one clock signal, at least one frame strobe signal, and at least one line strobe signal. The line strobe signal is used for a particular line that is enabled by the panel gate driver controller at the time the pixel value is pushed to the source driver for that particular line. The line strobe signal therefore drives the selected line with the appropriate timing. The control of the gate driver timing can be performed in a manner known to those skilled in the art. Also shown is bidirectional communication 57 between the controller 56 and a gate driver controller 280, which is used for timing management between the source drivers and the gate drivers.

[0060] 5B shows a particular embodiment of the encoder 42 for encoding analog values. A circuit diagram of the encoder 42 for one of the input vectors V is shown. The encoder circuit 42 includes a multiplier stage 71 with a number of multiplier stages 70 and an accumulator stage 72 including a differential amplifier 74.

[0061] Each multiplier stage 70 receives a differential pair of sample signals (+sample N-1 / -sample N-1 Each multiplier stage 70 is arranged to receive at a first (+) terminal and a second (-) terminal, respectively, a signal from each of the multiplier stages 70 (from +sample0 / -sample0 to +sample0 / -sample0). Each multiplier stage 70 also includes a terminal for receiving a chip from a code, an inverter 73, a set of switches S1-S1, S2-S2, S3-S3, a set of switches driven by clk1 and clk2, and storage devices C1 and C2 having equal values, each of which stores voltage samples upon actuation of the various switches, and therefore different voltages across each device at different times according to the switching sequence.

[0062] During operation, each multiplier stage 70 modulates its received analog signal differential pair by conditionally multiplying it by (+1) or (-1) depending on the value of the received chip. If the chip is (+1), when clk1 is active, S1-S1 and S3-S3 are closed and switch pair S2-S2 remains open. As a result, both the + and - sample differential pairs are stored in storage devices C1 and C2, respectively, without inversion (i.e., without multiplication by +1). On the other hand, when the chip is (-1), the complementary operation occurs. In other words, when clk1 is active, switch pair S1-S1 is open, switch pair S2-S2 is closed, and switch pair S3-S3 is closed. As a result, the differential pairs of samples are switched and stored in C1 and C2, respectively, and thus multiplied by -1.

[0063] The accumulator stage 72 operates to accumulate charge on the storage devices C1 and C2 for all of the multiplier stages 70. When clk1 transitions to an inactive state and clk2 transitions to an active state, all clk1 controlled switches (S3-S3, S4-S4) open and clk2 controlled switches (S5-S5, S6-S6) close. As a result, all charge on the first storage devices C1 of all multiplier stages 70 is amplified by the amplifier 78 and accumulates at a first input of the differential amplifier 74, while all charge on the second storage devices C2 of all multiplier stages 70 is amplified by the amplifier 78 and accumulates at a second input of the differential amplifier 74. In response, the differential amplifier 74 generates a pair of differential electromagnetic level (EM) signals. The amplifier 74 may use the same Vcm as the amplifier 78 immediately to its left. Depending on the implementation, the resistor R1 shown for each amplifier 78 and 74 may be the same or different, and the resistor R1 of amplifier 74 may be the same or different from that of amplifier 78. Capacitors C1, C2, C3, C4 should be the same size.

[0064] The above process is performed for all four vectors V0, V1, V2, and V3. Additionally, the above process is repeated continuously for as long as the stream of sample sets 22 is received by the SSVT transmitter 28. In response, four streams of differential EM power level signals are transmitted over the transmission medium.

[0065] (SSVT digital encoder and timing controller) 6 shows the SSVT transmitter and timing controller 150' in more detail. As previously mentioned, the present invention can modulate analog or digital pixel values. In this embodiment, the encoder 42' modulates and encodes digital samples from the distributor, rather than modulating and encoding analog samples as in FIG. 4.

[0066] Elements 26, 210-230 and 171 are implemented and performed as previously discussed in FIG. 4. The SSVT encoder 42' is modified with respect to the previously described encoders 250-256 as follows. Turning now to FIG. 5A, which shows the integrated transmitter 28, this circuit has been modified to not include the DAC 62. In other words, the samples output from the presentation bank 54 are output directly to the respective encoders 42 for digital encoding. Further details of the digital encoding are described in FIG. 8 below. After each digital encoder 42', its output digital EM signal is converted to an analog EM signal by a corresponding high frequency DAC 460-466 before being sent to the source driver on its respective EM path.

[0067] (SSVT decoding and integration with source driver) On the receiving side, the decoder of each source driver is responsible for decoding the stream of differential EM signals received on the transmission medium back into a format suitable for a display. In the suitable format, the video content contained in the samples can be presented frame-by-frame on a video display. As a result, video capture by any video source can be regenerated by a video sink. Alternatively, the decoded video information can be stored for later display in a time-shift mode.

[0068] (SSVT signal, encoding and decoding, resulting waveform) As previously mentioned, various embodiments of the present invention disclose, among other advantages, that analog signals are used to carry video information into the display set, eliminating the need for a DAC in the source driver.

[0069] For purposes of this disclosure, an electromagnetic signal (EM signal) is a variable represented as electromagnetic energy whose amplitude varies over time. EM signals propagate from a transmitter terminal to a receiver terminal over EM paths such as wire pairs (or cables), free space (or wireless), and optical or waveguide (fiber). EM signals may be characterized as being continuous or discrete independently in one of two dimensions (time and amplitude). A "pure analog" signal is a continuous-time and continuous-amplitude EM signal; a "digital" signal is a discrete-time and discrete-amplitude EM signal; and a "sampled analog" signal is a discrete-time and continuous-amplitude EM signal. This disclosure discloses a novel discrete-time, continuous-amplitude EM signal called a "spread-spectrum video transport" (SSVT) signal, which is an improvement over existing SSDS-CDMA signals. SSVT refers to the transmission of electromagnetic signals over an EM path or paths using improved spread-spectrum direct sequence (SSDS) based modulation.

[0070] Code Division Multiple Access (CDMA) is a well-known channel access protocol commonly used for wireless communication technologies, including cellular telephone communication. CDMA is an example of multiple access in which several different transmitters may transmit information simultaneously over a single channel. In telecommunications applications, CDMA allows multiple users to share a particular frequency band without interference from other users. CDMA employs direct sequence spread spectrum (SSDS) coding, which relies on a unique code to encode each user's data. Using the unique code, the transmissions of multiple users can be combined and transmitted without interference between the users. At the receiving end, the same unique code is used by each user to demodulate the transmission and recover each user's data, respectively.

[0071] SSVT signals differ from CDMA. When a stream of input video (for example) samples is received at an encoder, these are encoded by applying an SSDS-based modulation to each of a number of encoder input vectors to generate an SVTS signal. The SSVT signal is then transmitted over a transmission medium. At the receiver, the input SSVT signal is decoded by applying a corresponding SSDS-based demodulation to reconstruct the encoded samples. As a result, the original stream of time-series video samples, including color and pixel-related information, is conveyed from a single video source to a single video sink, unlike CDMA, which distributes data from multiple users to multiple receivers.

[0072] FIG. 7 shows a simple example of how signal samples (in this case analog values) are coded in an encoder and then transmitted over an electromagnetic path. Shown is an input vector of N analog values ​​902-908 representing the voltages of individual pixels in a video frame. These voltages may represent the luminance of a black and white image or the luminosity of a particular color value in a pixel (e.g., the R, G or B color value of the pixel) (i.e., each value represents a sensed or measured amount of light in a specified color space). Although pixel voltages are used in this example, this coding technique could be used with voltages representing any of a wide variety of signals from sensors (LIDAR values, audio values, tactile values, aerosol values, etc.), and the analog values ​​could represent other samples such as currents. Signal samples that are digital values ​​could also be coded, and this digital coding is described below. Furthermore, even though one encoder and one EM path are shown, one embodiment of the present invention works well with multiple encoders, each transmitting over an EM path.

[0073] Preferably, these voltages range from 0 to 1V for efficiency reasons, but different ranges are possible. These voltages are usually taken from the pixels in a row of a frame in a particular order, but other conventions can be used to select and order these pixels. Regardless of which convention is used to select these pixels and order them for encoding, that same convention will be used at the receiving end by the decoder to decode these voltages in the same order and place them in the resulting frame to which they belong. Similarly, if the frame is in color and uses RGB, the convention at the encoder could be that all of the R pixel voltages are encoded first, then the G and B voltages, or the convention could be that voltages 902-906 are the RGB values ​​of the pixels in the row, and the next three voltages 908-912 represent the RGB values ​​of the next pixel. Again, the same convention used by the encoder to order and encode the voltages is used by the decoder at the receiving end. Any particular convention for ordering the analog values ​​902-908 (whether by color value, by row, etc.) can be used as long as the decoder uses the same convention. As shown, any number N of analog values ​​902-908 can be presented for encoding at one time using the codebook 920, limited only by the number of entries in the codebook.

[0074] As mentioned above, the codebook 920 has an arbitrary number N of codes 932-938; i.e., in this simple example, the codebook has four codes, which means that four analog values ​​902-908 are encoded at a time. Many more codes could be used, such as 127 codes, 255 codes, etc., but due to practical considerations such as circuit complexity, it is preferable to use fewer codes. As is known in the art, the codebook 920 includes N mutually orthogonal codes, each of length L; in this example, L=4. Typically, each code is an SSDS code, but not necessarily a spreading code as discussed herein. As shown, each code is divided into L time intervals (also called "chips"), each time interval containing the binary value of that code. As shown in code representation 942, the code 934 may be represented in traditional binary form "1100", but the same code may also be represented as "11-1-1", as shown in code representation 944, for ease of use in modulating values, as will be described below. Codes 932 and 936-938 may also be represented by codes 942 or by 944. Note that each code of length L is not associated with a different computing device (such as a phone), a different person, or a different transmitter, as is done in CDMA.

[0075] Thus, to transmit the four analog values ​​902-908 over a transmission medium to a receiver (with a corresponding decoder), the following technique is used: Each analog value will be modulated by each chip in its corresponding code representation 944; for example, value 902 (i.e., .3) is modulated 948 in sequence by each chip in its code 932 representation 944. The modulation 948 may be a multiplication operator. Thus, modulating .3 with code 932 results in the sequence ".3, 3, 3, 3". Modulating .7 with code 934 results in ".7, 7, -.7, -.7"; a value "0" becomes "0, 0, 0, 0"; and a value "1" becomes "1, -1, 1, -1". Typically, the first chip of each code modulates its corresponding analog value, and then the next chip of each code modulates that analog value, although one implementation may also modulate a particular analog value with all chips of that code before moving on to the next analog value.

[0076] For each time interval, the modulated analog values ​​are summed at 951 (perceived vertically in this figure) to obtain analog output levels 952-958; for example, the sum of the modulation values ​​for these time intervals results in output levels of 2, 0, 6, and -1.4. These analog output levels 952-958 may be further normalized or amplified to match the voltage constraints of the transmission line and then transmitted sequentially as they are generated over the electromagnetic path of the transmission medium (such as a differential twisted pair). A receiver then receives these output levels 952-958 in that order and then decodes them using the same codebook 920 using the inverse of the encoding scheme shown here. The resulting pixel voltages 902-908 may then be displayed within the frame of a display at the receiving end according to the convention used. Thus, the analog values ​​902-908 are effectively synchronously encoded and transmitted over a single electromagnetic path in a series of L analog output levels 952-958. An infinite number of encoders and electromagnetic paths can also be used as shown and described herein. Furthermore, the number of N samples that can be encoded in this manner depends on the number of orthogonal codes used in the codebook.

[0077] Advantageously, even though the use of robust SSDS techniques (such as spreading codes) would result in significant bandwidth degradation, the use of mutually orthogonal codes, modulating each sample with a chip of its corresponding code, summing, and transmitting N samples in parallel using L output levels results in significant bandwidth gains. In contrast to traditional CDMA techniques, where binary numbers are coded consecutively and then summed, the present invention first modulates all samples (i.e., all analog or digital values, not single bits) with each chip in the corresponding code, and then sums their modulations at each time interval of the code to obtain the resulting analog voltage level for each particular time interval, thus exploiting the amplitude of the resulting waveform. It is these analog output levels that are transmitted over the transmission medium, not a representation of a binary number. Furthermore, the present invention facilitates the transmission of analog voltages from one video source to another video sink, i.e., from end-to-end, unlike CDMA techniques, which allow multiple accesses by different people, different devices, or different sources and transmit to multiple sinks. Furthermore, no compression is required for the transport of sample values.

[0078] 8 illustrates this novel encoding technique applicable to signal samples that are digital values, where digital values ​​902'-908' are digital representations of voltages. Using various examples of voltages, value 902' is "1101", value 904' is "0011", value 906' is "0001" and value 908' is "1000". Each digital value is modulated (digitally multiplied) by a representation 944 of each code (i.e. by "1" or "-1" depending on the chip of the code that corresponds to the digital value being modulated). Considering only the first time interval 940 of each code and adding the most significant bit (MSB), which is the sign bit, a modulation of "1101" results in "01101" (MSB "0" signifies a positive value), a modulation of "0011" results in "00011", a modulation of "0001" results in "00001", and a modulation of "1000" results in "01000". These modulation values ​​are shown and annotated on the first time interval. (Although not shown, modulating with a -1 chip results in a negative value that can be expressed in binary using the preferred binary representation for negative values).

[0079] By digitally summing, these modulation values ​​in the first time interval result in digital value 952' "011001" (again, the MSB is the sign bit); the other digital values ​​954'-958' are not shown in this example but are calculated in the same way. Considering this sum in base 10, we can verify that the modulation values ​​13, 3, 1 and 8 sum to 25. Although not shown in this example, typically an additional MSB is available for the result levels 952'-958' in that the sum may require more than six bits. For example, if the values ​​902'-908' are represented using 4 bits, the levels 952'-958' may be represented using a maximum of 10 bits in the case that there are 64 codes (adding the log2 of 64 bits). Or, if 32 modulation values ​​are summed, five more bits are added. The number of bits required for the output level depends on the number of codes.

[0080] The output levels 950' may first be normalized to accommodate the input requirements of the DAC, and then sequentially fed to the DAC 959 to convert each digital value to its corresponding analog value for transmission on the EM path. The DAC 959 may be a MAX5857 RF DAC (including a clock multiplying PLL / VCO and a 14-bit RF DAC core, where the complex path may be bypassed to directly access the RF DAC core), followed by a bandpass filter, not shown, and then a variable gain amplifier (VGA). In some situations, the number of bits used in the levels 950' is greater than the number allowed by the DAC 959, for example, the levels 952' are represented by 10 bits, but the DAC 959 is an 8-bit DAC. In these situations, the appropriate number of LSBs are discarded and the remaining MSBs are processed by the DAC, with no loss of visual quality of the resulting image on the display.

[0081] Advantageously, all digital values ​​are modulated and then all these modulated digital values ​​are digitally summed to generate a digital output level for conversion and transmission. This technique differs from CDMA, which modulates each binary digit of a digital value and then sums these modulated bits to generate an output. For example, assuming there are B bits in each digital value, with CDMA there would be a total of B x L power levels to transmit, whereas with this new digital (or analog) encoding technique there would only be a total of L power levels to transmit, thus having an advantage.

[0082] FIG. 9 shows a simulation (resembling an idealized oscilloscope trace) of an SSVT waveform 602 transmitted over an electromagnetic path after being output from an analog encoder, such as from one of the encoders 250-256 or from one of the DACs 460-466 (or after being digitally encoded and then converted by a DAC). The vertical axis is voltage, and the horizontal axis is the 100 ps oscilloscope measurement time interval. Note that the SSVT signal 602 is an analog waveform rather than a digital signal (i.e., the signal does not represent a binary number), and in this embodiment, may carry a range of voltages from about -15V to about +15V. The voltage values ​​of an analog waveform are (or at least can be) fully analog. Also, the voltage is not limited to some maximum value, although higher values ​​are impractical.

[0083] As explained before, analog voltage levels are transmitted in series over an electromagnetic path, with each level (either the analog output levels 952-958 after passing through a DAC or the digital output levels 952'-958') being the sum of modulated samples for each time interval. When transmitted, these output levels appear as waveforms, such as waveform 602. In particular, voltage level 980 represents the sum (i.e., output level) of modulated samples in a particular time interval. Using a simple example, the series of voltage levels 980-986 represents the transmission of four output levels. In this example, 32 codes are used, meaning that 32 samples can be transmitted in parallel; thus, voltage levels 980-986 (followed by a number of subsequent voltage levels depending on the number of chips in code L) form a parallel transmission of 32 coded samples (such as pixel voltages from a video source). After that transmission, the next set of L voltage levels of waveform 602 represents the transmission of the next 32 samples. In general, waveform 602 represents the encoding of analog or digital values ​​into analog output levels and the transmission of those levels within discrete time intervals to form a composite analog waveform.

[0084] FIG. 26 illustrates the decoding of analog input levels that have been coded using an encoder. As shown, L input levels 950 are received on a single electromagnetic path of a transmission medium. As described herein and above, a codebook 920 includes N orthogonal codes 932-938 that are used to decode the input levels 950 to generate an output vector of N analog values ​​902-908 (i.e., the same analog values ​​902-908 as coded above). To perform the decoding, as indicated by the vertical arrows, each input level 952-958 is modulated 961 by each chip of each code that corresponds to a particular index in the output vector 902-908. Considering the modulation of the levels 952-958 by a first code 932, such modulation produces a sequence of modulation values: "2, 0, .6, -1.4". Modulation of levels 952-958 with the second code 934 produces a sequence of modulation values ​​"2, 0, -.6, 1.4". Modulation with the third code 936 produces "2, 0, -.6, -1.4" and modulation with the fourth code 938 produces "2, 0, .6, 1.4".

[0085] The modulation values ​​of each series are then summed to generate one of the analog values ​​902-908, as indicated by the horizontal arrows. For example, the first series is summed to generate the analog value "1.2" (which becomes ".3" after normalization using a scale factor of "4"). In a similar manner, the modulation values ​​of the other three series are summed to generate the analog values ​​"2.8", "0" and "4", resulting in an output vector of analog values ​​902-908 after normalization. It is possible for each code to modulate an input level and then sum its series, or for all codes to modulate an input level before summing each series. Thus, the output vector of N analog values ​​902-908 is carried in parallel using L output levels. Although no example of decoding of digital input levels is shown in these examples, one skilled in the art will recognize that performing such decoding is straightforward after reading the encoding of digital values ​​in the above description.

[0086] 27A, 27B and 27C show that the encoder and decoder can operate on analog or digital samples. Various analog and digital encoders and decoders are described above. As explained above, in some cases, there may be more than one EM path, and accordingly, there may be more than one encoder / decoder pair and a corresponding number of DACs or ADCs.

[0087] FIG. 27A illustrates the use of an analog encoder and corresponding analog decoder. The input to the analog encoder 900 is analog samples 970 or digital samples 971 that are converted to analog by a DAC 972 located in the analog encoder. In this manner, the analog or digital samples arriving at the analog encoder can be encoded for transmission over an electromagnetic path on a transmission medium. The analog decoder 900' decodes the encoded analog samples to generate analog samples 970 for output. The analog samples 970 may be used as is or converted to digital samples using an ADC (not shown).

[0088] FIG. 27B illustrates the use of a digital encoder and a corresponding analog decoder. The input to the digital encoder 901 is digital samples 971 or analog samples 970 that are converted to digital by an ADC 973 located in the digital encoder. Because the encoder is digital, a DAC 959 located in the encoder converts the encoded samples to analog before transmission over an electromagnetic path. In this manner, analog or digital samples arriving at the digital encoder can be encoded for transmission over an electromagnetic path on a transmission medium. An analog decoder 900' decodes the encoded analog samples to generate analog samples 970 for output. The analog samples 970 may be used as is or converted to digital samples using an ADC (not shown).

[0089] FIG. 27C illustrates the use of a digital decoder to decode an encoded analog signal that arrived via an electromagnetic path on a transmission medium. The encoded analog signal is transmitted using an analog or digital encoder as just described. An ADC 974 located in the digital decoder 976 receives the encoded analog samples transmitted via the electromagnetic path and converts the samples to digital. These encoded digital samples are then decoded by the digital decoder 976 into digital samples 978 (corresponding to the values ​​of the input vector of samples originally encoded prior to transmission over the electromagnetic path). The digital samples 978 may be used as is or may be converted to analog samples using a DAC.

[0090] Due to such phenomena as attenuation, reflections due to impedance mismatch, and intrusive aggressor signals, every electromagnetic path degrades the electromagnetic signal propagating through it, and therefore the taken measurement of the input level at the receiving terminal is always subject to an error with respect to the corresponding output level made available at the transmitting terminal. Therefore, scaling of the input level at the receiver (or normalization or amplification of the output level at the transmitter) can be performed to correct, as known in the art. Furthermore, due to the process gain (i.e., due to an increase in L, which also increases the electrical elastic energy), the decoded input level at the decoder is normalized by a scale factor using the code length, as known in the art, to recover the transmitted output level. Furthermore, as described herein, it is preferred that L≧N≧2, but in some circumstances it is also possible that L is less than N (i.e., N>L≧2).

[0091] Specific Embodiments The above provides an overview of the integration of an SSVT transmitter with a timing controller, and the integration of an SSVT transmitter with a timing controller and a system on chip. Below are specific embodiments that provide examples of this integration.

[0092] FIG. 11 shows an 8K display set with an integrated SSVT transmitter and timing controller. The relevant portion of an 8K144 display set with an LCD / OLED display 328 is shown. The input to the display set's SoC 308 is a compressed digital video signal 302, which can be input via an HDMI connector 303 or an RJ-45 connector 305, among other suitable connector types. The SoC decompresses this digital data (and performs other processing as known in the art and described above) and forwards this modified digital data to the integrated timing controller and SSVT transmitter module 320 using a suitable V-by-One format 310 and rate as shown. One or more control signals 311 from the SoC to the integrated module 320 can have many functions, such as carrying configuration information or framing signals for downstream components. One function can be an adjustment of the gamma curve from SDR to HDR ("standard dynamic range" to "high dynamic range") or similar adjustment. Other functions include setting TCON operating parameters such as resolution, backlight type, etc.

[0093] The integrated module 320 can take different forms, such as a single integrated circuit or implementation on a printed circuit board, and can include a single TCON or two or more TCONs. The module 320 can be implemented as shown in Figures 2, 4, 5A, 6, 10, or in a similar manner as would be understood by one of ordinary skill in the art after reading this disclosure. Within the module 320, there is shown a TCON 314 and a SSVT transmitter 318 connected by a bus 316. The bus 316 passes, for example, 24 or 48 parallel digital signals (usually this is the standard output of the TCON) as input to the SSVT Tx 318. However, these numbers can vary depending on the implementation. Essentially, during each period of the SSVT Tx input clock, a number of pixels are transmitted. For example, the width of this bus, in pixels, is up to one row (about 23,000 sub-pixels) at the row rate, or a fraction of that at a corresponding multiple of the row rate.

[0094] Each of the SSVT transmitter encoders then transmits an SSVT signal 322 to a corresponding source driver 324 of a display 328. In this example, there are 24 encoders, which means there are 24 SSVT signals and 24 source drivers. As mentioned above, each source driver is preferably implemented as described herein and in U.S. patent application Ser. No. 17 / 900,570 (HYFYP009), integrating an SSVT receiver (with a corresponding decoder) with the elements of a traditional source driver.

[0095] 11, an example of an 8K120 display set is not shown, with 64 Vx1-HS at 2.3 GHz transfer from the SoC to the integrated module 320, and 24 SSVT signal pairs running at 634 MHz. Also not shown is how the module 320 replaces four prior art TCONs, each with a 16×Vx1-HS 4 GHz stream fed from the SoC 308. These four streams can be left as is and input to the module 320 individually, or combined into stream 310 as shown. Also not shown are the timing and framing control signals from the module 320 to the gate drivers of the display 328.

[0096] 12 shows an 8K display set with an integrated SSVT transmitter, timing controller and SoC. The relevant portion of an 8K144 display set with an LCD / OLED display 358 is shown. The input to the display set's integrated SoC, TCON and SSVT transmitter 350 is a compressed digital video signal 332, which may be input via an HDMI connector 333 or an RJ-45 connector 335, among other suitable connector types. The SoC decompresses this digital data (and performs other processing known in the art and described above) and internally forwards this modified digital data to the integrated timing controller and SSVT transmitter.

[0097] The integrated module 350 can take different forms, such as a single integrated circuit or implementation on a printed circuit board, and can include a single TCON or two or more TCONs. The integration of the TCON and SSVT transmitter can be implemented as shown in Figures 2, 4, 5A, 6, 10, or in a similar manner as would be understood by one of ordinary skill in the art after reading this disclosure. The integration with the SoC is performed by passing the signal 164 from the SoC to the unpacker 26 internally. It is contemplated that the integrated implementation could be a single chip, or multiple chips side-by-side, or a multi-chip package (that looks like a single chip, but actually contains two or three chips). In one particular embodiment, the 64xVx1 signal 310 of Figure 11 is replaced with a custom intra-chip interface bus that transmits more bits. Since no chip pins are required, the bus width is ten times larger and the rate is reduced.

[0098] Each of the SSVT transmitter encoders then transmits a SSVT signal 352 to a corresponding source driver 354 of a display 358. In this example, there are 24 encoders, which means there are 24 SSVT signals and 24 source drivers. As mentioned above, each source driver is preferably implemented as described herein and in U.S. patent application Ser. No. 17 / 900,570 (HYFYP009), integrating an SSVT receiver (with a corresponding decoder) with the elements of a traditional source driver. In such a source driver, no DAC is required.

[0099] Not shown is an example of an 8K120 display set with 24 SSVT signal pairs running at 634 MHz, which could be implemented as shown in Figure 12. Also not shown are the timing and framing control signals from module 350 to the gate drivers of display 358.

[0100] FIG. 13 illustrates one particular embodiment of an integrated module 320 using digital encoding. As shown, 64 streams of Vx1 samples 362 are received at corresponding 64 Vx1 receivers 364, each of which delivers a stream of 8-bit RGB samples 365 per color channel to a distributor 366. The distributor 366 can be implemented as shown at 40 in FIG. 5A or as shown in FIG. 14A or 14B. Each of the total of 24 parallel buses 368 then delivers the 64 samples (N=64) to one of 24 encoders 370, each of which digitally encodes the N samples and outputs a digital signal that is converted by one of 24 digital-to-analog converters 372 to a SSVT EM signal 374 and delivered to the display source driver. The term "15 or more bits per level" means that each analog level output reflects 15 or more bits of information.

[0101] FIG. 14A illustrates one possible implementation of the distributor of FIG. 13 in more detail. As shown, there are 64 stream inputs 365 from the Vx1 receiver 364, each input containing a serial stream of RGB samples. The samples of these streams are stored in a line buffer 376. The line buffer samples are then arranged into a set of 24 input vectors 378 (one input vector per encoder) using any particular arrangement. As shown, each input vector receives its 64 samples from 64 sequential locations in the line buffer, but the samples can be arranged in any desired order when placed into each input vector. Once an input vector is filled, the samples are all delivered in parallel to the encoders for encoding. In this example, each of the 24 input vectors encodes 1 / 24 of an 8K×3 input line (i.e., 960 lines for each encoder). Each input vector clocks in 64 samples (or 60 samples) at a time, but there can be up to 960 blocks clocked in following that input vector. For example, input vector #23 receives input from columns 0-959, vector #22 receives input from columns 960-1919, and so on. More specifically, during one coding interval, 64 locations from the line buffer are coded via one input vector with 64 locations. The encoder transmits 60 samples and 4 subband signals. The coding process is repeated 16 times to convey all 960 samples per row during each line interval. The assembly bank, relay bank, and presentation bank are not shown in this implementation of this simplified diagram. They can be used as shown in FIG. 5A to implement the array.

[0102] FIG. 14B shows another possible implementation of the distributor of FIG. 13 in more detail. In this implementation, no line buffers are used and samples are aligned directly from the stream inputs to the input vector. As shown, there are 64 stream inputs 365 from the Vx1 receiver 364, each input containing a serial stream of RGB samples. Input samples from any stream input can be assigned to any location of the input vector according to a predefined alignment. As an example, the first two positions of the input vector 378 come from the first and second stream inputs, the next two positions come from the third and first stream inputs, and the fifth position comes from the second stream input. In this example, three of the positions of the input vector 379 come from the last three stream inputs, thus showing that any alignment is possible.

[0103] FIG. 15 illustrates one particular embodiment of an integrated module 320 using analog coding. As shown, 64 streams of Vx1 samples 382 are received at corresponding 64 Vx1 receivers 384, which each deliver a stream of 8-bit per color channel (24-bit per pixel) RGB samples 385 to a distributor 386. The distributor 386 can be implemented as shown at 40 in FIG. 5A or as shown in FIG. 14A or 14B. Each of a total of 24 parallel buses 388 then delivers 64 samples (N=64) to a digital-to-analog converter 392 (or to 64 DACs in parallel, respectively), after which the converted samples are delivered in parallel to one of 24 encoders 390, each of which uses analog coding to encode those N samples, and then outputs a SSVT EM signal 394 for delivery to the display source driver. The term "15 or more bits per level" means that each analog level output reflects 15 or more bits of information.

[0104] Figure 16 shows one of the digital encoders from Figure 13 in more detail. As explained above with reference to Figure 8 (and elsewhere), a codebook 397 contains a code associated with each input sample, and a chip counter 396 is used to step through each of the chips of the code during modulation. In operation, each modulator 371 modulates its corresponding digital sample with the current chip of the associated code, and all of the samples are summed by summer 373 to generate one of the output levels. This operation is repeated for each chip of the code, generating L output levels that are then converted to analog and output as the SSVT signal 374.

[0105] Figure 17 shows one of the analog encoders from Figure 15 in more detail. As explained above with reference to Figure 7 (and elsewhere), a codebook 397 contains a code associated with each input sample, and a chip counter 396 is used to step through each of the chips of the code during modulation. In operation, each modulator 391 modulates its corresponding analog sample with the current chip of the associated code, and all of the samples are summed by a summer 393 to generate one of the output levels. This operation is repeated for each chip of the code, generating L output levels that are then output as the SSVT signal 394.

[0106] Figure 18 shows an 8K120 display set with an integrated SSVT transmitter, timing controller and SoC. This implementation is similar to that shown in Figure 12, except that each source driver multiplexes any number of input SSVT signals. The relevant parts of the display set are shown, including an LCD / OLED display 458. Timing and framing control signals from the module 450 to the gate drivers of the display 458 are not shown.

[0107] The input to the display set's integrated SoC, TCON and SSVT transmitter 450 is a compressed digital video signal 432, which may be input via an HDMI connector 433 or an RJ-45 connector 435, among other suitable connector types. The SoC decompresses this digital data (and performs other processing known in the art and described above) and internally forwards the modified digital data to the integrated timing controller and SSVT transmitter.

[0108] The integrated module 450 can take different forms, such as a single integrated circuit or implementation on a printed circuit board, and can include a single TCON or two or more TCONs. The integration of the TCON and SSVT transmitter can be implemented as shown in Figures 2, 4, 5A, 6, 10, or in a similar manner as would be understood by one of ordinary skill in the art after reading this disclosure. The integration with the SoC is performed by passing the signal 164 from the SoC to the unpacker 26 internally.

[0109] Each of the SSVT transmitter encoders then transmits an SSVT signal 452 to a corresponding source driver 354 of the display 458, and each source driver receives three SSVT signals (i.e., 3×SSVT pairs at 317×3Msamples / s). In this example, there are 48 encoders, which means that 48 SSVT signals and only 16 source drivers are needed for multiplexing. As mentioned above, each source driver is preferably implemented as described herein and in U.S. patent application Ser. No. 17 / 900,570 (HYFYP009), integrating an SSVT receiver (with corresponding decoder) with traditional source driver elements. In such a source driver, no DAC is required. The multiplexing of the three input SSVT signals to each source driver can be performed in a manner known to those skilled in the art. Advantageously, the multiplexing dramatically reduces the number and cost of source drivers.

[0110] (Integration of SSVT receiver and display source driver) As mentioned above, the SSVT signal 167 from the integrated SSVT transmitter and timing controller 150 or from the integrated SSVT transmitter, timing controller and SoC 140′ shown in various embodiments herein is conveyed to a display panel source driver 169. The following describes how an SSVT receiver can be integrated with such a source driver or drivers.

[0111] FIG. 19 shows a display source driver 586. Multiple source drivers can be cascaded as shown and as known in the art, and these multiple source drivers drive a display panel. As shown, the source driver 586 does not require a DAC (located in the signal path to convert digital samples to analog samples for display) as required in prior art source drivers. The input to the decoding unit 610 of each source driver is an analog SSVT signal 592 that is encoded upstream within the display unit itself or external to the display unit as described herein. As shown, the SSVT signal 592 is daisy-chained between the source drivers. In an alternative embodiment, each source driver has its own SSVT signal, and the TCON provides timing information to each source driver chip.

[0112] The decoding unit 610 may have any number (P) of decoders, but may also have only a single decoder. The unit 610 decodes one or more SSVT signals (described in more detail below) and outputs a number of reconstructed analog sample streams 612 (i.e., analog voltages) (the number of samples corresponds to the number of outputs of the source driver). These analog outputs 612 may not be in the voltage range required by the display panel, so scaling may be required and may be input to a level shifter 620 that shifts the voltage to a voltage range for driving the display panel using analog conversion. Any suitable level shifter may be used, such as a latch type or an inverter type, as known in the art. A level shifter may also be called an amplifier.

[0113] As an example, the voltage range output from the decoding unit may be 0 to 1V, and the voltage range output from the level shifter may be -8 to +8V (the inversion signal 622 is used to inform the level shifter to flip the voltage every other frame (i.e., the range will be -8 to 0V in one frame and 0 to +8V in the next frame). In this way, the SSVT signal does not need to flip its voltage every frame. The decoding unit provides a positive voltage range (for example) and the level shifter flips the voltage every other frame as the display panel expects. The decoding unit may also perform line inversion and dot inversion. The inversion signal tells the level shifter which voltage to switch. Some display panels, such as OLED, do not need to flip this voltage every other frame, in which case the inversion signal is not needed and the level shifter does not flip the voltage every other frame. Display panels, such as LCD, do need this voltage flip. The inversion signal 622 is recovered from the decoding unit, as described below.

[0114] The inputs to the level shifter 620 can also be gain and gamma values, where gain determines the degree of amplification to apply and the gamma curve relates luminous flux to perceived brightness, which is a linearization of human optical perception of luminous flux. Typically, in prior art source drivers, gain and gamma are both set values ​​determined by the manufacturing characteristics of the display panel. In analog level shifter 620, gain and gamma can be implemented as follows: Gamma is implemented in the digital part of the system in one embodiment, and level shifting and gain are implemented in the driver by setting the output stage amplification. In the case of gamma, this implementation is also possible in the output driver by implementing a non-linear amplification feature. Once shifted, the samples are output to output 634 and used to drive source electrodes in their corresponding columns of the display panel, as known in the art.

[0115] In order to properly encode the SSVT code for final display on a particular display panel (whether encoded within the display unit itself or further upstream outside the display unit), various physical features or characteristics of that display panel are required by the GPU (or other display controller) or any entity performing the SSVT encoding. These physical features are labeled 608 and include, among others, the resolution, tessellation, backlight layout, color profile, aspect ratio, and gamma curve. Resolution is a constant for a particular display panel. Tessellation refers to the way the plane of the panel is subdivided into areas in an orderly and predetermined manner, with the unit being the pixel. Backlight layout refers to the resolution and diffusion characteristics of the backlight panel. Color profile is the precise luminance response of all the primary colors, providing the precise color of the image. The aspect ratio of the display panel has a discrete, known value.

[0116] These physical characteristics of a particular display panel can be delivered, hardwired, or provided to a particular display controller in a variety of ways. In one example, signal 608 delivers the values ​​of these physical characteristics directly from the display panel (or from elsewhere in the display unit) to the SSVT transmitter 540. Alternatively, an SSVT transmitter 540 embedded within a particular display unit has these values ​​hard-coded into the transmitter. Alternatively, a particular display controller is intended for use only with a particular type of display panel, and the characteristic values ​​are hard-coded into that display controller.

[0117] The input to the display panel can also be a backlight signal 604 that instructs the backlight LEDs (i.e., when to switch on and at what level). In other words, the input to the display panel is typically a low-resolution representation of the image, meaning that the backlight LEDs turn on where the display needs to be bright and dim where the display needs to be dark. The backlight signal can be a monochrome signal that can also be embedded within the SSVT signal (i.e., it can be another independent parallel video signal that travels with the other parallel video signals, R, G, and B (for example)) and can be of low or high resolution.

[0118] The output from the decode unit 610 is a gate driver control signal 606 that shares timing control information with the gate drivers 560 at the left edge of the display panel to synchronize the gate drivers with the source drivers. Typically, each decode unit contains a timing acquisition circuit that obtains the same timing control information as the gate drivers, and one or more of the source driver flex foils (typically the left-most and / or right-most source drivers) route that timing control information to the gate drivers. The timing control information for the gate drivers is embedded within the SSVT signal and is recovered from that signal using established spread spectrum techniques.

[0119] Note that Figure 19 shows that the gate driver control signals originate within the decoder unit of the source driver (Figure 20 shows in more detail that the gate driver control signals 606 at the bottom originate in a channel aligner 787 associated with the decoder). Also note that Figures 2 and 10 show that the timing signal 171 does not travel with the SSVT signal.

[0120] Many variations of providing the gate control signal are possible. The gate signal is originally an independent signal (start pulse + clock + control), but can be carried together with the SSVT signal (but does not need to be encoded), as shown in Figure 20. The gate signal can also be extracted from the embedded clock signal of the SSVT signal (decoder -> framing -> aligner). However, in modern "gate-on-array" panels, the gate signal needs to be changed to multiple clock pulses through a dedicated clock generation integrated circuit, making extraction from the SSVT clock signal unlikely (but still possible with a suitable aligner function). As shown in Figures 2, 4, 6 and 10, the gate signal 171 does not travel with the SSVT signal. Usually, the source driver input timing is adjusted to the gate driver timing by the upstream TCON. In one particular implementation, the wiring loom sends the gate driver control signal in parallel with the source driver signal, but the gate driver control signal does not enter the source driver and is not generated by the source driver. Nevertheless, the signal 171 can propagate through the flex foil connecting the source drivers, or even through the source drivers themselves in another embodiment.

[0121] Typically, traditional display drivers are connected directly to the glass using "COF" (chip on flex or chip on foil) IC packages. Traditional COG (chip on glass) is also possible, but is not seen in larger displays. These drivers can be replaced with the new source drivers of Figures 19 and 20, thus making the existing display panel an SSVT capable panel. The inputs of these ICs are typically connected together by a PCBA, providing input signals from the video source and a timing controller. These can be close to or remote from the display panel, and transfer the video and control signals over inexpensive wires.

[0122] (Details of SSVT decoding and integration with source driver) At the receiving end, the decoder of each source driver is responsible for decoding the stream of differential EM level signals received on the transmission medium back into a suitable format for display. Once the suitable format is obtained, the video content contained in the samples can be presented frame by frame on a video display. As a result, the video captured by any video source can be regenerated by a video sink. Alternatively, the decoded video information can be stored for later display in a time-shifted mode.

[0123] FIG. 20 shows a more detailed diagram of the source driver's decoder unit 610. P represents the number of input electromagnetic pairs, each carrying an SSVT signal independent of the other pairs, except that it is an isochronous signal known to be generated in lock-step fashion by the transmitter's encoder. The source driver includes P decoders 780 and a collector (blocks 782, 786). The decoder 780 performs the inverse transformation of the transmitter's pair's encoder and reconstructs its input differential EM level signal into an output vector of N reconstructed samples (although single-ended inputs rather than differential inputs may be used). The collector assigns the decoder output vector samples (or "reconstructed samples") to their predetermined positions on the source driver input 612. The source driver input 612 includes S reconstructed samples corresponding to the driven column groups in the display panel. A re-timer function is included in the collector.

[0124] P decoders 780 (labeled 0 through P-1) are used to generate differential EM level signals level 0 through level P-1 In response, each of the decoders 780 receives a reconstructed sample (sample 0 through sample N-1 In this case, N differential pairs of vectors V0, V1, V2, V3 are generated. If there are four decoders 780 (P=4), four vectors V0, V1, V2, V3 are constructed respectively. The number of samples N is exactly equal to the number of orthogonal codes used for previous encoding. That is, N orthogonal codes are used, which means that N codes from the codebook are used.

[0125] The reconstruction banks 782 each store N reconstructed samples (sample 0 to sample 1) for each of the four decoder output vectors V0, V1, V2, and V3 at the end of each decoding interval. N-1 The voltage signals of these received differential pairs are then sampled and held for each of the four vectors V0, V1, V2, and V3 (samples N-1Each decoder output vector V0, V1, V2, V3 is output as a single voltage (sample 0 to sample 1), respectively. Essentially, each reconstruction bank reconstructs the differential pair voltages into a single voltage. The relay bank 786, as described in more detail below, outputs all the reconstructed samples (N n-1 1 to N0) and acts as an analog output buffer. Once the samples move into the relay bank 786, they are triggered by a latch signal 632 derived from the decoded SSVT signal. The latch signal can be daisy-chained between the source drivers. Once the samples are released from the relay bank, they are sent to the level shifter 620.

[0126] The decoder unit 610 also includes a channel aligner 787 and a relay controller 789 that receive framing and aperture information from each decoder 780. In response, the relay controller 789 adjusts the timing of the relay bank 786 to ensure that all samples come from a common time interval where a level signal was sent by the SSVT transmitter. As a result, the individual channels of the transmission medium do not all have to have the same length, since the channel aligner 787 and relay controller 789 compensate for any timing differences. The gate driver control signal 606 provides timing information to the gate drivers (or to intermediate circuitry), which in turn provides the correct timing and control signals to the gate drivers. The gate driver control signal 606 may originate from the channel aligner 787. Note that while FIG. 20 discloses a decoder that buffers samples in the relay bank 786 before level shifting (amplifying), it is also possible to level shift the samples before buffering and outputting them.

[0127] (Display panel source driver array) Figure 21 shows an alternative embodiment for implementing an array of source drivers. The array 650 is suitable for use in a display panel with 8K resolution and 144Hz refresh rate (i.e., an "8K144" panel). Figure 8 shows that in this embodiment, each source driver includes a single decoder (i.e., one decoder decoding unit) followed by a collector and an amplifier, whereas Figures 19 and 20 show that each source driver may have many decoders in the source driver's decoding unit. Either approach can be used.

[0128] Twenty-four 720 MHz SSVT signals 652-654 are shown, each of which is a twisted pair from the SSVT transmitter 540; that is, each twisted pair originates from the transmitter's encoder. Each pair is input to one of the decoders 656-658, each of which outputs 64 analog samples at a frequency of 11.25 MHz. Each of these samples is input to one of the 24 collectors 662-664, each of which collects 15 sets of these samples before updating its output once every 15 decoding intervals, as will be shown in more detail below. As noted above, each collector consists of a reconstruction bank and a repeater bank (not explicitly shown in this figure). These 960 analog samples from each collector are then input to one of the amplifiers 666-668 at a frequency of 750 kHz for amplification and then output onto a display column of the display panel at a frequency of 750 kHz (11.25 MHz x 64 / 960) as an amplified analog level 670. For clarity, signals 604, 606, 608, 622, 632 shown in Figures 19 and 20 are not shown.

[0129] In theory, if the encoded SSVT signal had a higher voltage and the decoded signal was at the sample voltage required by the display, the amplifier or level shifter could be omitted. However, since the SSVT signal is usually at a lower voltage (and a higher voltage output is required by the display), amplification is necessary. Note that while Figure 21 discloses a decoder that buffers and then amplifies the samples in collector 664, it is also possible to amplify and then collect (buffer) the samples for output. Either embodiment can be used.

[0130] Figure 22 is a block diagram of one of the decoders 656 from Figure 21. One of the SSVT signals 652 is shown input to the decoder. The decoder includes a chip counter 680, a codebook 682, typically stored in RAM, that contains the orthogonal codes used for encoding and decoding, and a block diagram 684 of a respective decoding circuit for each of 64 output analog samples 688. Each group of 64 analog samples is output as "valid" once every L cycles at 11.25 MHz. The decoding is described in more detail below along with specific circuit diagrams.

[0131] FIG. 23 is a block diagram of the collector from FIG. 21 and shows the relay bank 786 from FIG. 20 in more detail. Essentially, each collector performs serial-to-parallel conversion into a partitioned line buffer. The input to each of the collectors 662-664 shown is a set of 64 analog samples 690-692 from each decoder at a frequency of 11.25 MHz (reconstruction bank 782 not shown). As shown, during each decoding interval, a new set of 64 reconstructed samples that is input is stored in the collector, and each collector is filled once every 15 decoding intervals. As shown, after each of the 15 decoding intervals, the 960 stored samples 698 from each collector are output to their corresponding amplifiers 666-668 before being delivered to the corresponding column of the display panel, as shown. In one particular embodiment, each of the source drivers of FIG. 21 (e.g., the decoder 658, the collector 664, and the amplifier 668) are implemented in an integrated circuit, and each such integrated circuit can be mounted on the flexible PCB 584.

[0132] (Decoder Detailed Embodiment) 24 is a logic diagram of one of the four decoders 780. The decoder 780 includes a differential amplifier 1092 and a sample and hold circuit 1094 arranged to receive and sample and hold one of the four differential EM level signals received on the transmission medium. Other types of circuits (receivers) arranged to receive and sample and hold the input EM level signals may also be used. The sampled EM level signals are then fed to N decoder track circuits 1096 (N n-1 The sequence controller 1098 provides the same SSDS chips that were applied at the transmitter to each of the N decoder track circuits 1096. This results in a sample output (N n-1 〜N0) are provided to the reconstruction bank 782. Since the same SSDS chips used at the transmitter are used by each of the decoder track circuits 1096, the demodulated samples N n-1 ~N0 is the same as before modulation on the transmitting side.

[0133] The decoder controller 1098 for each of the decoders 780 also generates a number of control signals, including a strobe signal, an end of bank (EOB) signal, an aperture signal, and a framing signal. The EOB signal is provided to the reconstruction bank 782 and indicates when the relay bank 786 has completely filled with samples. When this occurs, the EOB signal is asserted to start the next set of reconstructed samples (N n-1 . . N0) and clears both the decoder track 1096 and the relay bank 786. The aperture control signal is provided to the sample and hold circuit 1094 and the framing signal is provided to the channel aligner 787 and to the relay controller 789.

[0134] Referring to FIG. 25, a diagram of an exemplary encoder track circuit 1096 is shown. The decoder track circuit 1096 includes a multiplier section and an accumulator section. The multiplier section includes a first switch pair S1-S1, a second switch pair S2-S2, a third switch pair S3-S3, and a pair of capacitors C1-C1 on the first (positive) and second (negative) power rails. The accumulator section includes additional transistor pairs S4-S4, S5-S5, S6-S6 and S7-S7, an operational amplifier, and a pair of capacitors CF-CF on the first (positive) and second (negative) power rails, respectively. For each demodulation cycle, a differential EM level signal pair is received at a first level input (level+) terminal and a second level input (level-) terminal. The differential EM level signal pair is demodulated in the multiplier section by conditional inversion by multiplying by either positive (1) or negative (-1) depending on the value of the received SSDS chip.

[0135] If the SSDS chip has a value of (+1), when clk1 is active, the transistor pairs S1-S1 and S3-S3 close while S2-S2 remains open. As a result, the voltage values ​​at the first level input (level+) terminal and the second level input (level-) terminal are passed and stored by the two capacitors C1 and C1 on the positive and negative rails, respectively. In other words, the input values ​​are multiplied by (+1) and no inversion occurs.

[0136] If the SSDS chip has a value of -1, the S1-S1 switches are both off, while the switches S2-S2 and S3-S3 are all turned on when clk1 is active. As a result, the voltage values ​​received at the positive or first (+) terminal and the negative or second (-) terminal are swapped. In other words, the input voltage value provided at the first or positive terminal is routed to and stored on the capacitor C1 on the lower negative rail, while the voltage value provided on the second or (-) terminal is switched to and stored on the capacitor C1 on the upper positive rail. Thus, the received voltage value at the input terminal is inverted, i.e., multiplied by (-1).

[0137] When clk1 goes to the inactive state, the stored charge on C1 and C1 remains. When clk2 goes to the active state, transistor pair S4-S4 opens while transistor pairs S5-S5 and S6-S6 close. The stored charge on capacitor C1 on the lower or negative rail and C1 on the upper or positive rail are then provided to the differential inputs of an operational amplifier. The output of the operational amplifier is the original + / - sample pair prior to transmit encoding.

[0138] The charge stored on the two capacitors C1 and C1 is also transferred to the capacitor CF on the upper or positive rail and the capacitor CF on the lower or negative rail when Clk2 is active. With each demodulation cycle, the charge on the capacitor C1 on the upper rail and the capacitor C1 on the lower rail are stored on the two capacitors CF and CF on the upper and lower rails, respectively. When the clk1 and EOB signals are both active, the transistor pair S7-S7 are both closed, shorting the plates of the capacitors CF and CF together. As a result, the stored charge is removed and the two capacitors CF and CF are reset and ready for the next demodulation cycle.

[0139] Since each decoder 780 has N decoder track circuits 1096, N decoded or original + / - sample pairs are regenerated every demodulation cycle. These N + / - sample pairs are then provided to a reconstruction bank 782 and then to a relay bank 786. As a result, the original set of samples is regenerated with its original color content information (e.g., S=3 for RGB).

[0140] The decoder track 1096 reconstructs the input level samples over a series of L cycles, demodulating each successive input level with the successive SSDS chips of the code of that track. The results of each of the L demodulations are stored on a feedback capacitor CF. When EOB is asserted during clk1 corresponding to the first demodulation cycle of a decoding cycle, CF is cleared after EOB to start accumulating again from zero volts or some other reset voltage. In various non-exclusive embodiments, the value of L is a predetermined parameter. In general, the higher the parameter L, the greater the SSDS process gain and the better the electrical resilience of the transmission of the SSVT signal on the transmission medium. On the other hand, the higher the parameter L, the higher the required frequency for the application of the SSVT modulation, which may degrade the signal quality due to insertion loss caused by the transmission medium. The above demodulation cycle is repeated again and again by each of the decoders. The end result is the recovery of the original time series set of samples (i.e., a set of S samples), each with their original color content information.

[0141] (Cell Phone Specific Embodiment) Figure 28 is a block diagram for carrying video samples using SSVT in a mobile phone. Prior art displays on existing OLED DDIC devices such as mobile phones require improvement due to the high refresh rate of 4K smartphone displays, MIPI receivers, SRAM, digital image processing, and extensive use of analog signals requiring approximately 1,000 digital-to-analog converters.

[0142] We propose a split OLED DDIC architecture that has the advantages of allowing optimal DDIC-TCON and DDIC-SD splitting, providing short-range MIPI transmission from the SoC, optimizing the digital DDIC-TCON for SRAM and image processing, providing an all-analog simplified DDIC, and requiring only a few digital-to-analog converters in the DDIC-TCON integrated with the SSVT transmitter.

[0143] Shown is a mobile phone (or smartphone) 500, which may be any similar handheld mobile device used for communication and display of images or videos. The device 500 includes a display panel 510, a traditional mobile SoC 520, an integrated DDIC-TCON (Display Driver IC-Timing Controller) and SSVT transmitter module 530, and an integrated analog DDIC-SD (DDIC-Source Driver) and SSVT receiver 540. The mobile SoC 520 and module 530 are internal components of the mobile phone, but are shown external to the mobile phone for ease of illustration.

[0144] Mobile SoC 520 is any standard SoC used in mobile devices, and delivers digital video samples to module 530 via MIPI DSI 524 (Mobile Industry Processor Interface Display Serial Interface) in a manner similar to the Vx1 input signal discussed above. Within module 530 is included an integrated DDIC-TCON with SSVT transmitter. Upon reading this disclosure and referring to the previous figures, one skilled in the art will understand how the SSVT transmitter can be implemented to output any number of analog SSVT signals 534. In this example, the SSVT transmitter outputs 12 pairs of SSVT signals at 380Msps. Timing and framing control signals from module 530 to the gate drivers of display panel 510 are not shown. Typically, for a mobile phone, the DDIC is located at the bottom edge of the phone and the SoC is approximately in the center of the device. Accordingly, the integrated DDIC-TCON / SSVT transmitter is located close to the SoC, within about 10 cm, or within about 1-2 cm. Because digital data transmission occurs at extreme frequencies, it is advantageous to keep conductor lengths as short as possible. For a table computer, that distance is about 25-30 cm or less.

[0145] These analog SSVT signals are received by an integrated analog DDIC-SD and SSVT receiver 540. A description of how to integrate a source driver with a SSVT receiver to receive any number of analog SSVT signals and generate voltages to drive a display panel is provided herein and in the above-mentioned U.S. patent application Ser. No. 17 / 900,570 (HYFYP009). Advantageously, only one source driver is required to drive the display panel 510, and the module 540 does not require any digital-to-analog converters.

[0146] (Other embodiments) The present invention includes the following other embodiments. 1. A device integrating a timing controller with an encoder, comprising: a line buffer controller for receiving at least one media signal of digital samples originating from a system-on-chip of a display set; a line buffer in communication with said line buffer controller and arranged to store said lines of digital samples; at least one DAC that receives a subset of said lines of said digital samples and outputs a subset of said analog samples; at least one encoder for encoding the output subset of analog samples from the at least one DAC to output a sequence of analog output values ​​presented to an electromagnetic path corresponding to the at least one encoder; a gate driver controller configured to receive a framing flag from said line buffer controller and output a gate driver control signal to a gate driver of said display set; 13. An apparatus comprising: 2. The device described in embodiment 1, which is integrated into a single integrated circuit of the display set. 3. The apparatus of embodiment 1, wherein the output values ​​are delivered over the electromagnetic path to corresponding decoders associated with source drivers of the display set. 4. The apparatus of embodiment 3, wherein the output values ​​are a sequence of analog values ​​delivered from the encoder to the decoder. 5. An unpacker for receiving a digital video signal from the system-on-chip and generating the at least one media signal. 2. The device of embodiment 1, further comprising: 6. The apparatus of embodiment 1, wherein the at least one media signal is a plurality of media signals that are R, G, B signals. 7. The apparatus of embodiment 1, wherein the line buffer controller receives three media signals, R, G, and B, stores the samples in the line buffer, and delivers the subset of the samples to the DAC. 8. The apparatus of embodiment 2, wherein the integrated circuit is located within about 10 cm of the system-on-chip. 9. A device in which a timing controller is integrated with an encoder, a line buffer controller for receiving at least one media signal of digital samples originating from a system-on-chip of a display set; a line buffer in communication with said line buffer controller and arranged to store said lines of samples; at least one encoder for inputting a subset of said digital samples and outputting a sequence of digital output values; a DAC that receives said sequence of digital output values ​​and outputs a sequence of analog output values ​​presented to an electromagnetic path corresponding to said at least one encoder; a gate driver controller configured to receive a framing flag from said line buffer controller and output a gate driver control signal to a gate driver of said display set; 13. An apparatus comprising: 10. The device of embodiment 9, integrated within a single integrated circuit of the display set. 11. The apparatus of embodiment 9, wherein the analog output values ​​are delivered over the electromagnetic path to at least one corresponding decoder associated with a source driver of the display set. 12. The apparatus of embodiment 11, wherein the output values ​​are a sequence of analog values ​​delivered from the encoder to the decoder. 13. An unpacker for receiving a digital video signal from the system-on-chip and generating the at least one media signal. 10. The device of embodiment 9, further comprising: 14. The apparatus of embodiment 9, wherein the at least one media signal is a plurality of media signals that are R, G, B signals. 15. The apparatus of embodiment 9, wherein the line buffer controller receives three media signals, R, G, and B, stores the samples in the line buffer, and delivers the subset of the samples to the DAC. 16. The apparatus of embodiment 10, wherein the integrated circuit is located within about 10 cm of the system-on-chip. 17. A device integrating a timing controller and an encoder together with a system-on-chip of a display set, comprising: a line buffer controller for receiving at least one media signal of digital samples originating from the system-on-chip, the timing controller, the encoder and the system-on-chip being integrated in an integrated circuit; a line buffer in communication with said line buffer controller and arranged to store said lines of digital samples; at least one DAC that receives a subset of said lines of said digital samples and outputs a subset of said analog samples; at least one encoder for encoding the output subset of analog samples from the at least one DAC to output a sequence of analog output values ​​presented to an electromagnetic path corresponding to the at least one encoder; a gate driver controller configured to receive a framing flag from said line buffer controller and output a gate driver control signal to a gate driver of said display set; 13. An apparatus comprising: 18. A device integrating a timing controller and an encoder together with a system-on-chip of a display set, comprising: a line buffer controller for receiving at least one media signal of digital samples originating from the system-on-chip, the timing controller, the encoder and the system-on-chip being integrated in an integrated circuit; a line buffer in communication with said line buffer controller and arranged to store said lines of samples; at least one encoder for inputting a subset of said digital samples and outputting a sequence of digital output values; a DAC that receives said sequence of digital output values ​​and outputs a sequence of analog output values ​​presented to an electromagnetic path corresponding to said at least one encoder; a gate driver controller configured to receive a framing flag from said line buffer controller and output a gate driver control signal to a gate driver of said display set; 13. An apparatus comprising:

[0147] Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that several variations and modifications can be practiced within the scope of the appended claims. Accordingly, the described embodiments should be considered as illustrative and not restrictive, and the present invention should not be limited to the details set forth herein, but should be defined by the full scope of the following claims and their equivalents.

Claims

1. An apparatus in which a timing controller is integrated with a transmitter, comprising: at least one receiver arranged to receive a plurality of streams of digital video samples originating from a system-on-chip of a display set; a distributor arranged to distribute the digital video samples of the stream to a plurality of input vectors according to a predetermined arrangement; a plurality of digital-to-analog converters (DACs) for each input vector for parallel conversion of the digital image samples of each input vector into analog image samples; an encoder for each input vector, encoding the analog video samples of that input vector into a sequence of analog values, the encoder being arranged to transmit the sequence of analog values ​​to a display of the display set via an electromagnetic path corresponding to that encoder; a gate driver controller configured to output gate driver control signals to gate drivers of the displays of the display set; 13. An apparatus comprising:

2. The device of claim 1 , integrated within a single integrated circuit of the display set.

3. 2. The apparatus of claim 1, wherein the sequence of analog values ​​of each of the encoders is delivered to a corresponding decoder of a source driver of the display set.

4. 2. The apparatus of claim 1, further comprising a line buffer arranged to receive the digital video samples of the stream, the distributor distributing the digital video samples from the line buffer to the input vector.

5. The apparatus of claim 1 , located within about 10 cm of the system-on-chip.

6. 2. The apparatus of claim 1, wherein the gate driver controller is further configured to receive a framing flag originating from an unpacker and to output the gate driver control signals based on the framing flag.

7. The apparatus of claim 6 , wherein the unpacker receives a digital video signal from the system-on-chip and generates the multiple streams of digital video samples.

8. 2. The apparatus of claim 1, wherein the distributor inputs the digital video samples of the stream at a first clock frequency and outputs the input vector to the DAC of the input vector at a second clock frequency that is slower than the first clock frequency, thus affecting clock domain crossing.

9. 2. The apparatus of claim 1, wherein each input vector has a length N and each encoder encodes its corresponding input vector of N analog video samples into a sequence of L analog values ​​by reference to a predetermined code set of N mutually orthogonal codes, each code having a length L, each of said codes being used to encode one of the N analog video samples.

10. 2. The apparatus of claim 1, wherein the sequence of multiple analog values ​​of each of the encoders is multiplexed with a source driver of the display.

11. 2. The device of claim 1, wherein the system-on-chip (SoC) is integrated with the timing controller and the transmitter within the device, the SoC receives a digital video signal from outside the display set, and the stream of digital video samples is derived from the digital video signal.

12. 10. The apparatus of claim 9, wherein L > N > 2.

13. 10. The apparatus of claim 9, wherein N>L≧2.

14. 2. The apparatus of claim 1, wherein the display includes at least one source driver arranged to receive the sequence of analog values ​​from each of the encoders, decode the sequence of analog values ​​to generate a plurality of analog samples, and output them at an output of the source driver, whereby the stream of digital video samples is displayed on the display of the display set.

15. An apparatus in which a timing controller is integrated with a transmitter, comprising: at least one receiver arranged to receive a plurality of streams of digital video samples originating from a system-on-chip of a display set; a distributor arranged to distribute the digital video samples of the stream to a plurality of input vectors according to a predetermined arrangement; an encoder for each input vector arranged to encode the digital image samples of said input vector into a sequence of digital values; a digital-to-analog converter (DAC) for each encoder that converts the sequence of digital values ​​into a sequence of analog values ​​that are transmitted to a display of the display set via an electromagnetic path corresponding to each encoder; a gate driver controller configured to output gate driver control signals to gate drivers of the displays of the display set; 13. An apparatus comprising:

16. 16. The device of claim 15, integrated within a single integrated circuit of the display set.

17. 16. The apparatus of claim 15, wherein the sequence of analog values ​​of each of the encoders is delivered to a corresponding decoder of a source driver of the display set.

18. 16. The apparatus of claim 15, further comprising a line buffer arranged to receive the digital video samples of the stream, the distributor distributing the digital video samples from the line buffer to the input vector.

19. The apparatus of claim 15 , located within about 10 cm of the system-on-chip.

20. 16. The apparatus of claim 15, wherein the gate driver controller is further configured to receive a framing flag originating from an unpacker, and to output the gate driver control signals based on the framing flag.

21. 21. The apparatus of claim 20, wherein the unpacker receives a digital video signal from the system-on-chip and generates the multiple streams of digital video samples.

22. 16. The apparatus of claim 15, wherein the distributor inputs the digital video samples of the stream at a first clock frequency and outputs the input vectors to the encoder at a second clock frequency that is slower than the first clock frequency, thus affecting clock domain crossings.

23. 16. The apparatus of claim 15, wherein each input vector has a length N and each encoder encodes its corresponding input vector of N digital video samples into a sequence of L digital values ​​by reference to a predetermined code set of N mutually orthogonal codes, each code having a length L, each of said codes being used to encode one of the N digital video samples.

24. 16. The apparatus of claim 15, wherein the sequence of analog values ​​of each of the encoders is multiplexed with a source driver of the display.

25. 16. The device of claim 15, wherein the system-on-chip (SoC) is integrated with the timing controller and the transmitter within the device, the SoC receives a digital video signal from outside the display set, and the stream of digital video samples is derived from the digital video signal.

26. 24. The apparatus of claim 23, wherein L > N > 2.

27. 24. The apparatus of claim 23, wherein N>L>2.

28. 16. The apparatus of claim 15, wherein the display includes at least one source driver arranged to receive the sequence of analog values ​​from each of the encoders and decode the sequence of analog values ​​to generate a plurality of analog samples to output at an output of the source driver, whereby the stream of digital video samples is displayed on the display of the display set.

29. A device integrating a DDIC-TCON (Display Driver Integrated Circuit - Timing Controller) with a transmitter, comprising: at least one receiver arranged to receive at least one stream of digital video samples originating from a mobile system-on-chip of a mobile telephone; a distributor arranged to distribute said digital video samples of said at least one stream to at least one input vector according to a predetermined arrangement; a digital-to-analog converter (DAC) for parallel converting the digital image samples of the at least one input vector into analog image samples; at least one encoder arranged to encode the analog video samples into a sequence of analog values ​​and transmit the sequence of analog values ​​via an electromagnetic path to a display panel of the mobile phone; a gate driver controller configured to output gate driver control signals to a gate driver of the display panel of the mobile phone; 13. An apparatus comprising:

30. 30. The device of claim 29, integrated within a single integrated circuit of the mobile phone.

31. 30. The apparatus of claim 29, wherein the sequence of analog values ​​is delivered to a corresponding decoder of a source driver of the mobile phone.

32. 30. The apparatus of claim 29, further comprising a line buffer disposed to receive the digital video samples, the distributor distributing the digital video samples from the line buffer to the input vector.

33. 30. The apparatus of claim 29, located within about 2 cm of the system-on-chip.

34. 30. The apparatus of claim 29, wherein the gate driver controller is further configured to receive a framing flag originating from an unpacker, and to output the gate driver control signals based on the framing flag.

35. 35. The apparatus of claim 34, wherein the unpacker receives a digital video signal from the system-on-chip and generates the at least one stream of digital video samples.

36. 30. The apparatus of claim 29, wherein the distributor inputs the digital video samples at a first clock frequency and outputs the input vector to the DAC at a second clock frequency that is slower than the first clock frequency, thus affecting clock domain crossing.

37. 30. The apparatus of claim 29, wherein the input vector has a length N, and wherein the encoder encodes the input vector of N analog video samples into a sequence of L analog values ​​by reference to a predetermined code set of N mutually orthogonal codes, each having a length L, each of the codes being used to encode one of the N analog video samples.

38. 38. The apparatus of claim 37, wherein L > N > 2.

39. 38. The apparatus of claim 37, wherein N>L≧2.

40. 30. The apparatus of claim 29, wherein the display panel includes a source driver arranged to receive the sequence of analog values ​​from each of the encoders and decode the sequence of analog values ​​to generate a plurality of analog samples to output at an output of the source driver, whereby the stream of digital video samples is displayed on the display panel of the mobile phone.

41. A device integrating a DDIC-TCON (Display Driver Integrated Circuit - Timing Controller) with a transmitter, comprising: at least one receiver arranged to receive at least one stream of digital video samples originating from a mobile system-on-chip of a mobile telephone; a distributor arranged to distribute said digital video samples of said at least one stream to at least one input vector according to a predetermined arrangement; at least one encoder arranged to encode the digital image samples of the input vector into a sequence of digital values; a digital-to-analog converter (DAC) for converting the sequence of digital values ​​into a sequence of analog values ​​that are transmitted via an electromagnetic path to a display panel of the mobile phone; a gate driver controller configured to output gate driver control signals to a gate driver of the display panel of the mobile phone; 13. An apparatus comprising:

42. 42. The device of claim 41, integrated within a single integrated circuit of the display set.

43. 42. The apparatus of claim 41, wherein the sequence of analog values ​​is delivered to a corresponding decoder of a source driver of the mobile phone.

44. 42. The apparatus of claim 41, further comprising a line buffer disposed to receive the digital video samples, the distributor distributing the digital video samples from the line buffer to the input vector.

45. 42. The apparatus of claim 41, located within about 2 cm of the system-on-chip.

46. 42. The apparatus of claim 41, wherein the gate driver controller is further configured to receive a framing flag originating from an unpacker, and to output the gate driver control signals based on the framing flag.

47. 47. The apparatus of claim 46, wherein the unpacker receives a digital video signal from the system-on-chip and produces the at least one stream of digital video samples.

48. 42. The apparatus of claim 41, wherein the distributor inputs the digital video samples at a first clock frequency and outputs the input vectors to the encoder at a second clock frequency that is slower than the first clock frequency, thus affecting clock domain crossings.

49. 42. The apparatus of claim 41 , wherein the input vector has a length N, and wherein the encoder encodes the input vector of N digital video samples into a sequence of L digital values ​​by reference to a predetermined code set of N mutually orthogonal codes, each of length L, each of the codes being used to encode one of the N digital video samples.

50. 50. The apparatus of claim 49, wherein L > N > 2.

51. 50. The apparatus of claim 49, wherein N>L≧2.

52. 42. The apparatus of claim 41, wherein the display panel includes a source driver arranged to receive the sequence of analog values ​​from each of the encoders and decode the sequence of analog values ​​to generate a plurality of analog samples to output at an output of the source driver, whereby the stream of digital video samples is displayed on the display panel of the mobile phone.

53. 1. A system for conveying video to a display panel of a display set, comprising: a transmitter integrated with a timing controller for receiving a plurality of streams of digital image samples originating from a system-on-chip of the display set, the transmitter including a gate driver controller arranged to encode the digital image samples into a plurality of sequences of analog values ​​and transmit the plurality of sequences of analog values ​​to the display panel via one electromagnetic path per sequence of analog values, the transmitter arranged to output gate driver control signals to a gate driver of the display panel; at least one source driver arranged to receive the sequence of analog values ​​from the transmitter and to decode each of the sequence of analog values ​​to generate a plurality of analog samples to output at an output of the source driver, so that the stream of digital video samples can be displayed on the display panel of the display set; Including, the system.

54. The transmitter, at least one digital-to-analog converter (DAC) for converting the digital video samples to analog video samples prior to the encoding, the encoding being analog encoding; 54. The system of claim 53, further comprising:

55. 54. The system of claim 53, wherein the encoding is digital encoding, and the transmitter further comprises at least one digital-to-analog converter (DAC) for converting an output of the encoding into the sequence of the plurality of analog values.

56. The transmitter, a distributor arranged to distribute the digital video samples of the stream to a plurality of input vectors according to a predetermined arrangement; at least one digital-to-analog converter (DAC) for each input vector, for converting the digital image samples of each input vector into analog image samples; an encoder for each input vector arranged to encode the analog video samples of the respective input vector into the sequence of analog values ​​and to transmit the sequence of analog values ​​to the display panel via an electromagnetic path corresponding to the respective encoder; 54. The system of claim 53, further comprising:

57. The transmitter, a distributor arranged to distribute the digital video samples of the stream to a plurality of input vectors according to a predetermined arrangement; an encoder for each input vector arranged to encode the digital image samples of said input vector into a sequence of digital values; a digital-to-analog converter (DAC) for each encoder that converts the sequence of digital values ​​to the sequence of analog values ​​that are transmitted to the display panel via an electromagnetic path corresponding to each encoder; 54. The system of claim 53, further comprising:

58. 1. A system for delivering video to a display panel of a mobile phone, comprising: a transmitter integrated with a timing controller for receiving a plurality of streams of digital video samples originating from a system-on-chip of the mobile phone, the transmitter including: a gate driver controller arranged to encode the digital video samples into a plurality of sequences of analog values ​​and transmit the plurality of sequences of analog values ​​to the display panel via one electromagnetic path per sequence of analog values; and an output gate driver control signal to a gate driver of the display panel; a source driver arranged to receive the sequence of analog values ​​from the transmitter and to decode each of the sequence of analog values ​​to generate a plurality of analog samples to output at an output of the source driver, whereby the stream of digital video samples can be displayed on the display panel of the mobile phone; Including, the system.

59. The transmitter, at least one digital-to-analog converter (DAC) for converting the digital video samples to analog video samples prior to the encoding, the encoding being analog encoding; 60. The system of claim 58, further comprising:

60. 60. The system of claim 58, wherein the encoding is digital encoding, and the transmitter further comprises at least one digital-to-analog converter (DAC) for converting an output of the encoding into the sequence of the plurality of analog values.

61. The transmitter, a distributor arranged to distribute the digital video samples of the stream to a plurality of input vectors according to a predetermined arrangement; at least one digital-to-analog converter (DAC) for each input vector, for converting the digital image samples of each input vector into analog image samples; an encoder for each input vector arranged to encode the analog video samples of each said input vector into the sequence of analog values ​​and to transmit the sequence of analog values ​​to the display panel via an electromagnetic path corresponding to each said encoder; 60. The system of claim 58, further comprising:

62. The transmitter, a distributor arranged to distribute the digital video samples of the stream to a plurality of input vectors according to a predetermined arrangement; an encoder for each input vector arranged to encode the digital image samples of said input vector into a sequence of digital values; a digital-to-analog converter (DAC) for each encoder that converts the sequence of digital values ​​to the sequence of analog values ​​that are transmitted to the display panel via an electromagnetic path corresponding to each encoder; 60. The system of claim 58, further comprising:

Images