Artificial neural network with analog and digital arrays

Abstract

A number of examples are described for providing an artificial neural network system with analog and digital arrays. In certain examples, the analog and digital arrays are coupled to shared bit lines. In other examples, the analog and digital arrays are coupled to separate bit lines.

Description

[Technical field]

[0001] (Priority Claim) This application claims priority from U.S. Provisional Patent Application No. 63 / 304,485, entitled "Artificial Neural Network Comprising A Digital Information Array," filed on January 28, 2022, and U.S. Patent Application No. 17 / 721,254, entitled "Artificial Neural Network Comprising An Analog Array And A Digital Array," filed on April 14, 2022, which are incorporated by reference herein.

[0002] FIELD OF THEINVENTION Numerous examples of artificial neural networks with analog and digital arrays are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks typically contain layers of interconnected "neurons" that exchange messages between each other.

[0004] FIG. 1 shows an artificial neural network, where circles illustrate layers of inputs or neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. Typically, there are one or more hidden layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions individually or collectively based on the data they receive from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of suitable hardware technology. Indeed, practical neural networks rely on a very large number of synapses, which allows high connectivity between neurons, i.e., a very high degree of parallelization of computation. In principle, such complexity can be achieved by digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which mainly perform low-precision analog calculations and therefore consume much less energy. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses.

[0006] Applicant previously disclosed in U.S. Patent Application Publication No. 2017 / 0337466(A1), incorporated by reference, an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses. The non-volatile memory array operates as an analog neural memory and comprises non-volatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each of which includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate insulated and disposed above a first portion of the channel region, and a non-floating gate insulated and disposed above a second portion of the channel region. Each of the plurality of memory cells stores a weight value corresponding to a number of electrons in the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values ​​to generate the first plurality of outputs. <Non-volatile memory cells>

[0007] Non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 ​​("the '130 patent"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (controlling the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controlling the conductivity of the second portion of the channel region 18) and a second portion extending upwardly above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0008] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the wordline terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the wordline terminal 22 through the insulator between them.

[0009] The memory cell 210 is programmed by hot electron source side injection (SSI) (electrons are injected into the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. Electrons flow from the drain region 16 towards the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on and current flows through the channel region 18, which is sensed as the erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off and no (or very little) current flows through the channel region 18, which is sensed as the programmed or "0" state.

[0011] Table 1 shows typical voltage / current ranges that may be applied to the terminals of memory cell 210 to perform read, erase, and program operations. Table 1: Operation of the Flash Memory Cell 210 of FIG. 2 [Table 1]

[0012] Other split-gate memory cell configurations are known, as are other types of flash memory cells. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the Flash Memory Cell 310 of FIG. [Table 2]

[0014] Figure 4 shows another type of flash memory cell, a three-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase and read operations (where erasure occurs through the use of an erase gate) are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage is applied to the source line during a program operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 410 of FIG. [Table 3]

[0016] Figure 5 shows another type of flash memory cell, a stacked gate memory cell 510. The memory cell 510 is similar to the memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and the control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is done by FN tunneling of electrons from the FG to the substrate, and programming is done by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, by electrons flowing from the source region 14 towards the drain region 16, and by a read operation that is similar to the read operation of the memory cell 210 with a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of Flash Memory Cell 510 of FIG. [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stack-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable, bi-level or multi-level one-time programmable) and CeRAM (correlated electron ram).

[0019] In order to utilize a memory array containing one of the non-volatile memory cell types in an artificial neural network as described above, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, a continuous (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed from a fully erased state to a fully programmed state, and vice versa, independently and continuously with minimal disturbance to other memory cells. This means that the cell storage is effectively analog, or can at a minimum store one of a number of discrete values ​​(such as 16 or 64 different values), making every memory cell in the memory array very precisely and individually tunable, and making the memory array ideal for storage and for fine tuning adjustments to the synaptic weights of neural networks. <Neural network using non-volatile memory cell array>

[0021] 6 conceptually illustrates a non-limiting example of a neural network utilizing the present example non-volatile memory array. The example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can be implemented using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, each pixel with 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping filters (kernels) of 3x3 pixels, applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels depending on the model). Specifically, the values ​​of the nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and, after summing the outputs of the multiplication, a single output value is determined and given by the first synapse of CB1 to generate one pixel of the feature map of layer C1. The 3x3 filter is then shifted by one pixel to the right in the input layer S0 (i.e., adding a column of 3 pixels to the right and dropping a column of 3 pixels on the left), so that the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps of layer C1 until all feature maps of layer C1 have been calculated.

[0023] In this example, in layer C1, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input with a kernel, and thus each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that layers and arrays referred to herein are logical, not necessarily physical, i.e., arrays are not necessarily oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of 16 different synaptic weight sets applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first weight set shared by all scans used to generate this first map) can identify circular edges, and a second map (generated using a second weight set different from the first weight set) can identify square edges or the aspect ratio of a particular feature, etc.

[0024] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. The purpose of the pooling function P1 is to average nearby positions (or a max function can be used), e.g., to reduce edge position dependency, and to reduce data size before going to the next operation. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). The synapse CB2 going from layer S1 to layer C2 scans the maps in layer S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 connect to all maps in layer S2 through respective synapses in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e. all neurons in layer C3 connect to all neurons in layer S3. The output at S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0025] Each layer of the synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0026] FIG. 7 is a block diagram of an array that can be used for that purpose. A vector-by-matrix multiplication (VMM) array 32 contains non-volatile memory cells and is utilized as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in FIG. 6). Specifically, the VMM array 32 includes an array of non-volatile memory cells 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the non-volatile memory cell array 33. Inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the non-volatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, the non-volatile memory cell array 33 stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and adds them for each output line (source line or bit line) to generate an output that becomes the input to the next layer or the input to the last layer. With the non-volatile memory cell array 33 performing the multiplication and addition functions, the need for separate multiplication and addition logic is eliminated and in-memory computation is also more power efficient.

[0028] The outputs of the non-volatile memory cell array 33 are provided to a differential summer (such as a summing op-amp or summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of the positive and negative weights.

[0029] The summed output values ​​of the differential summers 38 are then fed to an activation function block 39 which rectifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The rectified output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in FIG. 6) and are then applied to the next synapse to generate the next feature map layer or the last layer. Thus, in this example, the non-volatile memory cell array 33 constitutes a number of synapses (receiving inputs from a previous layer of neurons or from an input layer such as an image database), and the summing op-amps 38 and the activation function block 39 constitute a number of neurons.

[0030] The inputs to the VMM array 32 of FIG. 7 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0031] FIG. 8 is a block diagram illustrating the use of multiple layers of VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 8, an input (denoted Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be a voltage or a current. The first layer input D / A conversion can be done by using a function or a look up table (LUT) that maps the input Inputx to the appropriate analog level of the matrix multiplier of input VMM array 32a. The input conversion can also be done by an analog to analog (A / A) converter to convert an external analog input to the mapped analog input to input VMM array 32a.

[0032] The output generated by the input VMM array 32a is then provided as input to the next VMM array (hidden level 1) 32b, which in turn generates an output that is provided as input to the input VMM array (hidden level 2) 32c, and so on. The various layers of the VMM array 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or the multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or the multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. The example shown in FIG. 8 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example, and that the system may instead include more than two hidden layers and more than two fully connected layers. <Vector Matrix Multiplication (VMM) Array>

[0033] 9 shows a neuron VMM array 900 that is particularly suited for the memory cells 310 shown in FIG. 3 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0034] In the VMM array 900, control gate lines such as control gate line 903 run vertically (so that row-wise reference array 902 is orthogonal to control gate line 903) and erase gate lines such as erase gate line 904 run horizontally. Here, inputs to the VMM array 900 are provided on the control gate lines (CG0, CG1, CG2, CG3) and outputs of the VMM array 900 appear on the source lines (SL0, SL1). In one example, only the even rows are used, and in another example, only the odd rows are used. The current in each source line (SL0, SL1 respectively) performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0035] As described herein for neural networks, the non-volatile memory cells of VMM array 900, namely memory cells 310 of VMM array 900, are operationally configured to operate in the sub-threshold region.

[0036] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion (sub-threshold region) as follows: Ids=Io * e (Vg-Vth) / nVt =w * Io * e (Vg) / nVt In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, and Vt is the thermal voltage = k * where T / q, k is the Boltzmann constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) * u * Cox * (n-1) * Vt 2 where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV-log converter that uses memory cells (such as reference or peripheral memory cells) or transistors to convert the input current to an input voltage: Vg=n * Vt * log[Ids / wp * Io] where wp is the w of the reference or periphery memory cell.

[0038] For a memory array used as a vector matrix multiplier VMM array with current inputs, the output current is: Iout=wa * Io * e (Vg) / nVt , i.e. Iout = (wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt where wa=w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cells and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of a transistor is a function of the substrate body bias voltage, which is represented as Vsb, and can be modulated to compensate for various conditions at such temperature. The threshold voltage Vth can be expressed as:

number

[0039] The word line or control gate can be used as the input of the memory cell for an input voltage.

[0040] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=Beta * (Vgs-Vth) * Vds; beta = u * Cox * Wt / L W = α(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0041] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0042] For an IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert the input and output currents to input and output voltages.

[0043] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2 * beta * (Vgs-Vth) 2 , beta = u * Cox * Wt / L Wα(Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0044] The word lines, control gates, or erase gates can be used as inputs for memory cells operating in the saturation region, and the bit lines or source lines can be used as outputs for output neurons.

[0045] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (subthreshold, linear, or saturation) for each layer or layers of a neural network.

[0046] Other examples for the VMM array 32 of Figure 7 are described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] FIG. 10 shows a neuron VMM array 1000, which is particularly suitable for the memory cells 210 shown in FIG. 2 and is used as a synapse between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001 of a first non-volatile reference memory cell, and a reference array 1002 of a second non-volatile reference memory cell. The reference arrays 1001 and 1002 arranged in the columns of the array function to convert the current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1014 (partially shown) with the current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference mini-array matrix (not shown).

[0048] The memory array 1003 serves two purposes. First, it stores the weights in each memory cell that are used by the VMM array 1000. Second, it effectively multiplies the weights stored in it by the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1001 and 1002 convert to input voltages and provide to the word lines WL0, WL1, WL2, and WL3) and then adds all the results (memory cell currents) to generate an output for each bit line (BL0-BLN), which is the input to the next layer or the input to the last layer. By performing the multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current in each of the bit lines BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents for the VMM array 1000. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the operations of read, erase, and program. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] FIG. 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of non-volatile memory cells, a reference array 1101 of first non-volatile reference memory cells, and a reference array 1102 of second non-volatile reference memory cells. The reference arrays 1101 and 1102 run in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines run vertically in the VMM array 1100. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3) and outputs appear on the source lines (SL0, SL1) during a read operation. The current of each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents for VMM array 1100. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in FIG. 11 [Table 6]

[0052] 12 shows a neuron VMM array 1200, which is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of a first non-volatile reference memory cell, and a reference array 1202 of a second non-volatile reference memory cell. The reference arrays 1201 and 1202 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1212 (partially shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Multiplexer 1212 includes a corresponding multiplexer 1205 and cascoding transistor 1204 to ensure a constant voltage on each bit line (e.g., BLR0) of the first and second non-volatile reference memory cells during each read operation. The reference cells are tuned to a target reference level.

[0053] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200. Second, it effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert to input voltages and provide to the control gates (CG0, CG1, CG2, and CG3)) and then adds all the results (cell currents) to produce an output that appears on BL0-BLN and is the input to the next layer or the input to the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also power efficient, where the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current in each bit line is a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0054] VMM array 1200 implements one-way tuning of non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is added to the floating gate (e.g., an incorrect value is stored in the cell), the cell is erased and the series of partial programming operations starts over. As shown, two rows that share the same erase gate (e.g., EG0 or EG1) are erased together (also called a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents of the VMM array 1200. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of the VMM array 1200 of FIG. 12 [Table 7]

[0056] FIG. 13 shows a neuron VMM array 1300, which is particularly suited for the memory cells 310 shown in FIG. 3 and is utilized as part of synapses and neurons between the input layer and the next layer. The VMM array 1300 comprises a memory array 1303 of non-volatile memory cells, a reference array 1301 or a first non-volatile reference memory cell, and a reference array 1302 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 run vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 run horizontally. The VMM array 1300 is similar to the VMM array 1400, except that the VMM array 1300 implements bidirectional tuning, and each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of individual EG lines. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2 and BLR3 into control gate voltages CG0, CG1, CG2 and CG3 (through the action of diode-connected reference cells via multiplexer 1314) which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each of which sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents for VMM array 1300. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1300 in FIG. 13 [Table 8]

[0058] 22 shows a neuron VMM array 2200 that is particularly suited for the memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. The VMM array 2200 includes inputs INPUT0... INPUT N are bit lines BL0, ...BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated at source lines SL0, SL1, SL2, and SL3, respectively.

[0059] 23 shows a neuron VMM array 2300 that is particularly suited for memory cells 210 shown in FIG. 2 and is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ...OUTPUT N are bit lines BL0, ..., BL N is generated.

[0060] 24 shows a neuron VMM array 2400 that is particularly suited for the memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received at output OUTPUT0, ... OUTPUT N are bit lines BL0, ..., BL N is generated.

[0061] 25 shows a neuron VMM array 2500 that is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received at output OUTPUT0, ... OUTPUTN are bit lines BL0, ..., BL N is generated.

[0062] 26 shows a neuron VMM array 2600 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0、 ..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] 27 shows a neuron VMM array 2700 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT N are bit lines BL0, ..., BL N , 2701-(N-1) and 2701-N, which are coupled to the gates of the bit line control gates 2701-1, 2701-2, ..., 2701-(N-1) and 2701-N. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] 28 shows a neuron VMM array 2800 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0065] 29 shows a neuron VMM array 2900 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N , and each source line SL i is coupled to the source lines of all memory cells in column i.

[0066] 30 shows a neuron VMM array 3000 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M OUTPUT0, ..., OUTPUT N are vertical bit lines BL0, ..., BL N , and each bit line BL i is coupled to the bit lines of all memory cells in column i. <Long and short-term memory>

[0067] The prior art includes a concept called long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any given period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the period of time that information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] FIG. 14 illustrates an exemplary LSTM 1400. The LSTM 1400 in this example includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 1402 receives an input vector x1, an output vector (hidden state) h0 from cell 1401, and a cell state c0 from cell 1401, and generates an output vector h1 and a cell state vector c1. Cell 1403 receives an input vector x2, an output vector (hidden state) h1 from cell 1402, and a cell state c1 from cell 1402, and generates an output vector h2 and a cell state vector c2. Cell 1404 receives an input vector x3, an output vector (hidden state) h2 from cell 1403, and a cell state c2 from cell 1403, and generates an output vector h3. Additional cells can be used, the LSTM with four cells is just an example.

[0069] Figure 15 shows an example implementation of an LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. The LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and adder device 1509 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0071] FIG. 16 shows an example of an implementation of the LSTM cell 1500, the LSTM cell 1600. For the convenience of the reader, the same numbering scheme from the LSTM cell 1500 is used in the LSTM cell 1600. The sigmoid function devices 1501, 1502, and 1503, and the tanh device 1504 each include multiple VMM arrays 1601 and activation function blocks 1602. Thus, the VMM array proves to be particularly useful in LSTM cells used in certain neural network systems. The multiplier devices 1506, 1507, and 1508, and the adder device 1509 are implemented in a digital or analog manner. The activation function block 1602 can be implemented in a digital or analog manner.

[0072] An alternative example of LSTM cell 1600 (and another example of one implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-multiplexed manner. LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adder device 1708 for adding two vectors, a tanh device 1505 (which includes activation function block 1702), a register 1707 for storing the value i(t) as it is output from sigmoid function block 1702, and a register 1708 for storing the value f(t). * a register 1704 for storing c(t-1) as that value is output from the multiplier device 1703 via a multiplexer 1710; * A register 1705 for storing u(t) as its value is output from the multiplier device 1703 via a multiplexer 1710; * It includes a register 1706 for storing {tilde over (c)}(t) as its value is output from the multiplier device 1703 via a multiplexer 1710, and a multiplexer 1709.

[0073] Whereas LSTM cell 1600 includes multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 requires less space than LSTM cell 1600 because LSTM cell 1700 requires ¼ the space for the VMMs and activation function blocks compared to LSTM cell 1600.

[0074] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the example described below reduces the circuitry required outside the VMM array itself. <Gated Recurrent Unit>

[0075] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are the gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] 18 illustrates an exemplary GRU 1800. The GRU 1800 in this example includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and generates output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and generates output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and generates output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells may be used, and a GRU with four cells is merely an example.

[0077] FIG. 19 illustrates an example implementation of a GRU cell 1900 that may be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to the output vector h(t-1) and components from the input vector x(t). GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, a number of multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding the two vectors, and a complementary device 1908 for subtracting the input from 1 to generate an output.

[0078] FIG. 20 shows a GRU cell 2000, which is an example of one implementation of the GRU cell 1900. For the convenience of the reader, the same numbering method from the GRU cell 1900 is used in the GRU cell 2000. As can be seen from FIG. 20, the sigmoid function devices 1901 and 1902 and the tanh device 1903 each include a plurality of VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that the VMM array is particularly used in the GRU cell used in a specific neural network system. The multiplier devices 1904, 1905, 1906, the adder device 1907, and the complementary device 1908 are implemented in a digital or analog manner. The activation function block 2002 can be implemented in a digital or analog manner.

[0079] An alternative example of GRU cell 2000 (and another example of one implementation of GRU cell 1900) is shown in FIG. 21. In FIG. 21, GRU cell 2100 utilizes a VMM array 2101 and an activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much each component of the input vector contributes to the output vector. In FIG. 21, sigmoid function devices 1901 and 1902, and tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-multiplexed manner. GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors together, an adder device 2105 for adding two vectors together, a complementary device 2109 for subtracting the input from 1 to generate the output, a multiplexer 2104, and a value h(t-1) * A register 2106 for holding r(t) as its value is output from the multiplier device 2103 via multiplexer 2104, and a value h(t-1) * A register 2107 for holding z(t) as its value is output from the multiplier device 2103 via multiplexer 2104, and a register 2108 for holding the value ĥ(t) *and a register 2108 for holding (1-z((t)) as its value is output from the multiplier device 2103 via multiplexer 2104.

[0080] Whereas GRU cell 2000 includes multiple sets of VMM arrays 2001 and activation function blocks 2002, GRU cell 2100 includes only one set of VMM arrays 2101 and activation function blocks 2102, which are used to represent multiple tiers in the example of GRU cell 2100. GRU cell 2100 requires less space than GRU cell 2000 because GRU cell 2100 requires one-third the space for the VMM and activation function blocks compared to GRU cell 2000.

[0081] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the example described below reduces the circuitry required outside the VMM array itself.

[0082] The input to the VMM array can be an analog level, a binary level, a pulse, a time modulated pulse, or a digital bit (in this case a DAC is required to convert the digital bit to the appropriate input analog level), and the output can be an analog level, a binary level, a timing pulse, a pulse, or a digital bit (in this case an output ADC is required to convert the output analog level to a digital bit).

[0083] In general, for each memory cell in the VMM array, each weight W can be implemented by a single memory cell, or by a differential cell, or by two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are required to implement the weight W as the average of two cells.

[0084] FIG. 31 illustrates a VMM system 3100. In some examples, the weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). In the VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines that connect to memory cells that will store a positive weight W+, and the other half of the bit lines are designated as W- lines, i.e., bit lines that connect to memory cells that implement a negative weight W-. The W- lines are interspersed alternately among the W+ lines. The subtraction operation is performed by summing circuits, such as summing circuits 3101 and 3102, that receive currents from the W+ and W- lines. The output of the W+ lines and the output of the W- lines are combined together to effectively give W=W+-W- for each pair of (W+, W-) cells of every pair of (W+, W-) lines. Although described thus far with respect to W- lines interspersed alternatingly among W+ lines, in other examples the W+ and W- lines may be arbitrarily positioned anywhere within the array.

[0085] 32 shows another example. In a VMM system 3210, the positive weights W+ are implemented in a first array 3211 and the negative weights W− are implemented in a second array 3212 that is separate from the first array, and the resulting weights are appropriately combined together by a summing circuit 3213.

[0086] FIG. 33 shows a VMM system 3300. The weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). The VMM system 3300 comprises an array 3301 and an array 3302. Half of the bit lines in each of the arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines that connect to memory cells that store a positive weight W+, and the other half of the bit lines in each of the arrays 3301 and 3302 are designated as W- lines, i.e., bit lines that connect to memory cells that implement a negative weight W-. The W- lines are interspersed alternately among the W+ lines. Subtraction operations are performed by adder circuits, such as adder circuits 3303, 3304, 3305, and 3306, that receive current from the W+ and W- lines. The output of the W+ line and the output of the W- line from each array 3301, 3302, respectively, are combined together to effectively give W=W+-W- for each pair of (W+,W-) cells of every pair of (W+,W-) lines. In addition, the W values ​​from each array 3301 and 3302 may be further combined via summing circuits 3307 and 3308, meaning that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, and the final result from summing circuits 3307 and 3308 is one of two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system can be erased and programmed to hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] FIG. 34 shows a prior art VMM system 3400 that includes two separate array blocks: an analog array block 3405 and a digital array block 3415. The analog array block 3405 includes an analog array 3401, a row decoder 3402, and a high voltage decoder 3403. The analog array 3401 stores one of N different analog values, as described above. The digital array block 3415 includes a digital array 3411, a row decoder 3412, and a high voltage decoder 3413. The digital array block 3415 can be used to store system data, configuration data, operating system data (operating system, OS), and other data for the operation of the VMM system 3400. For example, the digital array 3411 can store digital data such as user ID, trim bits, manufacturing information, security codes, OS codes, and other information used by the VMM system 3400. In another example, the VMM system 3400 may include a separate digital non-volatile memory macro or external chip.

[0089] Because the analog array 3401 stores analog values ​​(multi-level values), a precise range of currents (due to multi-level at desired low power) is applied to the bit lines during a read operation compared to a digital array 3411 read operation (where each cell stores either a "1" or a "0"). Differences in the current levels used during a read operation can cause undesirable results such as leakage from high current cells of the digital cells (necessary for high speed reads, which can affect the accuracy of the read operation), bias conditions (which are different for analog vs. digital levels), and other results.

[0090] What is needed is an improved architecture for providing analog and digital arrays in artificial neural network systems while reducing leakage and other undesirable results. Summary of the Invention

[0091] A number of examples are described for providing artificial neural network systems including analog and digital arrays.

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[0134] [Brief description of the drawings]

[0135] [Figure 1] FIG. 1 illustrates an artificial neural network. [Diagram 2] 1 shows a prior art split-gate flash memory cell. [Diagram 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4]1 illustrates another prior art split-gate flash memory cell. [Diagram 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 7] FIG. 1 is a block diagram illustrating a VMM system. [Figure 8] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems. [Figure 9] 2 illustrates another example of a VMM system. [Figure 10] 2 illustrates another example of a VMM system. [Figure 11] 2 illustrates another example of a VMM system. [Figure 12] 2 illustrates another example of a VMM system. [Figure 13] Another example of a VMM system is shown below. [Figure 14] 1 shows a prior art long-term and short-term memory system. [Figure 15] An exemplary cell for use in a long- and short-term memory system is shown. [Figure 16] 16 illustrates an example implementation of the cell of FIG. 15. [Figure 17] 16 illustrates another exemplary implementation of the cell of FIG. 15. [Figure 18] 1 shows a prior art gated recurrent unit system. [Figure 19] 1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 20] 20 illustrates an example implementation of the cell of FIG. 19. [Figure 21] 20 illustrates another exemplary implementation of the cell of FIG. 19. [Figure 22] 2 illustrates another example of a VMM system. [Figure 23] 2 illustrates another example of a VMM system. [Figure 24] 2 illustrates another example of a VMM system. [Diagram 25] 2 illustrates another example of a VMM system. [Figure 26] 2 illustrates another example of a VMM system. [Figure 27] 2 illustrates another example of a VMM system. [Figure 28] 2 illustrates another example of a VMM system. [Figure 29] 2 illustrates another example of a VMM system. [Diagram 30] 2 illustrates another example of a VMM system. [Diagram 31] 2 illustrates another example of a VMM system. [Diagram 32] 2 illustrates another example of a VMM system. [Diagram 33] 2 illustrates another example of a VMM system. [Diagram 34] 1 illustrates an example of a VMM system that includes a digital array. [Diagram 35] An example of a VMM system is shown. [Diagram 36] 1 illustrates an example of a VMM system that includes a digital array. [Figure 37] 1 illustrates an example of a VMM system that includes a digital array. [Figure 38] 38 illustrates an additional aspect for the VMM system of FIG. [Figure 39A] FIG. 37 shows an exemplary design for the VMM system. [Figure 39B] FIG. 37 shows an exemplary design for the VMM system. [Figure 39C] FIG. 37 shows an exemplary design for the VMM system. [Diagram 40] 1 illustrates an example of a VMM system that includes a digital array. [Diagram 41] 1 shows an example of a digital array. [Figure 42A] 1 shows a differential current-to-voltage converter. [Figure 42B] 1 shows a differential sequential address register analog-to-digital converter. [Diagram 43] 1 illustrates an exemplary read operation for an analog array and a digital array.

Best Mode for Carrying Out the Invention

[0136] The artificial neural network described in this specification utilizes a combination of CMOS technology and a non-volatile memory array. <Overview of the VMM System>

[0137] FIG. 35 shows a block diagram of a VMM system 3500. The VMM system 3500 includes a VMM array 3501 including analog memory cells and digital memory cells, a row decoder 3502, a high-voltage decoder 3503, a column decoder 3504, a bit-line driver 3505, an input circuit 3506, an output circuit 3507, control logic 3508, and a bias generator 3509. The VMM system 3500 further includes a high-voltage generation block 3510 including a charge pump 3511, a charge pump regulator 3512, and a high-voltage analog precision level generator 3513. The VMM system 3500 further includes a (program / erase, or weight tuning) algorithm controller 3514, an analog circuit 3515, a control engine 3516 (which can perform functions such as arithmetic functions, startup functions, embedded microcontroller logic, etc., without limitation), and test control logic 3517. The systems and methods described below can be implemented in the VMM system 3500.

[0138] The input circuit 3506 may include circuits such as a digital to analog converter (DAC), a digital to pulses converter (DPC), an analog to analog converter (AAC), a pulse to analog level converter (PAC), or any other type of converter. The input circuit 3506 may implement one or more of normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3506 may implement a temperature compensation function for the input levels. The input circuit 3506 may implement an activation function such as ReLU or sigmoid. The output circuit 3507 may include circuits such as an ADC (analog to digital converter), an AAC (analog to analog converter, such as a current-to-voltage converter, a logarithmic converter), an APC (analog to pulse converter), or any other type of converter. The output circuit 3507 may implement an activation function such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 3507 may implement one or more of statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) of the neuron output. The output circuit 3507 may implement a temperature compensation function for the neuron output or the array output (such as the bit line output) to keep the power consumption of the array approximately constant, or to increase the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same.

[0139] As mentioned above, a neural network may include many different layers, and within each layer many calculations may be performed that require weight values ​​stored in one or more arrays within that layer. It may be appreciated that some layers will be used more than other layers, and that such layers are more important to the overall accuracy of the neural network based on their high frequency of use.

[0140] 36 shows a VMM system 3600 comprising an analog array 3601, a row decoder 3602, a high voltage decoder 3603, a digital array 3604, a row decoder 3605, and a high voltage decoder 3606. The analog array 3601 and the digital array 3604 share the same diffusion and metal interconnect bit lines. Unlike the prior art, the digital array 3604 has its own row decoder (row decoder 3605) and its own high voltage decoder (3606), which allows a first set of voltages and a second set of voltages to be applied simultaneously to the analog array 3601 and the digital array 3604, respectively. Optionally, the analog array 3601 and the digital array 3604 are fabricated on the same semiconductor die.

[0141] The digital array 3604 may optionally include a first array, which may be referred to as a user data array 3607 and includes rows for storing digital data (such as computer user data or operating system code) that is stored and retrieved by an external source, and a second array, which may be referred to as a system data array 3608 and includes rows for storing digital system data, i.e., data used by the VMM system 3600 itself and not stored and retrieved by an external source, which may also be referred to as a digital non-volatile register (NVR) or information row or array. Examples of data that may be stored in the system data array 3608 include user IDs, trim bits, configuration bits, manufacturing information, security codes, passwords, lock bits, and other system data. The performance of the system data array 3608 may be relaxed compared to the user data array 3607.

[0142] For example, the contents of the system data array 3608 may be read once at power-up or the beginning of system operation, and then not read during operation. As another example, the contents of the system data array 3608 may be erased or programmed only a few times throughout its life usage. Thus, read, program, or erase operations of the system data array 3608 can be performed at a slower speed than that of the user data array without much performance loss, since the system data array is used very infrequently. This difference in speed may be implemented in the VMM system 3600, for example, to conserve power when operating on the system data array 3608.

[0143] As another example, non-volatile memory cells have a characteristic called endurance, which refers to the number of times a non-volatile memory cell can be programmed or erased before it degrades to the point where it is no longer reliable or usable. Thus, because system data array 3608 is used much less during operation than user data array 3607, system data array 3608 may be provided with non-volatile memory cells of lower endurance than the non-volatile memory cells of user data array 3607.

[0144] Table 9 shows exemplary operating voltages used in VMM system 3600, where CG-main, EG-main, BL-main, and SL-main are a first set of voltages applied, respectively, to the control gate terminals, erase gate terminals, bit line terminals, and source line terminals of one or more memory cells in analog array 3601 by row decoder 3702 and high voltage decoder 3703, and CG-DIG, EG-DIG, BL-DIG, and SL-DIG are a second set of voltages applied, respectively, to the control gate terminals, erase gate terminals, bit line terminals, and source line terminals of one or more cells in digital array 3604 by row decoder 3705 and high voltage decoder 3706. Table 9: Operating voltages for the VMM system 3600 of FIG. [Table 9]

[0145] The ability to apply different sets of voltages to memory cells in analog array 3601 and memory cells in digital array 3604 enhances performance during neural read operations in analog array 3601 and digital read operations in digital array 3604, such as reduced leakage during read neural operations (caused by the ability to block high currents in digital cells that share the same bit lines as the analog cells) and higher speeds for digital cells due to higher current levels.

[0146] FIG. 37 shows an example VMM system 3700 comprising an analog array 3701, a row decoder 3702, a high voltage decoder 3703, a digital array 3704 (optionally comprising a user data array 3707 and a system data array 3708), a row decoder 3705, and a high voltage decoder 3706. VMM system 3700 is similar to VMM system 3600, except that the bit lines coupled to analog array 3701 are decoupled from the bit lines coupled to digital array 3704, meaning that array 3701 and digital array 3704 have separate bit lines. However, the bit lines of analog array 3701 share the same diffusion layer as the bit lines of digital array 3704. In another example, the bit lines of analog array 3701 and the bit lines of digital array 3704 have different diffusion layers in addition to being decoupled. The diffusion can be decoupled between the analog bit lines and the digital bit lines using one or more dummy rows. Optionally, analog array 3701 and digital array 3704 are fabricated on the same semiconductor die.

[0147] Table 10 shows the operating voltages used in the VMM system 3700, where CG-main, EG-main, BL-main, and SL-main are a first set of voltages applied by the row decoder 3702 and the high voltage decoder 3703 to the control gate terminals, erase gate terminals, bit line terminals, and source line terminals, respectively, of one or more memory cells in the analog array 3701, and CG-IFR, EG-IFR, BL-IFR, and SL-IFR are a second set of voltages applied by the row decoder 3705 and the high voltage decoder 3706 to the control gate terminals, erase gate terminals, bit line terminals, and source line terminals, respectively, of one or more memory cells in the digital array 3704. Table 10: Operating voltages for the VMM system 3700 of FIG. [Table 10]

[0148] 43 illustrates an exemplary read operation 4300 of an analog array (such as analog arrays 3601 and 3701 of FIGS. 36 and 37) and a digital array (such as digital arrays 3604 and 3704 of FIGS. 36 and 37). In operation 4301, during readout of the analog array, a first row decoder and a first voltage row decoder apply a first set of voltages to the analog array. In operation 4302, during readout of the digital array, a second row decoder and a second voltage row decoder apply a second set of voltages to the digital array, where the second set of voltages is different from the first set of voltages.

[0149] The ability to apply different sets of voltages to memory cells in analog array 3701 and digital array 3704 enhances performance during neural read operations of analog array 3701 and digital read operations of digital array 3704, such as reduced leakage during read neural operations (caused by the ability to block high currents of digital cells that share the same bit lines as the analog cells) and higher speeds for digital cells due to higher current levels.

[0150] 38 illustrates an additional aspect of VMM system 3700 further comprising column decoder 3801 and column decoder 3802. Column decoder 3801 is coupled to bit lines BL0, ..., BLn which are coupled to columns of analog array 3701. Column decoder 3802 is coupled to bit lines BLD0, ..., BLDn which are coupled to columns of digital array 3704. Digital array 3704 optionally comprises user data array 3707 and system data array 3708. Thus, analog array 3701 and digital array 3704 have separate column decoders to further reduce leakage during read neural operations.

[0151] 39A and 39B respectively show VMM systems 3901 and 3902 which are exemplary designs of VMM system 3700, and FIG. 39C shows VMM system 3903 which has an exemplary design of VMM system 3600.

[0152] In FIG. 39A, the VMM system 3901 comprises an analog array 3701 and a digital array 3704. An exemplary bit line BL0 is coupled to the analog array 3701, and an exemplary bit line BLIFR0 is coupled to the digital array 3704. The bit line BL0 coupled to the analog array 3701 may be referred to as an analog array bit line BL0 and uses metal layers M1-M4 in the analog array 3701, with metal layers M2-M4 also connecting to peripheral circuits (such as column decoders), while the bit line BLIFR0 coupled to the digital array 3704 may be referred to as a digital array bit line BLIFR0 and uses only metal layer M1. The analog array 3701 and the digital array 3704 are part of the same physical array 3904. The physical array 3904 comprises a substrate 3905 and a diffusion layer 3906, both of which are shared by the analog array 3701 and the digital array 3704. The physical array 3904 is separated by using separate metal interconnects for the analog array 3701 and the digital array 3704. For example, as can be seen, the analog array bit line BL0 and the digital array bit line BLIFR0 are separated from each other. Using the same physical array 3904 for both the analog array 3701 and the digital array 3704 reduces any physical effects from process uniformity and area overhead that would arise in the use of separate physical arrays.

[0153] In FIG. 39B, VMM system 3902 includes analog array 3701 and digital array 3704. Exemplary bit line BL0 is coupled to analog array 3701 and may be referred to as analog array bit line BL0, and exemplary bit line BLIFR0 is coupled to digital array 3704 and may be referred to as digital array bit line BLIFR0. Analog array bit line B0 uses metal layers M1-M4 in analog array 3701, and M2-M4 also connect to peripheral circuits (such as column decoders), while digital array bit line BLIFR0 uses only metal layer M1. Analog array 3701 and digital array 3704 are part of the same physical array 3907. Physical array 3907 includes substrate 3908, diffusion layer 3909, and diffusion layer 3910. Substrate 3908 is shared by analog array 3701 and digital array 3704. Diffusion layer 3909 is part of analog array 3701 but not digital array 3704, and diffusion layer 3910 is part of digital array 3704 but not analog array 3701. Physical array 3907 is separated by using separate metal interconnects and separate diffusion layers for analog array 3701 and digital array 3704. For example, as can be seen, bit line BL0 serving analog array 3701 and bit line BLIFR0 serving digital array 3704 are separate from each other, and diffusion layer 3909 of analog array 3701 is separate from diffusion layer 3910 of digital array 3704. Using the same physical array 3907 for both analog array 3701 and digital array 3704 reduces any physical effects from process uniformity and area overhead that would occur with the use of separate physical arrays.

[0154] In FIG. 39C, VMM system 3903 includes analog array 3601 and digital array 3604. Exemplary bit line BL0 is coupled to analog array 3601, and exemplary bit line BLIFR0 is coupled to digital array 3604. Here, bit line BL0 and bit line BLIFRO are the same bit line, both using metal layers M1-M4. Metal layers M2-M4 also connect to peripheral circuitry (such as column decoders). Analog array 3601 and digital array 3604 are part of the same physical array 3911. Physical array 3911 includes substrate 3912 and diffusion layer 3913, both of which are shared by analog array 3601 and digital array 3604. Unlike physical arrays 3904 and 3907 of FIGS. 39A and 39B, physical array 3911 is not split. For example, as can be seen, bit lines BL0 and BLIFR0 are the same and connect to analog array 3601 and digital array 3604. Using the same physical array 3911 for analog array 3601 and digital array 3604 reduces any physical effects from process uniformity and area overhead that would arise in the use of separate physical arrays.

[0155] 40 illustrates an exemplary VMM system 4000 comprising an analog array 4001, a digital array 4002 (optionally comprising a user data array 4008 and a system data array 4009), a digital array 4003 (optionally comprising a user data array 4006 and a system data array 4007), a column decoder 4004, and a column decoder 4005. The column decoder 4004 is coupled to bit lines BL0,...,BLn that are coupled to columns of the analog array 4001. The column decoder 4005 is coupled to bit lines BLD0,...,BLDn that are coupled to columns of the digital arrays 4002 and 4003. Here, each of the digital arrays 4003 and 4002 can be used to store any type of digital data, including digital user data for non-volatile storage operations. Analog array 4001 and digital arrays 4002, 4003 have separate column decoders to reduce leakage and improve performance (like faster speed). Optionally, two or more of analog array 4001, digital array 4003, and digital array 4002 are fabricated on the same semiconductor die.

[0156] 41 shows a digital array 4100, which may be any of the digital arrays 3604, 3704, 4002, or 4003 described above. In this example, the digital array 4100 comprises a user data array 4101 and a system data array 4102. The user data array 4101 and the system data array 4102 may be accessed independently of each other as follows: (1) The user data array 4101 is accessed with an average frequency f1, while the system data array 4102 is accessed with an average frequency f2, where f1 and f2 may be different and f2 may be smaller than f1. (2) the user data array 4101 has an access time of t1 while the system data array 4102 has an access time of t2, where t1 and t2 may be different and t2 may be greater than t1, which means that a read or write operation is slower for the system data array 4102 than for the user data array 4101, and (3) the user data array 4101 has an endurance e1 while the system data array 4102 has an endurance e2, where e1 and e2 may be different and e2 may be less than e1. This may allow for larger manufacturing tolerances and less power consumption for the system data array 4102 compared to the user data array 4101.

[0157] FIG. 42A shows a differential current-to-voltage converter 4201 that can read analog data from analog arrays 3601, 3701, and 4001 using a first set of voltages and digital data from digital arrays 3604, 3704, 4002, and 4003 using a second set of voltages in VMM systems 3600, 3700, 4000, respectively.

[0158] The differential current-to-voltage converter 4201 comprises an operational amplifier 4203, variable integration resistors 4204 and 4205, and a common mode circuit 4206 (used for the differential amplifier implementation of the operational amplifier 4203). The differential current-to-voltage converter 4201 converts two current inputs IBL+ and IBL- into differential output voltages VO+ and VO-, where the output voltage is proportional to the resistance of the variable resistors 4204 and 4205. The input currents IBL+ and IBL- are, optionally, currents representing positive and negative weights. For example, IBL+ can be a bitline current that is a current Iw+ from a single cell or a sum of currents from multiple w+ cells coupled to the bitline, and IBL-can can be a bitline current that is a current Iw- from a single cell or a sum of currents from multiple w- cells coupled to the bitline. Such positive and negative weights can be used in a neural network to present weights (W=W+-W-). In another example, the two input currents IBL+ and IBL- can represent cell currents (in this case used to verify cell current targets in weight tuning, which means programming or erasing a cell to a target current), or bit line currents and reference currents from the array.

[0159] Optionally, the bias current for operational amplifier 4203 and / or common mode circuit 4206 can be set to a higher current level for digital readout than for analog readout.

[0160] Optionally, registers 4204 and 4205 can be set to different values ​​for digital and analog readouts. Optionally, registers 4204 and 4205 can be set to different values ​​when converter 4201 is used for cell verification in a weight tuning operation (such as programming or erasing a memory cell to a target current). Figure 42B shows a differential successive-approximation register (SAR) analog-to-digital converter (ADC) 4202, which can read digital data from analog arrays 3601, 3701, and 4001 using a first set of voltages and digital arrays 3604, 3704, 4002, and 4003, respectively, in VMM systems 3600, 3700, 4000, or read analog data using a second set of voltages.

[0161] The differential successive approximation register analog-to-digital converter 4202 converts an analog input or a differential analog input to a digital output using a binary search through all possible quantization levels to identify the appropriate digital output.

[0162] The differential successive approximation register analog-to-digital converter 4202 comprises a binary capacitive digital-to-analog converter (CDAC) 4207, a binary CDAC 4208 (complementary to CDAC 4207), a comparator 4209, and a SAR logic and register 4210.

[0163] A differential successive approximation register analog-to-digital converter (SAR ADC) 4202 receives differential voltage inputs Vinp and Vinn, for example provided by a differential current-to-voltage converter 4201. The SAR logic and registers 4210 cycles through all possible digital bit combinations and then controls switches in CDACs 4207 and 4208 to couple the voltage sources to the capacitors. When the output of the comparator 4209 flips, the digital bit combination in the SAR logic and registers 4210 is output as a digital output. Optionally, the SAR logic and registers 4210 generates an additional 1-bit digital output DMAJ in the digital output that is "1" if the majority of the bits in the digital value are "1" and "0" if the majority of the bits in the corresponding digital value are not "1".

[0164] Optionally, resistors 4204 and 4205 can be set to a different resistance value for a digital read operation than for an analog read operation.

[0165] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed between them) and "indirectly" (with an intermediate material, element, or gap disposed between them). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed between them) and "indirectly adjacent" (with an intermediate material, element, or gap disposed between them), "attached" includes "directly attached" (with no intermediate material, element, or gap disposed between them) and "indirectly attached" (with an intermediate material, element, or gap disposed between them), and "electrically coupled" includes "directly electrically coupled" (without an intermediate material or element disposed between them that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed between them that electrically connects the elements together). For example, forming an element "above the substrate" can include forming the element directly on the substrate, with no intermediate materials / elements between them, and forming the element indirectly on the substrate, with one or more intermediate materials / elements between them.

Claims

1. 1. An artificial neural network system comprising: an analog array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; a digital array of non-volatile memory cells arranged in rows and columns; a plurality of bit lines, each bit line in the plurality of bit lines connected to a column of non-volatile memory cells in the analog array and a column of non-volatile memory cells in the digital array.

2. a first row decoder coupled to the analog array; a first high voltage row decoder coupled to said analog array.

3. a second row decoder separate from the first row decoder and coupled to the digital array; 3. The artificial neural network system of claim 2, further comprising: a second high voltage row decoder separate from said first high voltage row decoder and coupled to said digital array.

4. 4. The artificial neural network system of claim 3, wherein the first row decoder and the first high voltage row decoder apply a first set of voltages to the analog array during readout of the analog array.

5. 5. The artificial neural network system of claim 4, wherein the second row decoder and the second high voltage row decoder apply a second set of voltages to the digital array during readout of the digital array, the second set of voltages being different than the first set of voltages.

6. 4. The artificial neural network system of claim 3, further comprising readout circuitry used during readout of said analog array and during readout of said digital array.

7. 7. The artificial neural network system of claim 6, wherein during readout of the digital array, the readout circuitry outputs a "1" if a majority of the output bits generated by the readout circuitry are "1" and outputs a "0" if less than a majority of the output bits generated by the readout circuitry are "1".

8. 2. The artificial neural network system of claim 1, wherein said digital arrays comprise a user data array and a system data array.

9. 9. The artificial neural network system of claim 8, wherein the system data array is read, programmed, or erased at a slower rate than the user data array.

10. 9. The artificial neural network system of claim 8, wherein the readout speed of said system data array is slower than that of said user data array.

11. 9. The artificial neural network system of claim 8, wherein the durability of said system data array is less than the durability of said user data array.

12. 1. An artificial neural network system comprising: an analog array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; a digital array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns, the analog array and the digital array being fabricated on the same semiconductor die; a first plurality of bitlines, each bitline in the first plurality of bitlines coupled to a column of non-volatile memory cells in the analog array; a second plurality of bit lines, each bit line in the second plurality of bit lines coupled to a column of non-volatile memory cells in the digital array, the second plurality of bit lines being decoupled from the first plurality of bit lines.

13. a first row decoder coupled to the analog array; a first high voltage row decoder coupled to said analog array.

14. a second row decoder separate from the first row decoder and coupled to the digital array; 14. The artificial neural network system of claim 13 further comprising: a second high voltage row decoder separate from said first high voltage row decoder and coupled to said digital array.

15. 15. The artificial neural network system of claim 14, wherein the first row decoder and the first high voltage row decoder apply a first set of voltages to the analog array during readout of the analog array.

16. 16. The artificial neural network system of claim 15, wherein the second row decoder and the second high voltage row decoder apply a second set of voltages to the digital array during readout of the digital array, the second set of voltages being different than the first set of voltages.

17. 13. The artificial neural network system of claim 12, wherein the first plurality of bit lines and the second plurality of bit lines share a diffusion layer.

18. 20. The artificial neural network system of claim 17, wherein the first plurality of bitlines and the second plurality of bitlines have different metal interconnects.

19. 13. The artificial neural network system of claim 12, wherein the first plurality of bit lines and the second plurality of bit lines have different diffusion layers.

20. 20. The artificial neural network system of claim 18, wherein the first plurality of bitlines and the second plurality of bitlines have different metal interconnects.

21. 13. The artificial neural network system of claim 12, wherein said digital array comprises a system data array.

22. 13. The artificial neural network system of claim 12, further comprising readout circuitry used during readout of the analog array and readout of the digital array.

23. 22. The artificial neural network system of claim 21, wherein during readout of the digital array, a readout circuit outputs a "1" if a majority of the output bits generated by the readout circuit are "1" and outputs a "0" if less than a majority of the output bits generated by the readout circuit are "1".

24. 13. The artificial neural network system of claim 12, further comprising a second digital array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns.

25. 25. The artificial neural network system of claim 24, wherein each bit line in said second plurality of bit lines is coupled to a column of non-volatile memory cells in said second digital array.

26. 13. The artificial neural network system of claim 12, wherein said digital array of non-volatile memory cells comprises a user data array and a system data array.

27. 27. The artificial neural network system of claim 26, wherein the system data array has a slower speed of one or more of read, program, or erase operations than the user data array.

28. 27. The artificial neural network system of claim 26, wherein a speed of a read operation of said system data array is slower than a speed of a read operation of said user data array.

29. 27. The artificial neural network system of claim 26, wherein the durability of said system data array is less than the durability of said user data array.

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