System and method for efficiently reducing reflected power associated with an HFRF generator - Patents.com

Abstract

A method for reducing reflected radio frequency (RF) power is described. The method includes receiving a voltage signal from an output of a match. The method further includes dividing the voltage signal into a plurality of bins and identifying a bin from the plurality of bins that includes a zero crossing. The bin is associated with a frequency of a radio frequency (HF) signal. The method further includes applying a fixed multiplier to the frequency of the HF signal to generate a plurality of offsets. The method includes operating an HFRF generator according to the plurality of offsets during periods when the voltage signal is positive or negative.

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The embodiments described in this disclosure relate to systems and methods for efficiently reducing reflected power associated with high frequency (HF) radio frequency (RF) generators. [Background technology]

[0002] The background discussion provided herein is intended to provide a general context for the present disclosure. Work by the currently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be regarded as prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure.

[0003] A plasma tool includes one or more radio frequency (RF) generators that are coupled to a plasma chamber in which a wafer is placed. The RF generators provide an RF signal to the plasma chamber. Process gases are provided to the plasma chamber to generate a plasma in the plasma chamber, which is used to process the wafer.

[0004] However, it is desirable to control the processing of the wafers to achieve desired results, and further, it is desirable for the wafers to be processed efficiently.

[0005] It is in this context that embodiments of the present disclosure are described. Summary of the Invention

[0006] DETAILED DESCRIPTION OF THE DRAWINGS The present disclosure provides a system and method for efficiently reducing reflected power associated with a high frequency (HF) radio frequency (RF) generator. It should be understood that the present invention may be embodied in any form, such as a process, an apparatus, a system, hardware, or a method via a computer readable medium. Several embodiments are described below.

[0007] In one embodiment, a method of reducing reflected RF power is described. The method includes receiving a voltage signal from an output of a match coupled to a low frequency (LF) RF generator and an HFRF generator. The method further includes dividing the voltage signal into a plurality of bins and identifying a bin from the plurality of bins that includes a zero crossing. The bin is associated with a frequency of an HFRF signal generated by the HFRF generator. The method further includes applying a first fixed multiplier to the offset frequency of the HFRF signal to generate a plurality of negative offsets and applying a second fixed multiplier to the frequency of the HFRF signal to generate a plurality of positive offsets. The method includes operating the HFRF generator according to the plurality of negative offsets during periods when the voltage signal is positive and operating the HFRF generator according to the plurality of positive offsets during periods when the voltage signal is negative.

[0008] In one embodiment, a controller for reducing reflected RF power is described. The controller includes a processor that receives a voltage signal from an output of a match coupled to an LFRF generator and an HFRF generator. The processor divides the voltage signal into a number of bins and identifies a bin from the number of bins that includes a zero crossing. The bin is associated with a frequency of an HFRF signal generated by the HFRF generator. The processor further applies a first fixed multiplier to the frequency of the HFRF signal to generate a number of negative offsets and applies a second fixed multiplier to the frequency of the HFRF signal to generate a number of positive offsets. The processor operates the HFRF generator according to the number of negative offsets during periods when the voltage signal is positive and operates the HFRF generator according to the number of positive offsets during periods when the voltage signal is negative. The controller includes a memory device coupled to the processor.

[0009] In one embodiment, a plasma system for reducing reflected RF power is described. The plasma system includes an LFRF generator for generating an LFRF signal and an HFRF generator for generating an HFRF signal. The plasma system further includes a match coupled to the LFRF generator and the HFRF generator. The match receives the LFRF signal and the HFRF signal and outputs a modified RF signal. The plasma system includes a controller coupled to the LFRF generator, the HFRF generator, and the match. The controller receives a voltage signal from an output of the match, divides the voltage signal into a number of bins, and identifies a bin from the number of bins that includes a zero crossing. The bin is associated with a frequency of the HFRF signal generated by the HFRF generator. The controller further applies a first fixed multiplier to the frequency of the HFRF signal to generate a number of negative offsets and applies a second fixed multiplier to the frequency of the HFRF signal to generate a number of positive offsets. The controller operates the HFRF generator in accordance with the plurality of negative offsets during periods when the voltage signal is positive, and operates the HFRF generator in accordance with the plurality of positive offsets during periods when the voltage signal is negative.

[0010] Advantages of the systems and methods described herein include processing substrates in an efficient manner. Instead of determining a high frequency value for each bin to reduce the power reflected back to the HFRF generator, a multiplier is used during processing of the substrate. Application of the multiplier in this manner allows for a rapid reduction in the power reflected back to the HFRF generator, allowing for efficient processing of the substrate.

[0011] Further advantages of the systems and methods described herein include using a preset that includes an HF offset value generated based on a pre-stored multiplier. To reduce the high frequency reflected power of the plasma, it is not necessary to determine the HF offset value of several bins during substrate processing. Rather, the preset is used to reduce the reflected power and efficiently process the substrate.

[0012] A further advantage of the systems and methods described herein includes applying a zero HF offset value during some bins. During these bins, no positive or negative multiplier needs to be applied. Therefore, a zero multiplier is applied during these bins. This further increases the efficiency of reducing the power reflected back towards the HFRF generator.

[0013] Advantages of the systems and methods described herein include applying different multipliers in different states of an RF signal, such as an HFRF signal or an LFRF signal. By applying different multipliers in different states, different processes can be controlled in different ways. For example, an etch process is controlled by applying a first multiplier during state S1, a state having a high power level. A deposition process is controlled by applying a second multiplier during state S0, a state having a low power level.

[0014] Further advantages of the systems and methods described herein include not applying one or more multipliers during a transition state of an RF signal, such as an HFRF signal or an LFRF signal. Instead, the one or more multipliers are applied during a steady state of the RF signal, such as state S1 or state S0. Compared with the change in the power value of the RF signal in the steady state, the power value of the RF signal in the transition state varies more frequently. Therefore, applying one or more multipliers during a transition state is time consuming and inefficient. By not applying one or more multipliers during a transition state, the time to apply one or more multipliers can be reduced, reducing inefficiencies in substrate processing.

[0015] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0016] The embodiments can be understood by the following description taken in conjunction with the accompanying drawings.

[0017] [Figure 1] FIG. 1 is a diagram of one embodiment of a plasma system to illustrate the use of a low frequency (LF) radio frequency (RF) generator and a high frequency (HF) RF generator.

[0018] [Figure 2A] FIG. 2A is one embodiment of a graph to illustrate a clock signal.

[0019] [Figure 2B] FIG. 2B shows one embodiment of a graph plotting voltage signals to illustrate binning.

[0020] [Figure 3A] FIG. 3A shows one embodiment of a graph to illustrate the generation of an HF offset value when operating an HFRF generator during processing of a substrate.

[0021] [Figure 3B] FIG. 3B is one embodiment of a graph showing different presets being applied.

[0022] [Figure 3C] FIG. 3C illustrates one embodiment of a graph to illustrate a multiplier of zero being applied to the HFRF generator for a portion of a cycle of the clock signal.

[0023] [Figure 4A] FIG. 4A is one embodiment of a graph to illustrate a clock signal.

[0024] [Figure 4B] FIG. 4B is one embodiment of a graph to illustrate an RF signal generated by an HFRF generator.

[0025] [Figure 4C]FIG. 4C is one embodiment of a graph to illustrate that during hold-off periods, no multiplier is applied to the HFRF generator's reference high frequency value, but during frequency adjustment periods, a different multiplier is applied in different states of the RF signal of FIG. 4B. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] In the following embodiments, a system and method for efficiently reducing reflected power associated with a high frequency (HF) radio frequency (RF) generator is described. It will be apparent that the present embodiments may be practiced without some or all of the specific elements described below. In other instances, well-known process operations have not been described in detail in order to avoid unnecessarily obscuring the present embodiments.

[0027] 1 is a diagram illustrating one embodiment of a plasma system 100 to illustrate the use of a low frequency (LF) RF generator 102 and a high frequency (HF) RF generator 104. System 100 includes LFRF generator 102, HFRF generator 104, a host computer 106, a match 107, and a plasma chamber 108. Plasma system 100 further includes a voltage (V) sensor 110 and a power (P) sensor 112.

[0028] As an example, the LFRF generator 102 has an operating frequency of 400 kilohertz (kHz) or 2 megahertz (MHz). As a further example, the HFRF generator 104 has an operating frequency of 27 MHz or 60 MHz. Examples of the host computer 106 include a desktop, a laptop, a tablet, a controller, a smartphone, and the like. Examples of the match 107 include an impedance matching circuit or an impedance match or a matching circuit or an impedance matching network, and the like. In particular, the match 107 includes a first branch circuit and a second branch circuit. Each branch circuit includes one or more matching network elements. Examples of the matching network elements include a capacitor, an inductor, and a resistor, and the like. An example of the plasma chamber 108 includes a capacitively coupled plasma (CCP) chamber.

[0029] The host computer 106 includes a processor 114 and a memory device 116. Examples of the processor 114 include a central processing unit (CPU), an application specific integrated circuit (ASIC), a programmable logic device (PLD), etc. Examples of the memory device 116 include a read-only memory, a random access memory, etc.

[0030] The plasma chamber 108 includes a lower electrode LE and an upper electrode UE. A gap is formed between the lower electrode LE and the upper electrode UE, and a substrate S is placed in the gap on the top surface of the lower electrode LE for processing. An example of the substrate S is a semiconductor wafer on which an integrated circuit is formed.

[0031] The processor 114 is coupled to a memory device 116. The processor 114 is coupled to the LFRF generator 102 via a transfer cable 118 and to the HFRF generator 104 via a transfer cable 120. Examples of transfer cables include electrical cables that transfer data in parallel or serial, or using the Universal Serial Bus (USB) protocol. In the LFRF generator 102, the output 122 is coupled to an input 126 of the match 107 via an RF cable 124. Similarly, in the HFRF generator 104, the output 128 is coupled to an input 132 of the match 107 via an RF cable 130. The match 107 has an output 134 that is coupled to the lower electrode LE via an RF transmission line 136. A first branch of the match 107 is connected between the input 126 and the output 134, and a second branch of the match 107 is connected between the input 132 and the output 134. The upper electrode UE is coupled to ground potential.

[0032] The V sensor 110 is coupled to the processor 114 via a transfer cable 138, and the P sensor 112 is coupled to the processor 114 via a transfer cable 140. The V sensor 110 is coupled to the output 134 of the match 134. The P sensor 112 is also coupled to the output 128 of the HFRF generator 104.

[0033] The processor 114 generates a recipe signal 142 including a low frequency and one or more power levels of the RF signal 150 generated by the LFRF generator 102. As an example, the low frequency is equal to the operating frequency of the LFRF generator 102. The processor 114 transmits the recipe signal 142 to the LFRF generator 102 via the transmission cable 118. The processor 114 also generates a recipe signal 144 including a high frequency and one or more power levels of the RF signal 152 generated by the HFRF generator 104. As an example, the high frequency is equal to the operating frequency of the HFRF generator 104. The processor 114 transmits the recipe signal 144 to the HFRF generator 104 via the transmission cable 120.

[0034] Upon receiving recipe signal 142, LFRF generator 102 generates an RF signal 150 having a low frequency and one or more power levels as indicated in recipe signal 142. LFRF generator 102 transmits RF signal 150 to match 107 via output 122, RF cable 124, and input 126. Similarly, upon receiving recipe signal 144, HFRF generator 104 generates an RF signal 152 having a high frequency and one or more power levels as indicated in recipe signal 144. HFRF generator 104 transmits RF signal 152 to match 107 via output 128, RF cable 130, and input 132.

[0035] Upon receiving RF signal 150, the first branch of match 107 modifies the impedance of RF signal 150 to match the impedance of a load coupled to output 134 and the impedance of a source coupled to input 126 to provide a first modified RF signal. Examples of loads coupled to output 134 include RF transmission line 136 and plasma chamber 108. Examples of sources coupled to input 126 include RF cable 124 and LFRF generator 102. Similarly, upon receiving RF signal 152, the second branch of match 107 modifies the impedance of RF signal 152 to match the impedance of a load coupled to output 134 of match 107 and the impedance of a source coupled to input 132 of match 107 to provide a second modified RF signal.

[0036] The match 107 combines, such as by adding, the first modified RF signal to the second modified RF signal to output a modified RF signal 154 at the output 134. The modified RF signal 154 is transmitted from the output 134 via an RF transmission line 136 to the lower electrode LE. When a process gas, such as one or more fluorine-containing gases, oxygen-containing gases, nitrogen-containing gases, etc., is provided to the gap between the lower electrode LE and the upper electrode UE, in addition to the modified RF signal 154, a plasma is generated or maintained in the gap. The plasma processes the substrate S. Examples of processing the substrate S include etching features in the substrate S, depositing material on the substrate S, cleaning the substrate S, etc.

[0037] While the substrate S is being processed, the V sensor 110 measures the voltage at the output 134, outputs a voltage signal 156, and transmits the voltage signal 156 to the processor 114 via the transfer cable 138. Similarly, while the substrate S is being processed, the P sensor 112 measures the power, such as the source power or the reflected power, at the output 134, outputs a power signal 158, and transmits the power signal 158 to the processor 114 via the transfer cable 140.

[0038] In one embodiment, the V sensor 110 is coupled to the RF transmission line 136 at any location.

[0039] In one embodiment, the P sensor 112 is coupled to an RF cable 130 at any location.

[0040] 2A is one embodiment of a graph 200 to illustrate a clock signal 202. For example, the clock signal 202 is generated by the processor 114 (FIG. 1). The x-axis of the graph 200 plots time t from time t0 to time t40. The y-axis of the graph 200 plots the voltage of the clock signal 202. The clock signal 202 periodically transitions between a logic level 1 and a logic level 0. A logic level 1 corresponds to 5 volts and a logic level 0 corresponds to zero volts.

[0041] Clock signal 202 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t10. Clock signal 202 transitions from logic level 1 to logic level 0 at time t10 and remains at logic level 0 from time t10 to time t20. The transition between logic level 1 and logic level 0 is repeated from time t20 to time t40. Clock signal 202 has cycle n from time t0 to time t20 and successively continuing cycles (n+1) from time t20 to time t40, where n is a positive integer.

[0042] 2B illustrates one embodiment of a graph 210 plotting a voltage signal 212, such as a provided voltage signal, to illustrate binning. Graph 210 is generated by processor 114 (FIG. 1) upon receiving voltage signal 212, for example, from V sensor 110 (FIG. 1).

[0043] The graph 210 plots the voltage signal 220 versus time t. For example, the y-axis of the graph 210 represents the voltage of the voltage signal 220, and the x-axis of the graph 210 represents time t. The y-axis plots a number of voltage values ​​from V0 to V6 in the positive y-direction. Also, the y-axis plots a number of voltage values ​​from V0 to -V6 in the negative y-direction. The voltage value V6 is greater than the voltage value V0, and the voltage value -V6 is less than the voltage value V0. Specifically, the voltage value V0 is zero. As another example, the voltage value V0 is a negative value. For example, the x-axis of the graph 210 represents time t at which the voltage value of the voltage signal 212 is received by the processor 114 from the V sensor 110.

[0044] The voltage signal 212 is an example of the voltage signal 156 (FIG. 1) generated by the V sensor 110 (FIG. 1). The voltage signal 212 is indicative of the voltage of the first modified RF signal or is primarily indicative of the voltage of the RF signal 150 generated by the LFRF generator 102. For example, the voltage signal 212 is indicative of the voltage of the RF signal 150. As another example, the voltage signal 212 is primarily indicative of the voltage of the RF signal 150 and is minimally indicative of the voltage of the RF signal 152. Specifically, the voltage of the voltage signal 212 is the voltage of the RF signal 150. As another example, 90% of the voltage of the voltage signal 212 is the voltage of the RF signal 150, and the remaining 10% of the voltage of the voltage signal 212 is the voltage of the RF signal 152. The voltage signal 212 continues for multiple clock cycles of the clock signal 202 (FIG. 2A). For example, the voltage signal 212 continues from time t0 to time t20. The time interval from time t0 to t20 represents cycle n of clock signal 202. Voltage signal 212 further continues from time t20 to time t40, where the time interval from time t20 to t40 represents cycle (n+1) of clock signal 202.

[0045] The processor 114 divides the voltage signal 212 into a number of bins, such as 10 or 20 bins, during each cycle of the clock signal 202. For example, during cycle n, the voltage signal 212 is divided into bins 1 through 10, and during cycle (n+1), the voltage signal 212 is divided into bins 1 through 10, and so on. More specifically, the processor 114 divides the voltage signal 212 during each cycle of the clock signal 202. The voltage signal 212 is divided into 10 equal time intervals during each cycle, with each time interval designated by the processor 114 as a bin.

[0046] The processor 114 continues each bin for the same time interval. For example, bin 1 continues from time t0 to time t2, bin 2 continues from time t2 to time t4, bin 3 continues from time t4 to time t6, bin 4 continues from time t6 to time t8, and bin 5 continues from time t8 to time t10. Bin 5 may also be referred to herein as bin 0. Furthermore, bin 6 continues from time t10 to time t12, bin 7 continues from time t12 to time t14, bin 8 continues from time t14 to time t16, bin 9 continues from time t16 to time t18, and bin 10 continues from time t18 to time t20.

[0047] The processor 114 identifies bin 0 as the time interval that includes a point where the voltage signal 212 crosses the x-axis and designates the point as the negative zero crossing 214. For example, the processor 114 identifies the negative zero crossing 214 as a point where the voltage of the voltage signal 212 is zero and the slope of the voltage signal 212 is negative. In another example, at the negative zero crossing 214, the voltage of the voltage signal 212 is not zero. The slope of the voltage signal 212 is negative during the time interval of bin 0. The processor 114 identifies (e.g., designates) one of bins 1 through 10 that includes the negative zero crossing 214 as bin 0.

[0048] Bins 1 through 4 and a first portion of bin 0 form a positive cycle of the voltage signal 212, and a second portion of bin 0 and bins 6 through 10 form a negative cycle of the voltage signal 212. The first portion of bin 0 that is part of the positive cycle of the voltage signal 212 spans the time interval from time t8 to time t9 when the negative crossing 214 occurs, and the second portion of bin 0 that is part of the negative cycle of the voltage signal 212 spans the time interval from time t9 to time t10.

[0049] 3A is an illustration of one embodiment of a graph 300 illustrating the generation of an HF offset value operating the HFRF generator 104 (FIG. 1) during processing of a substrate S. When the HFRF generator 104 operates at an operating frequency, the HFRF generator 104 generates an RF signal 152 (FIG. 1) having an HF offset value. The graph 300 is generated by the processor 114 (FIG. 1). In the graph 300, the HF offset value of the RF signal 152 from a reference high frequency value HF0 is plotted on the y-axis versus time t. The x-axis of the graph 300 is plotted with time t. For example, the x-axis of the graph 210 is used as the x-axis of the graph 300.

[0050] The y-axis of graph 300 plots HF offset values ​​from high frequency value HF0, ranging from HF0 to HF6 in the positive y-direction and from HF0 to HF(-3) in the negative y-direction. Note that the HF offset value increases between HF0 and HF6 and decreases between HF0 and HF(-3). For example, HF offset value HF1 is greater than high frequency value HF0, HF offset value HF2 is greater than HF offset value HF1, and so on. Similarly, HF offset value HF(-1) is less than high frequency value HF0, HF offset value HF(-2) is less than HF offset value HF(-1), and so on.

[0051] The processor 114 determines that the HFRF generator 104 operates at a reference high frequency value HF0 during the time interval of bin 0, so that the RF signal 152 (FIG. 1) has a high frequency value HF0 during that time interval. For example, the high frequency value HF0 is determined by the processor 114 to reduce parameters associated with the HFRF generator 104 for bin 0. A description of the parameters and how the parameters of the bins are reduced is provided below.

[0052] The processor 114 applies a multiplier -M1 to the offset value offset from the high frequency value HF0 to generate HF offset values ​​from bin 1 to bin 4, where -M1 is a negative real number. The multiplier -M1 is also applied such that a first portion of the frequency signal 302 formed by the HF offset values ​​from bin 1 to bin 4 forms a negative cycle of the frequency signal 302. Specifically, the processor 114 multiplies the multiplier -M1 by a first offset value offset from the high frequency value HF0 to generate an HF offset value HF(-1), multiplies the multiplier -M1 by a second offset value offset from the high frequency value HF0 to generate an HF offset value HF(-2), and multiplies the multiplier -M1 by a third offset value offset from the high frequency value HF0 to generate an HF offset value HF(-3), where -M1 is a negative integer.

[0053] Each value HF(-1), HF(-2) and HF(-3) is an example of a negative offset with respect to the reference high frequency value HF0. The multiplier -M1 is determined by the processor 114 to form a negative cycle of the frequency signal 302, which has an inverse shape to the shape of the positive cycle of the voltage signal 212. In this manner, the multiplier -M1 is applied to the first to third offset values ​​to generate the first portion of the frequency signal 302 to have an inverse shape to the shape of the positive cycle of the voltage signal 212. In another example, the multiplier -M1 is not an integer but a negative real number that is used to generate the HF offset values ​​from bin 1 to bin 4. During the period from time t0 to time t10 when the voltage signal 212 has a positive cycle, the sheath of the plasma collapses and becomes highly capacitive, and the HF offset values ​​from bin 1 to bin 4 are controlled by the processor 114 to be negative values ​​with respect to the reference high frequency value HF0. The frequency signal 302 is illustrated using a series of points on the graph 300.

[0054] The processor 114 controls the HFRF generator 104 to operate with an HF offset value HF(-2) during bin 1, an HF offset value HF(-3) during bin 2, an HF offset value HF(-2) during bin 3, and an HF offset value HF(-1) during bin 4. For example, during one or more cycles, such as cycle n, cycle (n+1), and cycle (n+2), of the clock signal 202, the processor 114 controls the HFRF generator 104 to operate with HF offset values ​​HF(-2), HF(-3), HF(-2), and HF(-1) for bin 1 through bin 4. As another example, the processor 114 transmits HF offset values ​​HF(-3), HF(-2), and HF(-1) to the HFRF generator 104 in the recipe signal 144 (FIG. 1). The recipe signal 144 also includes an identification of each of bins 1 to 4, such as by a time period, and a correspondence, such as a unique relationship, between each of bins 1 to 4 and one of the HF offset values ​​HF(-2), HF(-3), HF(-2), and HF(-1). After receiving the recipe signal 144, the HFRF generator 104 generates an RF signal 152 having HF offset values ​​HF(-2), HF(-3), HF(-2), and HF(-1) according to the correspondence between bins 1 to 4 and the HF offset values ​​HF(-2), HF(-3), HF(-2), and HF(-1). Specifically, the HFRF generator 104 generates an RF signal 152 having an HF offset value HF(-2) during bin 1, an HF offset value HF(-3) during bin 2, an HF offset value HF(-2) during bin 3, and an HF offset value HF(-1) during bin 4.

[0055] The processor 114 determines the multiplier -M1 to reduce, e.g., minimize, a parameter, such as a voltage standing wave ratio (VSWR) or a reflection coefficient (Γ), associated with the HFRF generator 104 for bin 4. For example, during bin 4 of cycles (nm), the processor 114 receives the voltage signal 212 (FIG. 2B) and calculates the forward voltage V f Reflected voltage V r Determine the ratio of the forward voltage V in bin 4, where m is an integer less than n. f Reflected voltage V in bin 4 forr The ratio of these is the reflection coefficient in bin 4. The reflected voltage V r is reflected from the plasma chamber 108 (FIG. 1) through the RF transmission line 136, the second branch of the match 107, and the RF cable 130 towards the HFRF generator 104. f is the voltage of the RF signal 152 supplied from the RF generator 104 to the lower electrode LE via the RF cable 130, the match 107, and the RF transmission line 136. The forward voltage V f is stored in memory device 116 for access by processor 144. Processor 114 determines the supply voltage during bin 4 of voltage signal 212 and the forward voltage V f The difference between the reflected voltage and the reflected voltage V rThe processor 114 determines the supply voltage as a statistical value, such as the average or median of the voltage values ​​of the voltage signal 212 in bin 4. As another example, the processor 114 determines the VSWR for bin 4 as a ratio of the first sum to the second sum. The first sum is the sum of 1 and the magnitude of the reflection coefficient for bin 4, and the second sum is the difference between 1 and the magnitude of the reflection coefficient for bin 4. During bin 4 of cycles (nm), the processor 114 multiplies the first offset value of the RF signal 152 by a multiplier -M1 to output a high frequency value HF(-1) and operates the HFRF generator 104 with the HF offset value HF(-1) during bin 4 of cycles (nm). When operating the HFRF generator 104 with the HF offset value HF(-1) during bin 4 of cycle (nm) and receiving the parameter during bin 4 of cycle (nm), the processor 114 determines that during cycle (nm), the parameter has a lower value compared to the value of the parameter during cycle (nmp) of the clock signal 202, where (nmp) is an integer smaller than the integer (nm) and p is a positive integer. The value of the parameter during cycle (nmp) is determined by the processor 114 when the processor 114 controls the HFRF generator 104 to operate with the HF offset value HF(-0.5) by applying another multiplier -M1' instead of the multiplier -M1. In this manner, the processor 114 determines that the value of the parameter cycle (nm) is lower than the value of the parameter cycle (nmp), and therefore determines to operate the HFRF generator 104 with HF offset values ​​HF(-2), HF(-3), HF(-2), and HF(-1) determined based on the multiplier -M1 instead of the multiplier -M1'.

[0056] This parameter is indicative of the amount of power that is reflected from the plasma chamber 108 towards the HFRF generator 104. For example, this power is reflected from the plasma chamber 108, the RF transmission line 136, the match 107, and the RF cable 130 towards the HFRF generator 104. The power reflected towards the HFRF generator 104 is also referred to herein as high frequency reflected power.

[0057] Additionally, the processor 114 modifies the multiplier M1 in response to changes in plasma conditions. For example, as the ratio of the operating power of the LFRF generator 102 to the operating power of the HFRF generator 104 increases, the value of the multiplier M1 or the absolute value of the multiplier -M1 increases. As the ratio of the operating power of the LFRF generator 102 to the operating power of the HFRF generator 104 decreases, the value of the multiplier M1 or the absolute value of the multiplier -M1 decreases.

[0058] By applying the multiplier -M1 to bins 1 to 4, no determination or measurement of the high frequency reflected power is required to reduce the high frequency reflected power for bins 1 to 3. For example, during each time interval from bins 1 to 3, the processor 114 does not adjust the corresponding offset values, such as the second and third offset values ​​applied to the reference high frequency value HF0, based on the high frequency reflected power. Rather, the same multiplier -M1 is applied to the corresponding offset values ​​between bins 1 to 3 as is applied to the first offset value between bins 4. This improves the processing efficiency of the substrate S.

[0059] Further, the processor 114 applies another, e.g., different, multiplier M2 to the offset value from the high frequency value HF0 to generate HF offset values ​​for bins 6 through 10, where M2 is a positive integer or a positive real number. The multiplier M2 is also applied such that a second portion of the frequency signal 302 formed by the HF offset values ​​for bins 6 through 10 forms a positive cycle of the frequency signal 302. During the period from time t10 to time t20 when the voltage signal 212 has a negative cycle, the plasma sheath expands and becomes less capacitive, and the HF offset values ​​for bins 6 through 10 are controlled by the processor 114 to be positive. Specifically, the processor 114 multiplies the multiplier M2 by a fourth offset value offset from the high frequency value HF0 to generate a high frequency value HF0.5, multiplies the multiplier M2 by a fifth offset value offset from the high frequency value HF0 to generate a high frequency value HF1, and multiplies the multiplier M2 by a sixth offset value offset from the high frequency value HF0 to generate a high frequency value HF1.5. As a specific example, one or more of the first, second, third, fourth, fifth, and sixth offset values ​​are equal to each other. As another example, one or more of the first to sixth offset values ​​are different from one or more of the remaining first to sixth offset values.

[0060] The HF offset values ​​HF0.5, HF1, and HF1.5 are examples of positive offsets relative to the high frequency value HF0. The multiplier M2 is determined by the processor 114 to form a positive cycle of the frequency signal 302 that has an inverse shape to the shape of the negative cycle of the voltage signal 212. Thus, the multiplier M2 is applied to the fourth through sixth offset values ​​from the high frequency value HF0 to generate the second portion of the frequency signal 302 to have an inverse shape to the shape of the negative cycle of the voltage signal 212.

[0061] The processor 114 controls the HFRF generator 104 to operate with an HF offset value of HF0.5 during bin 6, an HF offset value of HF1 during bin 7, an HF offset value of HF1.5 during bin 8, an HF offset value of HF1 during bin 9, and an HF offset value of HF0.5 during bin 10. For example, during one or more cycles following cycle n of the clock signal 202, such as cycle n, cycle (n+1), cycle (n+2), etc., the processor controls the HFRF generator 104 to operate with the HF offset values ​​for bins 6 through 10. As another example, the processor 114 transmits HF offset values ​​HF0.5, HF1, and HF1.5 to the HFRF generator 104 in the recipe signal 144. The recipe signal 144 also includes an identification of each of bins 6 to 10, such as by a time period, and a correspondence, such as a unique relationship, between each of bins 6 to 10 and one of the HF offset values ​​HF0.5, HF1, and HF1.5. After receiving the recipe signal 144, the HFRF generator 104 generates an RF signal 152 having HF offset values ​​HF0.5, HF1, and HF1.5 according to the correspondence between bins 6 to 10 and the HF offset values ​​HF0.5, HF1, HF1.5, HF1, and HF0.5. In particular, the HFRF generator 104 generates an RF signal 152 having an HF offset value HF0.5 during bin 6, an HF offset value HF1 during bin 7, a high frequency value HF1.5 during bin 8, a high frequency value HF1 during bin 9, and an HF offset value HF0.5 during bin 10.

[0062] The processor 114 determines the multiplier M2 to reduce, e.g., minimize, a parameter associated with the HFRF generator 104 for bin 6. For example, during bin 6 of cycles (nm), the processor 114 receives the voltage signal 212 and the forward voltage V f Reflected voltage V r Determine the ratio of the forward voltage V in bin 6. f Reflected voltage V in bin 6 for r The ratio of the supply voltage between bin 6 of the voltage signal 212 and the forward voltage V in bin 6 is the reflection coefficient in bin 6.f The difference between the reflected voltage and the reflected voltage V r The processor 114 determines the supply voltage as a statistical value, such as the average or median, of the voltage values ​​of the voltage signal 212 in bin 6. The forward voltage V in bin 6 f is stored in the memory device 116 for access by the processor 144. As another example, the processor 114 determines the VSWR for bin 6 as a ratio of the first sum to the second sum. The first sum is the sum of 1 and the magnitude of the reflection coefficient for bin 6, and the second sum is the difference between 1 and the magnitude of the reflection coefficient for bin 6. During bin 6 of cycle (nm), the processor 114 multiplies the fourth offset value of the RF signal 152 with a multiplier M2 to output a high frequency value HF0.5 and operates the HFRF generator 104 at the HF offset value HF0.5 during bin 6. Upon operating the HFRF generator 104 at the HF offset value HF0.5 during bin 6 of cycle (nm) and receiving the parameter during bin 6 of cycle (nm), the processor 114 determines that the parameter has a low value during cycle (nm) compared to the value of the parameter received during cycle (nmp) of the voltage signal 212. The value of the parameter during cycle (nmp) is determined by the processor 114 when the processor 114 controls the HFRF generator 104 to operate at the HF offset value HF(0.75) by applying another multiplier M2' instead of the multiplier M2. In this manner, the processor 114 determines that the value of the parameter during cycle (nm) is lower than the value of the parameter during cycle (nmp), and therefore determines to operate the HFRF generator 104 at the HF offset values ​​HF0.5, HF1, HF1.5, HF1, and HF0.5 determined based on the multiplier M2 instead of the multiplier M2'.

[0063] Additionally, the processor 114 modifies the multiplier M2 in response to changes in plasma conditions. For example, as the ratio of the operating power of the LFRF generator 102 to the operating power of the HFRF generator 104 increases, the value of the multiplier M2 increases. As the ratio of the operating power of the LFRF generator 102 to the operating power of the HFRF generator 104 decreases, the value of the multiplier M2 decreases.

[0064] By applying the multiplier M2 to bins 6 through 10, no determination or measurement of the high frequency reflected power is required to reduce the high frequency reflected power for bins 7 through 10. For example, during each time interval from bins 7 through 10, the processor 114 does not adjust the corresponding offset values, such as the fifth and sixth offset values ​​applied to the reference high frequency value HF0, based on the high frequency reflected power. Rather, the same multiplier M2 is applied to the corresponding offset values ​​between bins 7 through 10 as is applied to the fourth offset value between bins 6. This improves the efficiency of processing the substrate S.

[0065] In this manner, by applying the multipliers, the efficiency of processing the substrate S by the processor 114 is improved. For example, instead of determining nine different HF offset values ​​for bins 1 through 4 and bins 6 through 10, multipliers -M1 and -M2 are determined and applied to the reference high frequency value HF0 in the manner described above. This increases the speed at which the HF offset values ​​can be applied when processing the substrate S.

[0066] The offset value is an offset from the reference high frequency value HF0, and is, for example, a frequency value. For example, the first offset value is determined by the processor 114 by subtracting the first frequency value from the reference high frequency value HF0. As another example, the fourth offset value is determined by the processor 114 by adding the second frequency value to the reference high frequency value HF0. Specifically, the first and second frequency values ​​are stored in the memory device 116 so as to be accessible by the processor 114.

[0067] In one embodiment, the high frequency reflected power is reduced during any of bins 1 to 3 of cycle n, or any of bins 7 to 10 of cycle n, or any combination thereof. Any of bins 1 to 3, or any of bins 7 to 10, or any combination thereof, is an example of a number of pre-set bins. For example, a parameter is determined by the processor 114 for any of bins 1 to 3 in the same manner as a parameter is determined for bin 4. Specifically, the processor 114 determines a parameter for bin 1 based on a voltage value of the voltage signal 212 during bin 1. The processor 114 determines an HF offset value for the operation of the HFRF generator 104 for bin 1 to reduce, e.g., minimize, a parameter associated with the HFRF generator 104 for bin 1. For example, if the HFRF generator 104 is operated at a first HF offset value during bin 1 of cycle (nmp), a first value of the reflection coefficient is determined by the processor 114 based on a first value of the voltage signal 212. Also, during bin 1 of cycle (nm), when the HFRF generator 104 is operated with the second HF offset value, the second value of the reflection coefficient is determined by the processor 114 based on the second value of the voltage signal 212. The processor 114 determines that the second value of the reflection coefficient is less than the first value of the reflection coefficient, and therefore determines to operate the HFRF generator 104 with the second HF offset value during bin 1 of cycle n. Instead of operating the HFRF generator 104 to have an HF offset value HF(-2) based on the multiplier -M1 during bin 1 of cycle n, the HFRF generator 104 is controlled to operate with the second HF offset value that reduces a parameter associated with the HFRF generator 104. The high frequency value HF0 is modified by the processor 114 according to the second HF offset value, and the HFRF generator 104 is controlled according to the second HF offset value. The processor 114 controls the HFRF generator 104 to operate with the second HF offset value during bin 1 of cycle n. For example, recipe signal 144 (FIG. 1) includes a second HF offset value corresponding to bin 1.

[0068] 3B is an embodiment of a graph 310 to illustrate applying different presets to reduce high frequency reflected power instead of controlling the HFRF generator 104 to apply the multipliers −M1 and −M2 during processing of the substrate S. The graph 300 plots the HF offset value of the HFRF generator 104 against time t. The HF offset value is plotted on the same y-axis as the y-axis of the graph 300 (FIG. 3A), and the time t is plotted on the same x-axis as the x-axis of the graph 300. For example, instead of applying the frequency signal 302, the first preset indicated by the frequency signal 352 or the second preset indicated by the frequency signal 354 is applied by the processor 114 to effectively reduce the high frequency reflected power. The processor 114 determines based on the voltage signal 212 that the parameters for one of bin 1 to bin 3 and bin 7 to bin 10 are outside the predetermined range stored in the memory device 116. In so determining, the processor 114 applies the first preset or the second preset multiplier to the high frequency value HF0 of bin 0. The multiplier for the first or second preset is determined by the processor 114 in the same manner as the multipliers -M1 and M2 are determined. The y-axis of the graph 310 has HF offset values ​​ranging from HF(-6) to HF9, with the HF offset values ​​increasing from HF6 to HF9 as described above.

[0069] The first and second presets are stored in the memory device 116 (FIG. 1) so as to be accessible to the processor 114. The first preset is generated by the processor 114 by applying a multiplier, for example, -M3 and M4, different from the multipliers -M1 and M2, to the high frequency value HF0 in the same manner as the multipliers -M1 and M2 are applied to the high frequency value HF0. For example, instead of multiplying the first offset value by the multiplier -M1, the first offset value is multiplied by the multiplier -M3, and instead of multiplying the fourth offset value by the multiplier M2, the fourth offset value is multiplied by the multiplier M4. The multipliers -M3 and M4 are examples of pre-stored multipliers generated by the processor 114 before the multipliers -M1 and M2 are generated. The multipliers -M3 and M4 are stored in the memory device 116 so as to be accessible to the processor 114 to generate the first preset. Similarly, the second preset is generated by the processor 114 by applying a multiplier different from the multipliers -M1 and M2, for example -M5 and M6, to the high frequency value HF0 in the same manner as the multipliers -M1 and M2 are applied to the high frequency value HF0. For example, instead of multiplying the first offset value by the multiplier -M1, the first offset value is multiplied by the multiplier -M5, and instead of multiplying the fourth offset value by the multiplier M2, the fourth offset value is multiplied by the multiplier M6. The multipliers -M5 and M6 are examples of pre-stored multipliers generated by the processor 114 before the multipliers -M1 and M2 are generated. The multipliers -M5 and M6 are stored in the memory device 116 so that the processor 114 can access them to generate the second preset.

[0070] Also, the first preset is applied for a plasma condition 2 that is different from the plasma condition 3 for which the second preset is generated. An example of a plasma condition is the ratio of the operating power of the LFRF generator 102 to the operating power of the HFRF generator 104. In particular, the first preset is applied when the ratio of the operating power of the LFRF generator 102 to the operating power of the HFRF generator 104 has a first value. The second preset is applied when the ratio of the operating power of the LFRF generator 102 to the operating power of the HFRF generator 104 has a second value. The second value is different from the first value. More particularly, the operating power of an RF generator, such as the LFRF generator 102 or the HFRF generator 104, represents the power level of an envelope of an RF signal generated by the RF generator. The envelope is a peak-to-peak amplitude or a zero-to-peak amplitude for a state of the RF signal. The frequency signal 302 is generated for the plasma condition 1.

[0071] The frequency signal 352 includes an HF offset value HF(−2.75) generated by the HFRF generator 104 during bin 1 of cycle n, an HF offset value HF(−1.75) generated by the HFRF generator 104 during bin 2 of cycle n, an HF offset value HF(−0.75) generated by the HFRF generator 104 during bin 3 of cycle n, and an HF offset value HF(−0.75) generated by the HFRF generator 104 during bin 4 of cycle n. The frequency signal 352 also includes a high frequency value HF0 generated by the HFRF generator 104 during bin 5 of cycle n, an HF offset value HF4 generated by the HFRF generator 104 during bin 6 of cycle n, an HF offset value HF6 generated by the HFRF generator 104 during bin 7 of cycle n, and an HF offset value HF8 generated by the HFRF generator 104 during bin 8 of cycle n. Frequency signal 352 includes HF offset value HF4 generated by HFRF generator 104 during bin 9 of cycle n and HF offset value HF2 generated by HFRF generator 104 during bin 10 of cycle n. Value HF0 is generated by HFRF generator 104 during bin 0 of cycle n, so bin 0 is maintained as bin 0 of frequency signal 352. HF offset values ​​for the remaining bins of frequency signal 352 are determined by processor 114 based on the high frequency value HF0 for bin 0.

[0072] The frequency signal 354 also includes a HF offset value HF(1) generated by the HFRF generator 104 during bin 1 of cycle n, a HF offset value HF(-2) generated by the HFRF generator 104 during bin 2 of cycle n, a HF offset value HF(-4) generated by the HFRF generator 104 during bin 3 of cycle n, a HF offset value HF(-3) generated by the HFRF generator 104 during bin 4 of cycle n, a high frequency value HF0 generated by the HFRF generator 104 during bin 5 of cycle n, a HF offset value HF(2) generated by the HFRF generator 104 during bin 6 of cycle n, a HF offset value HF3 generated by the HFRF generator 104 during bin 7 of cycle n, a HF offset value HF3 generated by the HFRF generator 104 during bin 8 of cycle n, a HF offset value HF2 generated by the HFRF generator 104 during bin 9 of cycle n, and a HF offset value HF1 generated by the HFRF generator 104 during bin 10 of cycle n. Because the value HF0 is generated by the HFRF generator 104 during bin 0 of cycle n, bin 0 is also bin 0' of the frequency signal 354. The HF offset values ​​for the remaining bins of the frequency signal 354 are determined by the processor 114 based on the high frequency value HF0 of bin 0.

[0073] Instead of using the parameters to determine an HF offset value between one or more of bin 1 to bin 3, or between one or more of bin 7 to bin 10, or a combination thereof to reduce high frequency reflected power, the processor 114 retrieves the first preset or the second preset from the memory device 116 and applies the HF offset value of the first preset or the second preset to the HFRF generator 104. For example, to apply the first preset during bin 1 of cycle n, the processor 114 controls the HFRF generator 104 to operate with an HF offset value HF(-2.75) instead of operating the HFRF generator 104 with an HF offset value HF(-2). As another example, to apply the second preset during bin 3, the processor 114 controls the HFRF generator 104 to operate with an HF offset value HF(-3) during bin 4 of cycle n instead of operating the HFRF generator 104 with an HF offset value HF(-1). The first or second preset is applied during cycle n. During the cycle (nm) of the clock signal 202 prior to cycle n, the first preset, the second preset, or a combination thereof is determined.

[0074] The processor 114 controls the HFRF generator 104 to operate with the first preset or the second preset HF offset value. For example, the processor 114 transmits the first preset or the second preset HF offset value in the recipe signal 144 (FIG. 1) to the HFRF generator 104 via the transfer cable 120. Upon receiving the first preset or the second preset HF offset value, the HFRF generator 104 generates the RF signal 152 to have the first preset or the second preset HF offset value.

[0075] In one embodiment, the first preset is generated based on multiplier -M1 instead of multiplier -M3, or multiplier M2 instead of multiplier M4.

[0076] In one embodiment, the second preset is generated based on multiplier -M1 instead of multiplier -M5, or based on multiplier M2 instead of multiplier M6.

[0077] 3C illustrates one embodiment of a graph 320 to illustrate that the multiplier applied to the HFRF generator 104 is zero for a portion of cycle n. The graph 320 plots the HF offset value of the HFRF generator 104 (FIG. 1) versus time t. The graph 320 includes a y-axis, which is the same as the y-axis of the graph 310 (FIG. 3B). The graph 320 also includes an x-axis, which is the same as the x-axis of the graph 310.

[0078] The graph 320 includes a frequency signal 330 that is the same as the frequency signal 302 (FIG. 3A) except that the processor 114 (FIG. 1) controls the HFRF generator 104 (FIG. 1) to apply a multiplier of zero during negative cycles of the voltage signal 212 (FIG. 2B). For example, instead of controlling the HFRF generator 104 to reduce the high frequency reflected power, the processor 114 controls the HFRF generator 104 to have a HF offset value of zero from the high frequency value HF0 between bins 6 to 10. In particular, the processor 114 controls the HFRF generator 104 to have a HF offset value of zero from the high frequency value HF0 between bins 6 to 10. More particularly, the processor 114 transmits the recipe signal 144 having a high frequency reference value HF0 between bins 6 to 10. The high frequency reference value HF0 is generated by multiplying the corresponding offset value, e.g., the fourth to sixth offset values, for bins 6 to 10 by a multiplier M2, which is zero. The high frequency reference value HF0 is transmitted to the HFRF generator 104 via the transfer cable 120 (FIG. 1). When the multiplier M2 is zero, a zero HF offset value is applied to the high frequency value HF0, so that the high frequency value HF0 is presented to the HFRF generator 104. The recipe signal 144 is transmitted to the HFRF generator 104, causing the HFRF generator 104 to operate with the high frequency value HF0 to the zero HF offset value from bin 6 to bin 10 of cycle n. Upon receiving the recipe signal 144, the HFRF generator 104 generates an RF signal 152 (FIG. 1) having a high frequency value HF0 to the zero HF offset value from bin 6 to bin 10 of cycle n.

[0079] As another example, instead of controlling the HFRF generator 104 to reduce the high frequency reflected power, the processor 114 controls the HFRF generator 104 to have a high frequency offset value of zero from the high frequency value HF0 during bin 1 to bin 4. In particular, the processor 114 transmits the recipe signal 144 having a high frequency reference value HF0 during bin 1 to bin 4. The high frequency reference value HF0 is generated by multiplying the corresponding offset value, e.g., the first to third offset values, for bin 1 to bin 4 by a multiplier -M1, which is zero. The high frequency reference value HF0 is transmitted to the HFRF generator 104 via the transmission cable 120. When the multiplier -M1 is zero, a zero HF offset value is applied to the high frequency value HF0, so that the high frequency value HF0 is presented to the HFRF generator 104. The recipe signal 144 is transmitted to the HFRF generator 104, and the HFRF generator 104 operates from the high frequency value HF0 to the zero HF offset value during bin 1 to bin 4 of cycle n. Upon receiving the recipe signal 144, the HFRF generator 104 generates an RF signal 152 (FIG. 1) having a HF offset value from high frequency value HF0 to zero during bin 1 to bin 4 of cycle n. In this manner, the processor 114 controls the HFRF generator 104 to have a HF offset value from high frequency value HF0 to zero during the positive cycles of the voltage signal 212.

[0080] By controlling the HFRF generator 104 to have a zero HF offset value from the high frequency value HF0 using a zero multiplier during a portion of cycle n, the control of the high frequency value of the HFRF generator 104 can be made efficient, for example, without the need to determine a multiplier −M1 or −M2 that reduces the high frequency reflected power.

[0081] In one embodiment, the processor 114 controls the HFRF generator 104 to have a HF offset value from high frequency value HF0 to zero during any portion of cycle n of the clock signal 202, such as from bin 3 to bin 7.

[0082] 4A is one embodiment of a graph 400 to illustrate a clock signal 402. The clock signal 402 is different from the clock signal 202 (FIG. 2A) described above. The x-axis of the graph 400 plots time t from time t0 to time t160. The y-axis of the graph 400 plots the voltage of the clock signal 402. The clock signal 402 is generated by the processor 114 (FIG. 1).

[0083] The clock signal 402 periodically transitions between logic levels 1 and 0. The clock signal 402 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t40. At time t40, the clock signal 402 transitions from logic level 1 to logic level 0 and remains at logic level 0 from time t40 to time t80. The transitions between logic levels 1 and 0 are repeated from time t80 to time t160. The transitions between logic levels 1 and 0 of the clock signal 402 are generated by the processor 114 and provided to the LFRF generator 102 in the recipe signal 142 (FIG. 1).

[0084] 4B is one embodiment of a graph 420 illustrating the power of an RF signal 422 generated by LFRF generator 102 (FIG. 1). RF signal 422 is an example of RF signal 150 (FIG. 1) generated and provided by LFRF generator 102. Graph 420 plots an envelope 424 of the power of RF signal 422 versus time t. Time t is plotted on the same x-axis as the x-axis of graph 400 (FIG. 4A). Envelope 424 is plotted relative to the y-axis of graph 420. The y-axis plots amounts of power ranging from -P6 to zero to zero to P6, where the amount of power increases from -P6 to P6. For example, the amount of power -P5 is greater than the amount of power -P6, which is greater than the amount of power -P4, and so on.

[0085] The envelope 424 relates to the power of the RF signal 422. For example, the envelope 424 is the peak-to-peak amplitude of the power of the RF signal 422. The envelope 424 periodically transitions between states S1 and S0 of the RF signal 422 in synchronization with the clock signal 402. For example, the envelope 424 transitions from power level P3 to power level P6 and from power level -P3 to power level -P6 at time t0, and maintains power levels P6 and -P6 from time t0 to time t40. The power levels P6 and -P6 represent the state S1 of the RF signal 422. The envelope 424 transitions from power level P6 to power level P3 and from power level -P6 to power level -P3 during the period from time t36 to time t40, forming a transition state TS1 of the RF signal 422. The envelope 424 maintains the power levels P3 and -P3 from time t40 to time t80, forming a state S0 of the RF signal 422. The envelope 424 transitions from power level P3 to power level P6 and from power level -P3 to power level -P6 during the period from time t76 to time t80, forming a transition state TS2 of the RF signal 422. Thus, the power levels P6 and -P6, P3 and -P3 are repeated from time t80 to time t160. The power levels of the RF signal 422 also represent the states of the RF signal 422, such as S1 and S0. The transitions between logic levels 1 and 0 of the clock signal 402 are generated by the processor 114 and provided to the LFRF generator 102 within the recipe signal 142 (FIG. 1) to facilitate the RF signal 422 transitioning in synchronization with the clock signal 402.

[0086] The steady state of the RF signal 422 occurs during a period when the RF signal 422 does not transition from one state to another, and the transition state of the RF signal 422 occurs during a period when the RF signal 422 transitions from one state to another. For example, the first steady state is state S1 of the RF signal 422, and the second steady state is state S0 of the RF signal 422. State S1 occurs during a first period from time t0 to time t36, and state S0 occurs during a second period from time t40 to time t76. Each of the first period and the second period is an adjustment window. As an example, the first transition state TS1 is the state of the RF signal 422 during a period from time t36 to time t40, and the second transition state TS2 is the state of the RF signal 422 during a period from time t76 to time t80. In a first transition state, the RF signal 422 transitions from state S1 to state S0, and in a second transition state, the RF signal 422 transitions from state S0 to state S1. As an example, the power value of the RF signal 422 changes more frequently during the transition state compared to the changes in the power value of the RF signal 422 during the steady state. As another example, during the transition state, the changes in the power level of the RF signal 422 state may have a positive or negative slope. In the steady state, the slope of the power level is zero or substantially zero.

[0087] In one embodiment, the RF signal 422 is replaced by another RF signal generated by the HFRF generator 104 (FIG. 1). The other RF signal is an example of the RF signal 152 (FIG. 1) generated by the HFRF generator 104. The other RF signal transitions from state S1 to state S0 and from state S0 to state S1 in synchronization with the clock signal 402 in the same manner that the RF signal 422 transitions between states S1 and S0. During state S1, the other RF signal has a greater power level compared to the power level of the other RF signal during state S0. The transitions between logic levels 1 and 0 of the clock signal 402 are generated by the processor 114 and provided to the HFRF generator 104 in the recipe signal 144 (FIG. 1) to facilitate the other RF signal transitioning in synchronization with the clock signal 402.

[0088] In one embodiment, both RF signals 150 and 152 periodically transition between corresponding states S1 and S0 in synchronization with clock signal 402.

[0089] 4C is one embodiment of a graph 430 to illustrate that a multiplier is applied to an offset value to determine the HF offset value of the HFRF generator 104 (FIG. 1) during a hold-off period and is applied during a frequency tuning period. The hold-off period is indicated by a diagonal line in graph 420 (FIG. 4B). Graph 430 plots the HF offset value for a high frequency value HF0 of the HFRF generator 104 versus time t. The HF offset value of the HFRF generator 104 is plotted on the y-axis, which is the same as the y-axis of graph 300 (FIG. 3A). Time t is plotted on the x-axis, which is the same as the x-axis of graph 300.

[0090] The processor 114 controls the HFRF generator 104 to operate at a high frequency value HF0 to a HF offset value during a steady state of the RF signal 422 (FIG. 4B), such as states S1 and S0, and to operate at a high frequency value HF0 to a HF offset value during transition states TS1 and TS2 of the RF signal 422. A multiplier is also applied during transition states TS1 and TS2. For example, the processor 114 transmits a recipe signal 144 to the HFRF generator 104, which includes the duration of the steady state of the RF signal 422 to be generated, the duration of transition states TS1 and TS2 of the RF signal 422, the HF offset value of the frequency signal 302 during steady state S1, the HF offset value of the frequency signal 432 during steady state S0, the HF offset value of the frequency signal 302 during a first transition state TS1, and the HF offset value of the frequency signal 432 during a second transition state TS2. The transition states TS1 and TS2, and the frequency signal 432 are described below.

[0091] During state S1, processor 114 controls HFRF generator 104 to have an HF offset value as indicated by frequency signal 302, and during transition state TS1, processor 114 controls the operating frequency of HFRF generator 104 to have the HF offset value of frequency signal 302. For example, during transition state TS1, processor 114 controls the operating frequency of HFRF generator 104 to have the HF offset value of frequency signal 302 during transition state TS1.

[0092] The processor 114 controls the HFRF generator 104 to have an HF offset value as indicated by the frequency signal 432 during state S0 of the RF signal 422, and controls the HFRF generator 104 to have the HF offset value of the frequency signal 432 during transition state TS2. For example, during transition state TS2, the processor 114 controls the operating frequency of the HFRF generator 104 to have the HF offset value of the frequency signal 432 during transition state TS2. The processor 114 controls the HFRF generator 104 to have the HF offset value of the frequency signal 432 in a manner similar to how the processor 114 controls the HFRF generator 104 to have the HF offset value of the frequency signal 302.

[0093] The processor 114 also controls the HFRF generator 104 to have an HF offset value from the high frequency value HF0 based on a first multiplier set during state S1 and transition state TS1 of the RF signal 422, and to have an HF offset value from the high frequency value HF0 based on a second multiplier set during state S0 and transition state TS2 of the RF signal 422. At least one multiplier of the first set is different from at least one multiplier of the second set. For example, multipliers -M1 and M2 are used during steady state S1 and transition state TS1 of the RF signal 422, and multipliers -M7 and M8 are used during steady state S0 and transition state TS2 of the RF signal 422. The processor 114 applies multipliers -M1 and M2 to operate the HFRF generator 114 based on the multipliers -M1 and M2 during state S1 and transition state TS1 of the RF signal 422, similarly to applying multipliers -M7 and M8 to operate the HFRF generator 114 based on the multipliers -M7 and M8 during state S0 and transition state TS2 of the RF signal 422. For example, the multipliers -M7 and M8 are applied to determine the HF offset value of the frequency signal 432.

[0094] However, in transition states TS1 and TS2, the multipliers -M1, M2, -M7, and M8 are not determined based on the parameters. For example, during transition state TS1, the processor 114 does not determine a multiplier -M1 to reduce, e.g., minimize, a parameter associated with the HFRF generator 104 for bin 4. As another example, during transition state TS1, the processor 114 does not determine a multiplier M2 to reduce a parameter associated with the HFRF generator 104 for bin 6. Rather, the same multipliers -M1 and M2 determined for steady state S1 are used for transition state S1. As yet another example, during transition state TS2, the processor 114 does not determine a multiplier -M7 to reduce a parameter associated with the HFRF generator 104 for bin 4. As another example, during transition state TS2, the processor 114 does not determine a multiplier M8 to reduce a parameter associated with the HFRF generator 104 for bin 6. Rather, the same multipliers -M7 and M8 determined for steady state S0 are used for transition state TS2.

[0095] During a transition state of the RF signal 422, the processor 114 adjusts or applies the frequency of the HFRF generator 104. For example, during a transition state of the RF signal 422, the processor 114 performs a combination of bin frequency adjustment and pyramid adjustment during the transition state of the RF signal 422 to reduce high frequency reflected power. In particular, during a transition state, the processor 114 controls the HFRF generator 104 to adjust or apply offset values ​​to perform pyramid adjustment. In particular, during a transition state of the RF signal 422, the processor 114 controls the HFRF generator 104 to modify offset values ​​between bin 1 to bin 4 and bin 6 to bin 10 to apply pyramid adjustment. The offset values ​​between bin 1 to bin 4 and bin 6 to bin 10, if modified, are modified to reduce parameters between these bins. As another example, during a transition state of the RF signal 422, the processor 114 controls the HFRF generator 104 to operate with HF offset values ​​determined based on any multipliers described herein.

[0096] In one embodiment, the processor 114 applies multipliers -M7 and M8 instead of multipliers -M1 and M2 during transition state TS1 and operates the HFRF generator 114 based on the multipliers -M7 and M8 during transition state TS1.

[0097] In one embodiment, the processor 114 applies the multipliers -M1 and M2 instead of the multipliers -M7 and M8 during the transition state TS2 and operates the HFRF generator 114 based on the multipliers -M1 and M2 during the transition state TS2.

[0098] The embodiments described herein may be practiced with a variety of computer system configurations including handheld hardware units, microprocessor systems, microprocessor-based or program-controlled consumer electronics, minicomputers, mainframe computers, etc. The embodiments described herein may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0099] In some implementations, the controller is part of a system that may be part of the examples described above. The system may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). The system may be integrated with electronics to control its operation before, during, and after processing of a semiconductor wafer or substrate. The electronics are referred to as a "controller" that may control various components or subparts of the system. The controller is programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and motion settings, wafer loading and unloading to and from the tool, and wafer loading and unloading to and from other transport tools and / or load locks connected or interlocked with the system, depending on the processing requirements and / or type of system.

[0100] In general, a controller is defined in various embodiments as an electronic device having various integrated circuits, logic, memory, and / or software to receive and issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits include chips in firmware form that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing processing on or in connection with semiconductor wafers. In some embodiments, the operational parameters are part of a recipe defined by a process engineer to accomplish one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0101] In some embodiments, the controller is part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may reside in the "cloud" or provide remote access as all or part of a fab host computer system to process wafers. The controller provides remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, examine trends or performance metrics from multiple manufacturing operations, and modify parameters of a current process, set up processing steps to follow a current process, or initiate a new process.

[0102] In some embodiments, a remote computer (e.g., a server) can provide process recipes to the system over a computer network, including a local network or the Internet. The remote computer includes a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of settings for processing the wafer. It can be understood that the settings are specific to the type of process to be performed on the wafer and the type of tool the controller interfaces with or controls. Thus, as described above, the controller can be distributed, such as with one or more discrete controllers, which are networked together and operate with a common purpose, such as performing the processes described herein. An example of a distributed controller for such purposes is one or more integrated circuits on the chamber that can communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of the remote computer), which are combined to control the processes on the chamber.

[0103] Non-limiting examples of plasma systems described in various embodiments include plasma etch chambers, deposition chambers, spin rinse chambers, metal plating chambers, clean chambers, bevel etch chambers, physical vapor deposition (PVD) chambers, chemical vapor deposition (CVD) chambers, atomic layer deposition (ALD) chambers, atomic layer etch (ALE) chambers, ion implantation chambers, track chambers, and any other semiconductor processing chambers related to or usable in the fabrication and / or manufacturing of semiconductor wafers.

[0104] It is noted that although the above operations are described with reference to a parallel plate plasma chamber, such as a CCP chamber, in some embodiments, the above operations also apply to other types of plasma chambers, such as an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, a plasma chamber including a conductor tool, a dielectric tool, an electron cyclotron resonance (ECR) reactor, etc. For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor in an ICP plasma chamber.

[0105] As described above, depending on the processing operations being performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a main computer, another controller, or tools used to transport materials to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0106] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations with data stored in computer systems. These computer-implemented operations manipulate physical quantities.

[0107] Some embodiments also relate to hardware units or devices for performing these operations. An apparatus is specifically configured for a special purpose computer. When defined as a special purpose computer, it is capable of performing operations for that special purpose, but also performs other processes, program execution or routines that are not part of the special purpose.

[0108] In some embodiments, the operations described herein are executed by a selectively activated computer, constituted by one or more computer programs stored in a computer memory, or obtained over a computer network. If data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0109] One or more embodiments described herein may also be fabricated as computer readable code on a non-transitory computer readable medium. The non-transitory computer readable medium is any data storage hardware unit, such as a memory device, that stores data, and the stored data is read by a computer system. Examples of non-transitory computer readable media include hard disks, network attached storage (NAS), ROM, RAM, compact disk ROMs (CD-ROMs), recordable CDs (CD-Rs), rewritable CDs (CD-RWs), magnetic tapes, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer readable medium includes computer readable tangible media distributed over network-coupled computer systems, allowing the storage and execution of the computer readable code in a distributed fashion.

[0110] Although some of the method operations described above are shown in a particular order, it will be appreciated that in various embodiments, other housekeeping operations may be performed between the method operations, the method operations may be coordinated to occur at slightly different times, the occurrence of the method operations may be distributed within the system to occur at various intervals, and may also occur in orders different than those described above.

[0111] It should be further noted that in one embodiment, one or more features of any of the above-described embodiments may be combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in this disclosure.

[0112] Although the above embodiments have been described in detail for a clearer understanding, it is apparent that certain changes and modifications are possible within the scope of the appended claims. Therefore, it should be recognized that the present embodiments are merely illustrative and not restrictive, and should not be limited to the details set forth herein, but may be modified within the scope of the appended claims and their equivalents.

Claims

1. 1. A method for reducing reflected radio frequency (RF) power, comprising: receiving a voltage signal from an output of a match coupled to a low frequency (LF) RF generator and a high frequency (HF) RF generator; Dividing the voltage signal into a number of bins; identifying a first bin from the plurality of bins that includes a zero crossing, the first bin being associated with a frequency of the HFRF signal generated by the HFRF generator; applying a first fixed multiplier to the frequency of the HFRF signal to generate a first plurality of negative offsets; applying a second fixed multiplier to the frequency of the HFRF signal to generate a first plurality of positive offsets; operating the HFRF generator according to the first plurality of negative offsets during periods when the voltage signal is positive; operating the HFRF generator according to the first plurality of positive offsets during periods when the voltage signal is negative; A method for providing the above.

2. 10. The method of claim 1 further comprising: receiving a parameter indicative of an amount of power reflected back toward the HFRF generator for a second bin of the plurality of bins; determining the first fixed multiplier based on the parameters; A method for providing the above.

3. 10. The method of claim 1 further comprising: receiving a parameter indicative of an amount of power reflected back toward the HFRF generator for a second bin of the plurality of bins; determining the second fixed multiplier based on the parameter to output a modified frequency.

4. 10. The method of claim 1 further comprising: identifying a pre-stored multiplier when the parameter is determined to be outside a predetermined range for a second bin of the plurality of bins; applying a pre-stored multiplier, instead of the first fixed multiplier, to the frequencies associated with the first bin to generate a second plurality of negative offsets; operating the HFRF generator according to the second plurality of negative offsets during periods when the voltage signal is positive; A method for providing the above.

5. 10. The method of claim 1 further comprising: identifying a pre-stored multiplier when the parameter is determined to be outside a predetermined range for a second bin of the plurality of bins; applying the pre-stored multiplier in place of the second fixed multiplier to the frequencies associated with the first bin to generate a second plurality of positive offsets; operating the HFRF generator according to the second plurality of positive offsets during periods when the voltage signal is negative; A method comprising:

6. 2. The method of claim 1, wherein the first fixed multiplier or the second fixed multiplier is zero.

7. 2. The method of claim 1, wherein operating the HFRF generator in accordance with the first plurality of negative offsets and operating the HFRF generator in accordance with the first plurality of positive offsets occur during a steady state period of the HFRF signal.

8. 2. The method of claim 1, wherein operating the HFRF generator in accordance with the first plurality of negative offsets and operating the HFRF generator in accordance with the first plurality of positive offsets occur during a state transition of an LFRF signal generated by the LFRF generator.

9. 2. The method of claim 1, wherein at least one of the first multiplier and the second multiplier for a first state of the LFRF signal generated by the LFRF generator is different from at least one of a third multiplier and a fourth multiplier for a second state of the LFRF signal.

10. 1. A controller for reducing reflected radio frequency (RF) power, comprising: receiving a voltage signal from an output of a match coupled to a low frequency (LF) RF generator and a high frequency (HF) RF generator; Dividing the voltage signal into a number of bins; identifying a first bin from the plurality of bins that includes a zero crossing, the first bin being associated with a frequency of the HFRF signal generated by the HFRF generator; applying a first fixed multiplier to the frequency of the HFRF signal to generate a first plurality of negative offsets; applying a second fixed multiplier to the frequency of the HFRF signal to generate a first plurality of positive offsets; operating the HFRF generator according to the first plurality of negative offsets during periods when the voltage signal is positive; a processor configured to operate the HFRF generator in accordance with the first plurality of positive offsets during periods when the voltage signal is negative; a memory device coupled to the processor; A controller comprising:

11. 11. The controller of claim 10, The processor, receiving a parameter indicative of an amount of power reflected back toward the HFRF generator for a second bin of the plurality of bins; A controller configured to determine the first fixed multiplier based on the parameter.

12. 11. The controller of claim 10, wherein the processor: receiving a parameter indicative of an amount of power reflected back toward the HFRF generator for a second bin of the plurality of bins; A controller configured to determine the second fixed parameter based on the parameter.

13. 11. The controller of claim 10, wherein the processor: identifying a pre-stored multiplier when the parameter is determined to be outside a predetermined range for a second bin of the plurality of bins; applying a pre-stored multiplier instead of the first fixed multiplier to the frequencies associated with the first bin to generate a second plurality of negative offsets; A controller configured to operate the HFRF generator in accordance with the second plurality of negative offsets during periods when the voltage signal is positive.

14. 11. The controller of claim 10, The processor, identifying a pre-stored multiplier when the parameter is determined to be outside a predetermined range for a second bin of the plurality of bins; applying the pre-stored multiplier in place of the second fixed multiplier to the frequencies associated with the first bin to generate a second plurality of positive offsets; a controller configured to operate the HFRF generator according to the second plurality of positive offsets during periods when the voltage signal is negative.

15. 11. The controller of claim 10, wherein the first fixed multiplier or the second fixed multiplier is zero.

16. 11. The controller of claim 10, wherein the HFRF generator is operated during a steady state period of the HFRF signal in accordance with the first plurality of negative offsets and the first plurality of positive offsets.

17. 11. The controller of claim 10, wherein the HFRF generator is operated during a state transition of the HFRF signal in accordance with the first plurality of negative offsets and the first plurality of positive offsets.

18. 11. The controller of claim 10, wherein at least one of the first multiplier and the second multiplier for a first state of an LFRF signal is different from at least one of a third multiplier and a fourth multiplier for a second state of the LFRF signal.

19. 1. A plasma system for reducing reflected radio frequency (RF) power, comprising: a low frequency (LF) RF generator configured to generate a LF RF signal; a high frequency (HF) RF generator configured to generate a HF RF signal; a match coupled to the LFRF generator and the HFRF generator, the match configured to receive the LFRF signal and the HFRF signal and to output a modified RF signal; a controller coupled to the LFRF generator, the HFRF generator, and the match; The controller: receiving a voltage signal from an output of the match; Dividing the voltage signal into a number of bins; identifying a bin from the plurality of bins that includes a zero crossing, the bin being associated with a frequency of the HFRF signal generated by the HFRF generator; applying a first fixed multiplier to the frequency of the HFRF signal to generate a plurality of negative offsets; applying a second fixed multiplier to the frequency of the HFRF signal to generate a plurality of positive offsets; operating the HFRF generator according to the plurality of negative offsets during periods when the voltage signal is positive; the plasma system being configured to operate the HFRF generator according to the plurality of positive offsets during periods when the voltage signal is negative.

20. 20. The plasma system of claim 19, the HFRF generator is operated during a steady state period of the LFRF signal in accordance with the plurality of negative offsets and the plurality of positive offsets; The plasma system wherein the HFRF generator is operated during state transitions of the LFRF signal in accordance with the plurality of negative offsets and the plurality of positive offsets.

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