Systems and methods for reducing variability in substrate characteristics - Patents.com

Abstract

A method for reducing variability between features of a substrate is described. The method includes generating a radio frequency (RF) signal by a single RF generator. The method further includes modifying the RF signal by the single RF generator to alternate between three or four states for a period of time.

Description

[Technical field]

[0001] The embodiments described in this disclosure relate to systems and methods for reducing variability in characteristics of a substrate. [Background technology]

[0002] The background discussion provided herein is intended to generally present the background of the present disclosure. The work of the presently named inventors, to the extent that their work is described in this background section, is not admitted explicitly or implicitly as prior art to the present disclosure, as are aspects of the description that may not otherwise be considered prior art at the time of filing.

[0003] One or more radio frequency (RF) generators generate one or more RF signals and provide the RF signals to a plasma reactor. The plasma reactor has a semiconductor wafer that is etched when the one or more RF signals are provided and an etchant gas is provided to the plasma reactor. The semiconductor wafer includes multiple features. When the RF signals are provided, the features are not etched uniformly.

[0004] It is in this context that the embodiments described in this disclosure are made. Summary of the Invention

[0005] The embodiments of the present disclosure provide a system and method for reducing the variability in the characteristics of a substrate. It should be appreciated that the embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a piece of hardware, or a method, on a computer-readable medium. Some embodiments are described below.

[0006] As the semiconductor industry aggressively scales pitch and aspect ratios increase, some etch processes struggle with various issues when etching dielectric layers under patterned hard masks. Issues such as recess loading, profile control, mask shape control, underetch, and feature-to-feature variation occur. Etching these dielectric layers is further constrained because the addition of bias power can lead to high mask loss and selectivity tradeoffs. Two-state pulsing using a radio frequency (RF) generator can provide control of ion energy and neutral density over a continuous wave (CW) or process. However, sometimes two-state pulsing is insufficient to etch some stacks with reduced pitch and high aspect ratios in the dielectric layers.

[0007] In one embodiment, the method described herein involves using three-state or four-state RF pulsing with a single frequency and a single generator. By using a three-state pulse etch, recess loading, profile, and mask shape control issues are overcome.

[0008] The systems and methods described herein significantly expand the process window and capabilities for etching dielectric layers, such as carbon layers, nitride layers, and low-k dielectric layers, under thin hard masks, where k is the dielectric constant. The systems and methods described herein allow additional control of ion energy and neutral or radical flux in etches that cannot tolerate high bias or low frequency. The systems and methods address challenges of feature-to-feature recess loading, feature-to-feature CD variation, mask shape control, and underetching.

[0009] In one embodiment, a method for reducing variability between features of a substrate is described that includes generating an RF signal that alternates between three or four states for a period of time.

[0010] In one embodiment, a controller for reducing variability between features of a substrate is described. The controller includes a processor that controls an RF generator to generate an RF signal. The RF signal alternates between three or four states for a period of time. The controller includes a memory device coupled to the processor.

[0011] In one embodiment, a plasma system is described. The plasma system includes an RF generator that generates an RF signal. The plasma system further includes a matcher coupled to the RF generator and a plasma chamber coupled to the matcher. The plasma system includes a controller coupled to the RF generator. The controller controls the RF generator to generate the RF signal. The RF signal alternates between three states for a period of time.

[0012] Some advantages of the systems and methods described herein include reducing variability in features of a first substrate. By applying a set of three conditions to the first substrate, the variability is reduced. Also, the variability in bars is reduced. Each bar is the distance between two consecutive features.

[0013] Additional advantages of the systems and methods described herein include continuing to reduce variability when a second substrate having a greater depth than the first substrate is used. By applying a set of three conditions followed by a set of four conditions to the second substrate, variability is reduced.

[0014] In one embodiment, instead of applying a set of three states followed by a set of four states to reduce variability in features, a set of four states is always applied. For example, a set of four states is applied instead of a set of three states when the mask opening CD of the patterned hard mask decreases. When the mask opening CD decreases, the aspect ratio of the features increases.

[0015] It should be noted that the number of states applied depends on one or more of a variety of factors, such as the depth of the substrate, the aspect ratio of the features, the mask CD, the mask shape, and the mask hardness, etc. For example, a softer mask is more likely to deform, in which case one or two states are applied to etch and shape the mask openings.

[0016] Certain other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0017] The embodiments will be understood by reference to the following description in conjunction with the accompanying drawings, in which it should be noted that some of the drawings are not to scale. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 illustrates an embodiment of a system for illustrating a radio frequency (RF) generator for processing a substrate.

[0019] [Figure 2A] 2 is an embodiment of a graph to illustrate multiple sets of states of an RF signal generated by the RF generator of FIG. 1.

[0020] [Figure 2B] FIG. 2 is an embodiment of a graph to illustrate a clock signal having multiple cycles.

[0021] [Figure 3A] FIG. 2 is a side view of one embodiment of a substrate.

[0022] [Figure 3B] 3B is a side view of one embodiment of a substrate that is the same as the substrate of FIG. 3A after it has been processed.

[0023] [Figure 3C] FIG. 3C is a plan view of an embodiment of a dielectric layer of the substrate of FIG. 3B.

[0024] [Figure 4] FIG. 2 is a diagram of one embodiment of a system for illustrating generation of multiple states of an RF signal generated by the RF generator of FIG.

[0025] [Diagram 5] FIG. 2 is an embodiment of a graph for illustrating multiple sets of RF signal conditions.

[0026] [Figure 6] FIG. 2 is a diagram of one embodiment of a system for illustrating generation of multiple states of an RF signal generated by the RF generator of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The following embodiments describe systems and methods for reducing variability in characteristics of a substrate. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to not unnecessarily obscure the embodiments.

[0028] 1 is a diagram of one embodiment of a system 100 to illustrate a radio frequency (RF) generator 102 for processing a substrate S. The system 100 includes the RF generator 102, a host computer 104, a matcher 106, and a plasma chamber 108. The host computer 104 includes a processor 110 and a memory device 112. The plasma chamber 108 includes a chuck 116, such as an electrostatic chuck (ESC), and an upper electrode 118. One example of the plasma chamber 108 is a capacitively coupled plasma (CCP) chamber.

[0029] Examples of host computers are desktop computers, laptop computers, smartphones, and tablets. An example of the RF generator 102 is a high frequency (HF) RF generator having a high frequency of operation, such as a fundamental frequency of 60 megahertz (MHz). For illustration purposes, the RF generator 102 is not a low frequency (LF) RF generator, such as a 400 kilohertz (kHz) RF generator or a 2 MHz RF generator, or is not an intermediate frequency RF generator, such as a 27 MHz RF generator. As another example, when the RF generator 102 operates at a high frequency of operation, the frequency of the RF signal 130 generated by the RF generator 102 ranges from 57 MHz to 63 MHz.

[0030] As an example, RF generator 102 is a single RF generator. For purposes of illustration, there are no other RF generators coupled to matcher 106 via RF cables. In the example, only RF generator 102 is coupled to matcher 106.

[0031] The high frequency of operation of the HF RF generator may be referred to herein as a single frequency. Also, RF generator 102 may be referred to herein as a single RF generator. For example, during a time period when RF generator 102 is powered on to provide RF signal 130, there are no other RF generators used in system 100 except for RF generator 102. When another, any other RF generator used in system 100 is powered off during that time period, RF generator 102 is powered on to provide RF signal 130. When the other RF generator is powered off, the other RF generator does not generate an RF signal.

[0032] It is difficult to etch a mask layer, such as a thin mask layer, of a substrate S using either a low frequency RF generator or an intermediate frequency RF generator. The low frequency generator and the intermediate frequency generator generate a large amount of power, which results in a large amount of ion energy of the plasma ions in the plasma chamber 108. The large amount of ion energy is not suitable for etching the mask layer. For example, the mask layer cannot be etched by the large amount of ion energy.

[0033] Examples of processors include central processing units (CPUs), microprocessors, application specific integrated circuits (ASICs), and programmable logic devices (PLDs). Examples of memory devices include random access memories (RAMs) and read only memories (ROMs).

[0034] An example of the matcher 106 includes a network of circuit components. For example, the matcher 106 includes a first branch circuit between the input 124 of the matcher 106 and the output 126 of the matcher 106. The branch circuit includes one or more of the circuit components, such as a resistor, a capacitor, and an inductor. For example, the branch circuit includes one or more series circuits and one or more shunt circuits. In this example, each of the series circuits includes one or more of the circuit components, and each of the shunt circuits includes one or more of the circuit components.

[0035] The chuck 116 includes a bottom electrode made from aluminum or an aluminum alloy. Similarly, the top electrode 118 is made from aluminum or an aluminum alloy. The top electrode 118 faces the chuck 116, and a substrate S is placed on the top surface of the chuck 116 for processing. Examples of substrates S include semiconductor wafers on which integrated circuits are fabricated.

[0036] The processor 110 is coupled to the memory device 112. The processor 110 is also coupled to the RF generator 102 via a transfer cable 120. By way of example, the transfer cable may transfer signals using a parallel transfer protocol, a serial transfer protocol, or a Universal Serial Bus (USB) protocol. The RF generator 102 is coupled to an input 124 of the matcher 106 via an RF cable 122. An output 126 of the matcher 106 is coupled to the chuck 116 via an RF transmission line 128.

[0037] The processor 110 generates and sends a recipe signal 126 to the RF generator 102 via the transfer cable 120. The recipe signal 126 includes a frequency of operation of the RF generator 102, a plurality of sets of a plurality of states of the RF signal 130 to be generated by the RF generator 102, a duty cycle of the states, and a time period during which the plurality of sets of states will occur. An example of a state of the RF signal is a power level of the RF signal. For illustration purposes, the state is an envelope of the amplitude of the RF signal. For further illustration purposes, the state is a peak-to-peak amplitude or a zero-to-peak amplitude of the RF signal. After receiving the recipe signal 126, the RF generator 102 generates an RF signal 130 having a set of states according to the time period of the set of states and a duty cycle of those states. The RF generator 102 sends the RF signal 130 to the input 124 of the matcher 106 via the RF cable 122.

[0038] The matcher 106 receives an RF signal 130 at an input 124, matches the impedance of a load coupled to an output 126 to the impedance of a source coupled to the input 124 to modify the impedance of the RF signal 130 and output a modified RF signal 132 at the output 126. An example of a source coupled to the input 124 includes an RF cable 122 and an RF generator 102. An example of a load includes an RF transmission line 128 and a plasma chamber 108. The modified RF signal 132 is sent from the output 126 via the RF transmission line 128 to the lower electrode of the chuck 116.

[0039] When one or more process gases, such as a nitrogen-containing gas, a fluorine-containing gas, and an oxygen-containing gas, are supplied to the gap between the chuck 116 and the upper electrode 118, and when the lower electrode receives the modified RF signal 132, a plasma is struck or maintained in the gap to process the substrate S. Examples of processing the substrate S include depositing one or more materials on the substrate S, etching the substrate S to create features on the substrate S, and cleaning the substrate S.

[0040] 2A is an embodiment of a graph 200 for illustrating a plurality of sets of states of an RF signal 202. The RF signal 202 is an example of an RF signal 130 (FIG. 1). The graph 200 plots the power level of the RF signal 202 versus time t. The power level is plotted on the y-axis and time t is plotted on the x-axis. On the y-axis of the graph 200, the power levels range from a power level P0 to a power level P10. An example of a power level P0 is zero. As an example, the power level P2 ranges from 0 watts (W) to 500 W. For illustrative purposes, the power level P2 is 200 W. Further, as an example, the power level P6 ranges from 100 W to 1500 W. For example, the power level P6 is 500 W. Also, as an example, the power level P10 ranges from 500 W to 5000 W. For illustrative purposes, the power level P10 is 1000 W. The power level increases in the positive y direction on the y-axis of graph 200. For example, the power level increases from P0 to P10. On the x-axis of graph 200, time t increases from time t0 to time t46.

[0041] The RF signal 202 alternates, such as transitioning periodically in a step-down manner, between the three states S3b, S2b, and S1b during the time period between time t0 and time t36. For example, during cycle 1 of the clock signal 212 (FIG. 2B), the RF signal 202 transitions from a zero power level to a power level P10 at time t0 and maintains the power level P10 from time t0 to time t1.5. During cycle 1 of the clock signal 212, the RF signal 202 transitions from power level P10 to power level P6 at time t1.5 and remains at power level P6 from time t1.5 to time t3.

[0042] During cycle 2 of the clock signal 212, the RF signal 202 transitions from power level P6 to power level P2 at time t3 and remains at power level P2 from time t3 to time t6. Power level P10 is state S3b of the RF signal 202, power level P6 is state S2b of the RF signal 202, and power level P2 is state S1b of the RF signal 202. Additionally, the time interval between times t0 and t1.5 is an example of a duty cycle for state S3b, the time interval between times t1.5 and t3 is an example of a duty cycle for state S2b, and the time interval between times t3 and t6 is an example of a duty cycle for state S1b. As an example, the duty cycle of state S3b ranges from 1% to 30%, the duty cycle of state S2b ranges from 5% to 60%, and the duty cycle of state S1b is the difference between 100% and the sum of the duty cycle of state S3b and the duty cycle of state S2b. For illustration purposes, the duty cycle of state S1b ranges from 10% to 94%. States S1b, S2b, and S3b form a set of states of the RF signal 202.

[0043] During cycles 3, 4, 5, and 6 of the clock signal 212, the RF signal 202 repeatedly transitions between the three states S3b, S2b, and S1b in the same manner as it transitioned from time t0 to time t6. For example, the RF signal 202 again transitions between power levels P10, P6, and P2 from time t6 to time t24 in the same manner that the RF signal 202 transitions between power levels P10, P6, and P2 from time t0 to time t6. The RF signal 202 continues to alternate, such as periodically transitioning between states S3b, S2b, and S1b in a step-down manner during the time period between time t24 and time t36.

[0044] It should be noted that the three states S3b, S2b, and S1b during the time period between time t0 and time t24 etch the mask layer of the substrate S and a first portion of the dielectric layer, such as a carbon-based layer or a low-k layer of the substrate S. An example of the first portion of the dielectric layer ranges between 5% and 80% of the dielectric layer. For illustrative purposes, the first portion of the dielectric layer is 50% of the dielectric layer. The dielectric layer is located immediately below the mask layer. Moreover, the states S3b, S2b, and S1b during the time period between time t24 and time t36 etch the remaining portion of the dielectric layer. An example of the remaining portion of the dielectric layer ranges between 20% and 60% of the dielectric layer. For illustrative purposes, the remaining portion of the dielectric layer is 50% of the dielectric layer. The time period between time t0 and time t36 may be referred to herein as a first time period.

[0045] In one embodiment, the three states S3b, S2b, and S1b repeat a first number of times, such as four or five or six times, during the time period between time t0 and time t36.

[0046] In one embodiment, a first power level, such as P10, of the RF signal has a power value, such as a peak-to-peak value or a zero-to-peak value of the power of the RF signal, which are within a preset range of each other. Also, a second power level, such as P6, of the RF signal has a power value, such as a peak-to-peak value or a zero-to-peak value of the power of the RF signal, which are within a preset range of each other. All power values ​​of the first power level do not include the power value of the second power level. For example, there is at least a 10% difference between the maximum power value of the second power level and the minimum power value of the first power level. In this example, the second power level is lower than the first power level. Another example of the first power level is P6, and the second power level is P2.

[0047] In one embodiment, state S2b is a power level between power level P6 and power level P10.

[0048] In one embodiment, state S1b is a power level between power level P2 and power level P6, or between power level P0 and power level P2.

[0049] In one embodiment, state S3b is a power level greater than power level P10, such as power level P11 or power level P12. Power level P12 is greater than power level P11, which is greater than power level P10.

[0050] In one embodiment, at least one state of the RF signal 130, such as continuous wave (CW), etches the mask layer or both the mask layer and the first portion of the dielectric layer of the substrate S. In this embodiment, three states S3b, S2b, and S1b etch the remaining portions of the dielectric layer.

[0051] 2B is one embodiment of a graph 210 to illustrate a clock signal 212 having cycle 1, cycle 2, and so on through cycle 11. The graph 210 plots the logic level, such as voltage, of the clock signal 212 on the y-axis and time t on the x-axis. The y-axis of the graph 210 has logic levels ranging from 0 to 1. Logic level 1 is greater than logic level 0. The processor 110 (FIG. 1) generates the clock signal 212 and sends the clock signal 212 to the RF generator 102 (FIG. 1) via the transmission cable 120 (FIG. 1) to synchronize the repetition of each set of states with the transitions of the clock signal 212. For example, states S3b, S2b, and S1b repeat at time t6 for a second time during the time period between times t6 and t12. As another example, states S3b, S2b, and S1b repeat for a third time at time t12, and for a third time during the time period between time t12 and time t18.

[0052] During cycle 1, clock signal 212 transitions from logic level 0 to logic level 1 at time t0 and maintains logic level 1 from time t0 to time t2. Also during cycle 1, clock signal 212 transitions from logic level 1 to logic level 0 at time t2 and maintains logic level 0 from time t2 to time t4. Logic levels 1 and 0 repeat in the same manner during each of cycles 2-11 as during cycle 1.

[0053] 3A is a side view of one embodiment of a substrate 300, which is an example of substrate S. Substrate 300 includes a mask layer 302, a dielectric layer 304, and a dielectric layer 306. Dielectric layer 304 is located immediately below mask layer 302, and dielectric layer 306 is located immediately below dielectric layer 304.

[0054] An example of the mask layer 302 is a layer made of a combination of silicon and carbon or a combination of silicon oxide and carbon. Another example of the mask layer 302 is a layer including photoresist, or silicon, or silicon dioxide (SiO2), or silicon nitride (SiN), or silicon oxynitride (SiON), or titanium nitride (TiN), or titanium oxide (TiO), or a combination of two or more thereof. By way of example, the mask layer 302 has a height ranging from 90 nanometers (nm) to 130 nm. For illustrative purposes, the mask layer 302 has a height of 110 nm.

[0055] The mask layer 302 includes multiple mask sublayers, such as a first mask sublayer and a second mask sublayer. As an example, the first mask sublayer has a different orientation of the pattern compared to the orientation of the pattern of the second mask sublayer. For example, the pattern of the second mask sublayer is angled relative to the pattern of the first mask sublayer.

[0056] An example of the dielectric layer 304 is one that includes a combination of carbon, hydrogen, oxygen, and nitrogen. As another example, the dielectric layer 304 is a carbon-based layer that includes carbon and one or more of hydrogen, oxygen, and nitrogen. As yet another example, the dielectric layer 304 is made of silicon, or SiON, or is a silicon-doped layer. As yet another example, the dielectric layer 304 is a low-k dielectric layer, such as a SiN layer or another nitride layer, where k is the dielectric constant. As an example, the dielectric layer 304 has a height ranging from 150 nm to 250 nm. For illustrative purposes, the dielectric layer 304 has a height of 200 nm.

[0057] An example of the dielectric layer 306 is an oxide-based layer. Another example of the dielectric layer 306 is a layer made of silicon, or a layer made of SiN, or a layer made of SiON, or a silicon-doped layer.

[0058] The layer height is measured vertically along the y-axis. The layer breadth is measured along the z-axis, and the layer width is measured along the x-axis. The x-axis is perpendicular to the y-axis, and the y-axis is perpendicular to the z-axis. The x-axis is also perpendicular to the z-axis. The layer height is sometimes referred to herein as the layer depth.

[0059] The states S3b, S2b, and S1b (FIG. 2A) of the RF signal 202 etch the mask layer 302 and the first portion of the dielectric layer 304 during a time period between time t0 and time t24. Moreover, the states S3b, S2b, and S1b of the RF signal 202 etch the remaining portion of the dielectric layer 304 during a time period between time t24 and time t36. The remaining portion of the dielectric layer 304 extends from the first portion of the dielectric layer 304 to the dielectric layer 306, and the first portion of the dielectric layer 304 extends from the mask layer 302 to the remaining portion of the dielectric layer 304. The first portion of the dielectric layer 304 is located below and adjacent to the mask layer 302, and the remaining portion of the dielectric layer 304 is located below and adjacent to the first portion of the dielectric layer 304. The dielectric layer 306 is located below the dielectric layer 304. The dielectric layer 306 is etched by a modified RF signal generated by a combination of the RF signal 130 and the LF RF signal generated by the LF RF generator.

[0060] When used, the LF RF generator is coupled to the additional input of the matcher 106 via an additional RF cable. The LF RF generator generates and sends an LF RF signal to the additional input of the matcher 106. The matcher 106 further includes a second branch circuit coupled between the additional input and the output 126. The second branch circuit is coupled to the additional input and the output 126. The second branch circuit includes one or more of the circuit components. The second branch circuit receives the LF RF signal and matches the impedance of the load to the impedance of the source coupled to the additional input to modify the impedance of the LF RF signal and output the additional modified RF signal. An example of a source coupled to the additional input includes an additional RF cable and an LF RF generator. The modified RF signal 132 (FIG. 1) and the additional modified RF signal are combined, such as summed or added, at the output 126 of the matcher 106 to output a combined modified RF signal. The combined modified RF signal is sent from an output 126 of the matcher 106 via an RF transmission line 128 to a lower electrode of the chuck 116 (FIG. 1) for processing the substrate S.

[0061] It should be noted that during the first time period when the mask layer 302 and the dielectric layer 304 are etched, the LF RF generator is turned off. For example, the processor 110 sends a recipe signal indicating a zero power level to the LF RF generator during the first time period. Upon receiving the recipe signal, the LF RF generator does not generate an LF RF signal and does not provide an LF RF signal to the matcher 106. When the dielectric layer 306 is to be etched, the LF RF generator is turned on to generate an LF RF signal having a positive power level. As another example, during the first time period when the LF RF generator is turned off, a single RF generator 102 is used.

[0062] 3B is a side view of an embodiment of a substrate 350 that is the same as substrate 300 after it has been processed. Substrate 350 includes mask layer 302 and dielectric layer 354. Mask layer 302 has features, such as trenches, etched therein. Some of the features are shown as features 356A and 356B. Additionally, dielectric layer 354 is the same as dielectric layer 304, except that dielectric layer 354 has features etched therein. The features are created by RF signal 130 (FIG. 1). Dielectric layer 354 has a bottom surface 358 adjacent to top surface 360 ​​of dielectric layer 306.

[0063] In one embodiment, each substrate 300 and 350 excludes the mask layer 302 .

[0064] In one embodiment, the substrate 300 includes a mask layer that is not etched to have features.

[0065] 3C is a plan view of one embodiment of dielectric layer 306 having features. For example, top surface 360 ​​of dielectric layer 306 has feature 362A and feature 362B formed therein. Note that each feature extends through mask layer 302 (FIG. 3A) and dielectric layer 304 (FIG. 3A) and extends slightly into the top surface of dielectric layer 306. The features in the plan view of dielectric layer 306 also represent a plan view of bottom surface 358 (FIG. 3B) of dielectric layer 354 (FIG. 3B).

[0066] There is a reduction in the variability in critical dimension (CD) between features due to the application of RF signal 130 (FIG. 1). For example, the diameter of feature 362A is within a predetermined range from the diameter of feature 362B. Also, the variability in bars, which are the distance between any two consecutive features, is reduced by the application of RF signal 130.

[0067] 4 is a diagram of an embodiment of a system 400 for illustrating the generation of states S3b, S2b, and S1b. System 400 includes an RF generator 402 and a host computer 104. RF generator 402 is an example of RF generator 102 (FIG. 1).

[0068] The RF generator 402 includes a digital signal processor (DSP) 404, a power controller PWRS3b, a power controller PWRS2b, a power controller PWRS1b, and a frequency controller FC. The power controllers PWRS3b, PWRS2b, and PWRS1b are components of a controller system 403. The RF generator 402 further includes a driver system (DRVR) 406 and an RF power supply 408.

[0069] An example of a controller includes a processor and a memory device. The controller's processor is coupled to the controller's memory device. For example, the controller is a microcontroller. An example of a driver system is a circuit including one or more transistors. The transistors are coupled to each other. An example of an RF power source is an electronic oscillator that produces an RF signal 130 having a radio frequency.

[0070] The processor 110 is coupled to the DSP 404 via the transfer cable 120. The DSP 404 is coupled to the power controllers PWRS3b, PWRS2b, and PWRS1b. The power controllers PWRS3b, PWRS2b, and PWRS1b, and the frequency controller FC are coupled to a driver system 406, which is coupled to an RF power supply 408. The RF power supply 408 is coupled to the RF cable 120 (FIG. 1).

[0071] The processor 110 generates and sends a recipe signal 412 to the DSP 404 via the transfer cable 120. The recipe signal 412 is an example of the recipe signal 126 (FIG. 1). The recipe signal 412 includes information about the RF signal 202 (FIG. 2A), such as a frequency of operation of the RF generator 402, a set of states S3b, S2b, and S1b of the RF signal 202, and a duty cycle of the states S3b, S2b, and S1b. The information about the RF signal 202 further includes a first time period, such as a time period between time t0 and time t36, during which one or more instances, such as occurrences, of the states S3b, S2b, and S1b will occur. The information about the RF signal 202 also includes instructions for initiating pulsing the RF signal 202 between the states S3b, S2b, and S1b. The DSP 404 stores in a memory device of the DSP the duty cycle of states S3b, S2b, and S1b, the first time period, and instructions for initiating the pulsing of the RF signal 202 during states S3b, S2b, and S1b.

[0072] Upon receiving the recipe signal 412, the DSP 404 identifies states S3b, S2b, and S1b and duty cycles for states S3b, S2b, and S1b from the recipe signal 412 and provides the states S3b, S2b, and S1b and the duty cycles to the power controllers PWRS3b, PWRS2b, and PWRS1b. For example, the duty cycles of states S3b and S3b are sent to the power controller PWRS3b, the duty cycles of states S2b and S2b are sent to the power controller PWRS2b, and the duty cycles of states S1b and S1b are sent to the power controller PWRS1b.

[0073] Each of the power controllers PWRS3b, PWRS2b, and PWRS1b stores a respective one of the states S3b, S2b, and S1b and a respective one of the duty cycles of the states S3b, S2b, and S1b. For example, the processor of the power controller PWRS3b stores the state S3b and the duty cycle at which the state S3b will occur in the memory device of the power controller PWRS3b, the power controller PWRS2b stores the state S2b and the duty cycle at which the state S2b will occur in the memory device of the power controller PWRS2b, and the power controller PWRS1b stores the state S1b and the duty cycle at which the state S1b will occur in the memory device of the power controller PWRS1b.

[0074] The DSP 404 also identifies a frequency of operation of the RF generator 402 from the recipe signal 412 and provides the frequency of operation to the frequency controller FC. The processor of the frequency controller FC stores the frequency of operation in a memory device of the frequency controller FC.

[0075] In addition, the DSP 404 receives the clock signal 212 from the processor 110 via the transmission cable 120. After receiving the clock signal 212, the DSP 404 sends a frequency control signal to the frequency controller FC and sends a power control signal to the power controller PWRS3b to provide the state S3b during the duty cycle of the state S3b. Upon receiving the power control signal, the power controller PWRS3b sends the state S3b to the driver system 406. Upon receiving the state S3b and the frequency of operation, the driver system 406 generates a drive signal based on the power level of the state S3b and the frequency of operation, and sends the drive signal to the RF power supply 408. Upon receiving the drive signal from the driver system 406, the RF power supply 408 generates an RF signal 202 having the state S3b during the duty cycle of the state S3b and having the frequency of operation.

[0076] The power controller PWRS3b determines that the time interval for the duty cycle of state S3b has ended and stops sending state S3b to the driver system 406 at the end of the duty cycle of state S3b. When the driver system 406 does not receive state S3b, the driver system 406 stops generating a drive signal based on state S3b. Without receiving a drive signal based on state S3b, the RF power supply 408 does not generate state S3b of the RF signal 202.

[0077] Moreover, at the end of the time interval for the duty cycle of state S3b, the DSP 404 sends a power control signal to the power controller PWRS2b to provide state S2b for the duty cycle of state S2b. Upon receiving the power control signal, the power controller PWRS2b sends state S2b to the driver system 406. Upon receiving state S2b and the frequency of operation, the driver system 406 generates a drive signal based on the power level of state S2b and the frequency of operation and sends the drive signal to the RF power supply 408. Upon receiving the drive signal from the driver system 406, the RF power supply 408 generates an RF signal 202 having state S2b for the duty cycle of state S2b and having the frequency of operation.

[0078] The power controller PWRS2b determines that the time interval for the duty cycle of state S2b has ended and stops sending state S2b to the driver system 406 at the end of the duty cycle of state S2b. When the driver system 406 does not receive state S2b, the driver system 406 stops generating a drive signal based on state S2b. Without receiving a drive signal based on state S2b, the RF power supply 408 does not generate state S2b of the RF signal 202.

[0079] Furthermore, at the end of the time interval for the duty cycle of state S2b, the DSP 404 sends a power control signal to the power controller PWRS1b to provide state S1b for the duty cycle of state S1b. Upon receiving the power control signal, the power controller PWRS1b sends state S1b to the driver system 406. Upon receiving state S1b and a frequency of operation, the driver system 406 generates a drive signal based on the power level of state S1b and the frequency of operation, and sends the drive signal to the RF power supply 408. Upon receiving the drive signal from the driver system 406, the RF power supply 408 generates an RF signal 202 having state S1b for the duty cycle of state S1b and having a frequency of operation.

[0080] The power controller PWRS1b determines that the time interval for the duty cycle of state S1b has ended and stops sending state S1b to the driver system 406 at the end of the duty cycle of state S1b. When the driver system 406 does not receive state S1b, the driver system 406 stops generating a drive signal based on state S1b. Without receiving a drive signal based on state S1b, the RF power supply 408 does not generate state S1b of the RF signal 202. In this manner, the DSP 404 controls the power controllers PWRS3b, PWRS2b, and PWRS1b and the frequency controller FC to generate an RF signal 202 having states S3b, S2b, and S1b and a frequency of operation during a first time period.

[0081] It should be noted that a change in power level for a state occurs when a new recipe signal indicating a change in power level for that state is received by DSP 404 from processor 110 via transfer cable 120. For example, processor 110 sends a recipe signal to DSP 404 that includes a power level greater than the power level of state S3b and a duty cycle for the greater power level. Upon receiving the greater power level and duty cycle, DSP 404 controls power controller PWRS3b to further control RF power supply 408 to increase the power level for state S3b to the greater power level for the time period of the duty cycle. Power controller PSRS3b is controlled in the same manner to achieve the greater power level during the duty cycle as power controller PSRS3b is controlled to achieve the power level of state S3b.

[0082] 5 is one embodiment of a graph 500 for illustrating multiple sets of states of an RF signal 502. The RF signal 502 is an example of an RF signal 130 (FIG. 1). The graph 500 plots the power level versus time t of the RF signal 502. The power level is plotted on the y-axis and the time t is plotted on the x-axis. On the y-axis of the graph 500, the power levels range from a power level P0 to a power level P13. The power levels increase in the positive y direction of the y-axis of the graph 500. For example, the power level increases from P0 to P13. On the x-axis of the graph 500, the time t increases from time t0 to time t42.

[0083] The RF signal 502 transitions periodically between a set of states S2a and S1a from time t0 to time t18. State S2a is at power level P6 and state S1a is at power level P2. At time t18, the RF signal 502 transitions between states S3b, S2b, and S1b until time t36. Then, beginning at time t36, the RF signal 502 alternates, transitioning periodically between four states S4c, S3c, S2c, and S1c, and so on. The RF signal 502 transitions between states S4c-S1c in a step-down manner during the time period between times t36 and t46. For example, during cycle 10 of the clock signal 212 (FIG. 2B), the RF signal 502 transitions from power level P2 to power level P13 at time t36 and maintains power level P13 from time t36 to time t37. Also, RF signal 502 transitions from power level P13 to power level P10 at time t37 and remains at power level P10 from time t37 to time t38. Moreover, RF signal 502 transitions from power level P10 to power level P6 at time t38 and remains at power level P6 from time t38 to time t39. RF signal 502 transitions from power level P6 to power level P2 at time t39 and remains at power level P2 from time t39 to time t41.

[0084] During cycles 11 and 12 of the clock signal 212, the RF signal 502 repeatedly transitions between power levels P13, P10, P6, and P2 in the same manner as the transitions during cycles 10 and 11. For example, the power levels P13, P10, P6, and P2 repeat from time t41 to time t46 in the same manner as the power levels P13, P10, P6, and P2 occur from time t36 to time t41.

[0085] The power level P13 is the state S4c of the RF signal 502, the power level P10 is the state S3c of the RF signal 502, the power level P6 is the state S2c of the RF signal 502, and the power level P2 is the state S1c of the RF signal 502. Also, the time interval between time t36 and time t37 is an example of a duty cycle of the state S4c, the time interval between time t37 and time t38 is an example of a duty cycle of the state S3c, the time interval between time t38 and time t39 is an example of a duty cycle of the state S2c, and the time interval between time t39 and time t41 is an example of a duty cycle of the state S1c. The states S4c, S3c, S2c, and S1c form a set of states of the RF signal 502. Also, the states S4c to S1c occur during a second time period. The second time period is from time t36 to time t46.

[0086] Note that states S4c, S3c, S2c, and S1c etch a dielectric layer of a substrate (not shown) that is deeper than dielectric layer 304 (FIG. 3A). For example, states S3b, S2b, and S1b etch a mask layer of a substrate (not shown) and one or more portions of a dielectric layer of a substrate (not shown). States S4c, S3c, S2c, and S1c etch a remaining portion of the dielectric layer, which is located below the mask layer, and which is located below one or more portions of the dielectric layer.

[0087] In one embodiment, three states are used to etch a substrate having a dielectric layer deeper than dielectric layer 304. For example, instead of using states S4c, S3c, S2c, and S1c in the previous example to etch the remaining portion of the dielectric layer, a high power level state is used in place of the power level of state S3b. The high power level is greater than the power level of state S3b.

[0088] In one embodiment, states S4c, S3c, S2c, and S1c repeat a second number of times. For example, instead of repeating twice during the time period between time t36 and time t46 as shown in FIG. 5, states S4c, S3c, S2c, and S1c occur once or repeat three times. As one example, the second number is equal to the first number of times states S3b, S2b, and S1b occur. As another example, the second number is different from the first number of times.

[0089] In one embodiment, state S3c has a different power level than the power level of state S3b, for example state S3c is at a power level between power level P10 and power level P13 or greater than power level P13.

[0090] In one embodiment, state S2c has a different power level than the power level of state S2b, for example state S2c is a power level between power level P6 and power level P10.

[0091] In one embodiment, state S1c has a different power level than the power level of state S1b, for example, state S1c is at a power level between power levels P2 and P6, or between power levels P0 and P2.

[0092] In one embodiment, states S3b, S2b, S1b, S4c, S3c, S2c, and S1c, duty cycles for states S3b, S2b, S1b, S4c, S3c, S2c, and S1c, a first time period for occurrence of states S3b, S2b, and S1b, and a second time period for occurrence of states S4c, S3c, S2c, and S1c are empirically determined by processor 110 during an experimental process. States S3b, S2b, S1b, S4c, S3c, S2c, and S1c are stored by processor 110 in memory device 112 for access during processing of substrate S.

[0093] In one embodiment, states S4c, S3c, S2c, and S1c occur at time t0 instead of states S3b, S2b, and S1b. States S4c-S1c occur for some time, such as, for example, from time t0 to time t46.

[0094] 6 is a diagram of an embodiment of a system 600 for illustrating generation of states S4c, S3c, S2c, and S1c. System 600 includes an RF generator 602 and a host computer 104. RF generator 602 is an example of RF generator 102 (FIG. 1).

[0095] The RF generator 602 includes the DSP 404, the controller system 403, the power controller PWRS4c, the power controller PWRS3c, the power controller PWRS2c, and the power controller PWRS1c. The RF generator 602 further includes a driver system 406 and an RF power source 408.

[0096] The DSP 404 is coupled to the power controllers PWRS4c, PWRS3c, PWRS2c, and PWRS1c. The power controllers PWRS4c, PWRS3c, PWRS2c, and PWRS1c are coupled to the driver system 406.

[0097] The processor 110 generates and sends a recipe signal 612 to the DSP 404 via the transfer cable 120. The recipe signal 612 is an example of the recipe signal 126 (FIG. 1). The recipe signal 612 includes a frequency of operation of the RF generator 602, a set of states S3b, S2b, and S1b of the RF signal 502, a set of states S4c, S3c, S2c, and S1c of the RF signal 502, and a duty cycle of the states S3b, S2b, S1b, S4c, S3c, S2c, and S1c. The recipe signal 612 further includes a first time period during which the set of states S3b-S1b will occur, and a second time period during which the states S4c, S3c, S2c, and S1c will occur. The recipe signal 612 further includes instructions to initiate pulsing the RF signal 502 between the states S3b, S2b, and S1b. The DSP 404 stores in a memory device of the DSP 404 the duty cycles of states S4c, S3c, S2c, and S1c, the second time period, and instructions for initiating the pulsing of the RF signal 502 during states S3b, S2b, and S1b.

[0098] Upon receiving the recipe signal 612, the DSP 404 identifies states S4c, S3c, S2c, and S1c from the recipe signal 612 and the duty cycles at which states S4c, S3c, S2c, and S1c will occur, and provides states S4c, S3c, S2c, and S1c and the duty cycles for states S4c, S3c, S2c, and S1c to the power controllers PWRS4c, PWRS3c, PWRS2c, and PWRS1c. For example, the duty cycles of states S4c and S4c are sent to the power controller PWRS4c, the duty cycles of states S3c and S3c are sent to the power controller PWRS3c, the duty cycles of states S2c and S2c are sent to the power controller PWRS2c, and the duty cycles of states S1c and S1c are sent to the power controller PWRS1c.

[0099] Each power controller PWRS4c, PWRS3c, PWRS2c, and PWRS1c stores a respective one of states S4c, S3c, S2c, and S1c and a respective one of the duty cycles of states S4c, S3c, S2c, and S1c. For example, the processor of power controller PWRS4c stores state S4c and the duty cycle at which state S4c occurs in a memory device of power controller PWRS4c, and the processor of power controller PWRS3c stores state S3c and the duty cycle at which state S3c occurs in a memory device of power controller PWRS3c.

[0100] At the end of the time interval for the duty cycle of state S1b and at the end of the first time period, the DSP 404 sends a power control signal to the power controller PWRS4c to provide state S4c during the duty cycle of state S4c. Upon receiving the power control signal, the power controller PWRS4c sends state S4c to the driver system 406. Upon receiving state S4c and a frequency of operation, the driver system 406 generates a drive signal based on the power level of state S4c and the frequency of operation and sends the drive signal to the RF power supply 408. Upon receiving the drive signal from the driver system 406, the RF power supply 408 generates an RF signal 502 having state S4c during the duty cycle of state S4c and having a frequency of operation.

[0101] The power controller PWRS4c determines that the time interval for the duty cycle of state S4c has ended and stops sending state S4c to the driver system 406 at the end of the duty cycle of state S4c. When the driver system 406 does not receive state S4c, the driver system 406 stops generating the drive signal based on state S4c. Without receiving a drive signal based on state S4c, the RF power supply 408 does not generate state S4c of the RF signal 502.

[0102] At the end of the time interval for the duty cycle of state S4c, the DSP 404 sends a power control signal to the power controller PWRS3c to provide state S3c for the duty cycle of state S3c. Upon receiving the power control signal, the power controller PWRS3c sends state S3c to the driver system 406. Upon receiving state S3c and the frequency of operation, the driver system 406 generates a drive signal based on the power level of state S3c and the frequency of operation and sends the drive signal to the RF power supply 408. Upon receiving the drive signal from the driver system 406, the RF power supply 408 generates an RF signal 502 having state S3c for the duty cycle of state S3c and having the frequency of operation.

[0103] Moreover, the power controller PWRS3c determines that the time interval for the duty cycle of state S3c has ended and stops sending state S3c to the driver system 406 at the end of the duty cycle of state S3c. When the driver system 406 does not receive state S3c, the driver system 406 stops generating the drive signal based on state S3c. Without receiving the drive signal based on state S3c, the RF power supply 408 does not generate state S3c of the RF signal 502.

[0104] At the end of the time interval for the duty cycle of state S3c, the DSP 404 sends a power control signal to the power controller PWRS2c to provide state S2c for the duty cycle of state S2c. Upon receiving the power control signal, the power controller PWRS2c sends state S2c to the driver system 406. Upon receiving state S2c and a frequency of operation, the driver system 406 generates a drive signal based on the power level of state S2c and the frequency of operation and sends the drive signal to the RF power supply 408. Upon receiving the drive signal from the driver system 406, the RF power supply 408 generates an RF signal 502 having state S2c for the duty cycle of state S2c and having a frequency of operation.

[0105] The power controller PWRS2c determines that the time interval for the duty cycle of state S2c has ended and stops sending state S2c to the driver system 406 at the end of the duty cycle of state S2c. When the driver system 406 does not receive state S2c, the driver system 406 stops generating the drive signal based on state S2c. Without receiving a drive signal based on state S2c, the RF power supply 408 does not generate state S2c of the RF signal 502.

[0106] At the end of the time interval for the duty cycle of state S2c, the DSP 404 sends a power control signal to the power controller PWRS1c to provide state S1c for the duty cycle of state S1c. Upon receiving the power control signal, the power controller PWRS1c sends state S1c to the driver system 406. Upon receiving state S1c and a frequency of operation, the driver system 406 generates a drive signal based on the power level of state S1c and the frequency of operation and sends the drive signal to the RF power supply 408. Upon receiving the drive signal from the driver system 406, the RF power supply 408 generates an RF signal 502 having state S1c for the duty cycle of state S1c and having a frequency of operation.

[0107] The power controller PWRS1c determines that the time interval for the duty cycle of state S1c has ended and stops sending state S1c to the driver system 406 at the end of the duty cycle of state S1c. When the driver system 406 does not receive state S1c, the driver system 406 stops generating a drive signal based on state S1c. Without receiving a drive signal based on state S1c, the RF power supply 408 does not generate state S1c of the RF signal 502. In this manner, the DSP 404 controls the power controllers PWRS4c, PWRS3c, PWRS2c, and PWRS1c and the frequency controller FC to generate an RF signal 502 having states S4c, S3c, S2c, and S1c and a frequency of operation during the second time period.

[0108] In an embodiment in which the RF signal 130 (FIG. 1) is to initiate pulsing between the four states S4c-S1c at time t0, the recipe signal 612 includes instructions to initiate pulsing the RF signal 502 between states S4c-S1c instead of instructions to initiate pulsing between states S3b, S2b, and S1b. The DSP 404 stores the instructions to initiate pulsing the RF signal 130 between states S4c-S1c in a memory device of the DSP 404. At time t0, the DSP 404 sends a power control signal to the power controller PWRS4c to provide state S4c for the duty cycle of state S4c.

[0109] In one embodiment, any of the functions described herein as being performed by the controllers PWRS3b, PWRS2b, PWRS1b, PWRS4c, PWRS3c, PWRS2c, PWRS1c, and FC may be performed by the DSP 404.

[0110] In one embodiment, any of the functions described herein as being performed by one or more of the controllers PWRS3b, PWRS2b, PWRS1b, PWRS4c, PWRS3c, PWRS2c, PWRS1c, and FC may be performed by a single controller or by two or more controllers.

[0111] It should be noted that in embodiments where states S4c-S3c are to be applied after states S3b-S1b, the LF RF generator is turned off for the first time period plus the second time period and turned on after the first time period plus the second time period.

[0112] The embodiments described herein may be practiced with a variety of computer system configurations including portable hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments described herein may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0113] In some embodiments, the controller is part of a system, which may be part of the examples described above. The system includes semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms, and / or specific processing components (wafer pedestal, gas flow system, etc.) for processing. The system is integrated with electronics for controlling its operation before, during, and after processing of a semiconductor wafer or substrate. The electronic circuitry is called a "controller," which may control various components or sub-parts of the system. The controller is programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected to or interfaced with the system, depending on the processing requirements and / or type of system.

[0114] In general, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips in the form of firmware, DSPs, ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software) that store program instructions. Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing processes on or for a semiconductor wafer. The operational parameters, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0115] The controller, in some embodiments, is part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or in all or part of a fab host computer system that allows remote access for wafer processing. The controller allows remote access to the system to monitor the current progress of a fabrication operation, to change parameters of a current process, to set up processing steps subsequent to a current process, or to initiate a new process, to examine the history of past fabrication operations, and to examine trends or performance metrics from multiple fabrication operations.

[0116] In some embodiments, a remote computer (e.g., a server) provides the process recipe to the system over a computer network, including a local network or the Internet. The remote computer includes a user interface that allows entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of settings for processing the wafer. It should be understood that those settings are specific to the type of process to be performed on the wafer and the type of tool the controller interfaces with or controls. Thus, as described above, the controller is distributed, such as by including one or more individual controllers that are networked together and function toward a common purpose, such as the process of implementing described herein. One example of a distributed controller for such purposes includes one or more integrated circuits on the chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that are combined to control the process in the chamber.

[0117] Without being limited thereto, in various embodiments, the plasma systems described herein include plasma etch chambers, deposition chambers, spin rinse chambers, metal plating chambers, clean chambers, bevel edge etch chambers, physical vapor deposition (PVD) chambers, chemical vapor deposition (CVD) chambers, atomic layer deposition (ALD) chambers, atomic layer etch (ALE) chambers, ion implantation chambers, track chambers, or any other semiconductor processing chambers related to or used in the creation and / or manufacturing of semiconductor wafers.

[0118] Additionally, while the operations described above have been described with respect to a parallel plate plasma chamber, e.g., a capacitively coupled plasma chamber, it should be noted that in some embodiments, the operations described above apply to other types of plasma chambers, including, e.g., plasma chambers including inductively coupled plasma (ICP) reactors, transformer coupled plasma (TCP) reactors, conductor tools, dielectric tools, electron cyclotron resonance (ECR) reactors, etc. For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor in an ICP plasma chamber.

[0119] As described above, depending on the process operations to be performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to carry containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0120] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations manipulate physical quantities.

[0121] Some of the embodiments also relate to hardware units or devices for performing these operations. The device is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processes, program executions or routines that are not part of its special purpose while still being capable of performing operations for its special purpose.

[0122] In some embodiments, the operations described herein are performed by a selectively activated computer or configured by one or more computer programs stored in a computer memory or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0123] One or more embodiments described herein may also be made as computer readable code on a non-transitory computer readable medium. A non-transitory computer readable medium is any data storage hardware unit, such as a memory device, that stores data, which is then read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disk ROM (CD-ROM), CD recordable (CD-R), CD rewriteable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, a non-transitory computer readable medium includes a computer readable tangible medium that is distributed across network-coupled computer systems such that the computer readable code is stored and executed in a distributed manner.

[0124] Although some of the method operations described above have been presented in a particular order, it should be understood that in various embodiments, other housekeeping operations are performed between the method operations, or the method operations are adjusted such that they occur at slightly different times or are distributed in a system that allows the method operations to occur at various intervals, or are performed in an order different from that described above.

[0125] Furthermore, it should be noted that in one embodiment, one or more features from any embodiment described above may be combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in this disclosure.

[0126] Although the above embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Thus, the present embodiments should be considered as illustrative rather than restrictive, and the embodiments should not be limited to the details given herein, but may be modified within the scope of the appended claims and their equivalents.

Claims

1. 1. A method for reducing variability between features of a substrate, comprising: generating a radio frequency (RF) signal by a single radio frequency (RF) generator; modifying the RF signal to transition between at least three states during a first time period; A method comprising:

2. 2. The method of claim 1, wherein modifying the RF signal to transition between the at least three states comprises transitioning the RF signal between the at least three states in a step-down manner, and wherein transitioning the RF signal in a step-down manner comprises: transitioning the RF signal from a first power level to a second power level, the first power level being greater than the second power level; transitioning the second power level to a third power level of the RF signal, the third power level being less than the second power level; A method comprising:

3. 10. The method of claim 1, wherein the RF signal is modified to transition the RF signal between the at least three states to etch a dielectric layer of the substrate.

4. 10. The method of claim 1, wherein the RF signal is modified to transition the RF signal between the at least three states to etch a mask layer and a first portion of a dielectric layer of the substrate, the at least three states of the RF signal etching a second portion of the dielectric layer, the second portion underlying the first portion.

5. 5. The method of claim 4, further comprising modifying the RF signal to transition to four states or to increase a power level of one of the at least three states during a second time period after the first time period, wherein the four states of the RF signal etch a third portion of the dielectric layer, the third portion being located below the second portion.

6. 10. The method of claim 1, wherein the RF signal is generated to have at least one state for etching a first portion of a dielectric layer of the substrate, and the RF signal is modified to transition the RF signal between the at least three states for etching a second portion of the dielectric layer, the second portion being located below the first portion.

7. 2. The method of claim 1, further comprising: supplying the RF signal to an impedance matching circuit; and during the supplying of the RF signal to the impedance matching circuit, no other RF signal is supplied to the impedance matching circuit.

8. 10. The method of claim 1, wherein the single RF generator has a single frequency of operation, the single frequency being a fundamental frequency of 60 megahertz (MHz).

9. The method of claim 1 , wherein the at least three states include at most four states.

10. 1. A controller for reducing variability between features of a substrate, comprising: a processor configured to control a single radio frequency (RF) generator to generate an RF signal, a processor configured to further control the single RF generator to transition the RF signal between at least three states during a first time period; a memory device coupled to the processor; A controller comprising:

11. 11. The controller of claim 10, wherein to control the single RF generator to transition the RF signal between the at least three states, the processor is configured to control the single RF generator to transition the RF signal between the at least three states in a step-down manner, and to transition the RF signal in the step-down manner, the processor: controlling the single RF generator to transition the RF signal from a first power level to a second power level, the first power level being greater than the second power level; controlling the single RF generator to transition the second power level to a third power level of the RF signal, the third power level being less than the second power level; A controller configured to:

12. 11. The controller of claim 10, wherein the RF signal is controlled to transition the RF signal between the at least three states to etch a dielectric layer of the substrate.

13. 11. The controller of claim 10, wherein the RF signal is controlled to transition the RF signal between the at least three states to etch a mask layer and a first portion of a dielectric layer of the substrate, the at least three states of the RF signal etching a second portion of the dielectric layer, the second portion underlying the first portion.

14. 14. The controller of claim 13, wherein the processor is configured to modify the RF signal to transition to four states or to increase a power level of one of the at least three states for a second time period after the first time period, the four states of the RF signal etching a third portion of the dielectric layer, the third portion underlying the second portion.

15. 11. The controller of claim 10, wherein the RF signal is generated to have at least one state for etching a first portion of a dielectric layer of the substrate, and the RF signal is modified to transition the RF signal between the at least three states for etching a second portion of the dielectric layer, the second portion being located below the first portion.

16. 11. The controller of claim 10, wherein the RF signal is supplied to an impedance matching circuit and during a period of time when the RF signal is supplied to the impedance matching circuit, no other RF signal is supplied to the impedance matching circuit.

17. 11. The controller of claim 10, wherein the single RF generator has a single frequency of operation, the single frequency being a fundamental frequency of 60 megahertz (MHz).

18. The controller of claim 10 , wherein the at least three states include at most four states.

19. 1. A plasma system comprising: a single radio frequency (RF) generator configured to generate an RF signal; a matcher coupled to the single RF generator; a plasma chamber coupled to the matcher; a controller coupled to the single RF generator, the controller comprising: controlling the single RF generator to generate the RF signal; controlling the single RF generator to transition the RF signal between at least three states during a first time period; a controller configured to: A plasma system comprising:

20. 20. The plasma system of claim 19, wherein to control the single RF generator to transition the RF signal between the at least three states, the controller is configured to control the single RF generator to transition the RF signal between the at least three states in a step-down manner, and to transition the RF signal in the step-down manner, the controller: controlling the single RF generator to transition the RF signal from a first power level to a second power level, the first power level being greater than the second power level; controlling the single RF generator to transition the second power level to a third power level of the RF signal, the third power level being less than the second power level; A plasma system configured to:

21. 20. The plasma system of claim 19, wherein the controller is configured to modify the RF signal to transition to four states or to increase a power level of one of the at least three states during a second time period after the first time period.

22. 20. The plasma system of claim 19, wherein the single frequency is a fundamental frequency of 60 megahertz (MHz) and the at least three states include at most four states.

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