Integrated circuits with non-preferential direction curved wiring

Abstract

Some embodiments of the present invention provide an integrated circuit (IC) having a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and a plurality of wiring layers, the plurality of wiring layers including a first set of one or more wiring layers having no preferred wiring direction and a second set of one or more wiring layers having a preferred wiring direction. In some embodiments, the first set of wiring layers includes a third and a fourth wiring layer, and the second set of wiring layers includes a fifth or more metal layers having successive adjacent layers having different (e.g., alternating) preferred wiring directions. In other embodiments, the first set of wiring layers includes a third wiring layer but not a fourth wiring layer, which in these embodiments has a preferred wiring direction.

Description

[Technical field]

[0001] An integrated circuit ("IC") is a device that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often defined on a semiconductor substrate and interconnected with metal wiring and vias to form multiple circuit components, such as gates, cells, memory units, computational units, controllers, decoders, etc. An IC typically includes multiple layers of wiring and vias that interconnect its electronic components and circuit components. Summary of the Invention

[0002] Some embodiments of the present invention provide an integrated circuit (IC) having a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and a plurality of wiring layers, the plurality of wiring layers including a first set of one or more wiring layers having no preferred wiring direction and a second set of one or more wiring layers having a preferred wiring direction. In some embodiments, the first set of wiring layers includes a third and a fourth wiring layer, and the second set of wiring layers includes a fifth or more metal layers having successive adjacent layers having different (e.g., alternating) preferred wiring directions. In other embodiments, the first set of wiring layers includes a third wiring layer but not a fourth wiring layer, which in these embodiments has a preferred wiring direction. Also, in some embodiments, the first and second wiring layers belong to the first set, and in other embodiments, the first and second wiring layers belong to the second set.

[0003] In some embodiments, each preferred wiring direction is a Manhattan direction (i.e., horizontal or vertical), and the preferred wiring directions of different adjacent layers alternate between horizontal and vertical. In other embodiments, the preferred wiring directions include other wiring directions (e.g., 45 degree or 60 degree wiring directions), and successive adjacent layers have different preferred wiring directions. In some embodiments, the preferred wiring direction on each layer is a direction that includes at least a certain threshold amount (e.g., 90% or 95%) of the wiring on that layer. In some embodiments, the non-preferred direction wiring on each layer of the first set of wiring layers includes interconnect wiring (also called wiring connections) that traverse in more than eight directions.

[0004] In some embodiments, each layer of the first set of wiring layers includes straight wires (i.e., wires having only straight segments) and curvilinear wires (i.e., wires having at least one curved segment). In some embodiments, the first set of wiring layers of an IC is used for wire connections that are shorter than the wire connections defined on the second set of wiring layers. In some embodiments, the first set of wiring layers in some embodiments is used for short local connections and the second set of wiring layers is used for longer connections.

[0005] In some embodiments, electronic design automation (EDA) tools (e.g., routers and compactors) that define the design of the IC consider preferred and non-preferred directions on each wiring layer while defining paths that result in metal wiring on those layers. In some embodiments, when the first set of wiring layers includes a third wiring layer and / or a fourth wiring layer, the EDA tool defines NPD curved paths for the third and / or fourth wiring layers, but also defines NPD curved paths for the first and second wiring layers. However, in some of these embodiments, the first and second wiring layers have preferred direction wiring in some of their regions, such as regions used for connections required to form electronic components (e.g., transistors) and circuit blocks (e.g., IP blocks) defined on the substrate of the IC at locations below these regions. In some embodiments, the EDA tool uses unused space on the first and second wiring layers to define NPD straight and / or curved paths, resulting in NPD straight / curved wiring on the corresponding layers of the manufactured IC. The NPD straight / curved wiring on the first and second layers reinforces the NPD straight / curved wiring on the third and / or fourth wiring layers.

[0006] In some embodiments, a first set of wiring layers of an IC is used to connect any nets that can be connected via wires on the first set of wiring layers, and a second set of wiring layers is used to connect any nets that cannot be fully connected via wires on the first set of wiring layers. In some of these embodiments, the design of the IC is based on straight and curved paths defined on the first N layers (N is an integer greater than 2), but only on straight paths on the next M layers (M is any integer) of the IC. Some embodiments allow straight and curved paths in the IC design for some of the lower wiring layers as well as some of the upper wiring layers (e.g., all of the wiring layers, or one or two of the first several lower wiring layers and the upper wiring layers). In some embodiments, a straight path is a path that has only one or more straight line segments, and a curved path is a path that has at least one curved segment.

[0007] In some embodiments, interconnects on the first set of wiring layers are defined using an NPD curve first router, and interconnects on the second set of wiring layers are defined by a preferred direction (PD) second router (e.g., a Manhattan router). The NPD first router generates paths on each layer of the first set of wiring layers that traverse more than eight different directions on that layer. In some embodiments, the first router also generates curved paths on the first set of wiring layers. The PD second router generates paths on each layer of the second set of wiring layers that are primarily along the preferred routing direction of that layer.

[0008] In some embodiments, the NPD first router defines a first set of straight and curved paths that traverse the first set of wiring layers to connect a first set of node pairs that are within a threshold distance of each other, while the PD second router defines a second set of straight paths that traverse the second set of wiring layers to connect a second set of node pairs that are more than a threshold distance from each other. While the first router in some embodiments can define both straight and curved paths, the second router in these embodiments does not generate any curved paths, e.g., any paths that have at least one curved edge (i.e., a curved edge that is not a straight line).

[0009] Some embodiments first define paths for a first set of wiring layers of an IC design, and then define paths for an upper second set of wiring layers of the IC design. For example, some embodiments perform NPD detailed routing for the first set of wiring layers without first performing global routing for those layers. These embodiments then perform global routing for the second set of wiring layers, and perform detailed routing for the second set of wiring layers after the global routing.

[0010] In some embodiments, the NPD detailed routing of the first set of wiring layers does not use any preferred wiring direction. This NPD detailed routing generates curved paths because it allows all angles of direction to be explored during the routing pathfinding operation and then allows curved edges to be used to define a path based on the completed pathfinding. In other embodiments, the NPD detailed routing only generates straight path paths in a large finite number of wiring directions, such as nine or more wiring directions, and does not generate designs with curved path segments. This is because in these embodiments, the routing operation pathfinding only explores extended paths along a finite number of wiring directions and then uses only straight edges along these wiring directions to define a path based on the completed pathfinding.

[0011] Also, in some embodiments, the NPD detail router generates curved paths on a subset of layers in the first set of wiring layers (e.g., on the first and second wiring layers) between areas on those layers that have predefined PD straight wiring (e.g., in areas on layers 1 and 2 used for wiring of IP blocks). Thus, in these embodiments, these subsets of lower wiring layers have regions with predefined PD straight wiring and areas between those regions that have NPD straight and curved wiring.

[0012] In some embodiments, the global and detailed routing for the PD wiring layer uses a Manhattan preferred direction, while in other embodiments, the global and detailed routing for the PD wiring layer uses other preferred wiring directions (e.g., 45 degree wiring or 60 degree wiring) in addition to or as an alternative to the horizontal and vertical wiring directions. In some embodiments, the NPD wiring layer is the first set of wiring layers of the IC design and the PD wiring layer is the second set of wiring layers of the IC design. In other embodiments, the NPD wiring layer includes the first two metal layers, the first three metal layers, or the first four metal layers of the IC design. In still other embodiments, the NPD wiring layer includes additional metal layers as described above.

[0013] In some embodiments, the NPD first set of wiring layers includes a first and a second subset of layers. In these embodiments, the method first performs a first detailed routing operation on the first subset of layers (e.g., the first or third wiring layer), and then performs a second detailed routing operation on the second subset of layers (e.g., the second or fourth wiring layer) after completing the first detailed routing operation. The method in some embodiments performs the first and second detailed routing operations by using an NPD detailed router to perform the first detailed routing operation, and then recursively calling the NPD detailed router to perform the second detailed routing operation.

[0014] The above "Summary" is intended to serve as a brief introduction of some embodiments of the present invention. It is not intended to be an introduction or summary of all inventive subject matter disclosed herein. The following "Description of the Invention" and the "Drawings" referenced in the "Description of the Invention" further describe not only the embodiments described in the "Summary of the Invention" but also other embodiments. Therefore, in order to understand all embodiments described herein, the "Summary of the Invention", the "Description of the Invention", the "Drawings", and the "Claims" must be thoroughly considered. Furthermore, the claimed subject matter is not limited by the illustrative details in the "Summary of the Invention", the "Description of the Invention", and the "Drawings".

[0015] The novel features of the invention are set forth in the appended claims. However, for purposes of illustration, certain embodiments of the invention are set forth in the following drawings. [Brief description of the drawings]

[0016] [Figure 1] 1 illustrates an IC having a novel non-preferential direction wiring architecture of some embodiments. [Diagram 2] 1 illustrates examples of curved wires defined on the first and second layers of an IC, as well as horizontal and vertical wires defined on the third, fourth, and fifth wiring layers of the IC, in accordance with some embodiments. [Diagram 3] 1 illustrates another example of an IC that uses the novel NPD wiring architecture of some embodiments. [Figure 4] An example is shown where the wires on the first two layers can only traverse in 16 possible linear directions. [Diagram 5] 1 shows an IC that uses 45 degree PD wiring on the sixth and seventh metal layers of the IC. [Figure 6A] 1 shows an example of an IC that has mostly shorted wires on the first and second metal layers, and mostly longer wires on the fifth metal layer. [Figure 6B]An example of an IC is shown having NPD curved traces on the first, second, and third metal layers, and PD traces on the fourth and fifth metal layers. [Figure 6C] An example of an IC having NPD curved traces on the first, second, third, and fourth metal layers, and PD traces on the fifth or higher metal layers is shown. [Figure 6D] An example of an IC is shown that has NPD straight and curved wiring on the third and fourth wiring layers, and in addition has straight and curved wiring on the first and second wiring layers in areas not occupied by PD wiring on those layers. [Figure 7] An example of an IC is shown in which all of its metal layers are NPD metal layers with full angle straight and curvilinear traces. [Figure 8] 1 illustrates a routing process that defines paths for connecting netlists associated with an IC design. [Figure 9] 1 illustrates the routing process of some embodiments that uses only detailed routing to define paths for an NPD wiring layer, and then uses global routing and detailed routing to define paths for a PD wiring layer. [Figure 10] 1 illustrates an NPD detailed routing process of some embodiments. [Figure 11] 1 shows two boundary crossings for the same net defined by two different detailed router instances that define NPD paths for two adjacent partitions. [Figure 12] An example of defined constraints is shown below. [Figure 13] 1 illustrates an example of another approach used by some embodiments to use route intersection data specified by one detailed router in one partition with a detailed router in an adjacent partition. [Figure 14] 1 illustrates another NPD detailed routing process of some embodiments. [Figure 15] 1 illustrates a process for manufacturing an IC having curved paths, according to some embodiments. [Figure 16]1 illustrates an example of five wiring layers of an IC design generated by one or more physical design tools of some embodiments. [Figure 17] 4 illustrates another example of a metal layer of an IC design defined to have curved path segments. [Figure 18] 1 shows two example routing processes for defining a curved NPD router to reduce the number of vias. [Figure 19] 1 shows two example routing processes for defining a curved NPD router to reduce the number of vias. [Figure 20] 1 shows an example of a set of nets that need to be connected via paths. [Figure 21] An example of a conventional Manhattan route on metal layers 3 and 4 connecting the pins of each of several nets shown in FIG. 20 is shown. [Figure 22] 21 shows an example of a curvilinear NPD path on metal layers 3 and 4 that connects the pins of each of several nets shown in FIG. [Figure 23] 1 illustrates an example of an NPD router of some embodiments. [Figure 24] 1 illustrates an example of a geometric router in some embodiments that uses a machine learning engine to identify geometric paths for a set of nets for which the topology router identifies topological paths. [Diagram 25] An example of a topology router is shown that tessellates a partition into 64 rectangular cells, which the topology router then uses to define a topology path. [Figure 26] Two alternative processes for defining partition sizes relative to the amount of computational and memory resources of a computer are presented. [Figure 27] Two alternative processes for defining partition sizes relative to the amount of computational and memory resources of a computer are presented. [Figure 28] 1 conceptually illustrates an electronic system in which some embodiments of the present invention may be implemented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In the following detailed description of the invention, numerous details, examples, and embodiments of the invention are set forth and explained. However, it will be apparent to one of ordinary skill in the art that the invention is not limited to the described embodiments, and that the invention may be practiced without some of the specific details and examples described.

[0018] Some embodiments of the present invention provide an integrated circuit (IC) having a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and a plurality of wiring layers, the plurality of wiring layers including a first set of one or more wiring layers having no preferred wiring direction and a second set of one or more wiring layers having a preferred wiring direction. In some embodiments, the first set of wiring layers includes a third and a fourth wiring layer, and the second set of wiring layers includes a fifth or more metal layers having successive adjacent layers having different (e.g., alternating) preferred wiring directions. In other embodiments, the first set of wiring layers includes a third wiring layer but not a fourth wiring layer, which in these embodiments has a preferred wiring direction. Also, in some embodiments, the first and second wiring layers belong to the first set, and in other embodiments, the first and second wiring layers belong to the second set.

[0019] In some embodiments, each preferred wiring direction is a Manhattan direction (i.e., horizontal or vertical), and the preferred directions (PD) of different adjacent layers alternate between horizontal and vertical directions. In other embodiments, the preferred wiring directions include other wiring directions (e.g., 45 degree or 60 degree wiring directions), and successive adjacent layers have different preferred wiring directions.

[0020] In some embodiments, the preferred wiring direction on each layer is a direction that includes at least a certain threshold amount (e.g., 90% or 95%) of the wiring on that layer. In some embodiments, the non-preferred direction wiring on each layer of the first set of wiring layers includes wiring (hereinafter also referred to as interconnects, interconnect lines, wires, or wire segments) that traverse along more than eight directions. In some embodiments, each layer of the first set of wiring layers includes curvilinear wires, i.e., wires having at least one curved segment. A curved segment is a segment that is curved rather than straight.

[0021] In some embodiments, electronic design automation (EDA) tools (e.g., routers and compactors) that define IC designs consider preferred and non-preferred directions on each wiring layer while defining paths that result in metal wiring on those layers. Some embodiments employ both PD and NPD EDA routers. The PD EDA router in some embodiments does not penalize path segments that traverse along the preferred wiring direction on a particular wiring layer while penalizing path segments that traverse along the non-preferred wiring direction on a particular wiring layer (e.g., evaluate wire length cost for path segments that traverse along the preferred wiring direction while evaluating wire length cost and penalty cost for path segments that traverse along the non-preferred wiring direction). By penalizing path segments that traverse along the non-preferred direction, the EDA router ensures that more than a threshold amount (e.g., 90% or 95%) of paths on a PD wiring layer are along the preferred wiring direction of that layer.

[0022] In some embodiments, the NPD router defines paths on a first set of wiring layers of an IC design. Unlike the PD router, the NPD router in some embodiments does not penalize routing in any particular direction on wiring layers in the first set, and thus does not generate designs in which more than a threshold amount (e.g., 90% or 95%) of the paths on an NPD wiring layer are along any of the preferred wiring directions. In other words, the NPD router in some embodiments does not penalize paths along either straight or curved directions to generate a bias toward eight or fewer preferred wiring directions on a layer.

[0023] In some embodiments, the NPD router does not penalize routing along a set of nine or more specific wiring directions, but does penalize routing along one or more wiring directions that are not in the set of unpenalized wiring directions. In some embodiments, the NPD router (or NPD routing operations) defines curved and / or straight paths that traverse more than eight wiring directions on a wiring layer, but the PD router (or PD routing operations) does not define any curved paths, only straight paths. Some examples of such PD and NPD routers and routing operations are described further below.

[0024] In some embodiments, a straight line path is a path that has only one or more straight line segments (also called straight edges), and a curved path is a path that has at least one curved segment (also called curved edge). A preferred direction (PD) straight line path in some embodiments is a path that has its straight line segments on each layer that traverse along the PD of that layer. In other embodiments, a PD straight line path is a path that has a majority of its straight line segments on each layer that traverse along the PD of that layer.

[0025] 1 illustrates an IC 100 having a novel non-preferred direction wiring architecture of some embodiments. As illustrated, the IC 100 includes a substrate 105 and multiple wiring layers (also referred to as metal layers). The wiring layers include a first wiring layer 102 and a second wiring layer 104 that have no preferred wiring direction, and a third wiring layer 106, a fourth wiring layer 108, and a fifth wiring layer 110 that have first, second, and third preferred directions (PD), respectively. Thus, the first and second layers do not have wire segments that traverse primarily along one direction (e.g., do not have more than 90% of the wire segments that traverse along one direction), while the third, fourth, and fifth layers have their wire segments that traverse primarily along the preferred wiring direction of each of these layers (i.e., have more than 90% or 95% of their wires that traverse).

[0026] 1, the preferred wiring directions of different adjacent PD wiring layers alternate between horizontal and vertical directions, i.e., the third wiring layer 106 has a horizontal preferred direction, the fourth wiring layer 108 has a vertical preferred direction, and the fifth wiring layer 110 has a horizontal preferred direction wiring. In some embodiments, the IC 100 further includes a metal layer 0, as well as multiple other metal layers (e.g., a sixth, seventh, and eighth metal layer). Metal layer 0 is a substrate layer in some embodiments, or is the first layer above the substrate layer in other embodiments.

[0027] 2 illustrates an example of curved wires 200 defined on the first layer 102 and second layer 104 of an IC 100, as well as horizontal wires 205 and vertical wires 210 defined on the third wiring layer 106, fourth wiring layer 108, and fifth wiring layer 110 of the IC. In some embodiments, multiple electronic components (e.g., active components such as transistors and diodes, or passive components such as resistors and capacitors) are defined on an IC substrate, and these electronic components are connected to each other via interconnect wiring (e.g., wires 200, 205, and 210) on the wiring layers (e.g., layers 102-110 of the IC 100) to form multiple microcircuits (e.g., Boolean gates) and / or larger circuits (e.g., functional blocks).

[0028] Thus, wires 200, 205, and 210 on metal layers 102-110 are defined to electrically connect circuit nodes (e.g., points, contacts, terminals, or regions of a circuit element, or between two circuit elements of a circuit) to form electrical components (e.g., transistors, diodes, etc.) and circuits. Wires on different metal layers are connected through one or more vias (not shown) to establish a continuous electrical connection to connect two different nodes through wires that traverse different metal layers. Such a continuous electrical connection can be viewed as a multi-layer wire or interconnect that traverses multiple wiring layers to connect two different electrical nodes of an IC.

[0029] As shown in FIG. 2, the first metal layer 102 and the second metal layer 104 have straight wires 201 and curved wires 200 that traverse in any possible direction. In some embodiments, the wires on these layers can traverse at any possible angle since these layers have no preferred wiring direction. Also, as shown by curved wire 200a on the first metal layer, a curved wire can be formed by one or more straight wire segments and one or more curved wire segments on a metal layer. The curved wire segments in some embodiments are segments that have a shape defined by a nonlinear equation. Also, in some embodiments, the curved wire segments are continuously smooth wire segments that bend without using sharp angles.

[0030] Unlike the first metal layer 102 and the second metal layer 104, the third metal layer 106, the fourth metal layer 108, and the fifth metal layer 110 have preferred wiring directions and have wiring interconnects that are primarily transverse to their preferred wiring directions, e.g., the third metal layer has primarily horizontal wires, the fourth metal layer has primarily vertical wires, and the fifth metal layer has primarily horizontal wires. The PD wiring layers may have wires that transverse in a non-preferred direction. Thus, as shown in FIG. 2 and other figures described below, each PD wiring layer is shown to have a small amount of wires that transverse in a non-preferred direction. These NPD wire segments on the PD wiring layers are shown in FIG. 2 and other figures as small diagonal or Manhattan jogs here and there on these layers in the non-preferred direction. These jogs may occur at the ends of wires on the metal layer or between two other wire segments on the metal layer. A Manhattan jog defined in an IC design may result in a curved segment on the PD wiring layer of a manufactured IC as a result of manufacturing limitations.

[0031] 3 illustrates another example of an IC 300 that uses the novel NPD wiring architecture of some embodiments. Similar to the IC 100 of FIG. 1, the IC 300 has NPD wiring on its first layer 302 and second layer 304, and conventional Manhattan PD wiring on its third layer 306, fourth layer 308, and fifth layer 310. However, unlike the IC 100, the IC 300 has only straight wires defined on its first two layers 302 and 304. In other words, the EDA tool that defined the wiring on these two layers did not define curved wires on these layers, but instead defined only straight wires that traverse these layers 302 and 304. Although small curved segments may be inadvertently formed at angled junctions between wire segments due to manufacturing constraints, the EDA tool does not intentionally define such curved segments.

[0032] In this example, the wires on the first two layers 302 and 304 traverse in all possible linear directions (i.e., traverse at any angle between 0 and 360). In other embodiments, the wires on the NPD wiring layers (such as the first and second layers of FIG. 3) do not traverse in all possible linear directions, but rather in a large number of linear directions (e.g., 10, 16, 20, or more linear directions). For example, FIG. 4 shows IC 400, which is similar to IC 300 of FIG. 3, except that the wires on the first two layers 402 and 404 can traverse in only 16 possible linear directions (i.e., 0, 30, 45, 60, 90, 120, 135, 150, 180, 210, 225, 240, 270, 315, 330, and 360 degrees).

[0033] Other embodiments use other preferred direction wiring for the PD wiring layers, such as the third, fourth, and fifth wiring layers of FIGS. 1-4. FIG. 5 shows an IC 500 that is similar to the IC 100 of FIG. 1, except that it uses 45 degree PD wiring on the sixth metal layer 502 and the seventh metal layer 504 of the IC. The sixth layer 502 has 45 degree PD wiring, and the seventh layer 504 has -45 degree PD wiring. Still other embodiments use other preferred directions on the metal layers that have PD wiring (e.g., using 60 degree wiring). In some embodiments, the NPD wiring layers of the IC (e.g., the first wiring layer 102 and the second wiring layer 104 of the IC 100) are used primarily for short local connections, and the PD wiring layers (e.g., the third wiring layer 106, the fourth wiring layer 108, and / or the fifth wiring layer 110) are used primarily for longer connections.

[0034] 6A shows an example of an IC 600 that has primarily shorter wires on the first and second wiring layers 102 and 104 to facilitate local connections between underlying circuit nodes, and primarily uses longer wires on the fifth wiring layer 110 for longer connections between circuit nodes. The third and fourth wiring layers 106 and 108 in this example have a combination of shorter, medium length, and longer wires. The shorter wires on these layers 106 and 108 are used to connect nearby circuit nodes that cannot be connected via wiring on the NPD wiring layers 102 and 104 due to congestion on these layers. Wires on one metal layer (e.g., the shorter wires on the third layer 106) connect through vias to wires on other metal layers (e.g., the wires on the first and second layers 102 and 104) to form continuous electrical connections to connect circuit nodes.

[0035] In some embodiments, the router that defines the wiring on the metal layers of IC 600 defines straight and curved wires for the first and second wiring layers of the EDA design of IC 600. For all other metal layers, the router only defines straight path, and these paths may occasionally have Manhattan or diagonal jogs that appear as curved jogs when manufactured. Despite these occasional unintentional curved jogs, IC 600 does not have as many curved wire segments on and above metal layer 3 as there are on metal layers 1 and 2.

[0036] This is not the case in other embodiments. For example, in some embodiments, the router uses a wiring model in which the third wiring layer is a wiring layer that primarily uses NPD curvilinear wiring. FIG. 6B shows an example of an IC 625 whose design is defined by an EDA tool (e.g., a router) that uses NPD curvilinear wiring on the first wiring layer 102, the second wiring layer 104, and the third wiring layer 606. In other embodiments, the router uses a wiring model in which the third and fourth wiring layers are wiring layers that primarily use NPD curvilinear wiring. FIG. 6C shows an example of an IC 650 whose design is defined by an EDA tool (e.g., a router) that uses NPD curvilinear wiring on the first wiring layer 102, the second wiring layer 104, the third wiring layer 606, and the fourth wiring layer 608.

[0037] 6B and 6C, the router of some embodiments not only defines straight and curved NPD paths on the third wiring layer, or the third and fourth wiring layers, but also defines straight and curved NPD paths on the first and second wiring layers. However, in some embodiments, the first and second wiring layers are completely open during the routing of the straight or curved NPD paths.

[0038] In other embodiments, the first and second wiring layers are not completely open during the routing of straight or curvilinear NPD paths. For example, the first two wiring layers in some embodiments have areas used for straight or diagonal PD wiring. These areas include, for example, areas used by wires connecting circuit blocks (e.g., IP blocks), which are typically defined on the substrate at locations below these areas. Thus, in such embodiments, the NPD router not only defines straight and curvilinear NPD paths on the third wiring layer or the third and fourth wiring layers, but also opportunistically defines straight and curvilinear NPD paths in unused space on the first and second wiring layers that is not used for PD wiring required to define the circuit blocks (e.g., IP blocks) of the IC.

[0039] In yet other embodiments, the first and second wiring layers have only PD wiring, since they are routed only by the PD router. In these embodiments, the only wiring layers that are NPD wiring layers are the layers above the first and second wiring layers. For example, in some embodiments, the third and fourth wiring layers are NPD wiring layers with NPD straight and curved wires, and all other layers are PD wiring layers with PD straight wires. In addition to the third and fourth wiring layers, ICs and IC designs of other embodiments have one or more other upper wiring layers as NPD wiring layers with NPD straight and curved wires.

[0040] FIG. 6D shows one such example. This figure shows an IC 675 with NPD straight and curvilinear wiring on a third wiring layer 624 and a fourth wiring layer 626 designed using NPD routing for the entirety of the third and fourth wiring layers. In addition to these NPD wiring layers, the IC 675 has NPD straight and curvilinear wiring on the first wiring layer 620 and the second wiring layer 622 in areas not occupied for PD wiring on these layers. As shown, the first wiring layer 620 has three regions 680, 682, and 684 with PD wiring, and the second wiring layer 622 has two regions 686 and 688 with PD wiring. As further shown, the IC 675 has NPD straight and curvilinear wiring in the remaining areas on the first wiring layer 620 and the second wiring layer 622 that are outside of the regions 680-688. In some embodiments, the NPD router that defines NPD paths on the third wiring layer 624 and the fourth wiring layer 626 also opportunistically defines NPD straight and curved paths in areas on the first wiring layer 620 and the second wiring layer 622 that are not used for PD wiring of circuit blocks of the IC.

[0041] In some embodiments, the NPD router uses the lower NPD wiring layers (i.e., the first through fourth wiring layers) primarily for short local connections and the upper PD wiring layers (i.e., the fifth and higher wiring layers) primarily for longer connections. The NPD router in some of these embodiments uses the first and second wiring layers for very short connections that can start and end in one continuous unused space on one or both of these wiring layers, and then uses the third and fourth wiring layers for short connections that cannot be made by using one continuous unused space on the first and second wiring layers. In some embodiments, the first and second wiring layers have more PD wiring area than that shown in FIG. 6D because the IC has more IP blocks that use such PD wiring on the lower wiring layers of the IC. Also, in some embodiments, the IP blocks use PD wiring on other metal layers (e.g., the third and / or fourth metal layers).

[0042] In Figures 6A-6D, the IC has PD wiring on the top metal layer such that after the last NPD metal layer, all subsequent metal layers have PD wiring. This is not the case in other embodiments. For example, an IC in some embodiments has one or more of its top metal layers and one or more of its bottom metal layers as NPD metal layers, while having a PD metal layer between these top and bottom NPD metal layers. The NPD metal wiring on these top and bottom metal layers is fabricated in some embodiments based on NPD straight or curved paths defined by an NPD router on the wiring layer (of the EDA design) corresponding to these metal layers. In one such embodiment, the IC has external pins defined on its last metal layer, and the top NPD metal layer uses the NPD straight and curved paths (defined based on the straight and curved NPD paths) as optimal interconnects (e.g., shortest length and / or shortest delay paths) to connect the external pins to the via locations on the top layer, allowing signals to traverse the metal layers quickly down or up from pin to pin.

[0043] FIG. 7 shows another example of an IC with NPD metal layers over the first through fourth metal layers. In this figure, IC 700 is similar to IC 600, except that all of its metal layers are NPD metal layers with full-width straight and curvilinear wiring. Like IC 600 in FIG. 6A, IC 700 has shorter wires on its first wiring layer 102 and second wiring layer 104 primarily to facilitate local connections between underlying circuit nodes, and longer wires on its third wiring layer 706, fourth wiring layer 708, and fifth wiring layer 710. The fifth wiring layer 710 has longer wires, and the third wiring layer 706 and fourth wiring layer 708 have a combination of shorter, medium length, and longer wires.

[0044] 7, the shorter wires on the third and fourth layers are used to connect nearby circuit nodes that cannot be connected via wires on the first wiring layer 102 and second wiring layer 104 due to congestion on these layers. Also, wires on one metal layer (e.g., the shorter wires on the third layer 706) connect through vias to wires on other metal layers (e.g., the wires on the first layer 102 and second layer 104) to form continuous electrical connections to connect circuit nodes.

[0045] As described above, some embodiments use several EDA tools to define IC designs that, when manufactured, result in the ICs shown in Figures 1-7. These EDA tools operate based on wiring models that define PD and / or NPD straight and / or curvilinear wiring for each wiring layer of the IC design. In some embodiments, the wiring models shown for the ICs in Figures 1-7 correspond to the wiring models that the EDA tools use when designing the IC.

[0046] The IC in some embodiments includes several multi-layer interconnect junctions to allow interconnect wiring to traverse from a lower curved non-preferred direction wiring layer (e.g., the first and second wiring layers) to an upper preferred direction wiring layer (e.g., the third and fourth wiring layers). The multi-layer interconnect junctions in some embodiments are arranged on the IC according to a particular configuration, such as an array. Each multi-layer interconnect junction in some embodiments includes several vias connecting a curved non-preferred direction wiring layer (e.g., one of the first and second layers) to a preferred direction wiring layer (e.g., one of the third and fourth layers). Each such junction in some embodiments also includes vias connecting two curved non-preferred direction wiring layers and / or two preferred direction wiring layers.

[0047] The IC in some embodiments includes several buffers defined within a threshold distance from each of several multi-layer interconnect junctions. These buffers are used to drive signals on longer interconnect wires on preferred direction wiring layers (e.g., the third and fourth wiring layers). The IC in some embodiments also includes several buses on the first wiring layer and / or the second wiring layer, each bus enabling interconnects on the first and second wiring layers to bypass at least one multi-layer interconnect junction.

[0048] In some embodiments, the wiring connections on the lower NPD wiring layers (such as layers 3 and 4, or layers 1 through 4) are defined using an NPD first router, and the wiring connections on the upper PD wiring layers (such as layers 5 and above) are defined by a PD second router (e.g., a Manhattan router). The NPD first router generates paths on each of the lower layers that traverse more than eight different directions on each of these layers. The first router in some embodiments also generates curvilinear paths on the lower wiring layers. The use of such routers is described further below.

[0049] 8 illustrates a routing process 800 for defining paths for connecting a netlist associated with an IC design. The netlist identifies a number of nets, each net corresponding to two or more nodes in the IC design that need to be connected by one or more paths. As shown, process 800 defines paths on a first set of lower wiring layers using a first, non-preferred direction router (at 805) and defines paths on a second set of upper wiring layers using a second, preferred direction router (at 810). In some embodiments, the second router (used in 810) is one of the commercially available routers sold today, such as those sold by Cadence, Inc. or Synopsys, Inc.

[0050] In some embodiments, the first set of wiring layers includes the first and second wiring layers and the second set of one or more wiring layers includes the third through seventh wiring layers. In other embodiments, the first set of wiring layers includes the first through third wiring layers and the second set includes the fourth through seventh wiring layers. In yet other embodiments, the first set of wiring layers includes the first through fourth wiring layers and the second set includes the fifth through seventh wiring layers.

[0051] As mentioned above, the first and second wiring layers in some embodiments contain PD wiring (e.g., Manhattan wiring) for circuit blocks (e.g., IP blocks) used in the IC design. In these embodiments, the NPD router uses the space available on the first and second wiring layers to define NPD paths (e.g., straight or curved NPD paths) and also uses the third metal layer, and a fourth metal layer if a fourth layer is available for NPD wiring, to define the NPD paths.

[0052] In other embodiments, the first set of wiring layers includes only the third wiring layer, or the third and fourth wiring layers, but not the first and second wiring layers. In some embodiments, only one or more of the lower wiring layers are used to define the NPD straight or curved paths, while in other embodiments, one or more of the upper wiring layers can be used to define the NPD paths, as further described above.

[0053] Also, in some embodiments, the first router (used in 805) is formed by two routing components: a topology router and a geometric router. The topology router in some embodiments tessellates each IC design layer into several polygons (also called faces) and then defines the topological paths (to connect nets) by referencing the edges of the tessellated layers. A particular topological path has its position defined by its relative position with respect to other topological paths along the edges it crosses. The topology router in some embodiments also uses nodes associated with the faces of the polygons to model vias between wiring layers that are traversed by the topological path. In these embodiments, the topological paths are defined not only by edges, but also by face nodes and their relative positions with respect to each other by referencing these edges and face nodes.

[0054] In some embodiments, each specific topological path is defined by the coordinates of the pair of nodes (in the netlist) connected by the topological path, or even simply by referencing the pair of nodes as the start and end of the topological path. This specific start and end of the topological path distinguishes it from a global path. Another feature that also distinguishes a topological path from a global path is that a topological path has segments (defined by reference to tessellated edge intersections) associated with specific wiring layers (e.g., different segments of a topological path in some embodiments may be on different wiring layers). Global paths, on the other hand, can be defined without reference to the specific wiring layers that they cross.

[0055] The geometric router in some embodiments then defines a geometric realization for each topological path by snapping the topological path to a grid (imposed on the wiring layer) along the allowed wiring direction for the layer. In embodiments that allow curved segments, this snapping allows the wire segments to be curved. In some embodiments, the topological path does not have any width or specific coordinates of its segments other than the coordinates of the two nodes (e.g., two pins) connected by the topological path. Instead of snapping each topological path to a grid, the geometric router in some embodiments defines a width for each topological path and then leaves it to a subsequent compactor to fully geometrically draw the path (e.g., generate a complete geometric definition of the path). In some such embodiments, the geometric router defines, for each topological path, several intermediate coordinates of that path, such that the geometric path it generates for the topological path not only has some width, but also one or more intermediate coordinates that define two or more path segments. One topological path can have many different geometric realizations (i.e., one topological path can be associated with many geometric paths).

[0056] In some embodiments, paths on the non-preferred direction lower wiring layers traverse more than eight directions (e.g., 20, 90, 180, 360, etc. directions). In some embodiments, these paths on some or all of the lower layers are all straight lines (e.g., the first two wiring layers), while in other embodiments, the paths on all of the lower layers (e.g., the first four wiring layers) include curved and straight line paths.

[0057] In some embodiments, the paths defined by the first router connect node pairs that are within a threshold distance of each other, and the paths defined by the second router connect node pairs that are more than a threshold distance from each other. To connect node pairs that are more than a threshold distance from each other, the routing process 800 uses both the first and second routers, for example, using the first router to define path segments that traverse along a lower non-preferred direction wiring layer and using the second router to define path segments that traverse along an upper preferred direction wiring layer. To facilitate the operation of the second router when it must complete a path that is partially completed by the first router, the first router in some embodiments defines one or more of its NPD path segments on the first set of wiring layers to locations used on these layers, up to vias to the second set of wiring layers. The second router then begins its routing operations from these via locations to complete the path that was only partially completed by the first router.

[0058] Some embodiments first define paths that traverse a first set of lower wiring layers of the IC design, and then define paths that traverse upper wiring layers of the IC design. For example, some embodiments perform global routing, then a first NPD detailed routing, and then a second PD detailed routing. Other embodiments perform NPD detailed routing for the lower first set of wiring layers of the IC design without first performing global routing for those layers. These embodiments then perform PD global routing, and after the global routing, perform PD detailed routing to define PD paths that use the upper second set of wiring layers of the IC design.

[0059] The NPD detailed routing in some embodiments does not limit its pathfinding process to exploring only one or more preferred wiring directions or to penalize other wiring directions on the first set of wiring layers. The NPD detailed routing in some embodiments allows its pathfinding to explore all angles for its path extensions on this set of wiring layers, thus generating curved paths that are then geometrically depicted through the use of curved wire segments. In other embodiments, the NPD detailed routing only explores the pathfinding in a large finite number of wiring directions, such as nine or more wiring directions, and does not generate designs with curved path segments.

[0060] In some embodiments, the global and detailed routing for the PD wiring layers uses a Manhattan preferred direction, while in other embodiments, the global and detailed routing for the PD wiring layers uses other preferred direction routing (e.g., 45 degree or 60 degree routing instead of or in addition to horizontal and vertical routing). In some embodiments, the first set of wiring layers includes the first two metal layers of the IC design, and the second set of wiring layers is metal layer 3 or greater of the IC design. In other embodiments, the first set of wiring layers includes more than the first two metal layers of the IC design, for example, layers 1-4.

[0061] In some embodiments, the first set of wiring layers includes a first and second subset of layers (e.g., includes a third wiring layer and a fourth wiring layer). In these embodiments, the method performs detailed routing on the first set of wiring layers by performing a first detailed routing operation on the first subset of layers (e.g., the third wiring layer) and, after completing the first detailed routing operation, performing a second detailed routing operation on the second subset of layers (e.g., the fourth wiring layer). The method in some embodiments performs the first and second detailed routing operations by using an NPD detailed router to perform the first detailed routing operation and then recursively invoking the NPD detailed router to perform the second detailed routing operation.

[0062] 9 illustrates a routing process 900 of some embodiments that uses only detailed routing to define NPD routes for some nets on a first set of lower wiring layers, and then uses global routing and detailed routing to define PD routes for the remaining nets on the first set of lower wiring layers and the second set of upper wiring layers. As shown, process 900 begins by performing (at 905) NPD detailed routing for some nets on the lower first set of wiring layers of an IC design, without first performing global routing for these nets on the lower first set of wiring layers. As will be further described below with reference to FIG. 10, the NPD detailed routing operation (at 905) attempts to connect as many nets as possible via wire segments on the first set of wiring layers (e.g., the first three metal layers or the first four metal layers).

[0063] To perform this NPD routing, process 900 sorts the nets based on the estimated length of the path to connect each net (i.e., based on the estimated wire length to connect each net). An example of using heuristics to calculate the estimated wire length of a net is provided below with reference to FIG. 18. The sorted order is ascending, with nets with shorter estimated lengths being higher in the order than nets with longer estimated lengths. Based on this order, the NPD routing process iteratively selects as many nets as possible starting from the top of the order with shorter nets and attempts to define NPD paths for the selected nets on the lower first set of wiring layers. The NPD detailed routing operation in some embodiments does not explore paths that use wire segments on the second set of upper wiring layers (e.g., the fifth or higher metal layers). In some embodiments, the second set of upper wiring layers is reserved for PD detailed routing, which is performed at 915, as described further below.

[0064] In some embodiments, the NPD detailed routing does not use any preferred wiring direction and therefore explores all angles of wiring direction. On the first two layers, the NPD detailed routing, in some embodiments, explores all-angle wiring in unoccupied space on these layers for circuit blocks with predefined wiring, such as IP blocks with predefined PD wiring.

[0065] In some embodiments, the NPD detailed routing generates curved paths when it explores curved directions during its path exploration. Alternatively, in some embodiments, the NPD detailed routing generates curved paths because its topology router identifies a topological path by referencing some tessellated edges and faces, and then the geometric router embeds the topological path as a geometric path having one or more straight path segments and / or curved path segments based on which is more optimal. In some embodiments, the geometric router only defines an initial geometric path for each topological path, leaving the final definition of the geometric path for a subsequent post-processing operation, such as a compaction operation. As described further below, the post-processing operation in some embodiments defines the geometric path based on one or more criteria, such as compacting the design to reduce the overall die size, or widening a path to reduce capacitive coupling between nearby wires.

[0066] In some embodiments, NPD detailed routing only explores paths in a finite number of wiring directions, such as eight or more wiring directions, and does not generate designs with curved path segments. In some embodiments, NPD detailed routing is performed by an NPD detailed router formed by a topology router and a geometric router, as described above.

[0067] After performing the NPD detailed routing at 905, process 900 performs (at 910) PD global routing on the remaining unrouted nets in the IC design, and after the global routing, performs PD detailed routing on these nets (at 915). The purpose of this global routing in some embodiments is to identify routes for nets for which no route was identified by the NPD routing at 905 (e.g., nets having nodes separated by a threshold distance that are not suitable for routing through the first set of wiring layers) or for which no complete route was defined by the NPD detailed routing at 905.

[0068] The PD detailed routing (at 915) in some embodiments performs path exploration and identifies path segments (i.e., wire segments) on all available wiring layers (i.e., on the first and second sets of wiring layers), but only along the preferred wiring direction that it associates with each wiring layer. In other embodiments, the PD detailed routing (at 915) performs path exploration and identifies path segments (i.e., wire segments) on the second set of upper PD wiring layers (e.g., metal layers 5 and above), and does not explore path segments on the first set of lower wiring layers. However, the path segments that the detailed routing identifies on the second set of wiring layers often connect to path segments that the NPD detailed routing defined on the first set of wiring layers.

[0069] Similar to the PD detailed routing (at 915) of some embodiments, the PD global routing (at 910) defines a global path that may partially traverse all available wiring layers, but only along the preferred wiring direction that the global router associates with each wiring layer. Alternatively, the PD global routing (at 910) in other embodiments defines its global path with respect to a second set of upper wiring layers having only PD wiring. As mentioned above, in some embodiments, the first set of wiring layers is the first four metal layers of the IC design, and the second set of wiring layers is metal layers 5 and above of the IC design. In other embodiments, the first set of wiring layers includes only the first two or three metal layers of the IC design, or includes only the third and / or fourth metal layers.

[0070] In some embodiments, the global routing defines a global path that traverses multiple layers, as the global path is defined by reference to a three-dimensional global routing grid. In other embodiments, the global routing uses a two-dimensional grid to define a two-dimensional global path. In some of these embodiments, different edges of the global path that are along different preferred wiring directions are associated with the wiring layers associated with those directions.

[0071] In some embodiments, the global and detailed routing operations at 910 and 915 use a Manhattan preferred direction. Examples of routers that perform the global and detailed routing operations at 910 and 915 include global and detailed routers available from Cadence, Inc. or Synopsys, Inc. In other embodiments, the global and detailed routing operations at 910 and 915 use other preferred direction wiring (e.g., 45 degree or 60 degree wiring instead of or in addition to horizontal and vertical wiring).

[0072] Figure 10 illustrates an NPD detailed routing process 1000 of some embodiments. In some embodiments, the process is used (at 905) to define NPD paths on a set of one or more NPD wiring layers. As shown, the process first divides (at 1005) an IC design into partitions. Figure 11 illustrates an example of a portion 1100 of an IC design divided into nine partitions. Then, for each identified partition, the process invokes (at 1010) an instance of an NPD detailed router to identify NPD topology paths for connecting each net to nodes that fall into the identified partition.

[0073] As described above, the NPD detailed routing of the first set of wiring layers in some embodiments performs a topology routing operation to identify topology paths. For each partition that must be routed, the topology NPD detailed router of some embodiments first tessellates the partition into multiple shapes (e.g., polygons such as triangles) and then defines the topology paths in terms of the edges of the tessellated shapes. In some embodiments, the topology router tessellates the partition into polygons of different shapes than the polygons used to divide the IC, e.g., in some embodiments, the partitions are rectangular and the tessellated shapes are triangles. In other embodiments, the tessellated polygons and the partition polygons have the same shape (e.g., rectangular), but the tessellated polygons are smaller such that there are multiple tessellated polygons within each partition polygon.

[0074] After a topological path is defined for each net being routed by the NPD detailed router, the NPD detailed router performs a geometric routing operation to embed each defined topological path as a geometric path into the IC design, as further described below with reference to operation 1025 of FIG. 10 .

[0075] In some embodiments, the NPD detail router defines NPD topology paths on multiple wiring layers simultaneously (e.g., on the first four wiring layers simultaneously). Thus, in these embodiments, the NPD topology paths defined at 1010 can traverse any of the first set of wiring layers. As will be further described below with reference to FIG. 12, the NPD detail routing in other embodiments is performed on a successive set of wiring layers (e.g., first on the first wiring layer 102, then on the second wiring layer 104, or on the first two wiring layers and then on the next two wiring layers if four or more wiring layers are available for NPD wiring in the IC design). In these embodiments, the NPD topology paths defined in each iteration of the detailed routing through 1010 traverse the set of wiring layers that are being routed in that iteration of the detailed routing. In addition to these layers, the NPD router in some of these embodiments also has at its disposal, in each of its iterations, the lower wiring layers that were routed in the previous iteration of the NPD detail routing operation.

[0076] When a net has nodes that fall into multiple partitions, in some embodiments, the topology routing of the NPD detailed router that defines the topology paths for each partition identifies an NPD topology path that crosses a partition boundary so that this NPD path can later be connected (i.e., stitched) to one or more NPD paths defined in one or more other partitions to connect to one or more nodes of the net in the one or more other partitions. This stitching in some embodiments is performed (1) by NPD detailed routing for the next set of NPD wiring layers when multiple rounds of NPD detailed routing are performed for multiple successive sets of NPD wiring layers, (2) by PD global and / or detailed routing performed after NPD detailed routing, and / or (3) by post-processing operations of the NPD detailed router of some embodiments.

[0077] After 1010, the process determines (at 1015) whether to repeat its detailed topology routing operations for the identified partitions to improve its identified NPD topology paths within each partition and / or to resolve inconsistent partition boundary crossings identified by two or more NPD router instances for two or more partitions that contain nodes of the same net. In some embodiments, the NPD topology routing for each partition is intended to connect as many nodes of each net that fall within the partition as possible with NPD topology paths that are defined by referencing edges that tessellate the NPD wiring layer being routed. In some embodiments, these edges include partition edges that define the partitions on the NPD wiring layer (e.g., the nine partitions of FIG. 11). These edges in some embodiments also include edges that tessellate the interior of each partition.

[0078] In some embodiments, the topological paths are also defined by referencing nodes defined within the tessellated polygons (called faces) defined by the edges in each tessellated partition, because these nodes are used to represent vias to other NPD wiring layers that are being simultaneously routed by the NPD detailed routing process 1000. In some embodiments, the topological detailed routing defines each topological path in terms of its position relative to other topological paths along the tessellated edge and face nodes. In defining these paths, the topology router considers the available path capacity along each tessellated edge and the via capacity along each tessellated face to ensure that too many topological paths are not defined to traverse any location on an NPD wiring layer or any via between two routed NPD wiring layers.

[0079] Due to congestion and other issues, it may not always be possible to connect the nodes in each partition with only NPD wire segments, or multiple NPD topology routing iterations may be required to identify NPD paths to connect all such nodes (e.g., after new constraints are defined after each iteration). Furthermore, two or more NPD router instances for two or more partitions that contain nodes of the same net will initially define routes separately for the nodes that fall within their respective partitions. These topology paths may result in inconsistent boundary crossings for the same net. For example, FIG. 11 shows two boundary crossings 1112 and 1114 for the same net defined by two different detailed router instances that define NPD paths for two adjacent partitions 1105 and 1107. These two boundary crossings are problematic because they have some other topology paths (shown in dashed lines) of some other nets between them.

[0080] When such inconsistent NPD paths exist for multiple partitions connecting nodes of a net, or when other non-optimal NPD paths are defined, process 1000, in some embodiments, determines that additional iterations of the NPD topology routing must be performed. As the process performs more iterations of the NPD topology routing at 1010, process 1000, in some embodiments, becomes less likely to perform another iteration of the NPD detailed routing. For example, in some embodiments, a penalty score is assigned to each inconsistent set of NPD detailed paths or non-optimal NPD detailed paths, and all penalty scores are aggregated at 1010 to generate an overall penalty score. As the number of iterations through 1010 increases, the process requires that there be a higher aggregate penalty score before performing another iteration of the NPD detailed routing.

[0081] If process 1000 determines (at 1015) that another iteration of its NPD topology routing must be performed, process 1000 defines (at 1020) one or more constraints for the next iteration of NPD topology routing at 1010. Alternatively, for this next iteration of NPD detailed routing at 1010, process 1000 may share information (e.g., boundary crossing information) about different path segments that different routers have identified for the same net between different partitions, so that the next iteration of topology routing operations can consider these other paths in defining their next set of paths. After 1020, the process returns to 1010 to perform this next iteration of routing.

[0082] Figure 12 shows an example of the constraints defined at 1020. To avoid the two inconsistent boundary crossings 1112 and 1114 of the two NPD paths defined for the common net in Figure 11, process 1000, in some embodiments, defines a constraint that specifies that the NPD detailed router instances for partitions 1102 and 1104 must identify their respective paths for this net to cross a smaller area 1205 at this boundary. This smaller area ensures that the two NPD detailed router instances are unlikely to identify other NPD paths for other nets between the two boundary crossings they identify for the common net.

[0083] In conjunction with or as an alternative to defining constraints at 1020, in some embodiments, process 1000 causes each particular NPD topology router instance that routed each particular partition in the previous iteration of 1010 to share information about the topological paths it defined with (1) each other NPD topology router instance, or (2) each NPD topology router instance that defined topological paths for partitions adjacent to the particular partition (e.g., for the eight partitions adjacent to partition 1105 in FIG. 11 ).

[0084] In some embodiments, the information provided by each particular NPD topology router instance to another NPD topology router instance includes the entire definition of each topological path defined by the particular router instance, while in other embodiments, the information includes only the partition boundary crossings (if any) of each topological path that cross a shared partition boundary. Each NPD topology router instance then uses the information provided by the other NPD topology router instances in its next iteration through 1010. The router instance uses this information to define how the topological paths that the router instance defines in its next topological routing iteration more closely match the estimated locations of associated topological paths defined by the other instances (i.e., the estimated locations of other topological paths in other partitions that must be stitched to the topological paths defined by the router instance in its next iteration).

[0085] If the process 1000 determines (at 1015) that it is not necessary to perform another iteration of the NPD detailed routing, the NPD detailed routing process 1000 embeds (at 1025) each defined topological path into the IC design as a geometric path using a geometric detailed router. For each topological path, this embedding defines one or more geometric path segments along one or more allowable wiring directions, which in some embodiments may include one or more of Manhattan and diagonal wiring directions, as well as curved wiring directions allowed on the NPD wiring layer. In some embodiments, this geometrization snaps each topological path to one or more grid locations along one or more of the allowed straight, diagonal, and curved directions. After 1025, the process ends.

[0086] 13 illustrates an example of another approach of some embodiments for using path intersection data specified by a detailed router instance of one of the adjacent partitions. In this approach, the IC design partitions are divided into two groups, a gray group and a white group, arranged in a checkerboard pattern. Several detailed router instances first perform NPD detailed routing on the gray partition. The partition boundary crossings that these routers identify are then passed to an NPD detailed router instance that then detailed routes the white partition, so that NPD paths traversing the white partition can respect the boundary crossings identified by the detailed router of the gray partition. As multiple iterations are performed on the white and gray partitions, the router instances for each set of colored partitions iteratively pass their boundary crossing information to the router instance of the next set of colored partitions until the routing iterations are finished.

[0087] FIG. 14 illustrates another NPD detailed routing process 1400 in some embodiments. This process 1400 is similar to process 1000, except that the process 1400 iteratively performs NPD detailed routing on different sets of one or more NPD wiring layers. To that end, the process 1400 includes operations 1405 and 1410 for selecting a successive set of one or more NPD wiring layers for detailed routing. After selecting (at 1405) a successive set of NPD wiring layers, the process 1400, in some embodiments, iteratively performs operations 1010-1020 to identify an NPD path that traverses the selected set of NPD wiring layers. When identifying an NPD path on the currently selected set of NPD wiring layers, the process 1400, in some embodiments, also explores a path search option in one or more lower wiring layers that are part of one or more previously selected sets of NPD wiring layers. In other embodiments, the process 1400 does not explore previously explored lower wiring layers while identifying an NPD path on the currently selected set of NPD wiring layers.

[0088] At 1410, the process determines whether it has selected the last set of NPD wiring layers. If not, the process returns to 1405 to select the next set of NPD wiring layers, and then repeats its operations until it determines in its last iteration through 1410 that it has selected the last set of NPD wiring layers. In some embodiments, the selected set of NPD wiring layers includes only one wiring layer at a time. In these embodiments, process 1400 defines NPD paths sequentially for successive individual NPD wiring layers, e.g., first for a first NPD wiring layer, then for a second NPD wiring layer, then for a third NPD wiring layer, etc. In other embodiments, the selected set of NPD wiring layers includes two or more NPD wiring layers that were selected simultaneously at 1405 for detailed routing.

[0089] Also, in some embodiments, process 1400 first selects the third wiring layer as its first NPD wiring layer to route, and explores only the first and second wiring layers to connect to pins on the substrate, and for opportunistic route expansion when it does not find a better option on the third layer. In some of these embodiments, process 1400 uses the first through third wiring layers for the same reasons while identifying NPD routes for the fourth NPD wiring layer.

[0090] If two or more NPD wiring layers are being routed simultaneously with another NPD wiring layer, an NPD path defined by a detailed router (which routes multiple NPD wiring layers simultaneously) may traverse multiple NPD wiring layers. To traverse different NPD wiring layers, the NPD path uses vias to connect different segments of the path on different NPD wiring layers.

[0091] Some embodiments use multi-beam mask writing to allow for curvilinear masks, which can then be used to generate curvilinear components on target wafers and dies. To take advantage of such mask writing and wafer production, some embodiments provide physical design EDA tools that generate the curvilinear designs. One example of such a physical design tool is the NPD detail router mentioned above, which generates curved paths.

[0092] To facilitate the generation of their curved designs (e.g., their curved paths), physical design EDA tools of some embodiments define their designs in the pixel domain rather than the contour domain. Because machine learning processes are often optimized to handle pixel-based data sets, pixel-based designs are also ideal for analyzing and generating curved designs by using machine learning. Indeed, many machine learning applications do not handle contour-based descriptions of data sets. Thus, by converting the physical design (e.g., routing) to operate in the pixel domain instead of the contour domain, some embodiments make machine learning much more accessible for use by physical design tools.

[0093] Similarly, to facilitate the creation of these masks, some embodiments use the pixel domain to perform the processing required to generate these masks, because a curvilinear mask operated in the pixel domain takes the same time as any Manhattan design. This processing is also often performed on a GPU in the pixel domain. GPUs are excellent single-instruction multiple-data (SIMD) machines in the pixel domain because a single instruction stream can be applied uniformly to many pixels, so the vast capabilities of GPU processing power for this type of pixel manipulation make them ideal. Relying on SIMD architectures can generate much higher computing throughput for processing physical designs and masks with curvilinear shapes.

[0094] Contours (also called geometry) are usually represented as piecewise linear polygons, but may also be represented in infinite resolution curve formats such as splines. Manipulating contours is the mathematical dual of manipulating pixel-based data, given the resolution limit. Mathematical duality means that functionally, anything that can be done on one can be done on the other. However, when run-time performance or efficiency is considered, the computational behavior of one can be quite different from the other, given a particular precision of the result as a target.

[0095] In general, manipulating shapes that are mostly large rectangles is faster in the contour domain (i.e., the geometry domain), and manipulating shapes that are mostly polygons or curves and have a higher vertex density is faster in the pixel domain. In the pixel domain, the pixel size is naturally defined from the resolution limit. Once the pixel size is defined, it does not matter whether the shapes being processed are curved or straight. Either computation is constant time. This is not the case for contour-based operations, since the computation time depends on the number of piecewise linear edge counts used to represent the contour. Also, given that many of these data processing operations are performed by high-performance GPUs, pixel-based analysis is preferred over contour-based analysis, since GPUs are SIMD machines that excel in the pixel domain.

[0096] To further elaborate on these points, a brief review of IC design and manufacturing will be useful. In the past, EDA systems for both design and manufacturing have used Manhattan shapes, often extended with 45 degree edges, as the basic building blocks to be calculated. A Manhattan shape is a shape with axis-parallel edges with 90 degree corners. A fundamental limitation in manufacturing semiconductors with shapes other than Manhattan shapes has been that in the past, all precision layers on a mask had their masks written with a Variable Shaped Beam (VSB) mask writer that exposed a rectangle of a specific minimum size (e.g., 1 nm to 100 nm on a side) and maximum size (e.g., 200 to 1000 nm on a side).

[0097] VSB writers expose the mask one rectangle at a time, so the mask writing time is roughly proportional to the number of rectangles that need to be written. Diagonal or curved lines can be approximated with a series of stepped rectangles. However, the number of rectangles can be very large, making the mask writing time very long to get a sufficiently accurate approximation. To target non-Manhattan features on the wafer, non-Manhattan features on the mask are required, even including the effects of optical proximity correction (OPC) or an advanced form of OPC called inverse lithography technology (ILT).

[0098] Non-Manhattan shapes on the mask were not practical for VSB writers except in very limited applications, so non-Manhattan shapes were not feasible for semiconductor design shapes targeted at the wafer. 45 degree triangles are an exception to the Manhattan limit for VSB machines. This led to the Cadence X-Architecture, which used 45 degree routing to reduce power consumption and improve chip performance.

[0099] VSB data preparation techniques using overlapping shots and mask-wafer mutual optimization are techniques that can be used to effectively target curvilinear features on the mask using a reasonable number of VSB shots. However, such techniques are limited to 193i lithography for practical applications. EUV (extreme ultraviolet) masks have many smaller features that need to be written with higher precision (because EUV can "see" better than 193i), and therefore these techniques are not practically viable. Therefore, there is no general solution that allows curvilinear target design on the wafer for VSB mask writing.

[0100] In recent years, multi-beam mask writers have become available for production use in leading mask shops around the world. Multi-beam mask writers write masks with an array of fixed-sized pixels that expose the mask. Since the pixel size is fixed, the writing time of the machine does not vary with design complexity or shape as with VSB machines. This allows curved masks to actually be written as well as Manhattan shapes. This in turn allows for curved target design shapes on the wafer.

[0101] The physical design of semiconductor chips is computer-aided, either in interactive manipulation of geometry or in automatic placement and routing of the design. In either case, physical verification of the design against physical rules (such as spacing and minimum width or area rules) as well as connectivity extraction and parasitic extraction of electrical parameters (such as resistance, capacitance and inductance) are performed on the physical design. Today, the vast majority of these capabilities operate in the contour / geometry domain, since VSB mask writers can only reasonably write masks to target these wafer shapes and are better off optimizing for mostly rectangular designs, and indeed mostly Manhattan designs.

[0102] In contrast to these prior art techniques, some embodiments of the present invention use multi-beam mask writing to enable curvilinear masks and therefore curvilinear design targets on wafers. To take advantage of such mask writing and wafer production, some embodiments provide physical design tools that generate curvilinear designs. Just as a curvilinear design takes the same time to write on a multi-beam machine, a curvilinear mask manipulated in the pixel domain takes the same time as any Manhattan design.

[0103] Furthermore, when processing is performed on a GPU in the pixel domain, the advantages of SIMD architectures become evident, yielding much higher computing throughput, due to the enormous capacity of GPU processing power for that type of pixel manipulation, where a single instruction stream can be applied uniformly to all pixels. Just as curve designs take a long time to write on a VSB machine, curve masks operated on in the contour / geometry domain take much longer than a typical Manhattan design. This is because, whether the contour is represented as a piecewise linear polygon of some reasonable vertex spacing, or as some version of a spline or NURBS format, the number of vertices required increases with increasing curvature, and the computational algorithms that reside in the contour / geometry domain scale their execution time based on the number of vertices.

[0104] Given a particular resolution limit, it is not necessary to represent curvilinear shapes in the contour / geometry domain. In semiconductor manufacturing of curvilinear shapes, that resolution limit is provided by the fact that these masks are written with multi-beam mask writers. Multi-beam mask writers have a known pixel size that is used to print the mask. The resolution limit determined by that pixel size is the resolution limit that can be used to determine the pixel size needed to manipulate any semiconductor design in the pixel domain. This is a lower bound on the minimum pixel size that could possibly be needed to drive the required precision achievable in the manufacturing process.

[0105] However, other criteria may further limit the possible resolution of the output shape and therefore the design shape. For example, ILT is calculated in pixel dose. Some ILTs operate in the frequency domain (e.g., TrueMask ILT), but they also represent the mask in pixel dose. It is clear that there is a physical limit to the achievable resolution of any semiconductor device, whether the resolution of the mask, and therefore the resolution of the wafer, is limited by the pixel size of the mask writer, or by the pixel size of the ILT, or by some other pixel size. This determines the pixel size to which the contour / geometry operations are mathematically dual. However, the execution time of algorithms operating in the pixel domain is constant regardless of the amount of curve content and regardless of the shape. Furthermore, given GPU acceleration, the pixel domain calculations are massively parallelizable, which in turn significantly reduces the overall execution time.

[0106] FIG. 15 illustrates a process 1500 for fabricating ICs with curved paths, according to some embodiments of the invention. As illustrated, the process begins by defining (at 1505) paths in an IC design that are defined in the pixel domain or that are converted to the pixel domain after a routing stage. When defined in the pixel domain, each path is expressed in terms of the set of pixels occupied by the path in the three-dimensional space in which the IC design is defined. The IC design, in some embodiments, has one or more NPD wiring layers and one or more PD wiring layers, while in other embodiments, the IC design has only NPD wiring layers. One or more paths on each NPD wiring layer can be curved paths, where a curved path is a path that has one or more curved segments. On each NPD wiring layer, paths can also traverse more than eight linear directions in some embodiments.

[0107] During routing (at 1505), process 1500, in some embodiments, uses machine learning to perform its routing operations. For example, when geometrically drawing the topological path at 1025, process 1000, in some embodiments, uses machine learning to identify different estimated manufacturing wires to be generated on the IC or IC mask for different possible geometrizations of the same topological path of the net, in order to evaluate different geometrizations and select one of them as the geometric path of the net.

[0108] In some embodiments, a pixel-based definition of each possible geometric path for a net is fed to a machine-trained network (e.g., a neural network), which then generates estimated manufactured wires that are likely to be generated for the geometric paths on an IC or an IC mask used to manufacture the IC. The different estimated manufactured wires for the same net are then compared to one or more criteria (e.g., design rule checking or capacitance extraction criteria / modeling) to determine which of the geometric paths results in an estimated manufactured wire that best matches the criteria or does not violate any of the criteria.

[0109] After defining the path, the process 1500 then performs (at 1510) a compression operation that uses machine learning to find an optimal compression of the path. Some examples of such compression operations are described in U.S. Patent Application No. 17 / 992,876, which is incorporated herein by reference. Next, at 1515, the process 1500 uses OPC and ILT to generate a mask curve shape. At 1520, the process then uses a multi-beam mask manufacturing process to manufacture a mask for manufacturing ICs. At 1525, the process uses the mask to manufacture ICs. After 1525, the process ends.

[0110] In some embodiments, process 1500 iterates several times between its operations 1505-1515 to generate an acceptable mask that meets desired performance characteristics and / or to generate an IC design having an optimal set of paths for manufacturing the IC. These iterations are not shown in FIG. 15 so as not to obscure the description of process 1500 with unnecessary detail. U.S. Patent Application Serial No. 16 / 949270 describes iteratively performing physical design and mask manufacturing operations until an IC design having desired characteristics is identified. U.S. Patent Application Serial No. 16 / 949270 is incorporated herein by reference.

[0111] As mentioned above, curved wire segments can be inadvertently created on ICs designed to have only Manhattan or 45 degree wiring because Manhattan and diagonal jogs on PD wiring layers can result in curved jogs on these layers due to manufacturing limitations that make it difficult to create 45 degree or 90 degree junctions.

[0112] However, currently existing EDA tools do not generate IC designs with curved wiring or NPD full angle straight wiring on the wiring layers of the design. This is because EDA tools do not generate IC designs to be manufactured with a manufacturing process (e.g., mask making process) that is created to generate curved wires and NPD full angle straight wiring. FIG. 16 shows an example of five wiring layers 1602-1610 of an IC design generated by one or more physical design tools (e.g., one or more routers and / or compactors) of some embodiments. The first wiring layer 1602 and the second wiring layer 1604 are NPD curved layers with Manhattan path segments, diagonal path segments, and curved path segments, and the third layer 1606, the fourth layer 1608, and the fifth layer 1610 are PD layers with alternating Manhattan PD layers.

[0113] The five wiring layers 1602-1610 of the IC design in some embodiments are then used to define masks that generate the five wiring layers of IC 100 in FIG. 2. Similar to the metal layers shown in FIG. 16, the physical design tools of some embodiments define similar sets of metal layers for the IC designs of other ICs shown in other figures above (e.g., FIGS. 1-7). Like their corresponding ICs, the wiring layers in the IC design in some embodiments have paths on NPD wiring layers that have straight (e.g., Manhattan or diagonal) segments and curved segments. The paths on these wiring layers are then used to generate masks that can then be used to fabricate ICs with NPD straight and curved wiring.

[0114] Although the first two wiring layers 1602 and 1604 are shown to be NPD curved layers, in other embodiments, the IC design has other NPD wiring layer architectures as described above. For example, in some embodiments, the third and fourth wiring layers of the IC design are NPD wiring layers, and the first and second wiring layers have blocks of PD wiring, with the area between them free for NPD straight and curved routing.

[0115] 17 illustrates another example of a metal layer 1700 of an IC design that is defined to have curved path segments. This metal layer is the fourth metal layer of the IC design. As shown, the fourth metal layer 1700 has a preferred vertical routing direction. This layer also has a bus 1720 with a set of curved jogs 1725 that allow the bus to be repositioned on the metal layer to get around an obstacle 1750 on this layer. The curved jogs 1725 allow the bus to move to the left as it moves from the bottom side of this layer to its top side.

[0116] Curved jogs in IC designs are much more preferred than Manhattan or diagonal jogs in IC designs because they are much closer to what will be fabricated on an IC and are therefore more useful design structures to analyze for modeling of IC components in the design (e.g., for capacitance extraction modeling). Curved jogs are also more preferred because they can be fabricated to occupy less space than horizontal or diagonal jogs defined in the IC design (i.e., curved jogs can be generated more compactly than Manhattan or diagonal jogs).

[0117] Curved wiring in IC designs and ICs also has several advantages over straight wiring. For example, curved wire jogs have less resistance than Manhattan wire jogs because they provide a smoother path for the flow of electricity. Also, as mentioned above, curved jogs are closer to what will ultimately be produced in the IC, so they are more accurately modeled in the IC design. Furthermore, curved jogs are also more reliably manufacturable than Manhattan or diagonal jogs because they are closer to what will be manufactured than Manhattan or diagonal jogs.

[0118] Vias can be a source of manufacturing reliability issues for ICs. Therefore, some embodiments use a curvilinear NPD router designed to reduce the number of vias. In some embodiments, this reduction sometimes comes at the expense of having longer curvilinear NPD paths on individual NPD wiring layers, but this sacrifice is acceptable due to the reliability cost of the vias and the relatively small cost of slightly longer short net connections. Figures 18 and 19 show two example routing processes 1800 and 1900 that define a curvilinear NPD router to reduce the number of vias. Figure 19 achieves this by routing one NPD wiring layer at a time, while Figure 18 achieves this by making the vias much more expensive than the wire length.

[0119] As shown, process 1800 of FIG. 18 first identifies (at 1805) a subset of short nets to attempt to route on an NPD wiring layer of the IC design being routed. In some embodiments, the IC design is a design of an entire IC or a portion of an IC. Some embodiments identify "short" nets by using heuristics to calculate an estimated wirelength for each net, sorting the nets based on the calculated estimates, and then selecting a subset of the nets based on the sorted order. Examples of heuristics for each net in some embodiments include a size bounding box for the net (e.g., a rectangular area that contains all pins of the net), the length of the Steiner tree connecting the pins of the net, etc.

[0120] Also, based on the sorted order, process 1800 in some embodiments selects a certain percentage of the nets (e.g., 40% or 50%) for NPD curve routing (i.e., selects a certain percentage of the nets with the shortest estimated wirelengths based on the sorted order), while in other embodiments process 1800 makes this selection based on another criteria (e.g., by selecting all nets with calculated estimated wirelengths less than a threshold estimated wirelength).

[0121] At 1810, process 1800 selects a set of two or more wiring layers to route. In its first iteration through 1810, process 1800 in some embodiments selects a first and a second wiring layer. In some embodiments, the first and second wiring layers have regions with predefined PD wiring for connecting electronic components to the circuitry of predefined circuit blocks (such as IP blocks). In such embodiments, the NPD router identifies NPD straight and curvilinear paths in the unused space between the regions with PD wiring on these layers. In performing path searching to identify such paths on the first and second wiring layers in these embodiments, the NPD router does not penalize any routing direction. After NPD routing on one of the first two layers, more than a threshold amount (e.g., 90%) of wires may still be along the preferred direction, so that when routing is complete, that layer still appears as a PD wiring layer.

[0122] At 1815, process 1800 performs its NPD routing operation to identify NPD routes that traverse on the NDP wiring layer selected at 1810 for the number of short nets identified at 1805 for which no route has yet been defined. The routing operation at 1815 is biased against the use of vias, but does not penalize any routing direction in order to bias routing against any direction, as described above.

[0123] To bias the vias, the routing process 1800 in some embodiments uses a much higher cost for vias between NPD wiring layers of the current set of layers being routed (i.e., last selected in 1810) than a wirelength cost, which represents the cost associated with the path length on any one of the NPD wiring layers of the current set of layers being routed. Also, the via cost between NPD wiring layers in some embodiments is higher than the via cost used later during PD routing in 1830 for vias between PD wiring layers or between an NPD wiring layer and a PD wiring layer.

[0124] Also, in some embodiments, the cost of a via from between two layers is a multiple of the wire length cost of a plane connection on one or both of these layers. In some of these embodiments, the cost of a via from between two NPD layers is a larger multiple of the wire length cost of a plane connection on one or both of these layers than the via cost between two PD layers or between an NPD layer and a PD layer. For example, in some of these embodiments, the via cost between two NPD wiring layers as evaluated by the NPD routing operation in 1815 is M times the wire length cost of a plane connection on one or both of the two NPD wiring layers, while the via cost between two PD wiring layers or between an NPD wiring layer and a PD wiring layer as evaluated by the PD routing operation in 1830 is N times the wire length cost of a plane connection on one or both of the two NPD wiring layers, where M is greater than N. In some embodiments, M is several times greater than N, for example, two or three times greater or more.

[0125] This biasing of vias reduces the number of vias that the routing operation at 1815 defines between NPD wiring layers of the current set of layers being routed. As noted above, in some embodiments, this reduction may come at the expense of longer curvilinear NPD paths on each NPD wiring layer, but this sacrifice may be acceptable due to the higher reliability cost of vias and the relatively small cost of slightly longer short net connections.

[0126] Each path identified for each net, in some embodiments, connects the pins of the net. Each identified path may also be a curvilinear path with one or more curved edges, or a linear path with only straight edges. In some embodiments, the routing operation at 1815 typically includes multiple iterations, each iteration collaboratively routing on multiple processing nodes (e.g., processing cores of one or more multi-core processors of the computer performing the routing) for some or all partitioned regions of the IC design. If one or more short nets span multiple partitions, partition crossing locations for each such short net may have to be identified through successive iterations of the routing operation at 1815 for the same set of NPD wiring layers to determine where and how to stitch together path segments defined in different partitions for one.

[0127] Examples of connecting different path segments defined for a net in different partitions have been described above with reference to Figures 11-14. Also as described with reference to these figures, some embodiments perform NPD routing at 1815 by first identifying topological paths for routed short nets and then geometrically drawing the identified topological paths for these nets. In other embodiments, the NPD routing at 1815 is purely a topological routing operation that identifies a topological path for each net, and after completion of the NPD paths for all short nets (e.g., after 1825), is followed by a geometricization operation that identifies geometric paths for the identified topological paths.

[0128] After performing the routing operation at 1815 for the currently selected set of wiring layers, there may be one or more identified "short" nets for which process 1800 has not yet identified a path. Thus, at 1820, process 1800 adds these short nets to a list of short nets that need to be routed in the next NPD routing iteration through 1815 or in a PD routing operation at 1830. In some embodiments, process 1800 maintains only one "nets to be routed" list for all of its iterations through NPD routing operation 1815, so there is no need to add short nets that are not being routed for NPD routing to the not-routed list.

[0129] At 1825, process 1800 determines whether it has selected all available wiring layers available for NPD routing. If not, the process returns to 1810 to select another set of wiring layers for NPD routing and then identify NPD paths on the newly selected set of wiring layers for the remaining unrouted short nets. In some embodiments, the wiring layers available for NPD routing are only a subset of the wiring layers, e.g., in some embodiments only layers 1-4, and do not include all of the wiring layers, e.g., not including wiring layers 5-7.

[0130] In some embodiments, the wiring layer sets selected in successive iterations for NPD routing through 1810 do not overlap, while in other embodiments they may be different sets but overlap with one or more wiring layers that are common between the two sets selected in the two iterations through 1810. Regardless of whether successive selected sets of wiring layers overlap, a subsequently selected wiring layer set includes at least one upper wiring layer that was not in the previously selected wiring layer set or sets.

[0131] In some embodiments, when process 1800 has routed all or most of the short nets on a previously selected wiring layer set, process 1800 adds to the list of "nets to be routed" one or more "medium" or longer length nets to be routed on a subsequently selected wiring layer set (i.e., the wiring layer set selected in 1810 after the last iteration through 1825). This approach ensures that NPD routing is used as much as possible for as many nets as possible. In some embodiments, process 1800 adds longer nets to the "nets to be routed" list based on their estimated wirelength (calculated by one of the heuristics described above), with nets with smaller estimated wirelengths being added before nets with larger estimates.

[0132] If the process determines (at 1825) that it has selected all available wiring layer sets for NPD routing, the process then invokes (at 1830) a PD router to route the remaining unrouted nets. In some embodiments where the routing operation at 1815 is a purely topological routing operation, process 1800 uses a geometric router to generate geometric paths for the topological paths defined for one or more sets of NPD wiring layers at 1815 before invoking the PD router to route the remaining unrouted nets. The PD router in some embodiments treats the NPD paths defined by process 1800 as obstacles in the routing graph, but otherwise proceeds with routing the unrouted nets that have PD paths defined on all wiring layers, including the NPD wiring layer that was routed by NPD routing process 1800. After 1830, the process ends.

[0133] In some embodiments, NPD routing operations 1805-1825 of process 1800 are performed by an NPD router, and PD routing operation 1830 is performed by a separate PD router. In other embodiments, both NPD and PD routing operations are performed by a single router that performs NPD routing on a first set of wiring layers (e.g., layers 1-4) while performing PD routing on a second set of wiring layers (e.g., layers 5 and above). To ensure that NPD routing is used only for shorter nets, routing process 1800, in some embodiments, penalizes NPD paths that are longer than a threshold distance or imposes constraints that prevent these paths from being longer than a threshold distance.

[0134] 19 illustrates an NPD routing process that reduces the number of vias between NPD wiring layers by routing one NPD wiring layer at a time. This reduction comes at the expense of longer curvilinear NPD paths on each wiring layer, but this sacrifice is acceptable due to the reliability cost of the vias and the relatively small cost of the longer short net connections.

[0135] As shown, process 1900 first identifies (at 1905) a subset of short nets to attempt to NPD route on a wiring layer of the IC design being routed. In some embodiments, the IC design is a design of an entire IC or a portion of an IC. Some embodiments identify "short" nets by using a heuristic to calculate an estimated wirelength for each net, sorting the nets based on the calculated estimates, and then selecting a subset of the nets based on the sorted order. Examples of such heuristics are described above with reference to FIG. 18.

[0136] At 1910, process 1900 selects a particular wiring layer (also referred to as a routing layer) that is available for NPD routing and is the next lowest wiring layer that the process has not yet selected for NPD routing. In some embodiments, process 1900 first selects (at 1910) a first wiring layer and in subsequent iterations through 1910 selects steps through the remaining wiring layers available for NPD routing, e.g., steps through layers 2-4. In other embodiments, process 1900 first selects (at 1910) a third wiring layer and in subsequent iterations through 1910 selects steps through the remaining wiring layers available for NPD routing, e.g., steps through layer 4. In some embodiments, the wiring layers available for NPD routing are only a subset of the wiring layers, e.g., in some embodiments only layers 1-4, and do not include all of the wiring layers, e.g., not including wiring layers 5-7.

[0137] Next, at 1915, the process 1900 identifies, for a number of short nets identified at 1905 for which no paths have yet been defined, NPD paths that traverse on the routing layer last selected at 1910. Each NPD path identified for each net, in some embodiments, connects two or more nodes (e.g., two or more pins) of the net. Each identified NPD path may be a curvilinear path with one or more curved edges (along with zero or more straight edges) or a straight path with only straight edges.

[0138] To identify each NPD path for each net during each iteration through 1915 performed for the particular selected wiring layer, process 1900 performs a path search to identify paths between two or more nodes of the net to be connected, and then embeds the identified paths as paths between the two or more nodes. This path search in some embodiments does not search for path extensions to any wiring layers above the particular NPD wiring layer to identify paths that traverse to an upper wiring layer and then traverse back to the particular NPD wiring layer or to a lower layer. In some embodiments, this path search searches for path extensions on the particular selected wiring layer and any wiring layers below the particular selected wiring layer. In other embodiments, this path search searches for path extensions only on the particular selected wiring layer. In some of these embodiments, the path search of the nets may identify incomplete paths for nets that terminate at via locations to upper layers. In some embodiments, subsequent iterations of NPD or PD routing performed for the upper layers then perform path search starting from these via locations to complete paths for these nets.

[0139] These different path finding approaches in different embodiments result in different paths being defined during the routing operation at 1915 for each particular wiring layer selected at 1910. In some embodiments, the routing operation at 1915 for the particular selected wiring layer does not use vias to any upper wiring layers not yet selected in any iteration through 1910 to identify paths that traverse to an upper layer and then back to the particular selected wiring layer or to lower layers. Also, this routing operation in some embodiments uses only vias to connect the particular selected wiring layer to (1) lower layers on which pins of the nets (being routed) are defined, or (2) lower layers for which path segments for these nets were previously identified in one or more previous iterations through 1910 (the iterations prior to the current iteration through 1910).

[0140] Other embodiments implement the "no vias" constraint differently. For example, to reduce or eliminate vias to lower wiring layers during routing of any one particular wiring layer, a routing operation for a lower wiring layer below the particular wiring layer identifies via locations for traversing from the lower wiring layer to the particular wiring layer, as described above. Additionally or alternatively, in some embodiments, the NPD routing process 1900 at the start of NPD routing for any one wiring layer (selected in 1910) defines expected contact locations on the selected wiring layer for connecting to lower layer pins or pin contacts. For any given pin, such expected contact locations on the selected wiring layer are either directly above the pin or pin contact if there is no obstruction to the lower pin or pin contact, or at an offset location above the lower pin or pin contact, which is connected to the pin or pin contact via a trace defined on the lower substrate and wiring layer via a path segment defined by the NPD routing process 1900 prior to starting NPD routing of the selected wiring layer.

[0141] In some embodiments, the routing operation at 1915 typically includes multiple iterations, with each iteration collaboratively routing all partitions of the IC design being routed by process 1900 on multiple processing nodes (e.g., processing cores of one or more multi-core processors of the computer performing the routing). If one or more short nets span multiple partitions used to divide the routing region, partition intersection locations are identified according to one of the methods described above with reference to Figures 11-14 and 18.

[0142] Also, as described with reference to these figures, some embodiments perform NPD routing at 1915 by first identifying topological paths for the routed short nets and then geometrically drawing these nets. In other embodiments, the NPD routing at 1915 is purely a topological routing operation that identifies topological paths for each net, and after completion of the NPD paths for all short nets (e.g., after 1925), is followed by a geometry operation that identifies geometric paths for the topologically identified paths.

[0143] After performing 1915 for the currently selected wiring layer (i.e., the wiring layer last selected in 1910), there may be one or more identified "short" nets for which process 1900 has not yet identified a route. Thus, in 1920, process 1900 adds these short nets to a list of short nets that need to be routed in the next NPD routing iteration through 1915 or in a PD routing operation in 1930. In some embodiments, process 1900 maintains only one "nets to be routed" list for all of its iterations through the NPD routing operation 1915, so there is no need to add short nets that are not being routed for NPD routing to the not-routed list.

[0144] At 1925, the process 1900 determines whether it has selected all available wiring layers for NPD routing. If not, the process returns to 1910 to select the next higher level wiring layer available for NPD routing and then identify NPD paths on the newly selected wiring layer for the remaining unrouted short nets.

[0145] In some embodiments, when process 1900 has routed all or most of the short nets on one or more previously selected NPD wiring layers, process 1900 adds one or more "medium" or longer length nets to be routed on the currently selected NPD wiring layer (i.e., the NPD wiring layer selected at 1910 after the last iteration through 1925) to a list of "nets to be routed". This approach ensures that NPD routing is used as much as possible for as many nets as possible. In some embodiments, process 1900 adds longer nets to the "nets to be routed" list based on their estimated wirelength (calculated by one of the heuristics described above), with nets with smaller estimated wirelengths being added before nets with larger estimates.

[0146] If the process determines (at 1925) that it has selected all available wiring layers for NPD routing, the process then invokes (at 1930) a PD router to route the remaining unrouted nets. In some embodiments where the path defined in 1915 is a topological path, process 1900 performs a geometry operation after 1925 to define a geometric path for the topological path before invoking the PD router to route the remaining unrouted nets. The PD router in some embodiments treats the NPD path defined by process 1900 as an obstacle in the routing graph, but otherwise proceeds with routing the unrouted nets that have PD paths defined on all wiring layers, including the wiring layer used by the NPD router to define the NPD path. After 1930, the process ends.

[0147] In some embodiments, the NPD routing operations 1905-1925 of process 1900 are performed by an NPD router, and the PD routing operation 1930 is performed by a separate PD router. In other embodiments, both the NPD and PD routing operations are performed by a single router that performs NPD routing on a first set of wiring layers (e.g., layers 1-4) while performing PD routing on a second set of wiring layers (e.g., layers 5 and above). To ensure that NPD routing is used only for shorter nets, routing process 1900, in some embodiments, penalizes NPD paths that are longer than a threshold distance or imposes constraints that prevent these paths from being longer than a threshold distance.

[0148] By not exploring via path extensions or by limiting via path extensions to reach pins or pin contacts of unrouted nets, the NPD routing process 1900 significantly reduces the number of vias it defines. In some embodiments, this reduction can come at the expense of longer curvilinear NPD paths on individual NPD wiring layers, but this sacrifice is tolerable due to the relatively small cost of longer short net connections versus the high reliability cost of vias.

[0149] 20-22 provide an example illustrating the significant reduction in the number of vias that can be obtained by using the NPD routing process 1900 of FIG. 19. FIG. 20 illustrates a set of nets that need to be connected through paths. In this illustration, the pins 2005 of each net that needs to be connected are linked through one or more lines 2010. Each connected set of lines and pins effectively represents a net that needs to be connected. As mentioned above, a net in some embodiments is a collection of pins that need to be connected.

[0150] Figure 21 shows conventional Manhattan paths on metal layers 3 and 4 connecting the pins of each of several nets shown in Figure 20. In Figure 21, the solid lines are on metal layer 3 with preferred horizontal routing, and the dashed lines are on metal layer 4 with preferred vertical routing. Each path in several of the paths shown has one or more horizontal path segments defined on the horizontal PD metal layer 3 and connected to one or more vertical path segments defined on the vertical PD metal layer 4. In each such path, each pair of connected horizontal and vertical segment pairs is connected through a via, resulting in a very large number of vias (e.g., 176) in Figure 21.

[0151] FIG. 22 shows curvilinear NPD paths on metal layers 3 and 4 connecting the pins of each of several nets shown in FIG. 20. In FIG. 22, the solid lines are on metal layer 3 with NPD directional wiring, and the dashed lines are on metal layer 4 with NPD directional wiring. Each NPD path has one or more curved path segments defined on one or two curvilinear NPD wiring layers. In each such path, the NPD path uses vias only to get from the pin connected to the path to the NPD wiring layer in which the path is defined, and does not use vias to connect the solid path segment on layer 3 to the dashed path segment on layer 4. This approach results in a significantly smaller number of vias (e.g., 20) in FIG. 22. This approach comes at the expense of some of the NPD paths on a given NPD layer having slightly longer lengths, especially when going around obstacles on the NPD layer. Examples of such longer length NPD paths (longer to go around obstacles) include NPD paths 2220, 2222, and 2224.

[0152] Also, in the example of FIG. 22, most of the NPD routing is defined on the third metal layer (i.e., most of the routing is shown in solid lines). This is because most of the routing can be defined on just one NPD wiring layer by allowing longer curved wires on one NPD wiring layer while avoiding vias to other NPD wiring layers. The longer lengths of the curved routing on metal layer 3 can be tolerated because these routings are still relatively short (i.e., do not require buffering) and avoid vias that are suboptimal from a manufacturing perspective. This approach also consumes less area on metal layer 4, which can now be used to define the NPD routing for some of the medium-sized nets.

[0153] 23 illustrates an NPD router 2300 of some embodiments. As shown, the NPD router 2300 includes a topology router 2305, a geometric router 2310, and a post-routing optimizer 2315. The topology router 2305 in some embodiments tessellates each NPD wiring layer of an IC design, or partitions of each such layer, into a number of polygons (also called faces), and then defines topology paths (for connecting nets) by referencing edges of the tessellated layers.

[0154] A particular topological path has its position defined by its relative position with respect to other topological paths along the edges that the particular topological path crosses. Some embodiments also use nodes associated with polygonal faces to model vias between NPD wiring layers that are traversed by a topological path. In these embodiments, topological paths are defined not only by edges, but also by face nodes and their relative positions with respect to each other by referencing these edges and face nodes. In some embodiments, each particular topological path is also defined by the coordinates of the pair of nodes (in the netlist) connected by the topological path, or simply by referencing the pair of nodes as the start and end points of the topological path.

[0155] The geometric router 2310 in some embodiments defines a geometric realization for each topological path defined by the topology router 2305. In some embodiments, the geometric router snaps each topological path to a grid (imposed on the wiring layer) along the allowed wiring direction for the layer. In embodiments that allow curved segments, this snapping allows the wire segments to be curved. To generate a geometric realization of a topological path, the geometric router 2310 in some embodiments searches for straight and curved realizations of edges in the topological path, thereby generating straight and curved edges.

[0156] In some embodiments, the geometric router 2310 defines specific geometric coordinates for the geometric paths it defines, and therefore specifies specific spacing between paths, whereas the topology router 2305 does not specify specific geometric coordinates for the topological paths it defines. However, in some embodiments, the topology router takes into account the expected wire thickness of the topological paths in order to track congestion along tessellated edges.

[0157] The post-routing optimizer 2315 attempts to improve the geometric path generated by the geometric router 2310 based on one or more optimization criteria. In improving the geometric path, the post-routing optimizer in some embodiments may move one or more edges of the geometric path and / or further define the geometric path by providing additional edges in the geometric path or combining some edges in the geometric path.

[0158] In some embodiments, optimizer 2315 is a compactor that defines a tighter compression of the geometric paths. The optimization criteria in this case reduces the size of the IC design. In other embodiments, the optimization criteria includes timing or spacing criteria that direct optimizer 2315 to more evenly space the geometric paths generated by geometric router 2310 to improve timing performance of signals traversing interconnects generated based on these paths.

[0159] A more even distribution of the geometric paths results in reduced parasitic capacitance due to the proximity of interconnect lines generated based on the geometric paths. In other words, spacing the paths more evenly reduces the parasitic capacitance loading on the wires, which in turn reduces signal delays due to parasitic capacitance. In yet other embodiments, the post-routing optimizer 2315 attempts to modify the geometric paths based on other criteria and / or based on multiple criteria.

[0160] As shown, the NPD router 2300 has a feedback loop from the post-routing optimizer 2315 to the geometric router 2310. The optimizer 2315 uses this feedback loop when it instructs the geometric router 2310 to identify a better set of one or more geometric routers for one or more nets in the IC design or partition being routed when the optimizer determines that this set of paths has sub-optimal performance (e.g., is too capacitively loaded or too long to meet timing constraints). The post-routing optimizer 2315 in some embodiments can instruct the geometric router 2310 to identify a better set of paths in multiple iterations until an optimal set of geometric paths is identified for the set of nets.

[0161] In some embodiments, the geometric router 2310 only defines an initial geometric path for each topological path, leaving the final definition of the geometric path for the post-routing optimizer 2315, which then defines a particular geometric path based on one or more criteria, such as compressing the design to reduce the overall die size, or widening a path to reduce capacitive coupling between nearby wires. For example, in some embodiments, a topological path does not have any width or particular coordinates of its segments other than the coordinates of the two nodes (e.g., two pins) connected by the topological path.

[0162] Instead of snapping each topological path to a grid, the geometric router in some embodiments defines a width for each topological path and then leaves it to a subsequent compactor to fully geometrically draw the path (e.g., generate a complete geometric definition of the path). In some such embodiments, the geometric router defines, for each topological path, some intermediate coordinates of that path, such that the geometric path it generates for the topological path not only has some width, but also has one or more intermediate coordinates that define two or more path segments. Then, based on a set of one or more criteria, the post-routing optimizer 2315 defines a particular geometric path. In some embodiments, the post-routing optimizer 2315 comprises a compactor that uses a machine-trained network to improve the geometric path generated by the geometric router. The above-incorporated U.S. patent application Ser. No. 17 / 992,876 describes some examples of compactors that use machine-trained networks to improve paths in IC designs.

[0163] FIG. 24 illustrates an NPD router 2400 of some embodiments having a geometric router 2410 with a machine learning engine (e.g., a machine trained neural network) that identifies geometric paths for a set of nets for which the topology router 2405 of the NPD router 2400 identifies topological paths. The figure illustrates a topology router 2405 providing a set of topological paths 2402 that it identifies for a set of nets on an NPD wiring layer. Each topological path is defined by referencing edges 2404 of rectangular grid cells 2406 that tessellate a partition of the NPD wiring layer. In this example, four grid cells 2406 are shown that contain four topological paths 2402, two of which bypass an obstacle 2408 in one of the cells. If more than one topological path intersects an edge, the intersection of each topological path of that edge is defined in terms of where any other topological paths intersect that same edge, e.g., an edge intersection of one path is identified as being between one vertex of the edge and an edge intersection of another path.

[0164] FIG. 24 also shows that the geometric router 2410 generates four geometric paths 2412 for the four topological paths 2402. In some embodiments, each geometric path is defined by specific geometric coordinates associated with the pixels that define each geometric path. In some embodiments, the geometric router 2410 uses a machine-trained neural network that takes topological paths (e.g., the edge intersections of each topological path) as input and generates a geometric path that corresponds to the input topological path as output. Also, in some embodiments, the geometric paths generated by the geometric router are paths that mimic the expected manufactured shape of the paths.

[0165] In some embodiments, the neurons of the neural network are trained by using a number of previously computed training sets, each set including a pair of input topological paths and their corresponding output geometric paths computed by a geometric router using one of the known EDA techniques to geometrically map the topological paths (e.g., by snapping the topological paths to a grid). The output geometric paths in some embodiments are the manufactured shape of the geometric paths, which in some embodiments are generated by inspecting the actual interconnect shapes after manufacturing, while in other embodiments are generated by passing the geometric paths of each training set through a machine-trained network that generates the expected manufactured shape of the geometric paths. Some of the training sets also include obstacles defined in the areas traversed by the topological paths and the geometric paths.

[0166] During training, the topology path of each training pair is fed through the neural network to generate an output geometric path, which is then compared to the geometric path of the training pair to generate difference values. The difference values ​​of several training pairs are then used to calculate a loss function value, which is then back-propagated through the neural network to reconstruct the trainable parameters of the neural network.

[0167] In some embodiments, multiple instances of an NPD router simultaneously define paths for multiple partitions of an NPD wiring layer of an IC design. For example, in some of these embodiments, each topology router instance (that defines a topological path for a partition) of an NPD router tessellates its partition into a number (e.g., 16, 32, 50, 100, 128, 256) of rectangular cells and then defines its topological path by referencing the edges of these cells that are crossed by the topological path. To geometrically draw each of the topological paths identified by its topology router instance, the geometric router instance in some of these embodiments iteratively (1) selects a different set of adjacent rectangular cells and (2) uses its machine-trained neural network to geometrically draw the portion of the topological path that passes through the selected set of adjacent rectangular cells.

[0168] For example, Figure 25 illustrates an example where the topology router 2405 tessellates a partition into 64 rectangular cells 2502, which the topology router 2405 then uses to define a topological path. The figure also illustrates that the geometric router 2410 in some embodiments uses its machine-trained neural network four times to geometrically draw a topological path that first passes through the top left 16 cells 2512, the top right 16 cells 2514, the bottom left 16 cells 2516, and the bottom right 16 cells 2518. In some embodiments, the topology router 2405 tessellates the partition it is routing into more than 64 cells.

[0169] Some embodiments run multiple instances of the NPD router simultaneously on multiple processing cores of a computer to define routes for multiple partitions of an NPD wiring layer or a set of two or more NPD wiring layers of an IC design. This approach allows data calculated by each NPD router instance for each partition to be shared with other NPD router instances that require access to this data as they perform multiple iterations of their routing operations that depend on data calculated by other NPD router instances. The NPD router instances can share data via messaging or through a common memory that they share.

[0170] For example, when first and second NPD router instances respectively calculate first and second path segments of a topological path of at least one net traversing first and second cells, for the Nth iteration of its routing operation, the first NPD router instance defining the topological path of the first cell needs to know about the topological path calculated by the second NPD router instance defining the topological path of a second cell adjacent to the first cell.

[0171] In such a case, the first NPD router instance needs to know where the second topological path segment (computed for a particular net by the second NPD router instance) crosses the shared edge between the first cell and the second cell. With this knowledge, the first NPD router instance can ensure that it does not define a conflicting edge crossing location for the first topological path segment it computes across the same edge for a particular net. Note that short nets typically enter one or two adjacent partitions, resulting in their paths traversing only one to three partitions; the three partition case typically includes nets that have pins in two diagonally adjacent partitions, for which a path needs to traverse another horizontally / vertically adjacent partition to reach the adjacent diagonal partition.

[0172] In some embodiments, the size of the partitions used to divide an NPD wiring layer or set of two or more NPD wiring layers being routed simultaneously by an NPD router is related to the amount of computational and memory resources of the computer used to perform the concurrent NPD routing of some or all of the partitions. Figures 26 and 27 show two alternative processes 2600 and 2700 for defining partition sizes related to the amount of computational and memory resources of the computer. In these examples, multiple NPD routers simultaneously define NPD paths (e.g., topological NPD paths) for some or all of the partitions used to divide an NPD wiring layer or set of two or more NPD wiring layers being routed.

[0173] Process 2600 of Figure 26 first selects (at 2605) a desired partition size for dividing a routing region (e.g., an NPD wiring layer of an IC design) into multiple partitions that are routed simultaneously on multiple processing cores of a computer. Process 2600 then selects a computer with a sufficient amount of computational and memory resources (e.g., number of cores and amount of cache or RAM memory) to simultaneously handle the NPD routing (e.g., topology routing) of all partitions on multiple NPD router instances that run simultaneously and share their data in a common memory.

[0174] In some embodiments, the NPD router instances do not share memory, but communicate data regarding their respective routing of adjacent partitions via messaging or some other mechanism, and in some embodiments, each NPD router instance is allocated sufficient memory to allow the data that the router instance computes in each iteration of its routing for a partition to remain in memory (as opposed to first moving the data to disk and then back into memory) for the router instance to use in its next iteration of its routing operation.

[0175] Meanwhile, process 270 of Figure 27 first selects (at 2705) a computer running multiple NPD router instances running simultaneously to route some or all of the partitions of the routing region. This computer has a certain amount of computational and memory resources (e.g., a certain number of cores and a certain amount of cache or RAM memory), based on which process 2700 then specifies a desired partition size to divide the routing region into several partitions that are routed simultaneously on the computer's multiple processing cores.

[0176] Many of the above features and applications are implemented as a software process specified as a set of instructions recorded on a computer-readable storage medium (also referred to as a computer-readable medium). When these instructions are executed by one or more processing units (e.g., one or more processors, processor cores, or other processing units), these instructions cause the one or more processing units to perform the actions indicated in the instructions. Examples of computer-readable media include, but are not limited to, CD-ROMs, flash drives, RAM chips, hard drives, EPROMs, etc. Computer-readable media does not include carrier waves and electronic signals that pass wirelessly or over wired connections.

[0177] As used herein, the term "software" is meant to include applications stored on magnetic storage devices or firmware resident in read-only memory that can be loaded into memory for processing by a processor. Also, in some embodiments, multiple software inventions can be implemented as subparts of a larger program while remaining separate software inventions. In some embodiments, multiple software inventions can also be implemented as separate programs. Finally, any combination of separate programs that together implement a software invention described herein is within the scope of the invention. In some embodiments, the software program, when installed to operate on one or more electronic systems, defines one or more specific machine implementations that execute and perform the operations of the software program.

[0178] 28 conceptually illustrates an electronic system 2800 in which some embodiments of the present invention are implemented. The electronic system 2800 may be a computer (e.g., a desktop computer, a personal computer, a tablet computer, a server computer, a mainframe, a blade computer, etc.), or any other type of electronic device. As shown, the electronic system includes various types of computer-readable media and interfaces for various other types of computer-readable media. In particular, the electronic system 2800 includes a bus 2805, one or more processing units 2810, a system memory 2825, a read-only memory 2830, a permanent storage device 2835, input devices 2840, and output devices 2845.

[0179] The bus 2805 collectively represents all system, peripheral, and chipset buses that communicatively connect the numerous internal devices of the electronic system 2800. For example, the bus 2805 communicatively connects one or more processing units 2810 to a read-only memory (ROM) 2830, a system memory 2825, and a permanent storage device 2835. From these various memory units, the one or more processing units 2810 retrieve instructions to execute and data to process in order to perform the processes of the present invention. The one or more processing units may be single processors or multi-core processors in different embodiments.

[0180] The ROM 2830 stores static data and instructions required by the one or more processing units 2810 and other modules of the electronic system. The permanent storage device 2835, on the other hand, is a read-write memory device. This device is a non-volatile memory unit that stores instructions and data even when the electronic system 2800 is off. Some embodiments of the invention use mass storage devices (such as magnetic or optical disks and their corresponding disk drives) as the permanent storage device 2835.

[0181] In other embodiments, a removable storage device (such as a floppy disk, flash drive, etc.) is used as the permanent storage device. Like the permanent storage device 2835, the system memory 2825 is a read-write memory device. However, unlike the storage device 2835, the system memory is a volatile read-write memory, such as a random access memory. The system memory stores some of the instructions and data that the processor needs at run time. In some embodiments, the processes of the present invention are stored in the system memory 2825, the permanent storage device 2835, and / or the read-only memory 2830. From these various memory units, the one or more processing units 2810 retrieve instructions to execute and data to process in order to execute the processes of some embodiments.

[0182] The bus 2805 also connects to input devices 2840 and output devices 2845. The input devices allow a user to communicate information and select commands to the electronic system. The input devices 2840 include alphanumeric keyboards and pointing devices (also called "cursor control devices"). The output devices 2845 display images produced by the electronic system. Output devices include printers and display devices such as cathode ray tubes (CRT) or liquid crystal displays (LCD). Some embodiments include devices such as touch screens that function as both input and output devices.

[0183] 28, the bus 2805 also couples the electronic system 2800 to a network 2865 via a network adapter (not shown). As such, the computer can be part of a network such as a network of computers (such as a local area network ("LAN"), a wide area network ("WAN"), or an intranet), or the Internet. Any or all of the components of the electronic system 2800 may be used in conjunction with the present invention.

[0184] Some embodiments include electronic components such as microprocessors, storage, and memory that store computer program instructions on machine-readable or computer-readable media (alternatively referred to as computer-readable storage media, machine-readable media, or machine-readable storage media). Some examples of such computer-readable media include RAM, ROM, read-only compact discs (CD-ROM), recordable compact discs (CD-R), rewritable compact discs (CD-RW), read-only digital versatile discs (e.g., DVD-ROM, dual-layer DVD-ROM), various recordable / rewritable DVDs (e.g., DVD-RAM, DVD-RW, DVD+RW, etc.), flash memory (e.g., SD cards, mini SD cards, micro SD cards, etc.), magnetic and / or solid-state hard drives, read-only and recordable Blu-Ray® discs, extra-high density optical discs, any other optical or magnetic media, and floppy disks. The computer-readable medium can store a computer program executable by at least one processing unit and including a set of instructions for performing various operations. Examples of computer programs or computer code include machine code, such as that produced by a compiler, and files containing high-level code that are executed by a computer, electronic component, or microprocessor using an interpreter.

[0185] While the above description primarily refers to microprocessors or multi-core processors executing software, some embodiments are performed by one or more integrated circuits, such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In some embodiments, such integrated circuits execute instructions stored on the circuit itself.

[0186] As used herein, the terms "computer," "server," "processor," and "memory" all refer to electronic or other technological devices. These terms exclude people or groups of people. For purposes of this specification, the terms display or display mean display on an electronic device. As used herein, the terms "computer-readable medium," "computer-readable medium," and "machine-readable medium" are entirely limited to tangible, physical objects that store information in a form that is readable by a computer. These terms exclude any wireless signals, wired download signals, and any other ephemeral or transitory signals.

[0187] Although the present invention has been described with reference to numerous specific details, those skilled in the art will recognize that the present invention may be embodied in other specific forms without departing from the spirit of the present invention. For example, some of the figures conceptually illustrate processes. Certain operations of these processes may not be performed in the exact order shown and described. Certain operations may not be performed in one continuous sequence of operations, and different specific operations may be performed in different embodiments. Furthermore, processes may be implemented using several sub-processes or as part of a larger macro process. Thus, those skilled in the art will recognize that the present invention should not be limited by the illustrative details set forth above, but should instead be defined by the appended claims.

Claims

1. 1. A method for designing an integrated circuit (IC), comprising: using a first router to define curvilinear paths on a first plurality of routing layers of the IC; using a second router to define preferred direction straight-line paths on a second plurality of routing layers; The method includes:

2. 2. The method of claim 1, wherein the second plurality of routing layers comprises at least a first routing layer and a second routing layer with first and second preferred routing directions, respectively.

3. using the first router includes using the first router to define a first plurality of curved paths, each traversing the first plurality of routing layers to connect at least two nodes of the IC; using the second router includes using the second router to define a second plurality of straight paths, each of which traverses the second plurality of routing layers to connect at least two nodes of the IC. The method of claim 1.

4. 4. The method of claim 3, wherein each curved path in the first plurality connects nodes that are within a threshold distance of each other, and each straight path in the second plurality connects nodes that are more than the threshold distance from each other.

5. 5. The method of claim 4, wherein the first router penalizes routes longer than the threshold distance to bias against defining routes longer than the threshold distance.

6. The method of claim 4 , wherein the first router employs a constraint that prevents the route defined by the first router from being longer than the threshold distance.

7. 4. The method of claim 3, wherein using the first router includes using the first router to define a third plurality of straight paths traversing the first plurality of routing layers to connect a third plurality of nodes of the IC.

8. 8. The method of claim 7, wherein each curved or straight path across the first plurality of routing layers connects nodes that are within a threshold distance of each other, and each straight path across the second plurality of routing layers connects nodes that are more than the threshold distance from each other.

9. The method of claim 8 , wherein the path generated by the second router is not a curvilinear path having at least one curved segment.

10. The method of claim 1 , wherein the first plurality of routing layers includes routing layer 3 and routing layer 4 , and the second plurality of routing layers includes routing layer 5 and routing layer 6 .

11. The method of claim 1 , wherein the second plurality of routing layers includes a routing layer 1 and a routing layer 2 .

12. The method of claim 1 , wherein the first plurality of routing layers includes a routing layer 1 and a routing layer 2 .

13. 13. The method of claim 12, wherein the first routing layer and the second routing layer each have a plurality of regions having preferred direction straight line paths for a given IP (intellectual property) circuit block, and using the first router includes using the first router to define a plurality of curved path segments on the first routing layer and the second routing layer between the regions having the preferred direction straight line paths for the IP circuit block.

14. a first plurality of routing layers having no preferred routing direction and having curved path segments; a second plurality of routing layers, each having at least one preferred routing direction and path segments that traverse primarily along the preferred routing direction of the layer; 1. An integrated circuit design comprising:

15. 15. The integrated circuit design of claim 14, wherein the first plurality of routing layers includes layers 3 and 4, and the second plurality of routing layers includes layers 5 and 6.

16. 20. The integrated circuit design of claim 15, wherein the second plurality of routing layers further comprises a layer 1 and a layer 2.

17. 15. The integrated circuit design of claim 14, wherein the first plurality of routing layers includes layers 1 through 4, and the second plurality of routing layers includes layers 5 and 6.

18. 15. The integrated circuit design of claim 14, wherein the second plurality of routing layers includes a routing layer 1 and a routing layer 2.

19. 20. The integrated circuit design of claim 18, wherein the routing layer 1 and the routing layer 2 each have a number of regions having preferred direction straight line paths for predefined intellectual property (IP) circuit blocks.

20. 20. The integrated circuit design of claim 19, wherein a plurality of curved path segments are defined on routing layer 1 and routing layer 2 between the regions having the preferred direction straight line paths for the IP circuit blocks.

21. 15. The integrated circuit design of claim 14, wherein each preferred routing direction is a horizontal direction or a vertical direction, and the preferred routing directions of different adjacent layers in the second plurality of layers alternate between a horizontal direction and a vertical direction.

22. 15. The integrated circuit design of claim 14, wherein each preferred routing direction is horizontal, vertical, or diagonal, and the preferred routing directions of different adjacent layers in the second plurality of layers alternate between horizontal, vertical, and diagonal.

23. 15. The integrated circuit design of claim 14, wherein routes on the first plurality of routing layers are defined using a non-preferred direction (NPD) first router that defines NPD routes in an IC design used to manufacture the IC, and routes on the second plurality of routing layers are defined by a preferred direction (PD) second router that defines PD routes in the IC.

24. 24. The integrated circuit design of claim 23, wherein the PD second router evaluates a penalty cost for segments of the path that traverse along one or more non-preferred directions of the second plurality of routing layers.

25. 25. The integrated circuit design of claim 24, wherein the PD second router does not evaluate penalty costs for segments of paths that traverse along one or more preferred directions of each routing layer in the second plurality of routing layers.

26. 24. The integrated circuit design of claim 23, wherein the NPD first router defines a plurality of curved edges on the first plurality of routing layers.

27. 27. The integrated circuit design of claim 26, wherein the PD second router does not define any curved edges on the second plurality of routing layers.

28. 15. The integrated circuit design of claim 14, wherein a router defines the routes on the first plurality of routing layers without identifying eight or fewer route directions as preferred route directions, and defines the routes on the second plurality of routing layers by identifying one or more route directions on each of the routing layers in the second plurality of routing layers as preferred directions for that layer.

29. 30. The integrated circuit design of claim 28, wherein the router defines the paths on the first plurality of routing layers without imposing any penalty costs on path segments along eight or more routing directions on each routing layer of the first plurality of routing layers, and defines the paths on the second plurality of routing layers by imposing a penalty cost on path segments along any direction on any layer in the second plurality of layers that is not one of the preferred routing directions of the layer.

30. 30. The integrated circuit design of claim 29, wherein the router defines the paths on the first plurality of routing layers without imposing any penalty costs on path segments along any routing direction on each routing layer of the first plurality of routing layers.

31. 30. The integrated circuit design of claim 29, wherein the router defines a plurality of paths each having at least one router-defined curve segment on the first plurality of routing layers, but does not define any paths with any router-defined curve segment on the second plurality of routing layers.

32. 15. The integrated circuit design of claim 14, wherein the first plurality of non-preferred direction routing layers includes shorter paths that serve as shorter connections for connecting different locations on a substrate of the IC, and the second plurality of preferred direction routing layers includes longer paths that serve as longer connections for connecting different locations on the IC substrate.

33. a first plurality of wiring layers having no preferred wiring direction and having curved wiring; a second plurality of wiring layers having at least a first preferred wiring direction and a second preferred wiring direction; 1. An integrated circuit comprising:

34. 34. The integrated circuit of claim 33, wherein the first plurality of wiring layers includes layers 3 and 4, and the second plurality of wiring layers includes layers 5 and 6.

35. 35. The integrated circuit of claim 34, wherein the second plurality of wiring layers further comprises a layer 1 and a layer 2.

36. 34. The integrated circuit of claim 33, wherein the first plurality of wiring layers includes layers 1 to 4, and the second plurality of wiring layers includes layers 5 and 6.

37. 34. The integrated circuit of claim 33, wherein the second plurality of wiring layers includes wiring layer 1 and wiring layer 2.

38. 38. The integrated circuit of claim 37, wherein said wiring layer 1 and said wiring layer 2 each have a plurality of regions having preferred direction straight wiring for a given IP (intellectual property) circuit block.

39. 40. The integrated circuit of claim 38 wherein a plurality of curvilinear wire segments are defined on wiring layer 1 and wiring layer 2 between the regions having PD wiring for the IP circuit blocks.

40. 34. The integrated circuit of claim 33, wherein each preferred wiring direction is a horizontal direction or a vertical direction, and the preferred wiring directions of different adjacent layers in the second plurality of layers alternate between horizontal and vertical directions.

41. 34. The integrated circuit of claim 33, wherein wiring on the first plurality of wiring layers is defined using a non-preferred direction (NPD) first router that defines NPD paths in an IC design used to manufacture the IC, and wiring on the second plurality of wiring layers is defined by a preferred direction (PD) second router that defines PD paths in the IC.

42. 42. The integrated circuit of claim 41, wherein the PD second router evaluates a penalty cost for segments of the path that traverse along one or more non-preferred directions of the second plurality of wiring layers.

43. 34. The integrated circuit of claim 33, wherein the first plurality of non-preferred direction wiring layers includes shorter wires that serve as shorter connections for connecting different locations on a substrate of the IC, and the second plurality of preferred direction wiring layers includes longer wires that serve as longer connections for connecting different locations on the IC substrate.

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