Integrated diamond substrates for thermal management

Abstract

An apparatus and method for thermal management is described herein. The apparatus includes an integrated circuit (IC) including at least one field effect transistor, each having a gate, a drain, and a source, and a diamond substrate bonded to the gate, drain, and source of each of the at least one FET, the diamond substrate including at least one tuning element. The method includes forming at least one FET on the IC, the at least one FET including a gate, a drain, and a source, and bonding a diamond substrate to the gate, drain, and source of each of the at least one FET, the diamond substrate including at least one tuning element.

Description

[Background technology]

[0001] In conventional devices and methods, diamond is grown on the backside of a semiconductor wafer after removing the host substrate to remove heat through the epitaxial (epi) layer. In such devices and methods, the semiconductor layer is exposed to high temperatures during diamond growth. Furthermore, removal of the semiconductor wafer from the handle wafer is difficult and may damage the epi layer. The high coefficient of thermal expansion (CTE) between diamond and the semiconductor wafer can cause excessive wafer bowing.

[0002] Another conventional device and method provides for bonding of epi material to a diamond substrate at the semiconductor wafer level after the original host substrate is removed. Semiconductor wafer level epi transfer requires an extremely smooth surface and a high degree of planarity for epi transfer. Summary of the Invention

[0003] In accordance with the concepts described herein, exemplary thermal management devices and methods are provided.

[0004] In accordance with the concepts described herein, the present disclosure provides exemplary devices and methods that integrate diamond substrates with mature, high-yield semiconductor epitaxial and manufacturing techniques with proven reliability, enabling lower channel temperatures at higher power dissipation levels.

[0005] In accordance with concepts described herein, exemplary thermal management devices and methods are provided for cooling monolithic microwave integrated circuits (MMICs).

[0006] In accordance with the concepts described herein, exemplary thermal management devices and methods are provided that utilize a unique method of integrating diamond into the active area to efficiently remove heat generated during operation of the MMIC.

[0007] In accordance with concepts described herein, exemplary thermal management devices and methods are provided that address the issue of thermal limitations in high power amplifiers.

[0008] In accordance with the concepts described herein, exemplary thermal management devices and methods are provided that address the integration and performance challenges of combining high power semiconductors with diamond substrates for efficient cooling of transistor channels under long pulse, high duty cycle operation.

[0009] In accordance with the concepts described herein, an exemplary thermal management device and method is provided for fabricating passive components that make up an MMIC utilizing diamond substrates using standard clean room manufacturing processes.

[0010] In accordance with concepts described herein, an exemplary thermal management device and method is provided for fabricating transistors using separate semiconductor wafers (eg, gallium nitride (GaN)-on-silicon carbide (SiC)).

[0011] In accordance with concepts described herein, exemplary thermal management devices and methods are provided that use thermocompression bonding (e.g., gold on gold (Au)) to integrate well-functioning transistors into diamond MMIC circuits.

[0012] An exemplary device for thermal management in accordance with the concepts described herein includes an integrated circuit (IC) including at least one field effect transistor, each having a gate, a drain, and a source, and a diamond substrate bonded to the gate, drain, and source of each of the at least one FET, the diamond substrate including at least one tuning element.

[0013] The IC may include a semiconductor substrate including one of gallium nitride (GaN), silicon carbide (SiC), and gallium arsenide (GaAs).

[0014] The integrated circuit includes a monolithic microwave integrated circuit (MMIC).

[0015] The IC further includes at least one tuning element.

[0016] The at least one tuning element on the IC includes at least one of at least one capacitor, at least one resistor, and at least one inductor.

[0017] The diamond substrate includes a single crystal diamond substrate and / or a polycrystalline diamond substrate.

[0018] The diamond substrate further includes metal contacts configured to bond the diamond substrate to the gate, drain, and source of each of the at least one FET.

[0019] The metal contacts include gold (AU) contacts.

[0020] The semiconductor substrate and the diamond substrate may each be 100 μm thick.

[0021] The AU contacts may be approximately 6 μm thick (eg, 6 μm thick in a three-layer interconnect architecture), although the AU contacts may be thinner than 6 μm.

[0022] A method of thermal management includes forming at least one field effect transistor (FET) on an integrated circuit (IC), each having a gate, a drain, and a source, and bonding a diamond substrate to the gate, drain, and source of each of the at least one FET, the diamond substrate including at least one tuning element. [Brief description of the drawings]

[0023] The methods and processes for making and using the disclosed embodiments may be understood by reference to the accompanying drawing figures. It is understood that the components and structures shown in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the concepts described herein. Like reference numerals designate corresponding parts throughout the different views. Moreover, embodiments are illustrated in the drawings by way of example, and not by way of limitation.

[0024] [Figure 1] FIG. 1 is a diagram of an exemplary embodiment of the concepts described herein. [Diagram 2] FIG. 1 is a diagram of an exemplary alternative embodiment of the concepts described herein. [Diagram 3] 1 is a diagram of an exemplary embodiment of a diamond substrate in accordance with concepts described herein; [Figure 4] 4 is a diagram of an exemplary embodiment of the diamond substrate of FIG. 3 and two MMIC ICs according to concepts described herein. [Diagram 5] 5 is a diagram of an exemplary embodiment of the diamond substrate and MMIC IC of FIG. 4, with the MMIC IC attached to the diamond substrate in accordance with concepts described herein. [Figure 6] 1 is a diagram of an exemplary embodiment of a diamond substrate in accordance with concepts described herein; [Figure 7] 7 is a diagram of an exemplary embodiment of the diamond substrate and MMIC IC of FIG. 6 according to concepts described herein. [Figure 8] 8 is a diagram of an exemplary embodiment of the diamond substrate and MMIC IC of FIG. 7, where the MMIC IC is attached to the diamond substrate in accordance with concepts described herein. [Figure 9] 1 is a flow chart of an exemplary method for manufacturing a semiconductor device in accordance with concepts described herein. [Figure 10] 4 is a flow chart of an exemplary alternative method for manufacturing a semiconductor device according to concepts described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] The present disclosure provides exemplary devices and methods that allow for more efficient cooling of high power MMICs compared to conventional diamond heat spreader backside methods because the diamond substrate in the exemplary embodiments of the present disclosure is within a few microns of the heat source in the channels, allowing heat to reach the diamond substrate through the high thermal conductivity Au.

[0026] The present disclosure provides exemplary devices and methods that are suitable for high volume, low cost manufacturing environments because they utilize proven thermo-compression bonding technology.

[0027] The present disclosure provides exemplary devices and methods that avoid the integration challenges faced by conventional devices and methods for fabricating GaN on diamond wafers / MMICs.

[0028] The present disclosure provides exemplary devices and methods that provide approximately 1.44 times higher power dissipation than conventional GaN-on-SiC field effect transistors (FETs) at the same channel temperature.

[0029] The present disclosure provides exemplary devices and methods that allow for a significant reduction in the process flow of a semiconductor wafer and reduce the overall risk to the semiconductor wafer in process (WIP). The layers fabricated on the semiconductor wafer are the critical layers and can have the greatest impact on the radio frequency (RF) performance of the MMIC. The reduced process flow allows for rapid electrical feedback on the process health, reducing in-line WIP risk exposure and reducing process yield risk.

[0030] The present disclosure provides exemplary devices and methods that apply to microwave GaN processes, high voltage GaN (HV GaN) processes, and scandium aluminum nitride (ScAlN) processes. All HV GaN and ScAlN processes require the advanced thermal management devices and methods of the present disclosure.

[0031] This disclosure provides example devices and methods applicable to GaN / diamond related technologies and 5G related technologies.

[0032] The present disclosure provides exemplary devices and methods for integrating semiconductor structures on diamond wafers to efficiently remove heat from active areas of transistors to reduce operating temperatures, extend device lifetimes, and / or increase dissipated power.

[0033] FIG. 1 is a diagram of an exemplary embodiment of the concepts described herein. In an exemplary embodiment, a semiconductor device 100 includes an integrated circuit 101 attached to a diamond substrate 103. In an exemplary embodiment, the integrated circuit 101 may include an MMIC including a semiconductor substrate 105 and at least one FET 107 formed on the semiconductor substrate 105. In another exemplary embodiment, the semiconductor substrate 105 may include at least one tuning element. The semiconductor substrate 105 may include SiC, GaN, GaAs, or any other suitable semiconductor material. The semiconductor substrate 105 and the diamond substrate 103 may each be about 100 μm thick, and the diamond substrate 103 may be single crystal diamond or polycrystalline diamond. However, the present disclosure is not limited thereto.

[0034] Each FET 107 includes a drain terminal, a gate terminal, and a source terminal, with ohmic contacts provided to each of the drain terminal, gate terminal, and source terminal. The tuning elements may include capacitors, resistors, inductors, and / or any other suitable electronic components. At least one metal layer 109 is formed on the ohmic contacts of the drain terminal, gate terminal, and source terminal of each FET 107, allowing connection of the drain terminal, gate terminal, and source terminal of each FET 107 to the diamond substrate 103.

[0035] The diamond substrate 103 includes metal contacts 111 for the drain, gate, and source terminals of each FET 107 on the integrated circuit 101. In one embodiment, the metal contacts 111 may be gold (Au), and each Au contact is 6 μm thick. However, the disclosure is not so limited. In another embodiment, the diamond substrate 103 may include at least one tuning element 113, 115, and 117. The tuning elements may include capacitors, resistors, inductors, and / or any other suitable electronic components. The Au contacts of the diamond substrate 103 are bonded to the drain, gate, and source terminals of each FET 107 on the integrated circuit 101, respectively.

[0036] 2 is a diagram of an alternative embodiment of the concepts described herein. In one exemplary embodiment, a semiconductor device 200 includes an integrated circuit 201 attached to a first side of a diamond substrate 203, the second side of which is attached to a heat sink 213.

[0037] The integrated circuit 201 may include an MMIC including a semiconductor substrate 205 and at least one FET 207 formed on the semiconductor substrate 205. In another embodiment, the semiconductor substrate 205 may include at least one tuning element. The semiconductor substrate 205 may include SiC, GaN, GaAs, or any other suitable semiconductor material. The semiconductor substrate 205 and the diamond substrate 203 may each be about 100 μm thick, and the diamond substrate 203 may be single crystal diamond or polycrystalline diamond. However, the disclosure is not limited in this respect.

[0038] Each FET 207 includes a drain terminal, a gate terminal, and a source terminal, with ohmic contacts provided to each of the drain terminal, gate terminal, and source terminal. The tuning element may include a capacitor, a resistor, an inductor, or any other suitable electronic component. At least one metal layer 209 is formed on the ohmic contacts of the drain terminal, gate terminal, and source terminal of each FET 107, allowing connection of the drain terminal, gate terminal, and source terminal of each FET 207 to the first side of the diamond substrate 203. Each metal layer 209 may be 1.5 μm thick. However, the present disclosure is not limited thereto.

[0039] The first side of the diamond substrate 203 includes metal contacts 211 for the drain, gate, and source terminals of each FET 207 on the integrated circuit 201. In one embodiment, the metal contacts 211 may be gold (Au), and each Au contact is 6 μm thick. However, the disclosure is not so limited. In another embodiment, the first side of the diamond substrate 203 may include at least one tuning element. The tuning element may include a capacitor, resistor, inductor, or any other suitable electronic component. The Au contacts on the first side of the diamond substrate 203 are bonded to the drain, gate, and source terminals of each FET 207 on the integrated circuit 201, respectively.

[0040] The heat sink 213 is connected to the second side of the diamond substrate 203 via at least one metal contact 215. The metal contact 215 may be 6 μm thick Au, although the disclosure is not limited in this respect.

[0041] 3 is a diagram of an exemplary embodiment of a diamond substrate 300 according to the concepts described herein. In an exemplary embodiment, the diamond substrate 300 includes a diamond semiconductor wafer 301, a backside metallization 303, an RF input pad 305, a direct current (DC) bias pad 307, an input matching network 309 (e.g., resistors, capacitors, inductors, and transmission lines), a pad 311 for connecting from an IC to a transistor terminal, an inter-stage matching network 313 (e.g., resistors, capacitors, inductors, and transmission lines), an output matching network 315 (e.g., resistors, capacitors, inductors, and transmission lines), and an RF output pad 317.

[0042] The diamond substrate 300 is suitable for low frequency MMICs with large gate perimeters. MMIC passive components (e.g. bond pads, transmission lines, resistors, inductors, capacitors, individual source vias) are fabricated on the high thermal conductivity diamond substrate 300. Conventional devices only use thin film devices, not MMICs. MMICs can contain multiple transistors. Conventional devices only use single transistors in hybrid type circuits.

[0043] The design parameters of the passive components are electrically matched with the diamond substrate 300. The backside of the diamond substrate 300 is metallized as it is the ground plane for grounding the transmission lines and individual source vias (ISVs).

[0044] 4 is a diagram of an exemplary embodiment of the diamond substrate 300 of FIG. 3 and two MMIC ICs 401 and 403 according to the concepts described herein. In an exemplary embodiment, the diamond substrate 300 is as described above. The first MMIC IC 401 includes a GaN transistor 405 with multiple transistor terminals (e.g., multiple fingers) on a SiC substrate. The second MMIC 403 includes a GaN transistor 407 with multiple transistor terminals (e.g., more fingers than the first MMIC 405) on a SiC substrate.

[0045] The GaN on SiC IC (or chip) includes a multi-finger FET for signal amplification and is aligned to a diamond substrate 300 .

[0046] 5 is a diagram of an exemplary embodiment of the diamond substrate 300 and MMIC ICs 401 and 403 of FIG. 4 according to concepts described herein, where the MMIC ICs 401 and 403 are attached to the diamond substrate 300. The GaN on SiC chips 401 and 403 with FETs are bonded to the diamond substrate 300 to form a high complexity MMIC. This completed circuit offers the thermal advantages of diamond along with a mature and reliable GaN on SiC FET process.

[0047] 6 is a diagram of an exemplary embodiment of a diamond substrate 600 according to the concepts described herein. In one exemplary embodiment, the diamond substrate 600 includes a diamond semiconductor wafer 601, a backside metallization 603, an RF input pad 605, a DC bias pad 607, an input matching network 609 (e.g., resistors, capacitors, inductors, and transmission lines), a pad 311 for connecting from an IC to a transistor terminal, an output matching network 613 (e.g., resistors, capacitors, inductors, and transmission lines), and an RF output pad 615.

[0048] The diamond substrate 600 is ideal for high frequency MMICs with small gate perimeters. All MMIC passive components (e.g., bond pads, transmission lines, resistors, inductors, capacitors, and individual source vias) are fabricated on the high thermal conductivity diamond substrate 600. Conventional devices only use thin film devices, not MMICs. MMICs can contain multiple transistors. Conventional devices only use a single transistor in a hybrid type circuit.

[0049] The design parameters of the passive components are electrically matched with the diamond substrate 600. The backside of the diamond substrate 600 is metallized as it is the ground plane for grounding the transmission lines and internal backside vias (ISVs).

[0050] 7 is a diagram of an exemplary embodiment of the diamond substrate 600 of FIG. 6 and a MMIC IC 701 according to the concepts described herein. In an exemplary embodiment, the diamond substrate 600 is as described above. The MMIC IC 701 includes a first GaN transistor 703 with multiple transistor terminals (e.g., multiple fingers) on a SiC substrate, an interstage matching network 705 (e.g., resistors, capacitors, inductors, and transmission lines), and a second GaN transistor 707 with multiple transistor terminals (e.g., more fingers than on the first GaN transistor 703) on a SiC substrate.

[0051] GaN transistors 703 and 707 and the interstage matching network (designed for GaN on SiC) are fabricated on a single GaN on SiC chip 701. Implementing this for higher frequency MMICs would result in larger chips and easier bonding to the diamond substrate 600.

[0052] Figure 8 is a diagram of an exemplary embodiment of the diamond substrate 600 and MMIC IC 701 of Figure 7 according to concepts described herein, where the MMIC IC 701 is attached to the diamond substrate 600. A GaN on SiC chip 701 with FETs and an interstage matching network is bonded to the diamond substrate 600 to form a high complexity MMIC. This completed circuit offers the thermal advantages of diamond along with a mature and reliable GaN on SiC FET process.

[0053] 9 is a flow chart of a method 900 of manufacturing a semiconductor device in accordance with concepts described herein. In an exemplary embodiment, the method 900 of manufacturing a semiconductor device includes forming an isolation region on a semiconductor substrate at step 901. A step 903 of the method 900 includes forming an ohmic contact on the semiconductor substrate.

[0054] Step 905 of method 900 includes forming a nitride layer on the semiconductor substrate. Step 907 of method 900 includes forming a gate stem and a gate top on the semiconductor substrate. Step 909 of method 900 includes passivating the gate. Step 911 of method 900 includes a nitride etch. Step 913 of method 900 includes forming a source connected field plate (SCFP). Step 915 of method 900 includes performing a mesa etch on the first side of the diamond substrate.

[0055] A step 917 of the method 900 includes forming a first metal layer on the first side of the diamond substrate. A step 919 of the method 900 includes forming a capacitor nitride layer on the first side of the diamond substrate. A step 921 of the method 900 includes forming a tantalum nitride (TaN) layer on the first side of the diamond substrate. A step 923 of the method 900 includes performing a nitride etch on the first side of the diamond substrate.

[0056] A step 925 of the method 900 includes forming a second metal layer on the first side of the diamond substrate. A step 927 of the method 900 includes forming a third metal layer on the first side of the diamond substrate. A step 929 of the method 900 includes attaching the first side of the diamond substrate onto a handle wafer. A step 931 of the method 900 includes forming ISVs on the second side of the diamond substrate.

[0057] A step 933 of the method 900 includes removing the diamond substrate from the handle wafer. A step 935 of the method 900 includes bonding the diamond substrate to the FET formed on the semiconductor substrate. A step 937 of the method 900 includes forming a passivation layer on the result of step 935 by atomic layer deposition (ALD) passivation.

[0058] FIG. 10 is a flow chart of an alternative method 1000 of fabricating a semiconductor device according to the concepts described herein. In an exemplary embodiment, the method 1000 of fabricating a semiconductor device includes forming at least one FET on an integrated circuit (IC) at step 1001, each FET including a drain terminal, a gate terminal, and a source terminal. In an exemplary embodiment, the integrated circuit may include an MMIC including a semiconductor substrate and at least one FET formed on the semiconductor substrate. In an exemplary embodiment, the semiconductor substrate may be SiC, GaN, GaAs, or any other suitable semiconductor material. In an exemplary embodiment, the semiconductor substrate may be 100 μm thick. However, the disclosure is not limited thereto.

[0059] Step 1003 of method 1000 includes forming ohmic contacts on the drain, gate, and source terminals of each FET on the integrated circuit. Step 1005 of method 1000 includes forming at least one tuning element on the integrated circuit. In an example embodiment, the at least one tuning element may be a capacitor, a resistor, an inductor, or any other suitable electronic component. Step 1007 of method 1000 includes forming at least one metal layer on the ohmic contacts on the drain, gate, and source terminals of each FET.

[0060] Step 1009 of method 1000 includes forming at least one tuning element on the diamond substrate. In an exemplary embodiment, the tuning element may be a capacitor, a resistor, an inductor, or any other suitable electronic component. In an exemplary embodiment, the diamond substrate may be 100 μm thick, and the diamond substrate may be single crystal diamond or polycrystalline diamond. However, the disclosure is not limited in this respect.

[0061] Step 1011 of method 1000 includes forming metal contacts on the diamond substrate corresponding to metal layers connected to the drain, gate, and source terminals of each FET on the integrated circuit. In an exemplary embodiment, the metal contacts may be Au, and each Au contact is 6 μm thick. However, the disclosure is not limited in this respect. Step 1013 of method 1000 includes bonding the metal contacts of the diamond substrate to metal layers corresponding to the drain, gate, and source terminals of each FET on the integrated circuit.

[0062] Although exemplary embodiments of the present disclosure have been described, it will be apparent to one of ordinary skill in the art that other embodiments incorporating these concepts may be used. The embodiments contained herein should not be limited to the disclosed embodiments, but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.

[0063] Elements of different embodiments described herein can be combined to form other embodiments not specifically described above. Various elements described in the context of a single embodiment may be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.

[0064] Various embodiments of the concepts, systems, devices, structures, and techniques for which protection is sought are described herein with reference to the associated drawings. As noted above, in an embodiment, the concepts and features described herein may be embodied in a digital multi-beam beamforming system. Alternative embodiments may be contemplated without departing from the scope of the concepts, systems, devices, structures, and techniques described herein.

[0065] It should be noted that in the above description and drawings, various connections and positional relationships between elements are described (e.g., above, below, next to, etc.). These connections and / or positional relationships may be direct or indirect unless otherwise specified, and the described concepts, systems, devices, structures, and techniques are not intended to be limiting in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships.

[0066] As an example of an indirect positional relationship, reference in this description to forming layer "A" above layer "B" includes the situation where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B" so long as the relevant properties and functions of layer "A" and layer "B" are not substantially altered by the intermediate layer(s). The following definitions and abbreviations shall be used in interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing," or any other variation thereof, are intended to be non-exclusive inclusive. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and may include other elements not expressly listed or other elements inherent to such composition, mixture, process, method, article, or device.

[0067] Moreover, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "one or more" and "one or more" are understood to include any integer number greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "multiple" is understood to include any integer number greater than or equal to two, e.g., 2, 3, 4, 5, etc. The term "connected" can include indirect and direct "connected."

[0068] References in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but that every embodiment may include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed to be within the knowledge of one of ordinary skill in the art to achieve such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0069] For purposes of this description, the terms "top", "bottom", "right", "left", "vertical", "horizontal", "top", "bottom" (to name a few) and their derivatives refer to the described structures and methods as oriented in the drawings. The terms "overlying", "on", "above", "located on" or "located on" mean that a first element, such as a first structure, is on a second element, such as a second structure, and that an intervening element, such as an interface structure, may be between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intervening element. Such terms may also be referred to as directional or positional terms.

[0070] The use of ordinal numbers such as "first," "second," "third," etc. in the claims to modify claim elements does not, in and of itself, imply any priority, precedence, or ordering of a claim element over other claim elements, or the chronological order in which method actions are performed, but is merely used as a label to distinguish one claim element with a particular name from another element with the same name (other than the use of the ordinal number) in order to distinguish between the claim elements.

[0071] The terms "approximately" and "about" may be used in some embodiments to mean within ±20% of a target value, in some embodiments within ±10% of a target value, in some embodiments within ±5% of a target value, and even in some embodiments within ±2% of a target value. The terms "approximately" and "about" may include the target value. The term "substantially equal" may be used to refer to values ​​that are in some embodiments within ±20% of each other, in some embodiments within ±10% of each other, in some embodiments within ±5% of each other, and even in some embodiments within ±2% of each other.

[0072] The term "substantially" may be used in some embodiments to refer to values ​​that are within ±20%, in some embodiments within ±10%, in some embodiments within ±5%, and even in some embodiments within ±2% of the comparison measurement. For example, a first direction that is "substantially" perpendicular to a second direction may refer to a first direction that is within ±20% of an angle of 90° with the second direction in some embodiments, within ±10% of an angle of 90° with the second direction in some embodiments, within ±5% of an angle of 90° with the second direction, and even in some embodiments within ±2% of an angle of 90° with the second direction.

[0073] It is to be understood that the disclosed subject matter is not limited in its application to the details of construction and the arrangements of components set forth in the following description or illustrated in the drawings, as the disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways.

[0074] It should also be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting. Thus, those skilled in the art will appreciate that the conception underlying the present disclosure may readily be utilized as a basis for the designing of other structures, methods, and systems for carrying out some of the purposes of the disclosed subject matter. Accordingly, the claims should be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the disclosed subject matter.

[0075] While the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it will be understood that the disclosure is made by way of example only, and that numerous changes can be made in the details of the implementation of the disclosed subject matter without departing from the spirit and scope of the disclosed subject matter.

Claims

1. 1. A device for thermal management, comprising: an integrated circuit (IC) including at least one field effect transistor (FET), each of the at least one FET including a gate, a drain, and a source; a diamond substrate bonded to the gate, the drain, and the source of each of the at least one FET, the diamond substrate including at least one tuning element; The device that contains

2. The device of claim 1 , wherein the IC further comprises a semiconductor substrate comprising one of gallium nitride (GaN), silicon carbide (SiC), and / or gallium arsenide (GaAs).

3. The device of claim 1 , wherein the integrated circuit comprises a monolithic microwave integrated circuit (MMIC).

4. The device of claim 1 , wherein the IC further comprises at least one tuning element.

5. The device of claim 4 , wherein the at least one tuning element on the IC comprises at least one of at least one capacitor, at least one resistor, and / or at least one inductor.

6. The device of claim 1 , wherein the diamond substrate comprises one of a single crystal diamond substrate and / or a polycrystalline diamond substrate.

7. 10. The device of claim 1, wherein the diamond substrate further comprises metal contacts configured to bond the diamond substrate to the gate, the drain, and the source of each of the at least one FET.

8. The device of claim 7 , wherein the metal contact comprises a gold (AU) contact.

9. The device of claim 2 , wherein the semiconductor substrate and the diamond substrate are each about 100 μm thick.

10. The device of claim 8 , wherein the AU contact is at least 6 μm thick.

11. 1. A method of thermal management comprising: forming at least one field effect transistor (FET) on an integrated circuit (IC), each of the at least one FET including a gate, a drain, and a source; bonding a diamond substrate to the gate, the drain, and the source of each of the at least one FET, the diamond substrate including at least one tuning element; The method includes:

12. 12. The method of claim 11, wherein the IC comprises a semiconductor substrate comprising one of gallium nitride (GaN), silicon carbide (SiC), and gallium arsenide (GaAs).

13. The method of claim 11 , wherein the integrated circuit comprises a monolithic microwave integrated circuit (MMIC).

14. The method of claim 11 , wherein the IC further comprises at least one tuning element.

15. The method of claim 14 , wherein the at least one tuning element on the IC comprises at least one of at least one capacitor, at least one resistor, and at least one inductor.

16. The method of claim 11 , wherein the diamond substrate comprises one of a single crystal diamond substrate and a polycrystalline diamond substrate.

17. 12. The method of claim 11, wherein the diamond substrate further comprises metal contacts configured to bond the diamond substrate to the gate, the drain, and the source of each of the at least one FET.

18. The method of claim 17 , wherein the metal contact comprises a gold (AU) contact.

19. The method of claim 12, wherein the semiconductor substrate and the diamond substrate are each 100 μm thick.

20. 20. The method of claim 18, wherein the AU contact is at least 6 μm thick.

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