Systems and methods for center frequency tuning - Patents.com

Abstract

Systems and methods for center frequency tuning are described. One of the methods includes receiving a voltage signal from an output of a matcher coupled to a low frequency (LF) radio frequency (RF) generator and a high frequency (HF) RF generator. The method further includes dividing the voltage signal into a plurality of bins for each cycle of a LFRF signal generated by the LFRF generator. The method also includes identifying a first bin from the plurality of bins in which a zero crossing occurs, accessing measurements of a parameter that occurred in a predetermined number of the plurality of bins, and calculating an operating frequency of the HFRF generator for the first bin based on the measurements of the parameter. The method includes controlling the HFRF generator to operate at the operating frequency during occurrence of the first bin.

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The embodiments described in this disclosure relate to systems and methods for center frequency tuning. [Background technology]

[0002] The discussion of the background art provided herein is intended to generally present the context of the present disclosure. The work of the presently named inventors, to the extent that their work is described in this background art section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted expressly or impliedly as prior art to the present disclosure.

[0003] One or more radio frequency (RF) generators are coupled to a plasma chamber. A semiconductor wafer is disposed within the plasma chamber. The one or more RF generators provide one or more RF signals to the plasma chamber to process the semiconductor wafer. It is desirable for the semiconductor wafer to be processed in a precise manner. Otherwise, efficiency in processing the semiconductor wafer is reduced.

[0004] It is in this context that the embodiments described in this disclosure are made. Summary of the Invention

[0005] The embodiments of the present disclosure provide a system and method for center frequency tuning. It should be appreciated that the embodiments can be implemented in numerous ways, for example, as a process, an apparatus, a system, a piece of hardware, or a method on a computer-readable medium. Some embodiments are described below.

[0006] In one embodiment, a method is described for reducing RF power reflected toward a high frequency (HF) radio frequency (RF) generator in a bin independent manner. The method includes receiving a voltage signal from an output of a match coupled to a low frequency (LF) RF generator and an HFRF generator. The method further includes dividing the voltage signal into a plurality of bins for each cycle of an LFRF signal generated by the LFRF generator. The method also includes identifying a first bin from the plurality of bins in which a zero crossing occurs, accessing measurements of a parameter that occurred in a predetermined number of bins of the plurality of bins, and calculating an operating frequency of the HFRF generator for the first bin based on the measurements of the parameter. The method includes controlling the HFRF generator to operate at the operating frequency during occurrence of the first bin.

[0007] In one embodiment, a controller for reducing RF power reflected towards an HFRF generator in a bin independent manner is described. The controller includes a processor. The processor receives a voltage signal from an output of an LFRF generator and a matcher coupled to the HFRF generator. The processor further divides the voltage signal into a plurality of bins for each cycle of an LFRF signal generated by the LFRF generator, identifies a first bin from the plurality of bins in which a zero crossing occurs, and accesses measurements of a parameter for a predetermined number of occurrences of the plurality of bins. The processor calculates an operating frequency of the HFRF generator for the first bin based on the measurements of the parameter, and controls the HFRF generator to operate at the operating frequency during occurrences of the first bin. The controller includes a memory device coupled to the processor.

[0008] In one embodiment, a plasma system is described. The plasma system includes an LFRF generator that generates an LFRF signal. The plasma system further includes an HFRF generator that generates an HFRF signal. The plasma system includes a matcher coupled to the LFRF generator and the HFRF generator. The matcher receives the LFRF signal and the HFRF signal to output a modified RF signal. The plasma system also includes a controller coupled to the LFRF generator, the HFRF generator, and the matcher. The controller receives a voltage signal from an output of the matcher, divides the voltage signal into a number of bins for each cycle of the LFRF signal, and identifies a first bin from the number of bins in which a zero crossing occurs. The controller further accesses measurements of a parameter for a predetermined number of occurrences of the number of bins, and calculates an operating frequency of the HFRF generator for the first bin based on the measurements of the parameter. The processor controls the HFRF generator to operate at the operating frequency during occurrences of the first bin.

[0009] Some advantages of the systems and methods described herein for center frequency tuning include taking into account a parameter for a predetermined number of bins or all bins during a cycle of operation of the LFRF generator. By taking into account a predetermined number of bins or all bins during a cycle of operation of the LFRF generator, the reflected HFRF power is reduced in a more accurate manner over the entire cycle of operation of the LFRF generator compared to when a parameter for a single bin is taken into account. A parameter is determined for a predetermined number of bins or all bins during a cycle of operation of the LFRF generator. From the values ​​of the parameter for the predetermined number of bins or all bins, a statistical value of the parameter is determined. Based on the statistical value, a reference high frequency value is determined for bin 0. Then, from the reference high frequency value, an HF offset value is determined for the remaining bins of the predetermined number of bins during a cycle of operation of the LFRF generator.

[0010] The reflected power is reduced in a bin-independent manner when a predetermined number of bins or all bins in a cycle of operation of the LFRF generator are considered. For example, in addition to considering the reflected HF power for bin 0, the reflected HF power is considered for additional bins in a cycle of operation of the LFRF generator. Thus, the reflected HF power is reduced independent of bin 0.

[0011] Further advantages of the systems and methods described herein for center frequency tuning include using statistics, such as the average value of reflected power for a predetermined number of bins or all bins during a cycle of operation of the LFRF signal, to determine the center frequency. Sometimes it is difficult to identify bin 0 and reduce the reflected power based only on bin 0. When bin 0 is incorrectly identified, it leads to mistuning. By using statistics, the possibility of mistuning resulting from bin misidentification is significantly reduced.

[0012] Certain other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0013] The embodiments are understood by reference to the following description in conjunction with the accompanying drawings. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram of an embodiment of a plasma system to illustrate the use of a low frequency (LF) radio frequency (RF) generator and a high frequency (HF) RF generator.

[0015] [Figure 2A] FIG. 2 is an embodiment of a graph for illustrating a clock signal.

[0016] [Figure 2B] FIG. 1 is an embodiment of a graph plotting a voltage signal, such as a transmit voltage signal, to illustrate binning.

[0017] [Figure 2C] FIG. 11 is an embodiment of a graph to illustrate a method for determining a reference high frequency numerical value for bin 0 based on multiple values ​​of a parameter for bins 1 to 10 during a cycle of a clock signal.

[0018] [Figure 3A] FIG. 2 is an embodiment of a graph for illustrating a clock signal.

[0019] [Figure 3B] FIG. 2 is an embodiment of a graph to illustrate an RF signal generated by an LFRF generator.

[0020] [Figure 3C] FIG. 13 is an embodiment of a graph to illustrate that the values ​​of parameters during the hold-off period and during the frequency tuning period are used to determine the reference high frequency value. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The following embodiments describe systems and methods for center frequency tuning. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order not to unnecessarily obscure the embodiments.

[0022] 1 is a diagram of one embodiment of a plasma system 100 to illustrate the use of a low frequency (LF) RF generator 102 and a high frequency (HF) RF generator 104. System 100 includes LFRF generator 102, HFRF generator 104, a host computer 106, a matcher 107, and a plasma chamber 108. Plasma system 100 further includes a voltage (V) sensor 110 and a power (P) sensor 112.

[0023] As an example, the LFRF generator 102 has an operating frequency of 400 kilohertz (kHz) or 2 megahertz (MHz). Also, as an example, the HFRF generator 104 has an operating frequency of 27 MHz or 60 MHz. Examples of the host computer 106 include a desktop, a laptop, a tablet, a controller, and a smartphone. An example of a controller described herein is a combination of a processor and a memory device. The processor of the controller is coupled to the memory device of the controller. An example of the matcher 107 is an impedance matching circuit or an impedance matcher or a matcher circuit or an impedance matching network. For illustrative purposes, the matcher 107 includes a first branch circuit and a second branch circuit. Each branch circuit includes one or more matcher network elements. Examples of the matcher network elements include a capacitor, an inductor, and a resistor. An example of the plasma chamber 108 is a capacitively coupled plasma (CCP) chamber.

[0024] The host computer 106 includes a processor 114 and a memory device 116. Examples of the processor 114 include a central processing unit (CPU), an application specific integrated circuit (ASIC), and a programmable logic device (PLD). Examples of the memory device 116 include read-only memory and random access memory.

[0025] The plasma chamber 108 includes a lower electrode LE and an upper electrode UE. A gap is formed between the lower electrode LE and the upper electrode UE, and a substrate S is disposed in the gap on an upper surface of the lower electrode LE for processing. An example of the substrate S includes a semiconductor wafer on which an integrated circuit is fabricated.

[0026] The processor 114 is coupled to the memory device 116. The processor 114 is coupled to the LFRF generator 102 via a transfer cable 118 and to the HFRF generator 104 via a transfer cable 120. An example of a transfer cable includes an electrical cable that transfers data in a parallel or serial manner or using a Universal Serial Bus (USB) protocol. The LFRF generator 102 has an output 122 that is coupled to an input 126 of the matcher 107 via an RF cable 124. Similarly, the HFRF generator 104 has an output 128 that is coupled to an input 132 of the matcher 107 via an RF cable 130. The matcher 107 has an output 134 that is coupled to the lower electrode LE via an RF transmission line 136. A first branch of the matching circuit 107 is coupled between the input 126 and the output 134, and a second branch of the matching circuit 107 is coupled between the input 132 and the output 134. The upper electrode UE is coupled to ground potential.

[0027] The V sensor 110 is coupled to the processor 114 via a transfer cable 138, and the P sensor 112 is coupled to the processor 114 via a transfer cable 140. The V sensor 110 is coupled to an output 134 of the matcher 134. The P sensor 112 is also coupled to an output 128 of the HFRF generator 104.

[0028] The processor 114 generates a recipe signal 142, which includes a low frequency and one or more power levels of an RF signal 150 to be generated by the LFRF generator 102. As an example, the low frequency is equal to the operating frequency of the LFRF generator 102. The processor 114 sends the recipe signal 142 to the LFRF generator 102 via a transmission cable 118. The processor 114 also generates a recipe signal 144, which includes a high frequency and one or more power levels of an RF signal 152 to be generated by the HFRF generator 104. As an example, the high frequency is equal to the operating frequency of the HFRF generator 104. The processor 114 sends the recipe signal 144 to the HFRF generator 104 via a transmission cable 120.

[0029] Upon receiving recipe signal 142, LFRF generator 102 generates an RF signal 150 having a low frequency and one or more power levels as indicated in recipe signal 142. LFRF generator 102 sends RF signal 150 to matcher 107 via output 122, RF cable 124, and input 126. Similarly, upon receiving recipe signal 144, HFRF generator 104 generates an RF signal 152 having a high frequency and one or more power levels as indicated in recipe signal 144. HFRF generator 104 sends RF signal 152 to matcher 107 via output 128, RF cable 130, and input 132.

[0030] Upon receiving RF signal 150, the first branch of matcher 107 matches the impedance of a load coupled to output 134 with the impedance of a source coupled to input 126 to modify the impedance of RF signal 150 to provide a first modified RF signal. An example of a load coupled to output 134 includes RF transmission line 136 and plasma chamber 108. An example of a source coupled to input 126 includes RF cable 124 and LFRF generator 102. Similarly, upon receiving RF signal 152, the second branch of matcher 107 matches the impedance of a load coupled to output 134 of matcher 107 with the impedance of a source coupled to input 132 of matcher 107 to modify the impedance of RF signal 152 to provide a second modified RF signal.

[0031] The matcher 107 combines, such as sums, the first modified RF signal and the second modified RF signal to output a modified RF signal 154 at the output 134. The modified RF signal 154 is sent from the output 134 to the lower electrode LE via an RF transmission line 136. When one or more process gases, such as a fluorine-containing gas, an oxygen-containing gas, or a nitrogen-containing gas, are supplied to the gap between the lower electrode LE and the upper electrode UE in addition to the modified RF signal 154, a plasma is struck or maintained in the gap. The plasma processes the substrate S. Examples of processing the substrate S include etching features in the substrate S, depositing material on the substrate S, and cleaning the substrate S.

[0032] While the substrate S is being processed, the V sensor 110 measures the voltage at the output 134 and outputs a voltage signal 156, which is sent to the processor 114 via the transfer cable 138. Similarly, while the substrate S is being processed, the P sensor 112 measures the power, such as high frequency delivered power or high frequency reflected power, at the output 134 and outputs a power signal 158, which is sent to the processor 114 via the transfer cable 140. As an example, power is reflected from the plasma chamber 108, the RF transmission line 136, the matching box 107, and the RF cable 130 towards the HFRF generator 104. The power reflected towards the HFRF generator 104 may be referred to herein as high frequency reflected power.

[0033] In one embodiment, the V sensor 110 is coupled at any point on the RF transmission line 136.

[0034] In one embodiment, the P sensor 112 is coupled at any point on the RF cable 130.

[0035] 2A is one embodiment of a graph 200 to illustrate a clock signal 202. As an example, the clock signal 202 is generated by the processor 114 (FIG. 1). The x-axis of the graph 200 plots time t, ranging from time t0 to time t40. The y-axis of the graph 200 plots the voltage of the clock signal 202. The clock signal 202 periodically transitions between a logic level 1 and a logic level 0. Logic level 1 corresponds to 5 volts and logic level 0 corresponds to 0 volts.

[0036] Clock signal 202 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t10. At time t10, clock signal 202 transitions from logic level 1 to logic level 0 and remains at logic level 0 from time t10 to time t20. The transition between logic level 1 and logic level 0 repeats from time t20 to time t40. Clock signal 202 has cycle n from time t0 to time t20, followed consecutively by cycle (n+1) from time t20 to time t40, where n is a positive integer.

[0037] 2B is an illustration of an embodiment of a graph 210 plotting a voltage signal 212, such as an outgoing voltage signal, to illustrate binning. As an example, the graph 210 is generated by the processor 114 (FIG. 1) upon receiving the voltage signal 212 from the V sensor 110 (FIG. 1).

[0038] The graph 210 plots the voltage signal 220 versus time t. For example, the y-axis of the graph 210 represents the voltage of the voltage signal 220, and the x-axis of the graph 210 represents time t. The y-axis plots a number of voltage values ​​from V0 to V6 starting in a positive y-direction. The y-axis also plots a number of voltage values ​​from V0 to -V6 starting in a negative y-direction. The voltage value V6 is greater than the voltage value V0, and the voltage value -V6 is less than the voltage value V0. For illustrative purposes, the voltage value V0 is 0. As another illustrative example, the voltage value V0 is negative. As an example, the x-axis of the graph 210 represents the time t at which the voltage value of the voltage signal 212 is received by the processor 114 from the V sensor 110.

[0039] The voltage signal 212 is an example of the voltage signal 156 (FIG. 1) generated by the V sensor 110 (FIG. 1). The voltage signal 212 represents the voltage of the first modified RF signal or primarily represents the voltage of the RF signal 150 generated by the LFRF generator 102. For example, the voltage signal 212 represents the voltage of the RF signal 150. As another example, the voltage signal 212 primarily represents the voltage of the RF signal 150 and also minimally represents the voltage of the RF signal 152. For illustration, the voltage of the voltage signal 212 is the voltage of the RF signal 150. As another example, 90% of the voltage of the voltage signal 212 is the voltage of the RF signal 150, and the remaining 10% of the voltage of the voltage signal 212 is the voltage of the RF signal 152. The voltage signal 212 spans multiple clock cycles of the clock signal 202 (FIG. 2A). For example, the voltage signal 212 spans from time t0 to time t20, with the time interval between time t0 and time t20 representing cycle n of the clock signal 202. The voltage signal 212 further spans from time t20 to time t40, with the time interval between time t20 and time t40 representing cycle (n+1) of the clock signal 202.

[0040] The processor 114 divides the voltage signal 212 into a number of bins, such as 10 or 20 bins, during each cycle of the clock signal 202. For example, during cycle n, the voltage signal 212 is divided into bins 1-10, during cycle (n+1), the voltage signal 212 is divided into bins 1-10, etc. To further illustrate, the processor 114 divides the voltage signal 212 during each cycle of the clock signal 202. The voltage signal 212 is divided into 10 equal time intervals during each cycle, with each time interval designated by the processor 114 as a bin.

[0041] Processor 114 extends each bin over the same time interval. For example, bin 1 spans from time t0 to time t2, bin 2 spans from time t2 to time t4, bin 3 spans from time t4 to time t6, bin 4 spans from time t6 to time t8, and bin 5 spans from time t8 to time t10. Bin 5 may be referred to herein as bin 0. Bin 6 also spans from time t10 to time t12, bin 7 spans from time t12 to time t14, bin 8 spans from time t14 to time t16, bin 9 spans from time t16 to time t18, and bin 10 spans from time t18 to time t20.

[0042] The processor 114 identifies bin 0 as the time interval that includes the point where the voltage signal 212 crosses the x-axis and determines that the point is a negative zero crossing 214. For example, the processor 114 determines that the point is a negative zero crossing 214 at which the voltage of the voltage signal 212 is zero and the slope of the voltage signal 212 is negative. As another example, at the negative zero crossing 214, the voltage of the voltage signal 212 is non-zero. The slope of the voltage signal 212 is negative during the time interval of bin 0. The processor 114 identifies, e.g., designates as being bin 0, one of bins 1-10 that includes the negative zero crossing 214.

[0043] Bins 1-4 and a first portion of bin 0 form a positive cycle of the voltage signal 212, and a second portion of bin 0 and bins 6-10 form a negative cycle of the voltage signal 212. The first portion of bin 0, which is part of the positive cycle of the voltage signal 212, spans the time interval from time t8 to time t9, when the negative crossing 214 occurs, and the second portion of bin 0, which is part of the negative cycle of the voltage signal 212, spans the time interval from time t9 to time t10.

[0044] 2C is an embodiment of a graph 220 to illustrate a method for determining a reference high frequency value HF0 for bin 0 based on multiple values ​​of a parameter for bins 1-10 in cycles (nm) of a clock signal 202, where m is an integer less than integer n. An example of a cycle (nm) is cycle (n-1) or cycle (n-2). Example parameters include voltage standing wave ratio (VSWR) and reflection coefficient (Γ).

[0045] Graph 220 plots HF offset values ​​versus time t of RF signal 152 (FIG. 1). As an example, the HF offset values ​​plotted on graph 220 are example operating frequencies of HFRF generator 104 (FIG. 1). The HF offset values ​​of RF signal 152 are plotted on the y-axis and time t is plotted on the x-axis, which is the same as the x-axis of graph 200 (FIG. 2A). As an example, the HF offset values ​​plotted on the y-axis of graph 220 range from HF(-4) to HF4. HF offset value HF4 is greater than HF offset value HF0, and HF offset value HF(-4) is less than reference high frequency value HF0.

[0046] The processor 114 determines, such as identifies or establishes, a reference high frequency value HF0 based on the values ​​of the parameters for all bins 1-10 in the cycle (nm). For example, the processor 114 controls the HFRF generator 104 to operate at the reference high frequency value HF0 during bin 0 of the cycle (nm). The processor 114 calculates a first set of 10 values ​​of the parameters for bins 1-10 in the cycle (nm) when the HFRF generator 104 operates based on the reference high frequency value HF0. As an example, the processor 114 controls the HFRF generator 104 to operate at an HF offset value HF(-4) during bin 1 of the cycle (nm). The HF offset value HF(-4) is a frequency offset from the reference high frequency value HF0. For example, the HF offset value HF(-4) is 4 MHz less than the reference high frequency value HF0.

[0047] The processor 114 accesses a correspondence, such as a one-to-one relationship, between the HF offset value HF(-4) and bin 1 from the memory device 116 (FIG. 1) to determine that the HF offset value HF(-4) should be applied during bin 1 of the cycle (nm). The HF offset value HF(-4) is an offset, such as a subtraction value, from the reference high frequency value HF0. Also, note that the HF offset value of the HFRF generator 104 is controlled to have a substantially inverse or inverse relationship with the voltage signal 212 during the cycle (nm). During the time period when the voltage signal 212 forms a positive cycle, the HF offset value of the HFRF generator 104 is controlled to be a negative offset from the reference high frequency value HF0, and during the time period when the voltage signal 212 forms a negative cycle, the HF offset value of the HFRF generator 104 is controlled to be a positive offset from the reference high frequency value HF0.

[0048] Continuing with the example, when the HFRF generator 104 operates at an HF offset value HF(−4) during bin 1, the processor 114 receives a voltage signal 212 during bin 1 from the V sensor 110 (FIG. 1) and detects a reflected voltage V r and forward voltage V f Calculate the first value of the parameter for bin 1 of cycles (nm) by determining the ratio of the reflected voltage V r and the forward voltage V in bin 1 f The ratio of reflected voltage V to the reflection coefficient in bin 1 is r is reflected from the plasma chamber 108 (FIG. 1) through the RF transmission line 136, the second branch of the matching box 107, and the RF cable 130 toward the HFRF generator 104. f is the voltage of the RF signal 152 supplied from the RF generator 104 to the lower electrode LE via the RF cable 130, the matching box 107, and the RF transmission line 136. The forward voltage V f is stored in memory device 116 for access by processor 144. The processor 114 determines the reflected voltage V ris expressed as the forward voltage V in bin 1 of the voltage signal 212 and the forward voltage V in bin 1. f and . The processor 114 determines the delivered voltage to be a statistical value, such as the average or median of the voltage values ​​of the voltage signal 212 received during bin 1. This statistical value is the first value of the parameter for bin 1. In a manner similar to the manner of determining the first value of the parameter for bin 1, the processor 114 determines the remaining nine parameter values ​​of the first set for bins 2-10 of the cycles (nm). During each of bins 2-10 of the cycles (nm), the processor 114 controls the HFRF generator 104 to operate at nine HF offset values, such as different HF offset values, each of the nine HF offset values ​​being associated with, e.g., having a one-to-one correspondence with, a corresponding bin of bins 2-10 of the cycles (nm). It is noted that during bin 0 of the cycles (nm), the HF offset value is 0. During bin 0, the processor 114 controls the HFRF generator 104 to operate at a reference high frequency value HF0.

[0049] Continuing with the illustration, the processor 114 accesses the correspondence from the memory device 116 to operate the HFRF generator 104 at nine HF offset values. When the HFRF generator 104 operates at nine HF offset values, the processor 114 receives values ​​of the voltage signal 212 from the V sensor 110 during bins 2-10 of cycles (nm) and calculates nine values ​​of the parameter similarly as a first value is calculated for bin 1. The nine values ​​of the parameter form part of a first set of parameter values. The processor 114 then calculates a statistical value, such as a mean or median, of the first set of values ​​of the parameter to output a first statistical parameter value.

[0050] Continuing with the example, processor 114 controls HFRF generator 104 to operate at reference high frequency value HF0' during bin 0 of cycle (n-m+p), where p is a positive integer and (n-m+p) is an integer greater than (nm) and less than n. Processor 114 calculates a second set of ten values ​​of parameters for bins 1 through 10 during cycle (n-m+p) when HFRF generator 104 operates at reference high frequency value HF0' just as processor 114 calculates the first set of ten values ​​of parameters. For purposes of illustration, processor 114 applies both positive and negative offsets from reference high frequency value HF0' but not from reference high frequency value HF0. To further illustrate, during bin 1 of cycle (n-m+p), the processor 114 controls the HFRF generator 104 to operate at a HF offset value HF(-3) from the reference high frequency value HF0', just as the processor 114 controls the HFRF generator 104 to operate at a HF offset value HF(-4) from the reference high frequency value HF0. The HFRF generator 104 operates at the HF offset value HF(-3) during bin 1 of cycle (n-m+p). When the HFRF generator 104 operates at the HF offset value HF(-3), the processor 114 receives the voltage signal 212 during bin 1 of cycle (n-m+p) and determines a value of the parameter for bin 1 of cycle (n-m+p) just as a first value of the parameter for bin 1 of cycle (nm) is calculated. Similarly, the processor 114 controls the HFRF generator 104 to operate at different HF offset values ​​during bins 2 to 10 of cycle (n-m+p) to determine the remaining values ​​of the second set of parameters.

[0051] Continuing with the example, the processor 114 then calculates a statistical value, such as the average or median, of the second set of parameter values ​​to output a second statistical parameter value. The processor 114 compares the first statistical parameter value to the second statistical parameter value to determine whether the first statistical parameter value is less than the second statistical parameter value. Upon determining that the first statistical parameter value is less than the second statistical parameter value, the processor 114 determines that the HFRF generator 104 should operate at the reference high frequency value HF0 and controls the HFRF generator 104 to operate at the reference high frequency value HF0 during one or more bin 0 of cycle n, (n+1), etc. On the other hand, upon determining that the second statistical parameter value is less than the first statistical parameter value, the processor 114 determines that the HFRF generator 104 should operate at the reference high frequency value HF0′ and controls the HFRF generator 104 to operate at the reference high frequency value HF0′ during one or more bin 0 of cycle n, (n+1), etc.

[0052] As another example, instead of using all of the bins, such as 10 bins or 20 bins, to determine the first statistical parameter value or the second statistical parameter value in the preceding examples, a predetermined number of bins, such as less than all of the bins of each cycle (nm) and (n-m+p) are used. For further illustration, the processor 114 accesses, such as reads, from the memory device 114 the voltages of the voltage signal 212 measured during bins 4-7 of cycles (n-m+p) and (nm) and determines the first statistical parameter value for bins 4-7 of cycle (nm) from the voltages measured during bins 4-7 of cycle (nm). In a further example, the processor 114 determines the second statistical parameter value for bins 4-7 of cycle (n-m+p) from the voltages measured during bins 4-7 of cycle (n-m+p). As another further example, the processor 114 determines a first statistical parameter value for bins 3 to 7 of cycles (nm) instead of bins 1 to 10, and determines a second statistical parameter value for bins 3 to 7 of cycles (n-m+p) instead of bins 1 to 10.

[0053] The predetermined number of bins includes bin 0. As one example, the predetermined number of bins is received from a user via an input device, such as a mouse or keyboard or keypad, coupled to the processor 114. As another example, identification information of the predetermined number of bins is received from a user via an input device. For further illustration, the user selects that bins 4-7 or bins 1-6 or bins 4-10 are used to determine the first statistical parameter value or the second statistical parameter value. As another example, the predetermined number includes all bins, such as 10 or 20 bins of each cycle (nm) and (n-m+p).

[0054] As another example, the processor 114 controls the HFRF generator 102 to operate at the reference high frequency value HF0 during bin 0 of the cycle (nm). When the HFRF generator 102 operates at the reference high frequency value HF0 to generate the RF signal 152 having the reference high frequency value HF0, the processor 114 determines a first VSWR value for bin 0 of the cycle (nm) as a ratio of the first sum to the second sum. The first sum is the sum of 1 and the magnitude of the first statistical parameter value, and the second sum is the difference between 1 and the magnitude of the first statistical parameter value. Moreover, the processor 114 controls the HFRF generator 102 to operate at the reference high frequency value HF0' during bin 0 of the cycle (n-m+p). When the HFRF generator 102 operates at the reference high frequency value HF0′ to generate an RF signal 152 having the reference high frequency value HF0′, the processor 114 determines a second VSWR value for bin 0 of cycle (n−m+p) as a ratio of the third sum to the fourth sum. The third sum is the sum of 1 and the magnitude of the second statistical parameter value, and the fourth sum is the difference between 1 and the magnitude of the second statistical parameter value. The processor 114 then determines whether the first VSWR value is less than the first VSWR value. Upon determining that the first VSWR value is less than the second VSWR value, the processor 114 controls the HFRF generator 102 to operate at the reference high frequency value HF0. Meanwhile, in response to determining that the second VSWR value is less than the first VSWR value, the processor 114 controls the HFRF generator 102 to operate at the reference high frequency value HF0′.

[0055] As another example, instead of using all of the bins, such as 10 bins or 20 bins, to determine the first or second VSWR value in the preceding examples, a predetermined number of bins are used. For example, less than all bins of each cycle (nm) and (n-m+p) are used. For further illustration, the processor 114 accesses, such as reads, from the memory device 114 the voltages of the voltage signal 212 measured during bins 4-7 of cycles (n-m+p) and (nm) and determines a first VSWR value for bins 4-7 of cycle (nm) from the voltages measured during bins 4-7 of cycle (nm). In a further example, the processor 114 determines a second VSWR for bins 4-7 of cycle (n-m+p) from the voltages measured during bins 4-7 of cycle (n-m+p). As another further example, the processor 114 determines a first VSWR for bins 3-7 of cycles (nm) instead of bins 1-10, and determines a second VSWR for bins 3-7 of cycles (n-m+p) instead of bins 1-10.

[0056] The processor 114 controls the HFRF generator 102 to operate at a reference high frequency value during bin 0 of any cycle of the clock signal 202 (FIG. 2A). For example, the processor 114 includes a reference high frequency value, such as HF0 or HF0′ for bin 0, in the recipe signal 144 (FIG. 1). The processor 114 further includes a time interval for bin 0 and an association, such as a unique relationship or link, between the high frequency value for bin 0 and the time interval for bin 0 in the recipe signal 144. The processor 114 sends the recipe signal 144 to the HFRF generator 104. Upon receiving the recipe signal 144, a controller in the HFRF generator 104 determines that the HFRF generator 104 should generate an RF signal 152 having the reference high frequency value HF0 or HF0′ during the time interval for bin 0. The controller of the HFRF generator 104 controls a power supply of the HFRF generator 104 to generate an RF signal 152 having the reference high frequency value HF0 or HF0′ during the time interval for bin 0.

[0057] Similarly, the processor 114 controls the HFRF generator 102 to operate at the HF offset value during the corresponding bins of bins 1-4 and 6-10 remaining in any cycle of the clock signal 202. For example, the processor 114 includes an HF offset value, such as HF(-4), for bin 1 in the recipe signal 144 (FIG. 1). The processor 114 further includes a time interval for bin 1 and an association, such as a unique relationship or link, between the HF offset value for bin 1 and the time interval for bin 1 in the recipe signal 144. The processor 114 sends the recipe signal 144 to the HFRF generator 104. Upon receiving the recipe signal 144, a controller in the HFRF generator 104 determines that the HFRF generator 104 should generate an RF signal 152 having an HF offset value during the time interval for bin 1. The controller of the HFRF generator 104 controls a power supply of the HFRF generator 104 to generate an RF signal 152 having an HF offset value HF(-4) during the time interval for bin 1.

[0058] In one embodiment, the processor 114 applies dynamic frequency tuning (DFT) to determine the high frequency value HF0 stored in the memory device 116. For example, in DFT, the processor 114 determines the high frequency value HF0 by rotating a high frequency impedance orbit on a Smith chart to minimize a parameter such as high frequency reflected power or gamma.

[0059] 3A is one embodiment of a graph 300 to illustrate a clock signal 302. The clock signal 302 is different from the clock signal 202 (FIG. 2A), described above. The x-axis of the graph 300 plots time t, ranging from time t0 to time t160. The y-axis of the graph 300 plots the voltage of the clock signal 302. The clock signal 302 is generated by the processor 114 (FIG. 1).

[0060] The clock signal 302 periodically transitions between logic level 1 and logic level 0. The clock signal 302 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t40. At time t40, the clock signal 302 transitions from logic level 1 to logic level 0 and remains at logic level 0 from time t40 to time t80. The transitions between logic level 1 and logic level 0 repeat from time t80 to time t160. The transitions between logic level 1 and logic level 0 of the clock signal 302 are generated by the processor 114 and provided to the LFRF generator 102 in the recipe signal 142 (FIG. 1).

[0061] 3B is one embodiment of a graph 320 to illustrate the power of an RF signal 322 generated by LFRF generator 102 (FIG. 1). RF signal 322 is an example of RF signal 150 (FIG. 1) generated and provided by LFRF generator 102. Graph 320 plots an envelope 324 of power versus time t of RF signal 322. Time t is plotted on the x-axis, which is the same as the x-axis of graph 300 (FIG. 3A). Envelope 324 is plotted on the y-axis of graph 320. The y-axis plots the amount of power ranging from -P6 to 0 and the amount of power ranging from 0 to P6. Note that the amount of power increases from -P6 to P6. For example, the amount of power -P5 is greater than the amount of power -P6, which is greater than the amount of power -P4, etc.

[0062] The envelope 324 is of the power of the RF signal 322. For example, the envelope 324 is the peak-to-peak amplitude of the power of the RF signal 322. The envelope 324 periodically transitions between state S1 of the RF signal 322 and state S0 of the RF signal 322 in synchronization with the clock signal 302. For example, the envelope 324 transitions from power level P3 to power level P6 and from power level -P3 to power level -P6 at time t0 and remains at power levels P6 and -P6 from time t0 to time t40. The power levels P6 and -P6 represent state S1 of the RF signal 322. The envelope 324 transitions from power level P6 to power level P3 and from power level -P6 to power level -P3 during the time period from time t36 to time t40 to form a transition state TS1 of the RF signal 322. The envelope 324 remains at power levels P3 and -P3 from time t40 to time t80 to form state S0 of the RF signal 322. The envelope 324 transitions from power level P3 to power level P6 and from power level -P3 to power level -P6 during the time period from time t76 to time t80 to form transition state TS2 of the RF signal 322. In this manner, the power levels P6 and -P6 and the power levels P3 and -P3 repeat from time t80 to time t160. Also, the power levels of the RF signal 322 represent states, such as states S1 or S0, of the RF signal 322. The transitions between logic level 1 and logic level 0 of the clock signal 302 are generated by the processor 114 and provided to the LFRF generator 102 within the recipe signal 142 (FIG. 1) to facilitate the RF signal 322 transitioning in synchronization with the clock signal 302.

[0063] A steady state of the RF signal 322 occurs during a time period when the RF signal 322 does not transition from one state to another, and a transition state of the RF signal 322 occurs during a time period when the RF signal 322 transitions from one state to another. For example, a first steady state is state S1 of the RF signal 322, and a second steady state is state S0 of the RF signal 322. State S1 occurs during a first time period from time t0 to time t36, and state S0 occurs during a second time period from time t40 to time t76. Each of the first time period and the second time period is a tuning window. As an example, a first transition state TS1 is a state of the RF signal 322 during a time period from time t36 to time t40, and a second transition state TS2 is a state of the RF signal 322 during a time period from time t76 to time t80. In a first transition state, the RF signal 322 transitions from state S1 to state S0, and in a second transition state, the RF signal 322 transitions from state S0 to state S1. As an example, during the transition state, the power value of the RF signal 322 changes more frequently compared to the changes in the power value of the RF signal 322 during the steady state. As another example, during the transition state, a positive or negative slope is created by the change in the power level of the state of the RF signal 322. The slope of the power level during the steady state is substantially zero or zero.

[0064] In one embodiment, instead of the RF signal 322, another RF signal generated by the HFRF generator 104 (FIG. 1) is used. The another RF signal is an example of the RF signal 152 (FIG. 1) generated by the HFRF generator 104. The another RF signal transitions from state S1 to state S0 and from state S0 to state S1 in synchronization with the clock signal 302 in the same manner that the RF signal 322 transitions between state S1 and state S0. During state S1, the another RF signal has a greater power level compared to the power level of the another RF signal in state S0. The transitions between logic level 1 and logic level 0 of the clock signal 302 are generated by the processor 114 and provided to the HFRF generator 104 in the recipe signal 144 (FIG. 1) to facilitate the another RF signal transitioning in synchronization with the clock signal 302.

[0065] In one embodiment, both RF signal 150 and RF signal 152 periodically transition between their corresponding states S1 and S0 in synchronization with clock signal 302.

[0066] FIG. 3C is one embodiment of a graph 330 to show that the value of a parameter during a hold-off period during which a transition state occurs is used to determine the reference high frequency value HF0. The hold-off period is illustrated by a diagonal line in graph 320 (FIG. 3B). The hold-off period is the period during which either transition state TS1 or TS2 (FIG. 3B) occurs. Graph 330 plots the HF offset value of HFRF generator 104 versus time t. The HF offset value of HFRF generator 104 is plotted on the y-axis, which is the same as the y-axis of graph 300 (FIG. 3A). Time t is plotted on the x-axis, which is the same as the x-axis of graph 300. Note that at time t29 of cycle (n+1), another negative zero crossing of voltage signal 212 (FIG. 2B) occurs.

[0067] The processor 114 (FIG. 1) determines that the reference high frequency value HF0 is to be applied in cycles n, (n+1), etc., based on the values ​​of the parameters calculated for the transition states of the RF signal 322 occurring during a predetermined number of bins of cycles (nm) and (n-m+p). For example, the processor 114 determines the reference high frequency value HF0 for a predetermined time interval, such as bin 0 of cycles n, (n+1), etc., of the clock signal 202 (FIG. 2A), in a manner similar to that described above with reference to FIG. 2C, and further, the processor 114 takes into account the values ​​of the parameters calculated for the transition states of the RF signal 322 occurring during a predetermined number of bins of cycles (nm) and (n-m+p).

[0068] As another example, to determine that the reference high frequency value HF0 is applied at cycle n, (n+1), etc., the processor 114 does not ignore the parameter value calculated based on the voltage signal 212 ( FIG. 2B ) received by the processor 114 from the V sensor 110 during the occurrence of a transition state such as TS2 in the cycle (nm). In this example, the transition state TS2 precedes the steady state S1 of the cycle (nm). For the sake of illustration, the processor 114 controls the HFRF generator 104 to operate at the reference high frequency value HF0 during bin 0 of the cycle (nm) of the clock signal 202. Also, in the example, the processor 114 controls the HFRF generator 104 to operate at the HF offset value of the RF signal 152 during the bin of the cycle (nm) in which the transition state TS2 of the cycle (nm) occurs. In the example, the processor 114 controls the HFRF generator 104 to operate at the HF offset value and at the reference high frequency value HF0 during the bin in which the steady state of the cycle (nm) occurs that immediately follows the transition state TS2 of the cycle (nm). In the example, the number of bins of cycles (nm) in which the transition state TS2 and the steady state S1 immediately following the transition state TS2 occur is equal to the predetermined number of bins. In the example, the correspondence between each of the HF offset values ​​or the reference high frequency numerical value HF0 and each time interval, such as each bin, to which each of the HF offset values ​​or the reference high frequency numerical value HF0 should be applied by the processor 114 is stored in the memory device 116 and accessed by the processor 114 from the memory device 116. Further, in the example, the HF offset value or the reference high frequency numerical value HF0 is accessed to control the HFRF generator 104 to operate at the HF offset value or the reference high frequency numerical value HF0.

[0069] Continuing with the example, one or more values ​​of the voltage signal 212 are received from the V sensor 110 during a predetermined number of bins in which the transition state TS2 and the steady state S1 of the cycle (nm) occur. In the example, during the time period of the predetermined number of bins, the HFRF generator 104 operates at a reference high frequency value HF0 and an HF offset value. In the example, the processor 114 determines a value of a parameter for each bin of the cycle (nm) based on one or more values ​​of the voltage signal 212 during a predetermined number of bins in which the transition state TS2 and the steady state S1 immediately following the transition state TS2 occur. The value of the parameter is determined for any bin of the cycle (nm) during the occurrence of the transition state TS2 from one or more values ​​of the voltage signal 212 in a manner similar to the manner in which the processor 114 determines the first value of the parameter for bin 1 of the cycle (nm) described with reference to FIG. 2C. In this manner, multiple values ​​of the parameter for the transition state TS2 of the cycle (nm) are determined by the processor 114. The processor 114 determines a statistical value of the parameter from the values ​​of the parameter for a predetermined number of bins for the transition state TS2 of cycle (nm) and the steady state S1 of the cycle (nm) immediately following it, in the same manner as the processor 114 determines a first statistical parameter value from the first set or a first order statistical value from the first order set. The processor 114 compares the statistical value to another statistical value, such as a second statistical parameter value or a second order statistical value of the parameter, to determine whether the statistical value is smaller than the other statistical value. The other statistical value is determined in the same manner as the statistical value of interest is determined, except that the other statistical value is determined for a predetermined number of bins of cycle (n-m+p), and is determined when the reference high frequency value HF0' is applied to the HFRF generator 104. It should also be noted that during cycle (n-m+p), the transition state TS2 and the steady state S1 occur during the predetermined number of bins of cycle (n-m+p).

[0070] Based on the comparison, the processor 114 decides to control the HFRF generator 104 to operate at the reference high frequency value HF0 and controls the HFRF generator 104 to operate at the reference high frequency value HF0 during a predetermined time interval, such as cycle n, bin 0 of (n+1). For example, when the statistical value in question is smaller than another statistical value, the processor 114 decides to control the HFRF generator 104 to operate at the reference high frequency value HF0. On the other hand, when the other statistical value is smaller than the statistical value in question, the processor 114 decides to control the HFRF generator 104 to operate at the reference high frequency value HF0'.

[0071] In one embodiment, the statistical value determined in the preceding example is instead based on parameter values ​​calculated for transition state TS1 and the steady state S0 immediately following transition state TS1 in cycle (nm), and another statistical value determined in the preceding example is instead based on parameter values ​​calculated for transition state TS1 and the steady state S0 immediately following transition state TS1 in cycle (n-m+p).

[0072] The embodiments described herein may be practiced with a variety of computer system configurations including portable hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments described herein may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0073] In some embodiments, the controller is part of a system, which may be part of the examples described above. The system includes semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms, and / or specific processing components (wafer pedestal, gas flow system, etc.) for processing. The system is integrated with electronics for controlling its operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as a "controller," which may control various components or sub-parts of the system. The controller is programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected to or interfaced with the system, depending on the processing requirements and / or type of system.

[0074] In general, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include firmware that stores program instructions, chips defined as digital signal processors (DSPs), ASICs, PLDs, one or more microprocessors, or chips in the form of microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing processes on or for a semiconductor wafer. The operational parameters, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0075] The controller, in some embodiments, is part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or in all or part of a fab host computer system that allows remote access for wafer processing. The controller allows remote access to the system to monitor the current progress of a fabrication operation, to change parameters of a current process, to set up processing steps that follow a current process, or to start a new process, to examine the history of past fabrication operations, and to examine trends or performance metrics from multiple fabrication operations.

[0076] In some embodiments, a remote computer (e.g., a server) provides the process recipe to the system over a computer network, including a local network or the Internet. The remote computer includes a user interface that allows entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of settings for processing the wafer. It should be understood that those settings are specific to the type of process to be performed on the wafer and the type of tool the controller interfaces with or controls. Thus, as described above, the controller is distributed, such as by including one or more individual controllers that are networked together and function toward a common purpose, such as the process of implementing described herein. One example of a distributed controller for such purposes includes one or more integrated circuits on the chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that are combined to control the process in the chamber.

[0077] Without being limited thereto, in various embodiments, the plasma systems described herein include plasma etch chambers, deposition chambers, spin rinse chambers, metal plating chambers, clean chambers, bevel edge etch chambers, physical vapor deposition (PVD) chambers, chemical vapor deposition (CVD) chambers, atomic layer deposition (ALD) chambers, atomic layer etch (ALE) chambers, ion implantation chambers, track chambers, or any other semiconductor processing chambers related to or used in the creation and / or manufacturing of semiconductor wafers.

[0078] Additionally, while the operations described above have been described with respect to a parallel plate plasma chamber, e.g., a capacitively coupled plasma chamber, it should be noted that in some embodiments, the operations described above apply to other types of plasma chambers, including, e.g., plasma chambers including inductively coupled plasma (ICP) reactors, transformer coupled plasma (TCP) reactors, conductor tools, dielectric tools, electron cyclotron resonance (ECR) reactors, etc. For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor in an ICP plasma chamber.

[0079] As described above, depending on the process operations to be performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to carry containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0080] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations manipulate physical quantities.

[0081] Some of the embodiments also relate to hardware units or devices for performing these operations. The device is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer is still capable of performing operations for its special purpose, while performing other processes, program executions or routines that are not part of its special purpose.

[0082] In some embodiments, the operations described herein are performed by a selectively activated computer or configured by one or more computer programs stored in a computer memory or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0083] One or more embodiments described herein may also be made as computer readable code on a non-transitory computer readable medium. A non-transitory computer readable medium is any data storage hardware unit, such as a memory device, that stores data, which is then read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disk ROM (CD-ROM), CD recordable (CD-R), CD rewriteable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, a non-transitory computer readable medium includes a computer readable tangible medium that is distributed across network-coupled computer systems such that the computer readable code is stored and executed in a distributed manner.

[0084] Although some of the method operations described above have been presented in a particular order, it should be understood that in various embodiments, other housekeeping operations are performed between the method operations, or the method operations are adjusted such that they occur at slightly different times or are distributed in a system that allows the method operations to occur at various intervals, or are performed in an order different from that described above.

[0085] Furthermore, it should be noted that in one embodiment, one or more features from any embodiment described above may be combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in this disclosure.

[0086] Although the above embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Thus, the present embodiments should be considered as illustrative rather than restrictive, and the embodiments should not be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

1. 1. A method for reducing RF power reflected back to a high frequency (HF) radio frequency (RF) generator in a bin independent manner, comprising: receiving a voltage signal from an output of a low frequency (LF) RF generator and a matcher coupled to the HF RF generator; Dividing the voltage signal into a number of bins for each cycle of a LFRF signal generated by the LFRF generator; identifying a first bin from the plurality of bins in which a zero crossing occurs; accessing measurements of a parameter occurring in a predetermined number of bins of the plurality of bins; calculating an operating frequency of the HFRF generator for the first bin based on the measurements of the parameters; controlling the HFRF generator to operate at the operating frequency during occurrence of the first bin; A method comprising:

2. 2. The method of claim 1, wherein the calculating the operating frequency of the HFRF generator based on the measurements of the parameters comprises: determining a first value for the operating frequency of the HFRF generator, wherein a first statistical value is determined for the first value from a first plurality of the measurements; determining a second value for the operating frequency of the HFRF generator, wherein a second statistical value is determined for the second value from a second plurality of the measurements; determining that the first value is less than the second value; determining that the first value is the operating frequency of the HFRF generator during the occurrence of the first bin; A method comprising:

3. The method of claim 1 , wherein the measurements include values ​​received during a transition state related to the power of the LFRF signal generated by the LFRF generator.

4. The method of claim 1 , wherein the parameter is a reflection coefficient or a voltage standing wave ratio.

5. The method of claim 1 , wherein the voltage signal has a negative slope at the zero crossing.

6. 2. The method of claim 1, wherein the predetermined number includes all of the plurality of bins for each cycle.

7. 2. The method of claim 1, wherein the predetermined number includes fewer than all of the plurality of bins for each cycle.

8. 1. A controller for reducing reflected RF power towards a high frequency (HF) radio frequency (RF) generator in a bin independent manner, comprising: receiving a voltage signal from an output of a low frequency (LF) RF generator and a matcher coupled to the HF RF generator; Dividing the voltage signal into a number of bins for each cycle of a LFRF signal generated by the LFRF generator; identifying a first bin from the plurality of bins in which a zero crossing occurs; accessing measurements of a parameter occurring in a predetermined number of bins of the plurality of bins; calculating an operating frequency of the HFRF generator for the first bin based on the measurements of the parameters; controlling the HFRF generator to operate at the operating frequency during occurrence of the first bin; A processor configured to: a memory device coupled to the processor; A controller comprising:

9. 9. The controller of claim 8, wherein to calculate the operating frequency of the HFRF generator based on the measured values ​​of the parameters, the processor comprises: determining a first value for the operating frequency of the HFRF generator, wherein a first statistical value is determined for the first value from a first plurality of the measurements; determining a second value for the operating frequency of the HFRF generator, wherein a second statistical value is determined for the second value from a second plurality of the measurements; determining that the first value is less than the second value; determining that the first value is the operating frequency of the HFRF generator during the occurrence of the first bin; A controller configured to:

10. The controller of claim 8 , wherein the measurements include values ​​received during a transition state related to a power of the LFRF signal generated by the LFRF generator.

11. The controller of claim 8 , wherein the parameter is a reflection coefficient or a voltage standing wave ratio.

12. The controller of claim 8 , wherein the voltage signal has a negative slope at the zero crossing.

13. 9. The controller of claim 8, wherein the predetermined number includes all of the plurality of bins for each cycle.

14. 9. The controller of claim 8, wherein the predetermined number includes fewer than all of the plurality of bins for each cycle.

15. a low frequency (LF) RF generator configured to generate a LF RF signal; a high frequency (HF) RF generator configured to generate an HF RF signal; a matcher coupled to the LFRF generator and the HFRF generator, the matcher configured to receive the LFRF signal and the HFRF signal to output a modified RF signal; a controller coupled to the LFRF generator, the HFRF generator, and the matcher; wherein the controller: receiving a voltage signal from an output of the matcher; Dividing the voltage signal into a number of bins for each cycle of the LFRF signal; identifying a first bin from the plurality of bins in which a zero crossing occurs; accessing measurements of a parameter occurring in a predetermined number of bins of the plurality of bins; calculating an operating frequency of the HFRF generator for the first bin based on the measurements of the parameters; controlling the HFRF generator to operate at the operating frequency during occurrence of the first bin; A plasma system configured to:

16. 16. The plasma system of claim 15, wherein to calculate the operating frequency of the HFRF generator based on the measured values ​​of the parameters, the controller further comprises: determining a first value for the operating frequency of the HFRF generator, wherein a first statistical value is determined for the first value from a first plurality of the measurements; determining a second value for the operating frequency of the HFRF generator, wherein a second statistical value is determined for the second value from a second plurality of the measurements; determining that the first value is less than the second value; determining that the first value is the operating frequency of the HFRF generator during the occurrence of the first bin; A plasma system configured to:

17. 16. The plasma system of claim 15, wherein the measurements include values ​​received during a transient state related to the power of the LFRF signal generated by the LFRF generator.

18. 16. The plasma system of claim 15, wherein the parameter is a reflection coefficient or a voltage standing wave ratio.

19. 16. The plasma system of claim 15, wherein the voltage signal has a negative slope at the zero crossing.

20. 16. The plasma system of claim 15, wherein the predetermined number includes fewer than all of the plurality of bins for each cycle.

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