SYSTEM AND METHOD FOR MESH CODING WITH REFLECTION SYMMETRY - Patent application

Abstract

Various implementations described in this disclosure include a method and system for encoding video. In one aspect, the method includes receiving a mesh using polygons representing a surface of an object, detecting a first region of symmetry in the mesh that includes a first line of symmetry, and dividing the first region of symmetry into a first subdivision and a second subdivision. The method includes recursively determining whether one of the first subdivision or the second subdivision includes the second region of symmetry until no region of symmetry is detected in both the first subdivision and the second subdivision. In response to detecting the second region of symmetry in one of the first subdivision or the second subdivision, the method includes determining a second line of symmetry in the second region of symmetry and dividing the first subdivision or the second subdivision into a third subdivision and a fourth subdivision, and compressing information of the third subdivision, the second line of symmetry, and the first line of symmetry into a bitstream.

Description

[Technical field]

[0001] Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 389,316, filed July 14, 2022, and entitled "Refection Symmetry-Based Mesh Coding," and is a continuation of and claims priority to U.S. Provisional Patent Application No. 18 / 208,111, filed June 9, 2023, and entitled "Systems and Methods for Reflection Symmetry-Based Mesh Coding," both of which are incorporated by reference in their entireties.

[0002] The disclosed embodiments relate generally to video coding, including, but not limited to, systems and methods for mesh coding with mirror symmetry. [Background technology]

[0003] Digital video is supported by a variety of electronic devices, such as digital televisions, laptop and desktop computers, tablet computers, digital cameras, digital recording devices, digital media players, video game consoles, smart phones, video teleconferencing devices, video streaming devices, etc. The electronic devices transmit, receive, or otherwise communicate digital video data across communication networks and / or store the digital video data in storage devices. Because communication networks have limited bandwidth capacity and storage devices have limited memory resources, video coding may be used to compress the video data according to one or more video coding standards before the video data is communicated or stored.

[0004] Many video codec standards have been developed. Examples of video coding standards include AOMedia Video 1 (AV1), Versatile Video Coding (VVC), Joint Exploration test Model (JEM), High-Efficiency Video Coding (HEVC / H.265), Advanced Video Coding (AVC / H.264), and Moving Picture Expert Group (MPEG) coding. Typically, video coding uses prediction methods (e.g., inter-prediction, intra-prediction, etc.) that exploit the redundancy inherent in the video data. The goal of video coding is to compress the video data into a format that uses a lower bitrate while avoiding or minimizing degradation of video quality.

[0005] HEVC (also known as H.265) is a video compression standard designed as part of the MPEG-H project. The H.265 / HEVC standard was published by ITU-T and ISO / IEC in 2013 (version 1), 2014 (version 2), 2015 (version 3) and 2016 (version 4). Versatile Video Coding (VVC) (also known as H.266) is a video compression standard intended as a successor to HEVC. The VVC / H.266 standard was published by ITU-T and ISO / IEC in 2020 (version 1) and 2022 (version 2). AV1 is an open video coding format designed as a replacement for HEVC. The validated version 1.0.0 with errata 1 of the specification was released on January 8, 2019. Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, encoding (compression) reduces bandwidth and / or storage space requirements. As described in more detail below, both lossless and lossy compression can be used. Lossless compression refers to techniques where an exact replica of the original signal can be reconstructed from the compressed original signal through a decoding process. Lossy compression refers to an encoding / decoding process where the original video information is not fully preserved during encoding and cannot be fully restored during decoding. With lossy compression, the reconstructed signal may not be identical to the original signal, but the distortion between the original and reconstructed signals is small enough that the reconstructed signal can be used for the intended application. The amount of acceptable distortion is application dependent. For example, a user of a particular consumer streaming application may tolerate more distortion than a user of a movie or television broadcast application. The compression ratio achievable by a particular encoding algorithm can be selected or adjusted to reflect different distortion tolerances. That is, a larger acceptable distortion typically allows for an encoding algorithm that results in larger loss and higher compression ratios.

[0007] This disclosure describes the use of a symmetric predictor that can significantly reduce redundant information in either or both of the vertex positions (x,y,z) and UV coordinates of the mesh of a 3D model. This is in contrast to existing mesh coding algorithms that may primarily exploit local properties of the mesh. 3D models exhibit strong mirror symmetry properties, especially for artifacts. In some embodiments, 3D character models are designed with a predefined A-pose or T-pose with a perfect plane of symmetry. Furthermore, this disclosure describes a more efficient method of coding than recursive symmetric division on folded meshes, which introduces more distortion, more folding, and less potential for saving bits. This disclosure also describes an encoding method for fully symmetric meshes that utilizes both mirror symmetry and mesh compression that uses both lossy and lossless coding. [Means for solving the problem]

[0008] According to some embodiments, a video encoding method is provided.

[0009] The method includes receiving a mesh using polygons representing a surface of an object, detecting a first region of symmetry in the mesh that includes a first line of symmetry and dividing the first region of symmetry into a first subdivision and a second subdivision. The method includes recursively determining whether one of the first subdivision or the second subdivision includes the second region of symmetry until no region of symmetry is detected in both the first subdivision and the second subdivision. In response to detecting the second region of symmetry in one of the first subdivision or the second subdivision, the method includes determining a second line of symmetry in the second region of symmetry and dividing the first subdivision or the second subdivision into a third subdivision and a fourth subdivision, and compressing information of the third subdivision, the second line of symmetry and the first line of symmetry into a bitstream. In some embodiments, the method includes receiving a mesh using polygons representing a surface of an object; determining a first line of symmetry of the mesh and dividing the mesh into a first portion and a second portion; and in response to determining that the first portion satisfies a first set of one or more criteria, the method includes determining a second line of symmetry of the first portion and dividing the first portion into a third portion and a fourth portion; and compressing information of the third portion of the mesh, the second line of symmetry and the first line of symmetry into a bitstream.

[0010] According to some embodiments, a computing system, such as a streaming system, a server system, a personal computer system, or other electronic device, is provided. The computing system includes control circuitry and a memory that stores one or more sets of instructions. The one or more sets of instructions include instructions for performing any of the methods described in this disclosure. In some embodiments, the computing system includes an encoder component and / or a decoder component.

[0011] According to some embodiments, a non-transitory computer-readable storage medium is provided that stores one or more sets of instructions for execution by a computing system, the one or more sets of instructions including instructions for performing any of the methods described in this disclosure.

[0012] From the above, devices and systems using methods for video encoding and decoding are disclosed, which can complement or replace conventional methods, devices and systems for encoding / decoding video.

[0013] The features and advantages described herein are not all-inclusive, and some additional features and advantages will be apparent to those skilled in the art, particularly in light of the drawings, specification, and claims provided in this disclosure. Furthermore, it should be noted that the language used in this specification has been selected primarily for ease of reading and instructional purposes, and not necessarily to describe in detail or define the boundaries of the subject matter described in this disclosure.

[0014] In order to allow the present disclosure to be understood in more detail, a more specific description will be given by referring to the features of various embodiments, some of which are illustrated in the accompanying drawings. However, the accompanying drawings are merely illustrative of the pertinent features of the present disclosure and should not be considered as necessarily limiting, and other useful features may be allowed in the accompanying drawings used in the description. This will be understood by those skilled in the art upon reading the present disclosure. [Brief description of the drawings]

[0015] [Figure 1] 1 is a block diagram illustrating an example of a communication system according to some embodiments. [Figure 2A] FIG. 2 is a block diagram illustrating example elements of an encoder component according to some embodiments. [Figure 2B]FIG. 2 is a block diagram illustrating example elements of a decoder component according to some embodiments. [Diagram 3] FIG. 1 is a block diagram illustrating an example of a server system according to some embodiments. [Figure 4] 1 is a mesh encoder with recursive symmetric decomposition and symmetric predictive coding according to some embodiments. [Diagram 5] 1 is an example of a fully recursive symmetric division in 2D according to some embodiments. [Figure 6] 1 is an example of a fully mirror-symmetric prediction according to some embodiments. [Figure 7] 1 is a planar representation with symmetry sets according to some embodiments. [Figure 8] 1 is an example of symmetric prediction used for a nearly symmetric mesh, according to some embodiments. [Figure 9] 1 is an example of mesh coding for an approximately symmetric mesh with symmetric predictive coding according to some embodiments. [Figure 10] 1 is a flow diagram illustrating an example of a method for encoding a mesh according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] According to common practice, the various features illustrated in the figures are not necessarily drawn to scale and like reference numerals may be used to denote like features throughout the specification and figures.

[0017] This disclosure describes both lossless and lossy mesh encoding techniques based on symmetry of mesh contents. In particular, the disclosed methods and systems relate to reflection-symmetric partitioning, reflection-symmetric prediction and reflection-symmetric encoding of mesh contents.

[0018] Examples of Systems and Devices 1 is a block diagram illustrating a communication system 100 according to some embodiments. The communication system 100 includes a source device 102 and a number of electronic devices 120 (e.g., electronic devices 120-1 through 120-m) communicatively coupled to each other via one or more networks. In some embodiments, the communication system 100 is a streaming system, for example, a streaming system used in conjunction with video-enabled applications, such as video conferencing applications, digital television applications, and media storage and / or distribution applications.

[0019] The source device 102 includes a video source 104 (e.g., a camera component or media storage) and an encoder component 106. In some embodiments, the video source 104 is a digital camera (e.g., configured to create an uncompressed video sample stream). The encoder component 106 generates one or more encoded video bitstreams from the video stream. The video stream from the video source 104 may be voluminous compared to the encoded video bitstream 108 generated by the encoder component 106. Because the encoded video bitstream 108 is voluminous (less data) compared to the video stream from the video source, the encoded video bitstream 108 requires less bandwidth to transmit and less storage space to store compared to the video stream from the video source 104. In some embodiments, the source device 102 does not include the encoder component 106 (e.g., configured to transmit uncompressed video data to one or more networks 110).

[0020] The one or more networks 110 carry information between the source device 102, the server system 112, and / or the electronic device 120 and represent any number of networks including, for example, wired (hardwired) and / or wireless communication networks. The one or more networks 110 may exchange data over circuit-switched and / or packet-switched channels. Exemplary networks include telecommunications networks, local area networks, wide area networks, and / or the Internet.

[0021] The one or more networks 110 include a server system 112 (e.g., a distributed / cloud computing system). In some embodiments, the server system 112 is or includes a streaming server (e.g., configured to store and / or distribute video content, such as an encoded video stream from the source device 102). The server system 112 includes a coder component 114 (e.g., configured to encode and / or decode video data). In some embodiments, the coder component 114 includes an encoder component and / or a decoder component. In various embodiments, the coder component 114 is instantiated as hardware, software, or a combination thereof. In some embodiments, the coder component 114 is configured to decode the encoded video bitstream 108 and re-encode the video data using various encoding standards and / or encoding methods to generate encoded video data 116. In some embodiments, the server system 112 is configured to generate multiple video formats and / or multiple video encodings from the encoded video bitstream 108.

[0022] In some embodiments, server system 112 functions as a Media-Aware Network Element (MANE). For example, server system 112 may be configured to prune encoded video bitstream 108 in order to tailor the potentially diverse bitstream to one or more of electronic devices 120. In some embodiments, a MANE is provided that is separate from server system 112.

[0023] Electronic device 120-1 includes a decoder component 122 and a display 124. In some embodiments, decoder component 122 is configured to decode encoded video data 116 to generate an output video stream that can be rendered on a display or other type of rendering device. In some embodiments, one or more of electronic devices 120 do not include a display component (e.g., are communicatively coupled to an external display device and / or include media storage). In some embodiments, electronic device 120 is a streaming client. In some embodiments, electronic device 120 is configured to access server system 112 to obtain encoded video data 116.

[0024] The source device and / or the electronic devices 120 are sometimes referred to as “terminal devices” or “user devices.” In some embodiments, one or more of the source device 102 and / or the electronic devices 120 are instances of a server system, a personal computer, a portable device (e.g., a smart phone, tablet, or laptop), a wearable device, a videoconferencing device, and / or other types of electronic devices.

[0025] As an example of the operation of the communication system 100, the source device 102 transmits an encoded video bitstream 108 to the server system 112. For example, the source device 102 may encode a stream of pictures captured by the source device. The server system 112 may receive the encoded video bitstream 108 and decode and / or encode the encoded video bitstream 108 using a coder component 114. For example, the server system 112 may apply a more optimal encoding to the video data for network transmission and / or storage. The server system 112 may transmit the encoded video data 116 (e.g., one or more encoded video bitstreams) to one or more of the electronic devices 120. Each electronic device 120 may decode the encoded video data 116 to recover the video pictures and display them accordingly.

[0026] In some embodiments, the transmission described above is a one-way data transmission. One-way data transmission may be used in some applications, such as in media serving applications. In some embodiments, the transmission described above is a two-way data transmission. Two-way data transmission may be used in some applications, such as in video conferencing applications. In some embodiments, the encoded video bitstream 108 and / or the encoded video data 116 are encoded and / or decoded according to any of the video encoding / compression standards described in this disclosure, such as HEVC, VVC, and / or AV1.

[0027] FIG. 2A is a block diagram illustrating example elements of an encoder component 106 according to some embodiments. The encoder component 106 receives a source video sequence from a video source 104. In some embodiments, the encoder component includes a receiver (e.g., transceiver) component configured to receive the source video sequence. In some embodiments, the encoder component 106 receives a video sequence from a video source located elsewhere (e.g., a video source that is a component of a device different from the encoder component 106). The video source 104 may provide the source video sequence as a digital video sample stream that may be of any suitable bit depth (e.g., 8-bit, 10-bit, or 12-bit), any color space (e.g., BT.601 Y CrCB or RGB), and any suitable sampling structure (e.g., Y CrCb 4:2:0 or Y CrCb 4:4:4). In some embodiments, the video source 104 is a storage device that stores pre-captured / prepared video. In some embodiments, the video source 104 is a camera that captures on-site image information as a video sequence. Video data may be provided as a number of individual pictures which, when viewed in sequence, achieve motion. A picture may simply be organized as a spatial array of pixels, each of which may contain one or more samples depending on the sampling structure, color space, etc. used. The relationship between pixels and samples will be readily understood by those skilled in the art. The following discussion will focus on samples.

[0028] The encoder component 106 may encode and / or compress pictures of the source video sequence into the encoded video sequence 216 in real time or may encode and / or compress pictures subject to other time constraints required by the application. Enforcing a proper encoding rate is one of the functions of the controller 204. In some embodiments, the controller 204 controls and is operatively connected to other functionalities described below. Parameters set by the controller 204 may include rate control related parameters (e.g., picture skip, quantizer and / or lambda value for rate-distortion optimization techniques), picture size, group of pictures (GOP) layout, maximum motion vector search range, etc. One skilled in the art can easily identify other functions of the controller 204 as related to the encoder component 106 that are optimized for a particular system design.

[0029] In some embodiments, the encoder component 106 is configured to operate in an encoding loop. As a simplified example, the encoding loop includes a source coder 202 (e.g., responsible for creating symbols, such as a symbol stream, based on an input picture to be encoded and one or more reference pictures) and a decoder 210 (at this location, not elsewhere). The decoder 210 reconstructs the symbols to create sample data (if the compression between the symbols and the encoded video bitstream is lossless) in the same way as a decoder (at another location). The reconstructed sample stream (sample data) is input to a reference picture memory 208. Since decoding the symbol stream results in a bit-correct result independent of the location of the decoder (at this location or elsewhere), the contents of the reference picture memory 208 are also bit-correct compared to the encoder at this location and the encoder at the other location. In this way, the predictive part of the encoder interprets the same sample values ​​as reference picture samples as if the decoder interpreted them when using predictions during decoding. The principles of such reference picture synchrony (and the resulting drift when synchrony cannot be maintained, for example due to channel errors) are known to those skilled in the art.

[0030] The operation of the decoder 210 may be the same as that of a decoder in place, such as the decoder component 122, described in detail below in conjunction with Figure 2B. However, and with some reference to Figure 2B, because symbols are valid and the encoding / decoding of symbols into an encoded video sequence by the entropy coder 214 and parser 254 may be lossless, the entropy decoding portion of the decoder component 122, including the buffer memory 252 and parser 254, may not be fully implemented in the decoder in place 210.

[0031] At this point, it can be said that any decoder technology other than parsing / entropy decoding present in the decoder must also necessarily be present in the corresponding encoder in substantially the same functional form. For this reason, the disclosed subject matter focuses on the operation of the decoder. The description of the encoder technology can be omitted since it is the reverse of the decoder technology described overall. Only certain parts require a more detailed description and are described below.

[0032] As part of its operations, the source coder 202 may perform motion compensated predictive coding to predictively code the input frame with reference to one or more previously coded frames from the video sequence designated as reference frames. In this manner, the coding engine 212 codes differences between pixel blocks of the input frame and pixel blocks of one or more reference frames that may be selected as one or more prediction references for the input frame. For example, the controller 204 may manage the coding operations of the source coder 202, including setting parameters and subgroup parameters used to code the video data.

[0033] The decoder 210 decodes the encoded video data of the frames that can be designated as reference frames based on the symbols produced by the source coder 202. The operation of the encoding engine 212 may be advantageously a lossy process. If the encoded video data is decoded by some video decoder (not shown in FIG. 2A), the reconstructed video sequence may be a copy of the source video sequence with some errors. The decoder 210 may repeat the decoding process that may be performed by a video decoder at another location on the reference frames, such that the reconstructed reference frames are stored in the reference picture memory 208. In this way, the encoder component 106 stores a copy of the reconstructed reference frame here (without transmission errors) that has a common content with the reconstructed reference frame that would be obtained by a video decoder at another location.

[0034] The predictor 206 may perform a prediction search for the coding engine 212. That is, for a new frame to be coded, the predictor 206 may search the reference picture memory 208 to obtain sample data (as candidate reference pixel blocks) and to obtain specific metadata such as reference picture motion vectors, block shapes, etc. that can carry suitable prediction references for the new picture. The predictor 206 may operate using one sample block per pixel block to detect suitable prediction references. In some examples, as determined by the search results obtained by the predictor 206, the input picture may include prediction references obtained from multiple reference pictures stored in the reference picture memory 208.

[0035] The output of all the above mentioned functionalities may undergo entropy coding in entropy coder 214. Entropy coder 214 converts the symbols produced by the various functionalities into an encoded video sequence by losslessly compressing the symbols according to techniques known to those skilled in the art (e.g. Huffman coding, variable length coding and / or arithmetic coding).

[0036] In some embodiments, the output of the entropy coder 214 is coupled to a transmitter. The transmitter may be configured to buffer one or more encoded video sequences created by the entropy coder 214 in preparation for transmission over a communication channel 218, and may be hardware / software coupled to a storage device that stores the encoded video data. The transmitter may be configured to integrate other data to be transmitted, such as encoded audio data and / or ancillary data streams (sources not shown), with the encoded video data obtained from the source coder 202. In some embodiments, the transmitter may transmit ancillary data along with the encoded video. The source coder 202 may include such data as part of the encoded video sequence. The ancillary data may comprise temporal / spatial / SNR enhancement layers, other forms of redundant data such as redundant pictures or slices, Supplementary Enhancement Information (SEI) messages, Visual Usability Information (VUI) parameter set fragments, etc.

[0037] The controller 204 may manage the operation of the encoder component 106. During encoding, the controller 204 may assign to each encoded picture a specific type of encoded picture that may affect the encoding technique applied to the respective picture. For example, a picture may be assigned as an Intra Picture (I-picture), a Predictive Picture (P-picture) or a Bi-directionally Predictive Picture (B-picture). An Intra Picture may be encoded and decoded without using any other frame in the sequence as a basis for prediction. In some video codecs, various types of Intra Pictures are possible, including, for example, Independent Decoder Refresh (IDR) pictures. Such variations of I-pictures and their corresponding applications and features will occur to those skilled in the art and will not be repeated in this description. A Predictive Picture may be encoded and decoded using intra or inter prediction, using at most one motion vector and reference index to predict sample values ​​for each block. Bidirectionally predictive pictures can use intra- or inter-prediction and can be coded and decoded using up to two motion vectors and reference indices to predict the sample values ​​of each block. Similarly, multiple-predictive pictures can use three or more reference pictures and associated metadata for the reconstruction of a block.

[0038] In general, a source picture can be spatially subdivided into a number of sample blocks (e.g., blocks of 4x4, 8x8, 4x8, or 16x16 samples, respectively) and the blocks can be coded one by one. Blocks can be coded predictively with reference to other (already coded) blocks, as determined by the coding assignment applied to the picture corresponding to each block. For example, blocks of an I-picture can be coded without prediction, or with prediction with reference to already coded blocks of the same picture (spatial or intra prediction). Pixel blocks of a P-picture can be coded without prediction, with spatial prediction, or with temporal prediction with reference to one previously coded reference picture. Blocks of a B-picture can be coded without prediction, with spatial prediction, or with temporal prediction with reference to one or two previously coded reference pictures.

[0039] A video may be captured in time order as multiple source pictures (video pictures). Intra-picture prediction (often abbreviated as intra-prediction) exploits spatial correlation within a given picture, while inter-picture prediction exploits correlation (temporal or other correlation) between pictures. In one example, a particular picture being coded / decoded, called a target picture, is divided into blocks. If a block in the target picture is similar to a reference block in a previously coded and still buffered reference picture in the video, the block in the target picture may be coded by a vector, called a motion vector. The motion vector points towards the reference block in the reference picture, and may have a third dimension to identify the reference picture when multiple reference pictures are used.

[0040] Encoder component 106 may perform encoding operations according to a pre-defined video encoding technique or standard, such as any of those described in this disclosure. In its operations, encoder component 106 may perform various compression operations, including predictive encoding operations that exploit temporal and spatial redundancy in the input video sequence. Thus, the encoded video data may conform to a syntax defined by the video encoding technique or standard being used.

[0041] 2B is a block diagram illustrating example elements of a decoder component 122 according to some embodiments. The decoder component 122 of FIG. 2B is coupled to a channel 218 and a display 124. In some embodiments, the decoder component 122 includes a transmitter coupled to a loop filter 256 and configured to transmit data to the display 124 (e.g., via a wired or wireless connection).

[0042] In some embodiments, the decoder component 122 includes a receiver connected to the channel 218 and configured to receive data from the channel 218 (e.g., via a wired or wireless connection). The receiver may be configured to receive one or more encoded video sequences that are decoded by the decoder component 122. In some embodiments, the decoding of each encoded video sequence is independent of the other encoded video sequences. Each encoded video sequence may be received from the channel 218, which may be hardware / software coupled to a storage device that stores the encoded video data. The receiver may receive the encoded video data along with other data, such as encoded audio data and / or ancillary data streams, and may forward the other data to a corresponding destination (not shown). The receiver may separate the encoded video sequence from the other data. In some embodiments, the receiver receives ancillary (redundant) data along with the encoded video. The ancillary data may be included as part of the encoded video sequence. The ancillary data may be used by the decoder component 122 to decode the data and / or more accurately reconstruct the original video data. For example, the side data may take the form of a temporal, spatial or SNR enhancement layer, a redundant slice, a redundant picture, a forward error correcting code, and so on.

[0043] According to some embodiments, the decoder component 122 includes a buffer memory 252, a parser 254 (sometimes referred to as an entropy decoder), a scaler / inverse transform unit 258, an intra picture predictor 262, a motion compensated predictor 260, an aggregater 268, a loop filter unit 256, a reference picture memory 266, and a current picture memory 264. In some embodiments, the decoder component 122 is implemented as an integrated circuit, a series of integrated circuits, and / or other electronic circuitry. In some embodiments, the decoder component 122 is implemented at least partially in software.

[0044] A buffer memory 252 is connected between the channel 218 and the parser 254 (e.g., connected to handle network jitter). In some embodiments, the buffer memory 252 is separate from the decoder component 122. In some embodiments, a separate buffer memory is provided between the output of the channel 218 and the decoder component 122. In some embodiments, in addition to the buffer memory 252 in the decoder component 122 (e.g., configured to handle playout timing), a separate buffer memory is provided outside the decoder component 122 (e.g., provided to handle network jitter). When receiving data from a store / forward device or an isochronous network with sufficient bandwidth and controllability, the buffer memory 252 may not be required, or the buffer memory 252 may be small. When used with a best effort packet network such as the Internet, the buffer memory 252 may be required, and it is useful that the buffer memory 252 can be a relatively large, optimally sized memory, and may be at least partially implemented in an operating system or similar element (not shown) outside the decoder component 122.

[0045] Parser 254 is configured to reconstruct symbols 270 from the encoded video sequence. The symbols may include, for example, information used to manage the operation of decoder component 122 and / or information for controlling a rendering device such as display 124. The control information for one or more rendering devices may take the form of, for example, Supplementary Enhancement Information (SEI message) or Video Usability Information (VUI) parameter set fragments (not shown). Parser 254 parses (entropy decodes) the encoded video sequence. The encoding of the encoded video sequence may conform to a video coding technique or standard and may follow principles well known to those skilled in the art, including variable length coding, Huffman coding, context-sensitive or non-context sensitive arithmetic coding, etc. Parser 254 may extract from the encoded video sequence a set of subgroup parameters for at least one of the subgroups of pixels in the video decoder based on at least one parameter corresponding to the group. A subgroup may include a Group of Pictures (GOP), a picture, a tile, a slice, a macroblock, a Coding Unit (CU), a block, a Transform Unit (TU), a Prediction Unit (PU), etc. Parser 254 may also extract from encoded video sequence information such as transform coefficients, quantizer parameter values, motion vectors, etc.

[0046] The reconstruction of symbols 270 may involve a number of different portions depending on the type of coded video picture or portion thereof (e.g., inter-picture and intra-picture, inter-block and intra-block) and other factors. Which portions are involved and how they are involved may be controlled by portion control information parsed by parser 254 from the coded video sequence. For clarity, the flow of such portion control information between parser 254 and the portions described below is not shown.

[0047] Further to the functional blocks already described, the decoder component 122 may be conceptually subdivided into a number of functional sections, as described below. In an actual implementation operating within commercial constraints, many of these sections may interact closely with each other and may be at least partially integrated with each other. However, for purposes of describing the disclosed subject matter, the conceptual subdivision into the functional sections described below will be maintained.

[0048] The scalar / inverse transform unit 258 receives the quantized transform coefficients and control information (such as the transform used, the block size, the quantization factor, and / or the quantization scaling matrix) from the parser 254 as one or more symbols 270. The scalar / inverse transform unit 258 may output a block containing sample values ​​that may be input to an aggregater 268.

[0049] In some examples, the output samples of the scaler / inverse transform unit 258 are suitable for intra-coded blocks, i.e., blocks that do not use predictive information from a previously reconstructed picture, but can use predictive information from a previously reconstructed part of the current picture. Such predictive information can be provided by the intra prediction unit 262. The intra prediction unit 262 may generate a block of the same size and shape as the block being reconstructed using surrounding already reconstructed information obtained from the current (partially reconstructed) picture obtained from the picture memory 264. The aggregator 268 may add, for each sample, the predictive information already generated by the intra prediction unit 262 to the output sample information provided by the scaler / inverse transform unit 258.

[0050] In other examples, the output samples of the scaler / inverse transformer 258 are suitable for inter-coded blocks, and possibly motion-compensated blocks. In such examples, the motion compensated predictor 260 may access the reference picture memory 266 to obtain samples used for prediction. The obtained samples may be motion compensated according to the symbols 270 related to the block, and then added to the output of the scaler / inverse transformer 258 (referred to as residual samples or residual signals in this example) by the aggregator 268 to generate output sample information. The addresses in the reference picture memory 266 from which the motion compensated predictor 260 obtains the prediction samples may be controlled by a motion vector. The motion vector may be available to the motion compensated predictor 260 in the form of a symbol 270, which may have, for example, X, Y and reference picture components. Motion compensation may also include interpolation of sample values ​​obtained from the reference picture memory 266 when sub-sample accurate motion vectors are used, motion vector prediction mechanisms, etc.

[0051] The output samples of the aggregater 268 may be subjected to various loop filtering techniques in the loop filter unit 256. The video compression techniques may include in-loop filter techniques that, while controlled by parameters as symbols 270 from the parser 254 included in the encoded video bitstream and made available to the loop filter unit 256, may also correspond to meta-information obtained when decoding previous (decoding order) portions of the encoded picture or encoded video sequence, and may also correspond to previously reconstructed loop-filtered sample values.

[0052] The output of the loop filter unit 256 may be a sample stream that can be output to a drawing device such as the display 124, but also stored in a reference picture memory 266 for use in later inter-picture prediction.

[0053] Some coded pictures, once fully reconstructed, can be used as reference pictures for future prediction. Once a coded picture is fully reconstructed and the coded picture is identified as a reference picture (e.g., by the parser 254), the reference picture in question can become part of the reference picture memory 266, and a new current picture memory can be reallocated before starting the reconstruction of the next coded picture.

[0054] The decoder component 122 may perform decoding operations according to a predefined video compression technique, which may be described in a document of a standard, such as any of those described in this disclosure. An encoded video sequence is said to comply with the syntax defined by the video compression technique or standard used in the sense that the encoded video sequence adheres to the syntax of the video compression technique or standard as defined in the video compression technique document or standard, and in particular as defined in its profile document. Compliance with some video compression techniques or standards may also be said to be such that the complexity of the encoded video sequence is within the limits defined by the level of the video compression technique or standard. In some examples, the level may have limitations on the maximum picture size, maximum frame rate, maximum reconstruction sample rate (e.g., measured in millions of samples per second), maximum reference picture size, etc. The limits imposed by the level may be further limited in some examples by the specification of a Hypothetical Reference Decoder (HRD) and metadata for HRD buffer management signaled in the encoded video sequence.

[0055] 3 is a block diagram illustrating a server system 112 according to some embodiments. The server system 112 includes a control circuit 302, one or more network interfaces 304, a memory 314, a user interface 306, and one or more communication buses 312 interconnecting these components. In some embodiments, the control circuit 302 includes one or more processors (e.g., a CPU, a GPU, and / or a DPU). In some embodiments, the control circuit includes one or more field programmable gate arrays (FPGAs), hardware accelerators, and / or one or more integrated circuits (e.g., application specific integrated circuits).

[0056] One or more network interfaces 304 may be configured to interface with one or more communication networks (e.g., wireless, wired, and / or optical networks). The communication networks may be local, wide area, metropolitan, vehicular, industrial, real-time, delay tolerant, and the like. Examples of communication networks include local area networks such as Ethernet, cellular networks (including WLAN, GSM, 3G, 4G, 5G, LTE, and the like), television wired or wireless wide area digital networks (including cable, satellite, and terrestrial broadcast television), vehicular and industrial networks (including CANBus), and the like. Such communications may be one-way, receive-only (e.g., television broadcast), one-way transmit-only (e.g., from a CANbus to a particular CANbus device), or bidirectional (e.g., communications to other computer systems using local or wide area digital networks). Such communications may include communications to one or more cloud computing networks.

[0057] The user interface 306 includes one or more output devices 308 and / or one or more input devices 310. The one or more input devices 310 may include one or more of a keyboard, a mouse, a trackpad, a touch screen, a data glove, a joystick, a microphone, a scanner, a camera, etc. The one or more output devices 308 may include one or more of an audio output device (e.g., a speaker), a visual output device (e.g., a display or monitor), etc.

[0058] The memory 314 may include high speed random access memory (such as DRAM, SRAM, DDR RAM, and / or other random access solid state memory devices) and / or non-volatile memory (such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, and / or other non-volatile solid state storage devices). Alternatively, the memory 314 includes one or more storage devices located remotely from the control circuitry 302. The memory 314 includes a non-transitory computer readable storage medium, or alternatively, a non-volatile solid state memory device in the memory 314 includes the non-transitory computer readable storage medium. In some embodiments, the memory 314, or the non-transitory computer readable storage medium of the memory 314, stores the following programs, modules, instructions, and data structures, or a subset or superset thereof: • An operating system 316 that handles various basic system services and contains procedures for performing hardware-dependent tasks; A network communications module 318 that is used to connect the server system 112 to other computing devices via one or more network interfaces 304 (e.g., via wired and / or wireless connections); An encoding module 320 for performing various functions related to encoding and / or decoding of data, such as video data. In some embodiments, the encoding module 320 is an instance of the coder component 114. The encoding module 320 may include, but is not limited to, one or more of the following: a decoding module 322 for performing various functions relating to decoding of the encoded data, such as those described above with respect to the decoder component 122; and an encoding module 340 for performing various functions relating to encoding data, such as those described above with respect to the encoder component 106; and A picture memory 352 that stores pictures and picture data, for use, for example, in conjunction with the encoding module 320. In some embodiments, the picture memory 352 includes one or more of the reference picture memory 208, the buffer memory 252, the current picture memory 264, and the reference picture memory 266.

[0059] In some embodiments, the decoding module 322 includes a parsing module 324 (e.g., configured to perform various functions described above with respect to the parser 254), a transform module 326 (e.g., configured to perform various functions described above with respect to the scalar / inverse transform unit 258), a prediction module 328 (e.g., configured to perform various functions described above with respect to the motion compensation prediction unit 260 and / or the intra picture prediction unit 262), and a filter module 330 (e.g., configured to perform various functions described above with respect to the loop filter 256).

[0060] In some embodiments, the encoding module 340 includes a code module 342 (e.g., configured to perform various functions described above with respect to the source coder 202 and / or the coding engine 212) and a prediction module 344 (e.g., configured to perform various functions described above with respect to the predictor 206). In some embodiments, the decoding module 322 and / or the encoding module 340 include a subset of the modules shown in Figure 3. For example, a prediction module shared by both the decoding module 322 and the encoding module 340 is used.

[0061] Each of the above-identified modules stored in memory 314 corresponds to a set of instructions for performing functions described in this disclosure. The above-identified modules (e.g., sets of instructions) need not be implemented as separate software programs, procedures, or modules, and thus various subsets of these modules may be combined or rearranged in different embodiments. For example, encoding module 320 may suitably not include separate decoding and encoding modules, and may even use the same set of modules to perform both sets of functions. In some embodiments, memory 314 stores a subset of the above-identified modules and data structures. In some embodiments, memory 314 stores additional modules and data structures not described above, such as an audio processing module.

[0062] In some embodiments, server system 112 includes a web server, a Hypertext Transfer Protocol (HTTP) server, a File Transfer Protocol (FTP) server, and web pages and applications implemented using Common Gateway Interface (CGI) scripts, PHP Hyper-text Preprocessor (PHP), Active Server Pages (ASP), Hyper Text Markup Language (HTML), Extensible Markup Language (XML), Java, JavaScript, Asynchronous JavaScript and XML (AJAX), XHP, Javelin, Wireless Universal Resource File (WURFL), or the like.

[0063] 3 illustrates a server system 112 according to some embodiments, although FIG. 3 is intended more as a functional description of various features that may be present in one or more server systems than as a structural overview of the embodiments described in this disclosure. In implementation, those skilled in the art will recognize that items shown separately can be combined and some items can be separated. For example, some items shown separately in FIG. 3 can be implemented on one server and some items can be implemented on one or more servers. The actual number of servers used to implement the server system 112 and how functionality is allocated among the servers will vary from implementation to implementation and will otherwise depend in part on the amount of data traffic the server system processes during peak and average usage periods.

[0064] Example encoding approaches VMesh is the current MPEG standard for compressing static and dynamic meshes. The current VMesh reference software separates the input mesh into a simple base mesh and a displacement vector, which are coded separately. Symmetry is a property of a geometric object when the object is mapped to itself by an operation. In Euclidean distance, reflection, translation, rotation, and combinations of these are a group of operations called symmetric transformations or Euclidean isometries. Mirror symmetry, or bilateral symmetry, is the most common symmetry that exists in both the living and non-living worlds. In some embodiments, all points and edges of a mirror-symmetric mesh have a one-to-one correspondence through a plane of symmetry. In addition to the above, many man-made objects are designed with mirror symmetry.

[0065] In some embodiments, one or more planes of symmetry of a mesh are detected in a simple manner using PCA, in some embodiments, one or more planes of symmetry of a mesh are detected in a more advanced manner using deep learning.

[0066] We can use mirror symmetry to create a folding mesh. A folding mesh M is a mesh that contains mutually exclusive regions.

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[0067] The methods and systems described in this disclosure include operations that can be used individually or combined in any order. The methods and systems described in this disclosure can be applied to any polygon mesh. In some embodiments, the mesh includes multiple 3D polygons. The proposed methods may be used for both lossy and lossless mesh compression. In this proposal, mirror symmetry is used as an example, where a symmetrical structure is a plane in 3D and a symmetrical structure is a line in 2D.

[0068] In some embodiments, a symmetric mesh is recursively divided and encoded. For example, the sub-mesh M i but

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[0069] Symmetric Sub-Mesh

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[0070] In a perfect symmetric state, the symmetric prediction is accurate and there is no misalignment.

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[0071] A symmetric region detection method is used for mesh division (P1). In mesh division, unconnected parts of a mesh are separated into independent sub-meshes. For example, a mesh representing the head of a virtual character wearing glasses can be separated into a sub-mesh for the glasses and a sub-mesh for the virtual character's head. The separated sub-meshes are then joined to one or more symmetric meshes (e.g.

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[0072] In step 404, the method determines whether to proceed with the symmetric split. For example, a cost function may be calculated to determine whether the symmetric split justifies using computing resources for the symmetric split (e.g.,

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[0073] In the case of a symmetric split (P2), either half of the symmetric mesh can be continued (e.g., continued for further processing and / or continued for encoding). In some embodiments, the half of the symmetric mesh with more vertices and faces (e.g., also referred to as the "symmetric part") is selected for further processing and / or encoding. Alternatively, the left symmetric region or the top symmetric region can be selected.

[0074] Example of encoding operation FIG. 5 shows an example of a fully recursive mirror symmetric partition as an example encoding process 500. In some embodiments, for each possible symmetric partition, a flag is signaled in the bitstream to indicate whether the respective partition is used or not. In some embodiments, for each possible symmetric partition, a flag is not signaled in the bitstream, and a decision is made to implicitly derive whether the respective partition is used or not. For each partition used, a description of the partition plane associated with the partition, including associated parameters, is signaled or derived. As in FIG. 3, the symmetric partitioning stops at step 2, since the final partitioning in step 3 is unnecessary (x1, x7 are already coded via symmetry lines p1, p3).

[0075] Step 1 in FIG. 5 shows a two-dimensional (2D) starting mesh with eight points x1, x2, x3, x4, x5, x6, x7, and x8. Instead of encoding all eight points, in step 1, only x1 and x5 are encoded to represent symmetric line p1. The symmetric line p1 passes through x1 and x5. In an embodiment where only the left part of the mesh is continued, step 2 in FIG. 5 shows how the left half of the mesh is left. In step 2, x7 and x3 are encoded to represent symmetric line p2, which passes through two points x7 and x3. In some embodiments, only the top half of the mesh is left as shown in step 3. Although step 3 involves encoding x8 and x4 to represent symmetric p3, line p3 maps x1 to x7, and step 3 is not necessary since x1 and x7 have been encoded in steps 1 and 2, respectively. Instead of encoding x8 and x4 to represent symmetric p3, only x8 is encoded. In addition to the encoded vertices / points, we also encode the connections between x7 and x8, and between x8 and x1.In step 2, we complete a symmetric partition of this mesh using reflections.

[0076] In the example shown in Figure 5, if the starting mesh has eight vertices, three vertices (e.g., x2, x4, and x6) can be derived without being coded (e.g., coding only the five vertices x1, x3, x5, x7, and x8). The eight-vertex mesh in Figure 5 also contains eight connections, six of which can be derived (e.g., coding only the connections between x7 and x8 and between x8 and x1).

[0077] Decryption operation example In some embodiments, a mirror-symmetric predictive coding is used to decode a complete mirror-symmetric mesh, where every edge and vertex has a corresponding edge and vertex for each mirror plane. In some embodiments, based on one or more coordinates already decoded and one or more connections already decoded, the remaining coordinates and connections are predicted based on information about the distance of the vertex from the symmetry line or plane, and the vertices that are at the same distance from the symmetry line or plane in the normal direction of the symmetry line or plane are decoded.

[0078] Using the coded information obtained from the example described with respect to FIG. 5 (e.g., x1, x3, x5, x7 and x8, the connection between x7 and x8, and the connection between x8 and x1 are coded), the starting mesh can be decoded as shown in FIG. 6.

[0079] 6 shows an example of a decoding process 600. In step 1 of the decoding process, the normal vector of the symmetric line p2 from x8 is calculated using the symmetric line p2.

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[0080] In step 2, after x6 is obtained, the normal vector of the symmetry line p1 is drawn at the same distance from the symmetry line p1 as x6 is away from the symmetry line p1.

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[0081] Symmetry Plane Encoding and Decoding Example In some embodiments, instead of using three 3d points to represent the symmetry plane p, we use only two 3D points of a symmetric pair (x1, x2) as shown in Figure 7. x2 is the symmetric of x1 across the symmetry plane p. At the decoder, the midpoint

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[0082] In some embodiments, the symmetric plane is encoded by modeling it with the equation ax+by+cz+d=0. The values ​​of (a,b,c,d) are signaled.

[0083] In some embodiments, an approximately symmetric mesh is recursively partitioned and encoded. As illustrated in Figure 8, an approximately symmetric mesh is a mesh that contains vertices that have a one-to-one correspondence through a plane of symmetry, and also one or more additional displacements from each vertex that are predicted through a full symmetric reflection.

[0084] In mesh 800, a line of symmetry 814 passes through vertex 812. Mirroring vertex 802 about line of symmetry 814 results in vertex 802', but mesh 800 includes vertex 816 displaced by distance d1 from point 802'. Mesh 800 further includes vertex 818 displaced by distance d2 from point 804', vertex 820 displaced by distance d3 from point 806', vertex 822 displaced by distance d4 from point 808', and point 824 displaced by distance d5 from vertex 810'. In mesh 800, all displacements d1, d2, d3, d4, and d5 are closer to line of symmetry 814 than the respective points obtained by mirroring the vertices about line of symmetry 814. In general, the displacements may be to the left or to the right of the mirrored point. In addition to the above, the displacements may extend in one or more directions (e.g., up / down displacements in addition to left / right displacements).

[0085] FIG. 9 shows an example of a coding scheme for use with nearly symmetric meshes. FIG. 9 shows a coding scheme 900 that differs from coding scheme 400 in that it includes a symmetric predictive encoder 902. The symmetric predictive encoder 902 includes circuitry for implementing step 904, which encodes two half-meshes (e.g.,

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[0086] Added D i represents the displacement vector. Equation (1) is a special case of equation (2) where all the displacements are zero. For an almost symmetric mesh, the asymmetric mesh, the symmetry plane and the displacement vector are encoded by the encoder.

[0087] The output of the comparison in step 904 is a displacement vector D, which is the difference between the actual position of each vertex and the symmetrically predicted position of the corresponding vertex. i The displacement vector D i The information about is compressed into a bitstream.

[0088] 10 is a flow diagram illustrating a method 1000 for encoding video in accordance with some embodiments. Method 1000 may be performed in a computing system (e.g., server system 112, source device 102, or electronic device 120) having control circuitry and memory for storing instructions executed by the control circuitry. In some embodiments, method 1000 is performed by executing instructions stored in a memory (e.g., memory 314) of the computing system.

[0089] A system receives 1002 a mesh using polygons representing a surface of an object. The system detects 1004 a first region of symmetry in the mesh that includes a first line of symmetry and divides the first region of symmetry into a first subdivision and a second subdivision. The system recursively determines 1006 whether one of the first subdivision or the second subdivision includes the second region of symmetry until no region of symmetry is detected in either the first subdivision or the second subdivision. In response to detecting 1008 a second region of symmetry in the first subdivision or the second subdivision, the system determines 1008 a second line of symmetry in the second region of symmetry and divides the first subdivision or the second subdivision into a third subdivision and a fourth subdivision, and the system compresses 1010 information of the third subdivision, the second line of symmetry, and the first line of symmetry into a bitstream.

[0090] In some embodiments, the first symmetry line is a plane used for symmetry reflection. In some embodiments, the system compresses the first set of information about the third subdivision into a bitstream. In some embodiments, before determining the symmetry plane of the mesh, the system divides the mesh into a first symmetric part and a second asymmetric part, and determining the symmetry plane of the mesh includes determining the symmetry plane of the first symmetric part and compressing the information of the second asymmetric part into a bitstream.

[0091] In some embodiments, dividing the mesh into a first symmetric portion and a second asymmetric portion includes separating the mesh into respective unconnected mesh components in response to determining that the mesh includes one or more unconnected mesh components. In some embodiments, compressing information about the first line of symmetry into a bitstream includes encoding a set of vertices of the first division. In some embodiments, the system reconstructs the mesh using the first line of symmetry, information about a normal direction of the first line of symmetry, and the encoded distances of the vertices from the first line of symmetry.

[0092] In some embodiments, determining the first line of symmetry includes determining a first plane of symmetry that includes the first line of symmetry, and compressing the information about the first line of symmetry into a bitstream includes encoding the first plane of symmetry. In some embodiments, the first plane of symmetry is encoded using a symmetric set of vertices that includes a first vertex and a second vertex, such that the second vertex is provided by mirroring the first vertex about the first plane of symmetry. In some embodiments, the first vertex of the symmetric set of vertices is encoded in the mesh data or signaled together with the first plane of symmetry. In some embodiments, the first plane of symmetry is modeled using a linear equation with four signaled parameters.

[0093] In some embodiments, the mirrored vertices are vertices of the first partition that are mirrored about a first line of symmetry, the mirrored vertices and corresponding vertices from the second partition have a first displacement, and the system compresses information related to the first displacement into the bitstream. In some embodiments, the system provides a displacement vector including respective displacements of a set of vertices of the first partition and a corresponding set of vertices of the second partition, and the system compresses information related to the displacement vector into the bitstream. In some embodiments, the first partition and the second partition comprise substantially symmetric meshes.

[0094] 10 depicts several logical stages in a particular order, the order of non-order-dependent stages may be changed, and other stages may be combined or removed. Some reordering and other groupings not specifically mentioned will be apparent to those of ordinary skill in the art, and thus the ordering and grouping depicted in this disclosure is not a limiting list. Moreover, it should be understood that the stages may be implemented in hardware, firmware, software, or any combination thereof.

[0095] Attention is now directed to several embodiments.

[0096] (A1) In one aspect, some embodiments include a video encoding method (e.g., method 1000). In some embodiments, the method is performed by a computing system (e.g., server system 112) having memory and control circuitry. In some embodiments, the method is performed by an encoding module (e.g., encoding module 320). In some embodiments, the method is performed by an entropy coder (e.g., entropy coder 214). The method includes (i) receiving a mesh using polygons representing a surface of an object, and (ii) detecting a first region of symmetry in the mesh that includes a first line of symmetry and dividing the first region of symmetry into a first division and a second division. The method includes (iii) recursively determining whether one of the first division or the second division includes the second region of symmetry until no region of symmetry is detected in both the first division and the second division. The method includes (iv) determining a second symmetry line within the second symmetry region in response to detecting a second symmetry region within one of the first division portion or the second division portion, and dividing the first division portion or the second division portion into a third subdivision portion and a fourth subdivision portion, and (v) compressing information of the third subdivision portion, the second symmetry line, and the first symmetry line into a bitstream.In some embodiments, the method includes the steps of (i) receiving a mesh (e.g., a 3D mesh (a 3D mesh having several 2D mesh segments)) using polygons (e.g., a triangular mesh) that represent a surface of an object; and (ii) determining a first line of symmetry of the mesh (e.g., the first line of symmetry is a first plane of symmetry) and dividing the mesh into a first division and a second division (e.g., if there is perfect symmetry, the first division is identical to the second division, and if they are nearly symmetric, the first division is smaller than a threshold amount). (iii) in response to determining that the first portion satisfies a first set of one or more criteria (e.g., the first set of one or more criteria includes a cost function, and the cost function for further dividing the sub-mesh is still below a threshold), determining a second symmetry line of the first portion (e.g., the second symmetry line is a line in a second symmetry plane) to divide the first portion into a third portion and a fourth portion; and (iv) compressing information of the third portion of the mesh, the second symmetry line, and the first symmetry line into a bitstream.

[0097] (A2) In some embodiments of A1, the method includes compressing a first set of information relating to the third subdivision (e.g., the first set of information includes connection information relating to the encoding points) into a bitstream.

[0098] (A3) In some embodiments of A1 or A2, the method includes dividing the mesh into a first symmetric portion and a second asymmetric portion before detecting the first symmetric region, where detecting the first symmetric region in the mesh comprises determining a first line of symmetry, and compressing information of the second asymmetric portion into a bitstream.

[0099] (A4) In some embodiments of A3, dividing the mesh into a first symmetric portion and a second asymmetric portion includes, in response to determining that the mesh includes one or more mesh components that are not connected, separating the mesh into respective unconnected mesh components.

[0100] (A5) In some embodiments of any of A1 to A4, the step of compressing information about the first line of symmetry into a bitstream includes a step of encoding a set of vertices of the first division (e.g., the set of vertices representing a line or plane of symmetry).

[0101] (A6) In some embodiments of any of A1-A5, the method further includes a step of reconstructing the mesh (e.g., determining the positions of one or more vertices that are not coded) using the first symmetry line, information about the normal direction of the first symmetry line, and the distances of the coded vertices from the first symmetry line (e.g., the directional characteristics for decoding are the inverse of the directional characteristics used for encoding, and the vertices are decoded using the second symmetry line before being decoded using the first symmetry line).

[0102] (A7) In some embodiments of any of A1 to A6, the step of determining the first line of symmetry includes a step of determining a first plane of symmetry that includes the first line of symmetry, and the step of compressing information about the first line of symmetry into a bitstream includes a step of encoding the first plane of symmetry.

[0103] (A8) In some embodiments of A7, the first plane of symmetry is encoded using a symmetric set of vertices including a first vertex and a second vertex, such that the second vertex is provided by reflecting the first vertex about the first plane of symmetry (e.g., the first plane of symmetry bisects a line connecting the first vertex to the second vertex).

[0104] (A9) In some embodiments of A8, a first vertex of the symmetric set of vertices is encoded in the mesh data or signaled along with the first symmetry plane.

[0105] (A10) In some embodiments of A7, the first plane of symmetry is modeled using a linear equation with four parameters that are signaled.

[0106] (A11) In some embodiments of any of A1 to A10, the mirrored vertex is a vertex of a first division portion that is mirrored about a first line of symmetry, and the mirrored vertex and a corresponding vertex obtained from the second portion (e.g., the corresponding vertex is a mirror reflection of the vertex of the first division portion about the first line of symmetry) have a first displacement, and the method includes a step of compressing information about the first displacement into a bitstream.

[0107] (A12) In some embodiments of A11, the method further includes providing a displacement vector including respective displacements between a set of vertices of the first division portion and a corresponding set of vertices of the second division portion, and the method includes compressing information relating to the displacement vector into a bitstream.

[0108] (A13) In some embodiments of A11, the first division portion and the second portion comprise approximately symmetric meshes (e.g., the approximately symmetric mesh includes a one-to-one vertex correspondence via a plane of symmetry and a corresponding displacement).

[0109] (A14) In some embodiments of any of A1 to A13, the first line of symmetry is a plane used for reflection with respect to symmetry.

[0110] The methods described in this disclosure may be used individually or combined in any order. Each of the methods may be performed by a processing circuit (e.g., one or more processors or one or more integrated circuits). In some embodiments, the processing circuit executes a program stored on a non-transitory computer-readable medium.

[0111] In another aspect, some embodiments include a computing system (e.g., server system 112) including a control circuit (e.g., control circuit 302) and a memory (e.g., memory 314) coupled to the control circuit, the memory storing one or more sets of instructions configured to be executed by the control circuit, the one or more sets of instructions including instructions for performing any of the methods described in this disclosure (e.g., A1-A14 above).

[0112] In yet another aspect, some embodiments include a non-transitory computer-readable storage medium that stores one or more sets of instructions for execution by control circuitry of a computing system, the one or more sets of instructions including instructions for performing any of the methods described in this disclosure (e.g., A1-A14 above).

[0113] Although the terms "first," "second," and the like may be used in this disclosure to describe various elements, it is understood that the elements are not necessarily limited by the terms, but are merely used to distinguish one element from another.

[0114] The terms used in this disclosure are only for the purpose of describing particular embodiments and are not intended to impose limitations on the claims. When used in the description of the embodiments and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms, unless the context clearly dictates otherwise. It is also understood that the term "and / or" used in this disclosure refers to and includes any possible combination of one or more of the associated listed items. It is further understood that the terms "comprises" and / or "comprising" used herein indicate the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0115] As used in this disclosure, the term "if" can be interpreted to mean "when" a stated precondition is true, "when" a stated precondition is true, "upon determining that" a stated precondition is true, "according to determining that" a stated precondition is true, or "upon detecting" that a stated precondition is true, depending on the context. Similarly, the phrase "if it is determined that [a stated precondition is true]" or "if [a stated precondition is true]" or "when [a stated precondition is true]" can be interpreted to mean "upon determining" that a stated precondition is true, or "upon determining" that a stated precondition is true, or "according to determining" that a stated precondition is true, or "upon detecting" that a stated precondition is true, or "upon detecting" that a stated precondition is true, depending on the context.

[0116] The foregoing description has been provided for illustrative purposes with respect to specific embodiments. However, the illustrative description above is not intended to be exhaustive or to limit the disclosed claims to the precise form consistent with the present invention. Many modifications and variations are possible in light of the above teachings. The embodiments have been selected and described to best explain the principles of operation and practical applications so that others skilled in the art may understand. [Explanation of symbols]

[0117] 100 Communication Systems 102 Source Device 104 Video Source 106 Encoder Components 108 Video Bitstream 110 Network 112 Server System 114 Coda Constituents 116 Video Data 120 Electronic Devices 122 Decoder Components 124 Display 202 Source Code 204 Controller 206 Predictor 208 Reference Picture Memory 210 Decoder 212 Encoding Engine 214 Entropy Coder 216 Video Sequences 218 Communication Channels 252 Buffer Memory 254 Parser 256 Loop filter section 258 Inverse conversion unit 260 Compensation Prediction Unit 262 Intra-picture prediction unit 264 Current Picture Memory 266 Reference Picture Memory 268 Collector 270 Symbols 302 Control circuit 304 Network Interface 306 User Interface 308 Output Device 310 Input Devices 312 Communication Bus 314 Memory 316 Operating Systems 318 Network Communication Module 320 Encoding Module 322 Decryption Module 324 Perth Module 326 Conversion Module 328 Prediction Module 330 Filter Module 340 Encoding Module 342 Code Module 344 Prediction Module 352 Picture Memory 400 Coding Framework 402 Arrow 404 Step 500 Encoding Process 600 Decryption Process 700 3D planes 800 mesh 802 Vertex 804 Vertex 806 Vertex 808 Vertex 810 Vertex 802' points 804' points 806' points 808' points 810' Vertex 812 Vertices 814 Line of symmetry 816 Vertex 818 Vertex 820 Vertex 822 Vertex 824 points 900 Coding Framework 902 Symmetric predictive coding unit 1000 ways

Claims

1. 1. A method of encoding a mesh executed by a computing system having a memory and one or more processors, the method comprising: receiving a mesh using polygons representing a surface of an object; detecting a first area of ​​symmetry in the mesh having a first line of symmetry and dividing the first area of ​​symmetry into a first division and a second division; recursively determining whether one of the first division unit or the second division unit includes a second symmetric region until a symmetric region is not detected in both the first division unit and the second division unit; In response to detecting the second symmetric region in one of the first division portion or the second division portion, determining a second symmetry line in the second symmetric region to divide the first division portion or the second division portion into a third subdivision portion and a fourth subdivision portion; compressing information of the third subdivision, the second symmetric line and the first symmetric line into a bit stream; A method comprising:

2. compressing a first set of information relating to said third subdivision into said bitstream. The method of claim 1 further comprising:

3. prior to detecting the first symmetric region, dividing the mesh into a first symmetric part and a second asymmetric part, wherein detecting the first symmetric region in the mesh comprises determining the first symmetry line; compressing the second asymmetric portion of information into the bitstream; The method of claim 1 further comprising:

4. The step of dividing the mesh into the first symmetric portion and the second asymmetric portion comprises: responsive to determining that the mesh includes one or more unconnected mesh components, separating the mesh into respective unconnected mesh components. The method of claim 3 further comprising:

5. The method of claim 1 , wherein compressing the information about the first line of symmetry into the bitstream comprises encoding a set of vertices of the first partition.

6. reconstructing the mesh using the first line of symmetry, information about the normal direction of the first line of symmetry, and the distances of the encoded vertices from the first line of symmetry. The method of claim 1 further comprising:

7. 2. The method of claim 1 , wherein determining the first line of symmetry comprises determining a first plane of symmetry that contains the first line of symmetry, and wherein compressing the information about the first line of symmetry into the bitstream comprises encoding the first plane of symmetry.

8. 8. The method of claim 7, wherein the first plane of symmetry is encoded using a symmetric set of vertices comprising a first vertex and a second vertex, such that a second vertex is provided by mirroring the first vertex about the first plane of symmetry.

9. The method of claim 8 , wherein the first vertex of the symmetric set of vertices is encoded in mesh data or signaled along with the first symmetry plane.

10. The method of claim 7 , wherein the first plane of symmetry is modeled using a linear equation having four signaled parameters.

11. 2. The method of claim 1, wherein a mirrored vertex is a vertex of the first subdivision that is mirrored about the first line of symmetry, the mirrored vertex and a corresponding vertex from the second subdivision having a first displacement, the method comprising compressing information about the first displacement into the bitstream.

12. 12. The method of claim 11, further comprising providing a displacement vector comprising respective displacements of a set of vertices of the first partition and a corresponding set of vertices of the second partition, the method including compressing information about the displacement vector into the bitstream.

13. The method of claim 11 , wherein the first division and the second division comprise substantially symmetric meshes.

14. The method of claim 1 , wherein the first line of symmetry is a plane used for reflection about the symmetry.

15. A control circuit; Memory, One or more sets of instructions stored in the memory and configured to be executed by the control circuitry, the one or more sets of instructions comprising: instructions to receive a mesh using polygons representing a surface of an object; instructions for detecting a first area of ​​symmetry in the mesh comprising a first line of symmetry and dividing the first area of ​​symmetry into a first division and a second division; instructions for recursively determining whether one of the first segmentation unit or the second segmentation unit includes a second symmetric region until a symmetric region is not detected in both the first segmentation unit and the second segmentation unit; instructions for determining a second line of symmetry within a region in response to detecting the second region of symmetry within one of the first division or the second division to divide the first division or the second division into a third subdivision and a fourth subdivision; instructions for compressing information of the third subdivision, the second symmetric line, and the first symmetric line into a bitstream; one or more sets of instructions comprising: A computing system comprising:

16. 16. The computing system of claim 15, wherein the one or more sets of instructions further comprise instructions for compressing a first set of information about the third subdivision into the bitstream.

17. 16. The computing system of claim 15, wherein the one or more sets of instructions further comprise instructions for dividing the mesh into a first symmetric portion and a second asymmetric portion prior to determining the symmetry plane of the mesh, and wherein determining the symmetry plane of the mesh comprises determining the symmetry plane of the first symmetric portion and compressing information of the second asymmetric portion into the bitstream.

18. 1. A non-transitory computer-readable storage medium storing one or more sets of instructions configured to be executed by a computing device having control circuitry and a memory, the one or more sets of instructions comprising: instructions to receive a mesh using polygons representing a surface of an object; instructions for detecting a first area of ​​symmetry in the mesh comprising a first line of symmetry and dividing the first area of ​​symmetry into a first division and a second division; instructions for recursively determining whether one of the first segmentation unit or the second segmentation unit includes a second symmetric region until a symmetric region is not detected in both the first segmentation unit and the second segmentation unit; instructions for determining a second line of symmetry within a region in response to detecting the second region of symmetry within one of the first division or the second division to divide the first division or the second division into a third subdivision and a fourth subdivision; instructions for compressing information of the third subdivision, the second symmetric line, and the first symmetric line into a bitstream; A non-transitory computer-readable storage medium comprising:

19. 20. The non-transitory computer-readable storage medium of claim 18, wherein the one or more sets of instructions further comprise instructions for compressing a first set of information about the third subdivision into the bitstream.

20. 20. The non-transitory computer-readable storage medium of claim 18, wherein the one or more sets of instructions further comprise instructions for dividing the mesh into a first symmetric portion and a second asymmetric portion prior to determining the symmetry plane of the mesh, wherein determining the symmetry plane of the mesh comprises determining the symmetry plane of the first symmetric portion and compressing information of the second asymmetric portion into the bitstream.

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