Exploiting computational symmetries to reduce errors in quantum computing

Abstract

Aspects of the present disclosure relate generally to systems and methods for use in implementing and / or operating a quantum information processing (QIP) system, and more particularly to using computational symmetries for error mitigation in quantum computation. The computer-implemented method of the present invention includes generating a quantum circuit by compiling a quantum program corresponding to a defined quantum computation, generating a plurality of execution variants of the quantum circuit by applying a first symmetry of one or more symmetries to the quantum circuit, running each of the plurality of execution variants on quantum hardware, receiving a plurality of measurement data sets indicative of computational outputs for each of the plurality of execution variants, and determining a result of the defined quantum computation by aggregating the plurality of measurement data sets.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 387,224, filed December 13, 2022, and U.S. Provisional Patent Application No. 63 / 312,205, filed February 21, 2022, the contents of which are incorporated by reference in their entireties herein.

[0002] Aspects of the present disclosure generally relate to systems and methods for use in implementing and / or operating quantum information processing (QIP) systems. [Background technology]

[0003] Trapped atoms are one of the main implementations of quantum information processing or quantum computing. Other implementations include, for example, those based on superconducting qubits or photonic qubits. Atom-based qubits may be used as quantum memories, as quantum gates in quantum computers and simulators, and may function as nodes for quantum communication networks. Qubits based on trapped atomic ions enjoy a rare combination of attributes. For example, qubits based on trapped atomic ions have very good coherence properties, can be prepared and measured with nearly 100% efficiency, and are easily entangled with each other by modulating the Coulomb interaction with a suitable external control field, such as an optical or microwave field. These attributes make atom-based qubits attractive for extended quantum operations, such as quantum computing or quantum simulation.

[0004] It is therefore important to develop new techniques to improve the design, fabrication, implementation, and / or control of various QIP systems used as quantum computers or quantum simulators, particularly QIP systems that involve operations based on atom-based qubits. Summary of the Invention

[0005] The following presents a simplified summary of one or more aspects to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is not intended to identify key or critical elements of all aspects or to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0006] This disclosure describes various aspects of methods and systems that use computational symmetry to reduce error accumulation in next-generation quantum architectures, including architectures used for QIP systems that handle operations based on atom-based qubits and / or solid-state based qubits.

[0007] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of only a few of the various ways in which the principles of the various aspects may be employed, and the description is intended to include all such aspects and their equivalents. [Brief description of the drawings]

[0008] The disclosed aspects are described below in conjunction with the accompanying drawings, which are provided to illustrate but not to limit the disclosed aspects, and in which like reference numerals represent like elements.

[0009] [Figure 1] FIG. 1 shows a diagram of atomic ions in a linear crystal or chain according to an aspect of the present disclosure. [Diagram 2] 1 illustrates an example of a quantum information processing (QIP) system according to an embodiment of the present disclosure. [Diagram 3] 1 illustrates an example of a computing device according to an aspect of the present disclosure. [Figure 4] 1 illustrates another example of a QIP system according to an embodiment of the present disclosure. [Figure 5A] 5 illustrates an example of an error mitigation subsystem that may be part of the QIP system illustrated in FIG. 4 according to an embodiment of the present disclosure. [Figure 5B] 5 illustrates another example of an error mitigation subsystem that may be part of the QIP system illustrated in FIG. 4 according to an embodiment of the present disclosure. [Figure 6] 1 is a schematic diagram of an example implementation of an error mitigation approach according to aspects of the present disclosure. [Figure 7] 13 shows simulation results for a symmetrized four-qubit circuit (on eight ions) with average under-rotation on all qubit pairs in accordance with an embodiment of the present disclosure. [Figure 8] 1 illustrates the effect of symmetrization on a 13-qubit single-output QFT-based adder circuit, according to an embodiment of the present disclosure. [Figure 9] 1 shows a comparison of fidelity improvement of various algorithms with and without symmetrization in accordance with aspects of the present disclosure. [Figure 10] 13 shows the results of a simulated 4-qubit small random circuit comprising an XX gate and a random single-qubit gate mapped to 8 qubits following a specific assignment, according to an embodiment of the present disclosure. [Figure 11] 1 illustrates an example of a method for implementing quantum computing using error mitigation techniques based on computational symmetry, according to aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The present disclosure recognizes and addresses the problem of error mitigation in quantum computers (QC). Searching for the best implementation of quantum computing on a physical qubit architecture can present several challenges. Instead, the present disclosure proposes to simultaneously use multiple circuit implementations and / or circuit variations (both collectively referred to as "execution variants") and then aggregate the measurement results. This approach promises strong noise cancellation and can address some systematic inaccuracies in quantum circuits, but compared to error correction, this approach uses time redundancy rather than extensive circuit redundancy. Empirical results demonstrate the performance improvement of ion trap quantum computers and scalable benefits in simulations.

[0011] Aspects of the present disclosure, individually or in combination, enable improving the performance of quantum computers with high-quality qubits by implementing error mitigation approaches based on computational and nonlinear aggregation symmetries. To avoid qubit-level and gate-level overhead, the error mitigation approaches of the present disclosure can distinguish an ideal quantum computation by its invariance under specific symmetries that arise at multiple levels of the physical implementation. Such symmetries are called computational symmetries or computational symmetries. Computational symmetries include computation-specific symmetries related to the specific quantum computation being performed. Aspects of the present disclosure can first generate variant circuit implementations using computational symmetries (e.g., computation-specific symmetries). Such variants can be run on one or more QCs. The collected measurement data (e.g., measurement statistics) can then be aggregated via linear or nonlinear techniques. As a result of such aggregation, the symmetrized effects of deterministic imprecision are nearly cancelled out and random noise is not amplified.

[0012] The error mitigation approach of the present disclosure provides tangible improvements to the technical field of quantum information processing (QIP). Indeed, on a commercially available trapped ion quantum computer, implementation of the error mitigation techniques of the present disclosure can improve the performance of several practical quantum algorithms by approximately 100 times, without qubit and / or gate overhead. More specifically, the error mitigation approach of the present disclosure has been validated on a commercially available QC for quantum algorithms of practical interest. For quantum machine learning (QML) circuits, linear aggregation can improve performance by 1.5 to 2 times. Nonlinear aggregation with voting can provide much larger improvements in some cases. For a 15 qubit quantum Fourier transform (QFT) adder circuit with voting, embodiments of the present disclosure provide approximately 100 times performance improvement, without distortion, over computations without such aggregation.

[0013] Moreover, the error mitigation approaches of the present disclosure may be applicable to multiple types of QIP and qubit technologies and are compatible with existing error mitigation strategies. Although various aspects of the error mitigation approaches are described with reference to QIP systems based on trapped atomic qubits, the present disclosure is not limited in that respect. Indeed, the error mitigation approaches of the present disclosure may be used in other types of QIP systems based on solid-state qubits. Furthermore, although described with reference to qubits, the error mitigation approaches of the present disclosure may also be implemented for other types of quantum devices, such as qubit devices, in some cases.

[0014] Solutions to the above problems will be described in more detail with respect to Figures 1-11, but Figures 1-3 provide background on QIP systems or quantum computers, and more specifically, atom-based QIP systems or quantum computers.

[0015] FIG. 1, shown below, shows a diagram 100 with a number of atomic ions 106 (e.g., atomic ions 106a, 106b, ..., 106c, and 106d) trapped in a linear crystal or chain 110 using a trap (which may be in a vacuum chamber as shown in FIG. 2). The trap may also be referred to as an ion trap. The illustrated ion trap may be constructed or fabricated on a semiconductor substrate, a dielectric substrate, or a glass die or wafer (also referred to as a glass substrate). The atomic ions 106 may be provided to the trap as atomic species for ionization and confinement in the chain 110.

[0016] In the example shown in FIG. 1, the trap includes electrodes for trapping or confining a number of atomic ions in chains 110 that are laser-cooled to be nearly stationary. The number of trapped atomic ions (N) can be configurable, and more or fewer atomic ions may be trapped. The atomic ions may be, for example, ytterbium ions ( 171 Yb + ions, etc.) Atomic ions are 171 Yb + The atomic ions are illuminated with laser (light) radiation tuned to the resonance of the ytterbium atom, and the fluorescence of the atomic ions is imaged onto a camera or other type of detection device. In this example, the atomic ions may be spaced apart from each other by about 5 microns (μm), but the separation may be less than 5 μm or more than 5 μm. The separation of the atomic ions is determined by a balance between external confinement forces and Coulomb repulsion, and need not be uniform. Furthermore, in addition to ytterbium atomic ions, neutral atoms, Rydberg atoms, different atomic ions, or different species of atomic ions may be used. The trap may be a linear RF power trap, but other types of confinement may be used, including optical confinement. Thus, the confinement device may be based on a variety of technologies, e.g., may hold ions, neutral atoms, or Rydberg atoms, with an ion trap being one example of such a confinement device. The ion trap may be, for example, a surface trap.

[0017] 2, shown below, is a block diagram illustrating an example of a QIP system 200 according to various aspects of the present disclosure. QIP system 200 may also be referred to as a quantum computing system, a quantum computer, a computing device, a trapped ion system, etc. QIP system 200 may be part of a hybrid computing system in which QIP system 200 is used to perform quantum computations and operations, and the hybrid computing system also includes a classical computer for performing classical computations and operations.

[0018] 2 shows a generic controller 205 configured to perform various control operations of the QIP system 200. Instructions for the control operations may be stored in a memory (not shown) within the generic controller 205 and may be updated over time via a communication interface (not shown). Although the generic controller 205 is shown separate from the QIP system 200, the generic controller 205 may be integrated with or be part of the QIP system 200. The generic controller 205 may include an automation and calibration controller 280 configured to perform various calibration, testing, and automation operations associated with the QIP system 200.

[0019] QIP system 200 may include an algorithm component 210 that may operate in conjunction with other parts of QIP system 200 to perform quantum algorithms or operations, including stacks or sequences of single qubit and / or multi-qubit (e.g., two qubit) operations, as well as combinatorial stacks or sequences of extended quantum computations. Thus, algorithm component 210 may provide instructions to various components of QIP system 200 (e.g., optical and trap controller 220) to enable the implementation of quantum algorithms or operations. Algorithm component 210 may receive information resulting from implementing a quantum algorithm or operation, process the information, and / or forward the information to other components of QIP system 200 or other devices for further processing.

[0020] QIP system 200 may include an optics and trap controller 220, which controls various aspects of trap 270 in chamber 250, including generating signals to control trap 270, and controls operation of lasers and optics that provide a light beam that interacts with atoms or ions in trap 270. Trap 270 may be referred to as an ion trap when used to confine or trap ions. However, trap 270 may be used to trap neutral atoms, Rydberg atoms, different atomic ions, or different species of atomic ions. The laser and optics may be at least partially located within optics and trap controller 220 and / or within chamber 250. For example, optics within chamber 250 may refer to optical components or optical assemblies.

[0021] The QIP system 200 may include an imaging system 230. The imaging system 230 may include a high resolution imager (e.g., a CCD camera) or other type of detection device (e.g., a photomultiplier tube or PMT) for monitoring the atomic ions while they are being provided to the trap 270 and / or after they have been provided to the trap 270. In one aspect, the imaging system 230 may be implemented separately from the optics and trap controller 220, although the use of fluorescence to detect, identify, and label atomic ions using image processing algorithms may need to be coordinated with the optics and trap controller 220.

[0022] In addition to the above-mentioned components, QIP system 200 may include a source 260 that provides atomic species (e.g., a plume or flux of neutral atoms) to a chamber 250 having a trap 270. Where atomic ions are the basis of quantum operations, trap 270 confines the ionized (e.g., photoionized) atomic species. Trap 270 may be part of the processor or processing portion of QIP system 200. That is, trap 270 may be considered to be the core of the processing operations of QIP system 200, since it holds the atomic-based qubits that are used to perform quantum operations or simulations. At least a portion of source 260 may be implemented separately from chamber 250.

[0023] It should be understood that the various components of the QIP system 200 described in Figure 2 are depicted at a high level for ease of understanding. Such components may include one or more subcomponents, details of which may be provided below as necessary to better understand certain aspects of the present disclosure.

[0024] Aspects of the present disclosure may be implemented at least in part using the general purpose controller 205 , the automation and calibration controller 280 , and / or the algorithm component 210 .

[0025] Referring now to FIG. 3 below, an example of a computer system or device 300 according to an aspect of the present disclosure is shown. The computer device 300 can represent, for example, a single computing device, multiple computing devices, or a distributed computing system. The computer device 300 may be configured as a quantum computer (e.g., a QIP system), a classical computer, or to perform a combination of quantum and classical computing functions, sometimes referred to as hybrid functions or operations. For example, the computer device 300 may be used to process information using quantum algorithms, classical computer data processing operations, or a combination of both. In some cases, the results of one set of operations (e.g., a quantum algorithm) are shared with another set of operations (e.g., classical computer data processing). A typical example of a computer device 300 implemented as a QIP system capable of performing quantum computations and simulations is, for example, the QIP system 200 shown in FIG. 2.

[0026] The computing device 300 may include a processor 310 for performing processing functions related to one or more of the functions described herein. The processor 310 may include one or more sets of processors or multi-core processors. Furthermore, the processor 310 may be implemented as an integrated and / or distributed processing system. The processor 310 may include one or more central processing units (CPUs) 310a, one or more graphics processing units (GPUs) 310b, one or more quantum processing units (QPUs) 310c, one or more intelligence processing units (IPUs) 310d (e.g., artificial intelligence or AI processors), or a combination of some or all of these types of processors. In one aspect, the processor 310 may refer to a general-purpose processor of the computing device 300, and the computing device 300 may also include additional processors 310 for performing further specific functions (e.g., including functions for controlling the operation of the computing device 300).

[0027] The computing device 300 may include a memory 320 for storing instructions executable by the processor 310 to perform operations. The memory 320 may also store data to be processed by the processor 310 and / or data resulting from processing by the processor 310. In one implementation, for example, the memory 320 may correspond to a computer-readable storage medium that stores code or instructions for performing one or more functions or operations. As with the processor 310, the memory 320 may refer to a general-purpose memory of the computing device 300, and the computing device 300 may also include additional memory 320 for storing instructions and / or data for further specific functions.

[0028] It will be appreciated that the processor 310 and memory 320 may be used in connection with various operations of the computing device 300, including, but not limited to, computing, calculation, simulation, control, calibration, system management, and other operations, including methods or processes described herein.

[0029] Additionally, the computing device 300 may include a communications component 330 that utilizes hardware, software, and services to provide for establishing and maintaining communications with one or more entities. The communications component 330 may also be used to communicate between components of the computing device 300 and between the computing device 300 and external devices, such as devices located across a communications network and / or devices serially or locally connected to the computing device 300. For example, the communications component 330 may include one or more buses and may further include transmit and receive chain components associated with transmitters and receivers, respectively, operable to interface with external devices. The communications component 330 may be used to receive updates regarding the operation or functionality of the computing device 300.

[0030] Additionally, computing device 300 may include data store 340, which may be any suitable combination of hardware and / or software that provides mass storage of information, databases, and programs used in connection with the operation of computing device 300 and / or any method or process described herein. For example, data store 340 may be a data repository for operating system 360 (e.g., a classical OS, a quantum OS, or both). In one implementation, data store 340 may include memory 320. In one implementation, processor 310 may execute operating system 360 and / or applications or programs, and memory 320 or data store 340 may store them.

[0031] The computing device 300 may also include a user interface component 350 configured to receive input from a user of the computing device 300 and further configured to generate output for presentation to the user or for provision (directly or indirectly) to a different system. The user interface component 350 may include one or more input devices, including but not limited to a keyboard, a numeric keypad, a mouse, a touch-sensitive display, a digitizer, navigation keys, function keys, a microphone, a voice recognition component, any other mechanism capable of receiving input from a user, or any combination thereof. Additionally, the user interface component 350 may include one or more output devices, including but not limited to a display, a speaker, a haptic feedback mechanism, a printer, any other mechanism capable of presenting output to a user, or any combination thereof. In one implementation, the user interface component 350 may send and / or receive messages corresponding to operations of the operating system 360. When the computing device 300 is implemented as part of a cloud-based infrastructure solution, the user interface component 350 may be used to enable a user of the cloud-based infrastructure solution to remotely interact with the computing device 300.

[0032] FIG. 4 illustrates an example of a QIP system according to an embodiment of the present disclosure. The example QIP system 400 illustrated in FIG. 4 includes a control subsystem 410 that is remotely located with respect to the example QIP system 400 and can receive a quantum program 404 from a computing device 402 that is operatively coupled (e.g., communicatively coupled) to the control subsystem 410. The computing device 402 can transmit data defining the quantum program 404 to the control subsystem 4 for execution in the quantum hardware 420 and applies the error mitigation approach described herein. As indicated by the dashed line, the computing device 402 can be external to the example QIP system 400. For example, the computing device 402 can be a user device (e.g., a classical computer) of an end user of the QIP system 400. The control subsystem 410 can retain the quantum program 404 in one or more memory devices 412. The quantum program 404 corresponds to a defined quantum computation. The defined quantum computation can be, for example, an n-qubit computation. Quantum programs 404 may include quantum circuits (and possibly subcircuits) that represent quantum algorithms associated with quantum computing. Examples of quantum algorithms include variational quantum algorithms, machine learning algorithms, Fourier transform algorithms, etc.

[0033] The control subsystem 410 can be operatively coupled to the quantum hardware 420 via a number of links 414 that enable the exchange of data and / or control signals between the control subsystem 410 and the quantum hardware 420. The quantum hardware 420 can embody or include one or more quantum computers. In some cases, the quantum hardware 420 embodies a cloud-based quantum computer. In other cases, the quantum hardware 420 embodies or includes a local quantum computer. The quantum hardware 420 includes a number of qubits 430 arranged in a particular layout, regardless of their spatial footprint. Each qubit of the qubits 430 can couple to the environment and / or to each other. Such couplings decouple and mitigate the quantum information contained in the qubits. Thus, the quantum hardware 420 can be noisy. The type of the number of links can be based on the type of qubits 430 used by the quantum hardware 420 for computation. In some cases, the number of links 414 can include wired links or optical links, or a combination of both. In other cases, the multiple links 414 may include microwave resonator devices or microwave transmission lines, or a combination of both.

[0034] The qubits 430 may include atomic qubits assembled in atomic traps. Thus, the atomic qubits may be referred to as trapped atomic qubits. In some cases, each of the atomic qubits may be a neutral atom. In other cases, each of the atomic qubits may be an ion, such as an ytterbium ion, a calcium ion, or a similar ion. The atomic qubits in such cases may be confined in an ion trap (e.g., trap 270 (FIG. 2)) and assembled into a linear array (such as a linear crystal or chain 110 (FIG. 1)). In other implementations, the qubits 430 may include one of several types of solid-state devices. Such devices may be embodied, for example, in Josephson junction devices, semiconductor quantum dots, or defects in semiconductor materials (such as vacancies in Si and Ge, or nitrogen vacancy centers in diamond).

[0035] The control subsystem 410 can cause the quantum hardware 420 to execute each of a plurality of execution variants. Such variants are illustrated in FIG. 4 as single-headed open arrows. In response, the control subsystem 410 can receive measurement data 418 indicative of computational output for each of the plurality of execution variants. The measurement data 418 can include a plurality of measurement data sets, each of which is indicative of computational output for a respective one of the plurality of execution variants. A particular execution of a quantum algorithm can be referred to as a "shot," and the control subsystem 410 can cause the quantum hardware 420 to iterate through the plurality of shots for a quantum computation. Thus, the control subsystem can accumulate counts corresponding to one or more measurement results on the qubits 430 as part of the execution of the quantum computation. Because a quantum computation can be performed on more than one qubit, the measurement results can be represented as a bit string that represents a particular target output state given a particular set of qubits involved in the quantum computation. The control subsystem 410 can provide at least a portion of the measurement data 418 to components of the control subsystem 410 and / or other subsystems (e.g., the post-processing subsystem 440).

[0036] The control subsystem 410 may also be operatively coupled to a post-processing subsystem 450 via a communication architecture 440. The communication architecture 440 may include a wired link, a wireless link, a network device (gateway device, server, etc.), or a combination thereof. The post-processing subsystem 450 may apply one or more post-processing techniques to the measurement data 418 received from the quantum hardware 420. By applying such techniques, the post-processing subsystem 450 may generate results 454 of the quantum computations performed by the quantum hardware. The post-processing subsystem 450 may transmit the results 454 (or data indicative of the results 454) to the computing 402 and / or other computing devices 458. The post-processing subsystem 450 may also cause the computing device 402 to present the results 454 in a particular manner. For example, the post-processing subsystem 450 may instruct the computing device 402 to present a user interface that includes the results 454.

[0037] To address noise and other types of errors (e.g., computational errors and miscalibration) in quantum hardware 420, rather than implementing error correction approaches, example QIP system 400 can apply various symmetrization strategies via an error mitigation subsystem formed by at least control subsystem 410 and post-processing subsystem 450. Even without hardware improvements, symmetrization strategies according to aspects of the present disclosure can improve the performance of QC as systematic errors vary between specific symmetric implementations. "Symmetrization," as used herein, refers to the process of creating variant implementations of quantum computing on specific hardware to reduce errors and improve QC performance.

[0038] To implement the symmetrization strategy, in some embodiments, a set of n qubit computations

number

number

number

number

number

number

number

number

number

number

number

number

number

[0039] Without intending to be bound by theory and / or modeling, by distributing quantum computations (e.g., n-qubit computations) across multiple computationally inherent symmetries, the effects of control inaccuracies can be at least partially offset without amplification of random errors. The exemplary QIP system 400 can implement the error mitigation techniques described herein by performing various steps, including, for example: 1. Define the symmetry Γ and the sample Γ'=Γ, 2. Generating circuit variants of Γ'; 3. Running each variant on QC hardware; 4. Aggregating all measurement statistics; Includes:

[0040] It is impractical to use all possible symmetries for a given quantum computation. Therefore, the exemplary QIP system 400 (FIG. 4) can sample from these symmetries. For error-free quantum computation, it is sufficient to use only identity symmetries. Assuming a single imprecision of a known type, very few symmetries may be sufficient, regardless of the size of the imprecision or the number of qubits 430. For example, in some scenarios, even two symmetries (e.g., qubit allocation and gate decomposition) may be sufficient to achieve satisfactory computation performance. As the dimensionality of the error space increases, more symmetries are likely to be sampled. The symmetry γ is

number

[0041] With respect to the sampling or selection of computationally intrinsic symmetries, uniformly random selection provides a computationally scalable sampling method in that a memory of all previously selected symmetries is not required to select the next symmetry γ. The k uniformly random symmetries are γ A uniformly random set of

number

[0042] Furthermore, the exemplary QIP system 400 (FIG. 4) can divide a given number of runs of a quantum circuit into batches, each batch being executed using a different realization (or variant implementation) that, by symmetry, should give the same result in the absence of inaccuracies. To aggregate the measurement datasets of the symmetrized runs, the exemplary QIP system 400 can apply a defined aggregation process to the measurement data 418 received from the quantum hardware 420. The aggregation process can include one of a linear aggregation process or a non-linear aggregation process. An example of a linear aggregation process is component-wise averaging. Examples of non-linear aggregation processes include weighted component-wise averaging, plurality voting, and weighted plurality voting. Applying the defined aggregation process to the measurement data 418 can provide strong performance improvements in commercial QC. In some implementations, the aggregation process includes component-wise averaging of frequencies in a given histogram showing the distribution of the computational output of each variant implementation. This is suitable for computations that have few or no zeros in the ideal probability distribution, such as VQE circuits or quantum machine learning (QML) circuits. Solely by way of example, panel (b) of Fig. 7 shows vectors representing the difference between the histograms of each variant and the ideal histogram. With proper sampling symmetry, these vectors cancel out and their sum converges to the ideal histogram / outcome as the number of variants increases. Component-wise averaging cannot recover the zero frequency in the ideal output distribution. Note that while averaging is related to the set combining operation, the union operation suggests a different aggregation method. That is, a voting-based aggregation process can filter out the low-frequency output and recover the zero frequency.

[0043] Aggregation by component-wise averaging is robust to any type of measurement statistics. As described herein, applying component-wise averaging can provide a factor of two in improving the fidelity of QML and VQE algorithms that generate a small number of low-frequency outputs.

[0044] In addition, or in other implementations, the aggregation process includes a majority vote. To apply such an aggregation process, the measurement data indicative of the computational output for each circuit variant defines a set of bit strings, one bit string per shot. Since each variant has the same number of shots, each shot can be represented by the same number of variant bit strings (see FIG. 6, panel (c) for an illustration). The winning bit string can be determined by a majority vote that further exceeds a defined voting threshold. Since the order of the bit strings does not matter, the per-shot voting is repeated many times for the scrambled order of the bit strings in each variant. The scrambling of the ordering generates different combinations of bit strings among the variants. If no winning bit string is found, the defined threshold can be reduced by 1. If no winning bit string exists for the defined threshold 2, the exemplary QIP system 400 can provide a per-component average of the variant histogram as a result of the quantum computation, which can be a common implementation for spread-out distributions and / or when the available samples lack statistical significance. After accumulating the counts from all winning bitstrings, the final histogram can be normalized. The defined voting threshold can be determined by training runs of a given QC architecture. Training runs performed on a set of circuits with known outputs also help determine the optimal number of variants, iterations, gate decompositions, etc. These hyperparameters are then used for multiple circuits.

[0045] By applying majority voting, up to 100 times performance improvement can be achieved for a 20 qubit commercial QC based on trapped atom qubits. Although not intending to be bound by theory and / or simulations, due to the nonlinearity of voting, majority voting can be a stable aggregation strategy for ideal output probabilities with l equally probable outputs and rl zero frequencies. That is, majority voting can be stable for this measurement statistic with at least one zero frequency output, and the output result is encoded in a small set of target output states. Whether the set of target output states is small or not is determined by the size of the Hilbert space associated with the qubits involved in the quantum computation and the number of measurements. For example, for a circuit on a 20 qubit QC, the set of 16 target output states is a small set. Yet, that same set is not small for a circuit on a 4 qubit, given that the 16 target output states span the entire Hilbert space for 4 qubits. Related quantum circuits include, for example, QFT-based adders, phase and amplitude estimation algorithms, and some Monte Carlo algorithms.

[0046] Note that for aggregation, the runtime and memory complexity may depend on the number of observed output states, not on the number of all possible states. In the case of component-wise averaging, the post-processing involved in aggregation involves simple or weighted merging of output counts (zero frequency is implicit). Majority voting can be performed on small groups of outputs, and thus the post-processing involved does not require significant memory. For example, memory usage does not exceed the size of all measured data plus the output results.

[0047] The control subsystem 410, the post-processing subsystem 450, and the communication architecture 440 may include one or more computing devices that may form an error mitigation subsystem. The error mitigation subsystem may include various computing resources that may host and execute one or more modules for executing the quantum program 404 in the quantum hardware 420 via the qubits 430 in accordance with aspects of the present disclosure. FIG. 5A presents an example of an error mitigation subsystem, purely by way of example. In some cases, the error mitigation subsystem 500 shown in FIG. 5A may be hosted by the computing device 300 (FIG. 3) or a system of computing devices having the architecture of the computing device 300. In other cases, the error mitigation subsystem 500 shown in FIG. 5A may be embodied in or hosted by the computing system 580 shown in FIG. 5B.

[0048] By way of example only, the error mitigation subsystem 500 can implement a symmetrization strategy according to aspects of the present disclosure. The error mitigation subsystem 500 can include an ingestion module 510 that can receive a quantum program 404 (FIG. 4). As discussed above, the quantum program 404 can include one or more quantum circuits that represent quantum algorithms, such as variational algorithms (e.g., VQE algorithms), Fourier transforms, machine learning algorithms, etc.

[0049] The error mitigation subsystem 500 may include a compilation module 520 that may compile the quantum program 404. As a result, the compilation module 520 may generate a quantum circuit. To compile the quantum program 404, the compilation module 520 may apply one or more optimizations.

[0050] The error mitigation subsystem 500 can include a symmetrization module 530 that can generate multiple execution variants (possibly including circuit variants) with the quantum circuit. To do so, the multiple execution variants can apply one or more computation-specific symmetries to the quantum circuit. As described herein, in some cases, rather than using a complete set of computation-specific symmetries, the symmetrization module 530 can include or use a symmetry selector component 534 that can sample the complete set of computation-specific symmetries. In this manner, the symmetry selector component 534 can select (or otherwise identify) at least one computation-specific symmetry from the complete set of computation-specific symmetries. Such a set can include at least one of qubit allocation, gate decomposition, permutation of commutative gates, addition of gates that hold defined states or modification of one or more gates, and measurements compensated by one or more modifications in post-processing.

[0051] The error mitigation subsystem 500 may include or be operatively coupled to a job execution module 540 that may cause the quantum hardware 420 (FIG. 4) to execute each of a plurality of execution variants. Such variants are shown as hollow arrows in both FIGS. 4 and 5A. The plurality of links 414 are represented by a single double-headed hollow arrow. In response to executing the execution of the plurality of execution variants, the job execution module 540 may receive measurement data (e.g., measurement data 418 (FIG. 4)) indicative of computational output for each of the plurality of execution variants. The measurement data may include a plurality of measurement data sets, each measurement data set indicative of computational output for a respective execution variant of the plurality of execution variants.

[0052] The error mitigation subsystem 500 can include an aggregation module 550 that can determine a result (e.g., being result 454 (FIG. 4)) of a defined quantum computation (e.g., an n-qubit computation) corresponding to the quantum program 404. To do so, the aggregation module 550 can aggregate multiple measurement data sets by applying an aggregation process (e.g., component-wise averaging or relative majority voting). In this manner, errors in the results of the defined computation can be mitigated, as described herein. The aggregation module 550 can persist the results in one or more memory devices 570 (referred to as memory 570).

[0053] The error mitigation subsystem 500 can include a reporting module 560 that can cause a computing device (e.g., computing device 402 (FIG. 4)) to provide the results. The computing device can be located remotely relative to the error mitigation subsystem 500. Providing the results can include displaying a user interface that includes one or more indicia representative of the results.

[0054] As previously mentioned, the error mitigation subsystem 500 can be embodied in or hosted by a computing system 580 shown in FIG. 5B. Thus, the computing system 580 can perform error mitigation based on computational symmetry in accordance with aspects described herein. The computing system 580 can include at least one processor 590 and at least one memory device 598 (referred to as memory 598). In some embodiments, the processor 590 can be located on a single computing device (e.g., a blade server device or another type of server device). In other embodiments, the processor 590 can be distributed across two or more computing devices (e.g., multiple blade server devices or other types of server devices).

[0055] The processor 590 may be operatively coupled to the memory 598 via, for example, one or more communication interfaces 594. The communication interface 594 may be appropriate for the particular configuration (localized or distributed) of the processor 590. In some embodiments, the communication interface 594 may include one or more bus architectures for communication of data and / or control signals. Examples of bus architectures include an Ethernet-based industrial bus, a Controller Area Network (CAN) bus, Modbus, other types of field bus architectures, etc. Additionally, or in other embodiments, the communication interface may include a wireless network and / or a wired network having a respective footprint.

[0056] The memory 598 can hold or otherwise store therein machine-accessible components (e.g., computer-readable and / or computer-executable components) and data according to the present disclosure. Thus, in some embodiments, machine-accessible instructions (e.g., computer-readable and / or computer-executable instructions) embody or otherwise configure each of the machine-accessible components in the memory 598. The machine-accessible instructions can be encoded in the memory 598 and configured to form each of the machine-accessible components. The machine-accessible instructions can be constructed (e.g., linked and compiled) and held in computer-executable form in the memory 598 or in one or more other machine-accessible non-transitory storage media. Specifically, as shown in FIG. 5B, in some embodiments, the machine-accessible components include an ingestion module 510, a compilation module 520, a symmetrization module 530, a job execution module 540, an aggregation module 550, and a reporting module 560. The memory 598 may also include data (not shown in FIG. 5B) that enables various of the functions described herein. The memory 598 may optionally include memory 570 (FIG. 5A). In some cases, the symmetrization module 530 may include a symmetry selector 534 and a variant generator 538. In some cases, the memory 930 may hold definitions of computational symmetries. Such definitions may be used to sample (or select) particular computational symmetries for symmetrization of quantum computations according to aspects described herein.

[0057] The machine-accessible components may be accessed and executed by at least one of the processors 590, either individually or in certain combinations. In response to execution, each of the machine-accessible components may provide functionality described herein in connection with the use of computational symmetries for error mitigation in quantum computing. Thus, execution of the machine-accessible components retained in memory 598 may cause the error mitigation subsystem 500 to operate in accordance with aspects described herein. More specifically, at least one of the processors 590 may execute the machine-accessible components to cause the error mitigation subsystem 500 to use computational symmetries for error mitigation in quantum computing in accordance with aspects of the present disclosure.

[0058] 5(B), computing system 580 may also include other types of computing resources that may enable or otherwise facilitate execution of the machine-accessible components retained in memory 598. These computing resources may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), memory, disk space, incoming and / or outgoing bandwidth, interfaces (such as I / O interfaces); controller devices; power supplies, etc. For example, memory 598 may also include programming interfaces (such as APIs), operating systems, software for configuring and / or controlling a virtualization environment, firmware, etc.

[0059] FIG. 6 illustrates a schematic of an exemplary implementation of an error mitigation approach according to an embodiment of the present disclosure. Such an implementation may be referred to as a symmetrization circuit implementation, and includes splitting the implementation into symmetrization variants represented by different qubit allocations, as shown in panel (a). The symmetrization circuit implementation also includes measuring each result affected by an individual inaccuracy, as shown in panel (b). The symmetrization circuit implementation also includes aggregate measurement statistics, as shown in panel (c). As applied by the exemplary QIP system 400 (FIG. 4), the symmetrization circuit implementation can also allow a device (such as a user device) to present a comparison of the difference between the averaged result and the result obtained through the relative majority vote. Such a comparison is shown in panel (d) of FIG. 6.

[0060] More specifically, first, for each qubit pair of the four selected qubit pairs, the execution variant is

number

[0061] Without intending to be bound by theory and / or modeling, the error mitigation approach, i.e., symmetrization approach, of the present disclosure is effective for at least the following reasons:

number

number

[0062] Furthermore, to mitigate the impact of inaccuracies,

number

number

number

number

number

[0063] In addition, all

number

number

number

number

number

number

[0064] The term δh in equation (2) Γ-inv can capture the effect of the remaining full depolarization error channel, i.e., the incoherent error. This residual error is, for example, ε<1-l / 2 n In the case of h, which has l output states at frequency l / 1, u can be reduced using aggregation techniques such as majority voting.

[0065] Furthermore, as a concrete example, the effect of symmetrization is shown in a four-qubit circuit (on eight trapped-ion qubits) with six two-qubit gates on different qubit pairs and random single-qubit gates mapped to eight ions. Gate miscalibration is modeled as a random under-rotation of multiple two-qubit gates fixed per qubit pair. An average under-rotation across all qubit pairs is assumed that induces similar errors for all variants, as shown in panel (a) of Figure 7. The symmetry Γ is represented by eight random qubit assignments γ. For each qubit assignment, the vector h u +δh γ-inv +δh γ To obtain, we simulated the corresponding inaccurate realizations. Specifically, in FIG. 7, panel (a) shows the use of qubit remapping as a symmetry, and panel (b) shows the combined use of qubit remapping and gate twirling. In panels (a) and (b), similar quantum circuit blocks are contrasted. Circles with dark grey sectors mark under-rotated gates, and circles with light grey sectors mark over-rotated gates. The dark grey sectors are tilted in one direction, and the light grey sectors are tilted in another direction. As shown in FIG. 7, all gates are under-rotated. Individual output errors are shown for simulations of eight mappings of a random circuit on eight qubits with under-rotation specified for each two qubit gate.

[0066] Figure 7 shows the ideal, individual, and symmetrized 256-dimensional vectors of the results, sorted by their two largest principal components (first, we perform a principal component analysis (PCA) on δh γ-inv +δh γThe charts 710 and 760 show the error after aggregation in the space of the first two principal components of the deviation from the ideal histogram for the biased (panel (a)) or symmetrized (panel (b)) imprecision. In the first case, the variant does not symmetrize the error since it is only exploring the qubit allocation symmetry, since all gates are under-rotated on average by some amount. Hence, the effect of the error δh Γ-inv remains after aggregation, as shown in chart 710. In the second case, shown in chart 760, an additional symmetry in the gate decomposition is introduced: δh Γ-inv is used to make the fully entangled XX gate zero. The effect of under-rotation in the fully entangled XX gate is -1 This is addressed by using an alternative implementation that combines the gate with a pair of X-gates, thus implementing the same ideal unitary, but which reverses the effect of under-rotation.

[0067] In this disclosure, an aggregation strategy for measurement statistics is a process that combines measurement statics from multiple implementations of the same computation. In the absence of errors, all implementations should produce identical statistics in the limit (at infinite iteration counts). An aggregation strategy is considered stable for a given type of statistics and produces another copy given a set of identical statistics of this type. Aggregation by component-wise averaging is very stable for any type of statistics. Yet aggregation by voting is not. This can be seen for the probability distribution (1-ε,ε) where voting-based aggregation approaches (1,0) for ε<1 / 2. While not intending to be bound by inferences and / or interpretations, what makes an aggregation strategy useful is (i) forcing any statistic to a statistic of a desired type and (ii) distilling the original statistic from multiple erroneous variants of the original. To this end, output probability distributions are analytically characterized for many quantum algorithms, including Shor and Grover's algorithm. The choice of aggregation can be determined by the type of output probability distribution of a given quantum algorithm.

[0068] For best performance, aggregation by majority voting can be used for quantum algorithms with ideal measurement statistics, including l outputs with frequency 1 / l. Such quantum algorithms have a zero-frequency output and a subset of target outputs that need to be determined. For quantum algorithms with different measurement statistics, aggregation by averaging can be used instead. By using aggregation by averaging, distortions can be avoided.

[0069] The impact of symmetrization and the choice of aggregation strategy are also experimentally verified herein by comparing the results of the desymmetrized computation with the symmetrized computation by component-wise averaging and relative majority voting. The experiment was carried out on a quantum computer configured to utilize 20 individually addressable qubits. More specifically, the quantum computer is a trapped ion quantum computer utilizing trapped ytterbium ions that are individually addressed by pulses of 355 nm light. These pulses can be designed to generate both Mφlmer-Sφlensen entangling gates between ions as well as single qubit rotations / gates. The quantum computer uses 22 such ions as qubits to perform quantum information processing. In this disclosure, the experiment was divided into 25 different maps (variants) between physical qubits and computational qubits, and 100 experimental shots were performed for each variant, resulting in a total of 2500 experimental iterations. For circuits on more than six qubits, permutations on the set of physical qubits were generated. Otherwise, two additional physical qubits were utilized to increase the number of diverse mappings. All variants were measured under similar conditions. To that end, for most experiments, computational jobs were run within one calibration cycle. In situations where running within a single calibration cycle was not feasible (e.g., due to ion chain losses), calibration parameters were carefully replicated.

[0070] Quantum computer performance is the statistical overlap between the actual output statistics pi and the ideal outcome qi.

number

[0071] The effect of symmetrization is demonstrated in a 13-qubit single-output QFT-based adder circuit. In panel (a) of Figure 8, 13 The largest output probability of is compared between the desymmetrized histogram, the component-averaged symmetric histogram, and the majority voted symmetric histogram. The first largest value corresponds to a bit string with ideal probability 1, and the rest should have output probability 0. The squares show the desymmetrized results using a single realization with 2500 replicate measurements (the total number of experiments is the same in all three cases). The diamonds represent a symmetrization of this run with 25 realizations per variant and 100 replicates, aggregated with component-wise averaging. The circles use the same realizations as the diamonds, but the symmetrized histograms are generated with majority voting. Panel (b) of Figure 8 shows the evolution of the error bars with the number of shots per variant. In this case, the symmetrized results continue to improve up to about 80 replicates per variant. From Figure 8, it can be seen that symmetrization with component-wise averaging does not improve the probability of the target bit string, but reduces the next largest probability, which allows for a dramatic increase in the probability of the target state after multiple votes (from about 1.5% to about 95%). As mismatched results between variants are filtered out, the probability of the target outcome is boosted. For a 15-qubit QFT-based adder, the improvement is over two orders of magnitude.

[0072] The impact of symmetrization on the performance of other computations can also be evaluated. For example, the impact of symmetrization on performance for several use cases is shown in FIG. 9, where panel (a) shows the performance of an algorithm with one output state (quantum Fourier transform-based adder, phase estimation, and amplitude estimation), panel (b) shows the performance of an algorithm with four output states (amplitude estimation and Monte Carlo sampling), and panel (c) shows the performance of algorithms with multiple output states (variational quantum eigensolver and quantum machine learning). Performance is represented by Hellinger fidelity, a metric shown in FIG. 9 as a function of circuit depth, expressed in number of two-qubit (2Q) Mφlmer-Sφlensen gates. The results of desymmetrization and symmetrization are shown for the same set of experiments, each consisting of 25 realizations with 100 iterations per variant. The desymmetrization fidelity is calculated as the average over the 25 individual fidelities of each variant. Thus, for algorithms with one output state, the asymmetric fidelity exactly matches the aggregated symmetrization results with component-wise averaging in panel (a).

[0073] More specifically, every job was shot 2500 times with output probability distributions that vary in the number of correct output states with nonzero probability, and therefore benefit differently from different aggregation strategies. In chart 910, the results of a QFT-based adder with a single output state, phase estimation, and amplitude estimation are shown. Symmetrization by majority voting (represented by the black circles) improves F H It can be seen that symmetrization by component-wise averaging (represented by diamonds) shows no improvement, while symmetrization by component-wise averaging (represented by diamonds) shows no improvement. In chart 930, the results of the amplitude estimation and Monte Carlo sampling circuits are compared before tracking the ancillary qubits. Symmetrization by majority voting (represented by black circles) still increases F Hsymmetrization by component-wise averaging (represented by diamonds) also balances the error across the four target states, so is better than desymmetrization (represented by squares). Chart 950 compares symmetrization for VQE and QML circuits. Such circuits have a wider irregular output probability distribution, so symmetrization by component-wise averaging (represented by diamonds) shows the best improvement, but symmetrization by majority voting (represented by circles) may skew the results. Circuits with more peaked output probability distributions can often benefit more from aggregation by majority voting.

[0074] Figure 10 shows the effect of symmetrization on a 4-qubit random circuit (shown in diagram 1010) with eight implementations that vary the qubit assignment to the eight ions (shown in diagram 1060, qubit assignments represented by grey circles). Gate miscalibration is modeled as a random under-rotation of multiple 2-qubit gates fixed per trapped ion pair. We assume an average under-rotation across all qubit pairs that causes similar errors for all variants (see Figure 7, panel (a)). The symmetry Γ is represented by eight random qubit assignments γ. For each qubit assignment, a vector h u +δh γ-inv +δh γ To obtain, we simulate the corresponding inexact realization.

[0075] In the first case (see panel (a) of FIG. 7), the qubit allocation varies between implementations (see diagram 1060), and in the other case (see panel (b) of FIG. 7), every fourth XX gate is a phase-flipped XX with a pair of X gates. -1 gate, thus implementing the same ideal unitary, but reversing the effect of underrotation (see panel (b) of Figure 7).

[0076] 11 illustrates an example of a computer-implemented method for implementing quantum computing using computational symmetry-based error mitigation techniques in accordance with one or more aspects of the present disclosure. A computing device or a system of computing devices may at least partially implement the exemplary computer-implemented method 1100 illustrated in FIG. 11. Implementing the computer-implemented method 1100 may include, for example, compiling and / or executing one or more of the blocks included in the computer-implemented method 1100. To that end, each computing device may include one or more processors, one or more memory devices, other types of computing resources (communication interfaces, bus architectures, etc.), combinations thereof, or similar resources.

[0077] In some cases, a computing system may at least partially implement the exemplary computer-implemented method 1100. The computing system may host the ingestion module 510, the compilation module 520, the symmetrization module 530, the job execution module 540, the aggregation module 550, and the reporting module 560. The computing system may perform the exemplary method 1100 by executing at least one of such modules. In one example, the computing system may be embodied in or comprise an error mitigation subsystem 500 according to various aspects described herein.

[0078] At block 1110, the computing system may receive or otherwise obtain, e.g., a quantum program corresponding to a defined quantum computation via ingestion module 510 (FIG. 5A). The defined quantum computation may be an n-qubit computation. The quantum program may include one or more quantum circuits that represent a quantum algorithm, such as a variational quantum algorithm.

[0079] At block 1120, the computing system may generate a quantum circuit by compiling the quantum program.

[0080] At block 1130, the computing system may generate multiple execution variants of the quantum circuit by applying one or more symmetries to the quantum circuit. As described herein, each symmetry of the one or more symmetries may be a computational symmetry (e.g., a computation-specific symmetry). Thus, in some cases, to generate the multiple execution variants, the computing system may select one or more symmetries from a set of computation-specific symmetries. Such a set may include at least one of measurements compensated by qubit allocation, gate decomposition, permutation of commutative gates, addition of gates that preserve defined states, or modification of one or more gates, and one or more modifications in post-processing. In some cases, selecting the one or more symmetries may include selecting a first symmetry and a second symmetry from the set of computation-specific symmetries, where the first symmetry and the second symmetry may reduce error correlation between the respective resulting execution variants. In one example, the computing system may select a particular symmetry from the set of computation-specific symmetries by, in some cases, executing symmetry selector 534 (FIG. 5A).

[0081] At block 1140, the computing system can cause quantum hardware (e.g., quantum hardware 420 (FIG. 4)) to execute each of the multiple execution variants. As described herein, in some cases, the quantum hardware can include multiple trapped atom qubits that are individually addressable by a continuous wave laser beam. In other cases, the quantum hardware can include multiple superconducting qubits that are individually addressable by microwave electromagnetic radiation.

[0082] At block 1150, the computing system may receive measurement data indicative of computational output for each of the plurality of execution variants. The measurement data includes a plurality of measurement data sets, each measurement data set indicative of computational output for a respective execution variant of the plurality of execution variants. The computing system may receive the measurement data via, for example, job execution module 540 (FIG. 5A).

[0083] At block 1160, the computing system may determine a result of the defined quantum computation (e.g., an n-qubit computation) by aggregating the multiple measurement data sets. In this manner, errors in the results of the defined computation may be mitigated, as described herein. The computing system may determine the result in such a manner, for example, via aggregation module 540 (FIG. 5A). In some cases, aggregating the multiple measurement data sets may include selecting an aggregation process for combining the multiple measurement data sets based on an output probability distribution corresponding to the defined computation. Additionally, or in other cases, aggregating the multiple measurement data sets may also include applying an aggregation process to the multiple measurement data sets. The aggregation process includes one of a linear aggregation process or a non-linear aggregation process. An example of a linear aggregation process is component-wise averaging. Examples of non-linear aggregation processes include weighted component-wise averaging, majority voting, and weighted majority voting. The multiple measurement data sets may define multiple sequences of bit strings. Thus, in some implementations, applying component-wise averaging may include determining an average number of occurrences for each bit string in the multiple sequences of bit strings over the multiple sequences of bit strings. In weighted component-wise averaging, the average number of occurrences for each bitstring can be obtained by assigning a weighting factor to each execution variant and weighting the number of occurrences for the execution variant using the weighting factor. In other implementations, applying the majority vote can include determining particular bitstrings that exhibit a number of occurrences that exceeds a defined threshold number across multiple sequences of bitstrings. In weighted majority voting, the number of occurrences for the execution variants can also be weighted according to the weighting factor for the respective execution variant.

[0084] At block 1170, the computing system may, for example, have a computing device provide the results via reporting module 560. The computing device may be located remotely relative to the computing system. For example, the computing device may be computing device 402 (FIG. 4). Providing the results may include displaying a user interface that includes one or more indicia representative of the results. The computing system may determine the results in such a manner, for example, via aggregation module 540 (FIG. 5A).

[0085] Numerous other aspects will become apparent from the foregoing detailed description and the accompanying drawings. These aspects are expressed by the following clauses.

[0086] Clause 1 includes a computer-implemented method including: generating a quantum circuit by compiling a quantum program corresponding to a defined quantum computation; generating a plurality of execution variants of the quantum circuit by applying a first symmetry of one or more symmetries to the quantum circuit; executing each of the plurality of execution variants on quantum hardware; receiving a plurality of measurement datasets indicative of computational outputs for each of the plurality of execution variants; and determining a result of the defined quantum computation by aggregating the plurality of measurement datasets.

[0087] Clause 2 includes clause 1, further including causing a computing device to provide the result.

[0088] Clause 3 includes any of the preceding clauses 1 or 2, and further includes selecting the one or more symmetries from a set of computationally intrinsic symmetries corresponding to the defined quantum computation.

[0089] Clause 4 includes any one of the preceding clauses 1-3, and wherein the selecting step includes selecting a first symmetry and a second symmetry from the set of computationally intrinsic symmetries, the first symmetry and the second symmetry reducing error correlation between respective resulting execution variants.

[0090] Clause 5 includes any one of preceding clauses 1 to 4, wherein aggregating the multiple measurement data sets includes selecting an aggregation process for combining the multiple measurement data sets based on an output probability distribution corresponding to the defined calculation, and applying the aggregation process to the multiple measurement data sets.

[0091] Clause 6 includes any one of clauses 1 to 5 preceding clauses, wherein the aggregation process includes component-wise averaging.

[0092] Clause 7 includes any one of the preceding clauses 1 to 6, wherein the plurality of measurement data sets defines a plurality of sequences of bit strings, and wherein applying the component-wise averaging includes determining, across the plurality of sequences of bit strings, an average number of occurrences for each bit string in the plurality of sequences of bit strings.

[0093] Clause 8 includes any one of clauses 1 to 7 preceding clauses, and the aggregation process includes a relative majority vote.

[0094] Clause 9 includes any one of the preceding clauses 1 to 8, wherein the plurality of measurement data sets defines a plurality of sequences of bit strings, and applying the relative majority voting includes determining particular bit strings that exhibit a number of occurrences exceeding a defined threshold number across the plurality of sequences of bit strings.

[0095] Clause 10 includes any one of the preceding clauses 1-9, including at least one of qubit allocation, gate decomposition, permutation of commutative gates, adding gates that hold defined states or modifying one or more gates, and measurements compensated by one or more modifications in post-processing.

[0096] Clause 11 includes a computing system including at least one processor and at least one memory device storing processor-executable instructions, the at least one memory device causing the computing system to perform at least the following steps in response to the processor-executable instructions being executed by the at least one processor: generating a quantum circuit by compiling a quantum program corresponding to a defined quantum computation; generating a plurality of execution variants of the quantum circuit by applying a first of one or more symmetries to the quantum circuit; causing quantum hardware to execute each of the plurality of execution variants; receiving a plurality of measurement datasets indicative of computational outputs for each of the plurality of circuit variants; and determining a result of the defined quantum computation by aggregating the plurality of measurement datasets.

[0097] Clause 12 includes clause 11 and also includes the at least one memory device storing further processor-executable instructions, and in response to the further processor-executable instructions being executed, further causing the at least one processor to provide the result to a computing device.

[0098] Clause 13 includes any of clauses 11 or 12, wherein the at least one memory device stores further processor-executable instructions, and in response to executing the further processor-executable instructions, further causes the at least one processor to select the one or more symmetries from a set of computationally intrinsic symmetries corresponding to the defined quantum computation.

[0099] Clause 14 includes any one of the preceding clauses 1 to 13, and wherein aggregating the multiple measurement data sets includes selecting an aggregation process for combining the multiple measurement data sets based on output probability distributions corresponding to the defined calculations, and applying the aggregation process to the multiple measurement data sets.

[0100] Clause 15 includes any one of the preceding clauses 1 to 14, wherein the aggregation process includes either component-wise averaging or majority voting.

[0101] Clause 16 includes a quantum information processing (QIP) system including at least one processor and at least one memory device storing processor-executable instructions that, in response to being executed by the at least one processor, cause the QIP system to: generate a quantum circuit by compiling a quantum program corresponding to a defined quantum computation; generate a plurality of execution variants of the quantum circuit by applying a first of one or more symmetries to the quantum circuit; cause quantum hardware to execute each of the plurality of execution variants; receive a plurality of measurement data sets indicative of computational outputs for each of the plurality of circuit variants; and determine a result of the defined quantum computation by aggregating the plurality of measurement data sets.

[0102] Clause 17 includes clause 16, wherein the at least one memory device stores further processor-executable instructions that, in response to being executed, further cause the at least one processor to provide the result to a computing device.

[0103] Clause 18 includes any of clause 16 or clause 17, and wherein aggregating the multiple measurement data sets includes selecting an aggregation process for combining the multiple measurement data sets based on an output probability distribution corresponding to the defined calculation, the aggregation process comprising one of a linear aggregation process or a non-linear aggregation process, and applying the aggregation process to the multiple measurement data sets.

[0104] Clause 19 includes any one of clauses 16-18 preceding clauses, wherein the quantum hardware comprises a plurality of trapped atom qubits individually addressable by a continuous wave laser beam.

[0105] Clause 20 includes any one of clauses 16-19 preceding clauses, wherein the quantum hardware comprises a plurality of superconducting qubits individually addressable by microwave electromagnetic radiation.

[0106] Various aspects of the disclosure may take the form of wholly or partially hardware aspects, wholly or partially software aspects, or a combination of software and hardware. Additionally, as described herein, various aspects of the disclosure (e.g., systems and methods) may take the form of a computer program product comprising a computer-readable non-transitory storage medium having computer-accessible instructions (e.g., computer-readable and / or computer-executable instructions), such as computer software, encoded or otherwise embodied in such storage medium. These instructions may be read or otherwise accessed and executed by one or more processors to perform or enable the performance of operations described herein. The instructions may be provided in any suitable form, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, assembler code, combinations of the foregoing, etc. Any suitable computer-readable non-transitory storage medium may be utilized to form a computer program product. For example, a computer-readable medium may include any tangible non-transitory medium for storing information in a form readable or otherwise accessible by one or more computers or processors operatively coupled thereto. The non-transitory storage medium may include read-only memory (ROM), random access memory (RAM), magnetic disk storage medium, optical storage medium, flash memory, and the like.

[0107] Aspects of the disclosure are described herein with reference to block diagrams and flowchart illustrations of methods, systems, devices, and computer program products. It should be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, may be implemented by computer-accessible instructions. In particular implementations, the computer-accessible instructions may be loaded or otherwise incorporated into a general-purpose computer, a special-purpose computer, or another programmable information processing device to generate a particular machine, such that an operation or function specified in one or more blocks of the flowchart may be implemented in response to execution on the computer or processing device.

[0108] Unless otherwise expressly stated, no protocol, procedure, process, or method described herein is intended to be interpreted as requiring that its acts or steps be performed in a particular order. Thus, if a process or method claim does not in fact recite an order in which its acts or steps should be followed, or if the claims or description of this disclosure are not otherwise specifically recited that the steps should be limited to a particular order, no order is intended to be inferred in any respect. This applies to all possible non-express bases for interpretation, including matters of logic regarding the sequence of steps or operational flow, the plain meaning derived from grammatical organization or punctuation, the number or type of aspects described in the specification or accompanying drawings, etc.

[0109] As used in this disclosure, including the accompanying drawings, terms such as "component," "module," "system," and the like, are intended to refer to computer-related entities or entities related to a device having one or more specific functions. An entity may be either hardware, a combination of hardware and software, software, or software in execution. One or more of such entities may also be referred to as a "functional element." By way of example, a component may be a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. For example, both an application running on a server or a network controller and the server or network controller may be components. One or more components may reside within a process and / or thread of execution, and the components may be localized on one computer and / or distributed among two or more computers. Also, these components may execute from various computer-readable media having various data structures stored thereon. The components may communicate via local and / or remote processes, such as according to signals having one or more data packets (e.g., data from one component interacting with another component in a local system, a distributed system via signals, and / or interacting with another system via a network such as the Internet). As another example, a component can be a device with particular functionality provided by mechanical parts operated by electrical or electronic circuitry, where the parts can be controlled or otherwise operated by program code executed by a processor. As yet another example, a component can be a device that provides particular functionality through electronic components without mechanical parts, where the electronic components can include a processor for executing program code that provides at least part of the functionality of the electronic components. As yet another example, an interface can include an I / O component or an application programming interface (API) component.Although the above examples are directed to component aspects, the illustrated aspects or features also apply to systems, modules, and the like.

[0110] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X uses A or B" is intended to mean any of the natural inclusive permutations. That is, if X uses A, if X uses B, or if X uses both A and B, then "X uses A or B" is satisfied under any of the foregoing examples. Furthermore, the articles "a" and "an," as used in this specification and the accompanying drawings, should be construed to mean "one or more" unless otherwise specified or clear from the context that the singular form is intended.

[0111] Moreover, the terms "example" and "such" are utilized herein to mean serving as an example or illustration. Any aspect or design described herein as an "example" or referred to in conjunction with the phrase "such" should not necessarily be construed as preferred or advantageous over other aspects or designs described herein. Rather, use of the terms "example" or "such" is intended to present a concept in a concrete manner. Terms such as "first," "second," "third," and the like, when used in the claims and description, are for clarity only and do not necessarily suggest or imply any order in time or space, unless otherwise clear from the context.

[0112] The term "processor" as used in this disclosure may refer to any computing processing unit or device that includes processing circuitry that can operate on data and / or signaling. The computing processing unit or device may include, for example, a single-core processor, a single processor with software multi-threaded execution capability, a multi-core processor, a multi-core processor with software multi-threaded execution capability, a multi-core processor with hardware multi-threading technology, a parallel platform, and a parallel platform with distributed shared memory. Furthermore, the processor may include an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a combinatorial programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. In some cases, the processor may utilize nanoscale architectures, such as molecular and quantum dot-based transistors, switches, and gates, to optimize space usage or improve the performance of the user equipment. The processor may also be implemented as a combination of computing processing units.

[0113] Additionally, terms such as "store," "data store," "data storage," "database," and substantially any other information storage component associated with the operation and functionality of a component refer to a "memory component," i.e., an entity incorporated in "memory" or a component that constitutes memory. It will be understood that the memory components described herein can be either volatile memory or non-volatile memory, or can include both volatile and non-volatile memory. Additionally, memory components can be removable or attached to a functional element (e.g., device, server).

[0114] By way of example only, non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which acts as external cache memory. By way of example, and not limitation, RAM is available in many forms, including synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), SyncLink DRAM (SLDRAM), and direct Rambus RAM (DRRAM®). Additionally, the disclosed memory components of the systems or methods herein are intended to comprise, but are not limited to, these and any other suitable types of memory.

[0115] Various aspects described herein may be implemented as a method, apparatus, or article of manufacture using standard programming and / or engineering techniques. Moreover, various aspects disclosed herein may also be implemented by program modules or other types of computer program instructions stored in a memory device and executed by a processor, or other combination of hardware, software, or hardware and firmware. Such program modules or computer program instructions may be loaded onto a general purpose computer, special purpose computer, or another type of programmable data processing apparatus to produce a machine, such that the instructions, executed on the computer or other programmable data processing apparatus, generate means for implementing the functions disclosed herein.

[0116] The term "article of manufacture" as used herein is intended to include a computer program accessible from any computer-readable device, carrier, or media. For example, computer-readable media can include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips, etc.), optical disks (e.g., compact disks (CDs), digital versatile disks (DVDs), Blu-ray disks (BDs), etc.), smart cards, and flash memory devices (e.g., cards, sticks, key drives, etc.).

[0117] The detailed description set forth herein in connection with the accompanying drawings is intended as a description of various configurations or implementations and is not intended to represent the only configurations or implementations in which the concepts described herein may be practiced. The detailed description includes specific details to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details or with variations of these specific details. In some instances, well-known components are shown in block diagram form, and some blocks may represent one or more well-known components.

[0118] The preceding description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the common principles defined herein can be applied to other variations without departing from the scope of the disclosure. Furthermore, although elements of the described aspects may be described or claimed in the singular, the plural is also contemplated unless limitation to the singular is expressly stated. Furthermore, unless otherwise stated, all or a portion of any aspect can be utilized with all or a portion of any other aspect. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. 1. A computer-implemented method comprising: generating a quantum circuit by compiling a quantum program corresponding to the defined quantum computation; generating a plurality of execution variants of the quantum circuit by applying a first symmetry of one or more symmetries to the quantum circuit; causing quantum hardware to execute each of the plurality of execution variants; receiving a plurality of measurement data sets indicative of computational outputs for each of the plurality of execution variants; determining a result of the defined quantum computation by aggregating the plurality of measurement data sets; 4. A computer-implemented method comprising:

2. The computer-implemented method of claim 1 , further comprising causing a computing device to provide the result.

3. The computer-implemented method of claim 1 , further comprising selecting the one or more symmetries from a set of computationally intrinsic symmetries corresponding to the defined quantum computation.

4. 4. The computer-implemented method of claim 3, wherein the selecting step comprises selecting a first symmetry and a second symmetry from the set of computationally intrinsic symmetries, the first symmetry and the second symmetry reducing error correlation between respective resulting execution variants.

5. aggregating the plurality of measurement data sets selecting an aggregation process for combining the plurality of measurement data sets based on an output probability distribution corresponding to the defined calculation; applying the aggregation process to the plurality of measurement data sets; The computer-implemented method of claim 1 , comprising:

6. The computer-implemented method of claim 5 , wherein the aggregation process comprises component-wise averaging.

7. 7. The computer-implemented method of claim 6, wherein the plurality of measurement data sets define a plurality of sequences of bit strings, and wherein applying the component-wise averaging comprises determining, across the plurality of sequences of bit strings, an average number of occurrences for each bit string in the plurality of sequences of bit strings.

8. The computer-implemented method of claim 5 , wherein the aggregation process includes a majority vote.

9. 9. The computer-implemented method of claim 8, wherein the plurality of measurement data sets define a plurality of sequences of bit strings, and wherein applying the majority voting comprises determining particular bit strings that exhibit a number of occurrences that exceeds a defined threshold number across the plurality of sequences of bit strings.

10. 2. The computer-implemented method of claim 1 , wherein the set of computationally intrinsic symmetries includes at least one of qubit assignments, gate decompositions, permutations of commutative gates, adding gates that preserve defined states, or modifying one or more gates, and measurements compensated by one or more modifications in post-processing.

11. 1. A computing system comprising: At least one processor; at least one memory device storing processor-executable instructions, the memory device being configured to, in response to the processor-executable instructions being executed by the at least one processor, provide to the computing system at least: generating a quantum circuit by compiling a quantum program corresponding to the defined quantum computation; generating a plurality of execution variants of the quantum circuit by applying a first symmetry of one or more symmetries to the quantum circuit; causing quantum hardware to execute each of the plurality of execution variants; receiving a plurality of measurement data sets indicative of calculated outputs for each of the plurality of circuit variants; determining a result of the defined quantum computation by aggregating the plurality of measurement data sets; at least one memory device that causes A computing system comprising:

12. 12. The computing system of claim 11, wherein the at least one memory device stores further processor-executable instructions that, in response to being executed, further cause the at least one processor to provide the result to a computing device.

13. 12. The computing system of claim 11, wherein the at least one memory device stores further processor-executable instructions that, in response to being executed, further cause the at least one processor to select the one or more symmetries from a set of computation-specific symmetries corresponding to the defined quantum computation.

14. aggregating the plurality of measurement data sets selecting an aggregation process for combining the plurality of measurement data sets based on an output probability distribution corresponding to the defined calculation; applying the aggregation process to the plurality of measurement data sets; The computing system of claim 11 , comprising:

15. The computing system of claim 14 , wherein the aggregation process includes either component-wise averaging or majority voting.

16. 1. A quantum information processing (QIP) system, comprising: At least one processor; at least one memory device storing processor-executable instructions, the processor-executable instructions being responsive to being executed by the at least one processor to provide the QIP system with: generating a quantum circuit by compiling a quantum program corresponding to the defined quantum computation; generating a plurality of execution variants of the quantum circuit by applying a first symmetry of one or more symmetries to the quantum circuit; causing quantum hardware to execute each of the plurality of execution variants; receiving a plurality of measurement data sets indicative of calculated outputs for each of the plurality of circuit variants; determining a result of the defined quantum computation by aggregating the plurality of measurement data sets; at least one memory device that causes A QIP system comprising:

17. 17. The QIP system of claim 16, wherein the at least one memory device stores further processor-executable instructions that, in response to being executed, further cause the at least one processor to provide the result to a computing device.

18. aggregating the plurality of measurement data sets selecting an aggregation process for combining the plurality of measurement data sets based on an output probability distribution corresponding to the defined calculation, the aggregation process being one of a linear aggregation process or a non-linear aggregation process; applying the aggregation process to the plurality of measurement data sets; 20. The computing system of claim 16, comprising:

19. 20. The QIP system of claim 18, wherein the quantum hardware comprises a plurality of trapped atom qubits individually addressable by a continuous wave laser beam.

20. 20. The QIP system of claim 18, wherein the quantum hardware comprises a plurality of superconducting qubits that are individually addressable by microwave electromagnetic radiation.

Images