Programmable Precision Etching

Abstract

A system and method for thinning a group of two or more dies is provided. An etching gas chemical is introduced into a plasma generator. Further, a plasma is generated by the plasma generator using the etching gas chemical. The two or more dies disposed in the etching chamber are then etched using the plasma to thin the two or more dies until the two or more dies reach a desired thickness. Further, a spatially variable closed-loop control of the etching rate of the etching step is implemented to achieve a spatially variable etching rate during the thinning of the two or more dies.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 314,725, entitled "Programmable Precision Etching," filed February 28, 2022, which is incorporated by reference in its entirety.

[0002] The present invention relates generally to wafer thinning, and more particularly to programmable precision etching for improving the accuracy of wafer thinning. [Background technology]

[0003] Wafer thinning is the process of removing material from the back side of a wafer to a desired final target thickness. The two most common methods of wafer thinning are conventional grinding and chemical mechanical planarization (CMP).

[0004] Conventional grinding is an aggressive mechanical process that utilizes diamond and resin-bonded grinding wheels mounted on a high-speed spindle to perform material removal. The grinding recipe defines the spindle revolutions per minute (rpm), the material removal rate, and the final target thickness of the workpiece. Harder materials, such as sapphire, typically require slower feed rates compared to more forgiving materials, such as silicon.

[0005] The wafer is positioned on a porous ceramic rotating vacuum chuck with the back side of the wafer facing up (towards the grinding wheel). Both the grinding wheel and the wafer chuck rotate during the grinding process. Deionized water is sprayed onto the workpiece to provide cooling and to wash away any material particles created during the grinding process. A grinding tape is applied to the front side of the wafer to protect the device from damage during thinning.

[0006] In conventional grinding, thinning is a two-step process. The first step is the coarse grinding, which performs the majority of the material removal. The second step is the fine grinding.

[0007] Polishing is the final step that produces a distortion-free surface that is flat, scratch-free, and mirror-like in appearance. Mechanical polishing requires separate processes and equipment from conventional grinding. Mechanical polishing is simply a minimal removal process of 2-3 μm of material and is typically only performed on silicon.

[0008] CMP uses an abrasive chemical slurry along with a polishing pad to effect material removal. CMP achieves more planarization compared to mechanical grinding, but is considered a "dirtier" and more expensive process. The wafer is attached to a backside film, such as a wax mount, that can be difficult to remove or leave residue on the front side of the wafer.

[0009] CMP has the advantage of being more forgiving when processing hard or exotic materials, such as tungsten. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] International Publication No. 2021 / 173873 Summary of the Invention [Problem to be solved by the invention]

[0011] Unfortunately, such processes still require improved precision in wafer thinning. [Means for solving the problem]

[0012] In one embodiment of the present disclosure, a method for thinning a group of two or more dies includes introducing an etching gas chemistry into a plasma generator. The method further includes generating a plasma using the etching gas chemistry by the plasma generator. The method further includes etching the two or more dies disposed in the etching chamber using the plasma to thin the two or more dies until the two or more dies reach a desired thickness. Furthermore, the method includes implementing spatially variable closed-loop control of an etch rate of the etching step to achieve a spatially variable etch rate during thinning of the two or more dies.

[0013] In another embodiment of the present disclosure, a system for thinning a group of two or more dies uses the method described above.

[0014] The foregoing has outlined rather generally the features and technical advantages of one or more embodiments of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the present disclosure that may form the subject of the claims of the present disclosure are described below.

[0015] A better understanding of the present disclosure can be obtained from the following detailed description considered in conjunction with the following drawings. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 illustrates an architecture for a precision substrate thinning (PST) apparatus according to an embodiment of the present disclosure. [Diagram 2] 1 is a flow chart of a method for performing substrate thinning using a dry etching process according to an embodiment of the present disclosure. [Diagram 3] 1 is a flowchart of a method for performing substrate planarization using nP3 according to an embodiment of the present disclosure. [Figure 4]1 is a flow chart of a method for performing substrate planarization using spatial etch rate control in accordance with an embodiment of the present disclosure. [Diagram 5] 1 is a flowchart of a method for minimizing total thickness variation (TTV) using nP3 according to an embodiment of the present disclosure. [Figure 6] 1 is a flow chart of a method for minimizing TTV using spatial etch rate control according to an embodiment of the present disclosure. [Figure 7] 2 illustrates an alternative architecture for a PST device compared to the architecture presented in FIG. 1 according to an embodiment of the present disclosure. [Figure 8] 1 illustrates an additional alternative architecture for a PST device in accordance with an embodiment of the present disclosure. [Figure 9] 1 is a flow chart of a method for performing precision substrate thinning using spatial etch rate control in accordance with an embodiment of the present disclosure. [Figure 10] FIG. 1 illustrates the change in etch rate as a function of temperature for silicon in accordance with an embodiment of the present disclosure. [Figure 11] FIG. 1 illustrates a thermal actuation subsystem of an embodiment of the present disclosure. [Figure 12A] 1 illustrates thermal simulation results to quantify the temperature across a die for a given heat input, according to an embodiment of the present disclosure. [Figure 12B] 1 illustrates thermal simulation results to quantify the temperature across a die for a given heat input, according to an embodiment of the present disclosure. [Figure 12C] 1 illustrates thermal simulation results to quantify the temperature across a die for a given heat input, according to an embodiment of the present disclosure. [Figure 12D] 1 illustrates thermal simulation results to quantify the temperature across a die for a given heat input, according to an embodiment of the present disclosure. [Figure 12E]1 illustrates thermal simulation results to quantify the temperature across a die for a given heat input, according to an embodiment of the present disclosure. [Figure 13] FIG. 1 illustrates a methodology for pulse width modulation (PWM) control of an illumination source used in one example of a thermal actuation subsystem according to an embodiment of the present disclosure. [Figure 14A] 1A-1C illustrate simulation and experimental results of an optical lens stack for focusing diverging light from a laser diode, according to an embodiment of the present disclosure. [Figure 14B] 1A-1C illustrate simulation and experimental results of an optical lens stack for focusing diverging light from a laser diode, according to an embodiment of the present disclosure. [Figure 15A] 1 illustrates a substrate-scale metrology method using a single point sensor according to an embodiment of the present disclosure; [Figure 15B] 1 illustrates a substrate-scale metrology method using a single point sensor according to an embodiment of the present disclosure; [Figure 15C] 1 illustrates a substrate-scale metrology method using a single point sensor according to an embodiment of the present disclosure; [Figure 16] 14A-14C illustrate inter-die features to address edge non-uniformity according to an embodiment of the present disclosure. [Figure 17] 1 is a flowchart of a method for generating inter-die features according to an embodiment of the present disclosure. [Figure 18A] 18A-18C are cross-sectional views for creating inter-die features using the steps described in FIG. 17 according to an embodiment of the present disclosure. [Figure 18B] 18A-18C are cross-sectional views for creating inter-die features using the steps described in FIG. 17 according to an embodiment of the present disclosure. [Figure 18C] 18A-18C are cross-sectional views for creating inter-die features using the steps described in FIG. 17 according to an embodiment of the present disclosure. [Figure 18D]18A-18C are cross-sectional views for creating inter-die features using the steps described in FIG. 17 according to an embodiment of the present disclosure. [Figure 18E] 18A-18C are cross-sectional views for creating inter-die features using the steps described in FIG. 17 according to an embodiment of the present disclosure. [Figure 18F] 18A-18C are cross-sectional views for creating inter-die features using the steps described in FIG. 17 according to an embodiment of the present disclosure. [Figure 19A] FIG. 1 illustrates an example process for profile correction using nP3 according to an embodiment of the present disclosure. [Figure 19B] FIG. 1 illustrates an example process for profile correction using nP3 according to an embodiment of the present disclosure. [Figure 20A] 1A-1C illustrate a process for profile correction using an intermediate film according to an embodiment of the present disclosure. [Figure 20B] 1A-1C illustrate a process for profile correction using an intermediate film according to an embodiment of the present disclosure. [Figure 20C] 1A-1C illustrate a process for profile correction using an intermediate film according to an embodiment of the present disclosure. [Figure 21] 1 is a flowchart of a method for PST using nP3 according to an embodiment of the present disclosure. [Figure 22] 1 illustrates a substrate having dies of different thicknesses according to an embodiment of the present disclosure. [Diagram 23] FIG. 1 illustrates an exemplary method for three-dimensional (3D) integration, one of the use cases for PST, according to an embodiment of the present disclosure. [Figure 24] 11 is a flowchart of an alternative method for generating inter-die features according to an embodiment of the present disclosure. [Figure 25A] 25A-25C are cross-sectional views for creating inter-die features using the steps set forth in FIG. 24 according to an embodiment of the present disclosure. [Figure 25B] 25A-25C are cross-sectional views for creating inter-die features using the steps set forth in FIG. 24 according to an embodiment of the present disclosure. [Figure 25C] 25A-25C are cross-sectional views for creating inter-die features using the steps set forth in FIG. 24 according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] As mentioned in the Background section, wafer thinning is the process of removing material from the back side of a wafer to a desired final target thickness. The two most common methods of wafer thinning are conventional side grinding and chemical mechanical planarization (CMP).

[0018] Conventional grinding is an aggressive mechanical process that utilizes diamond and resin-bonded grinding wheels mounted on a high-speed spindle to perform material removal. The grinding recipe defines the spindle revolutions per minute (rpm), the material removal rate, and the final target thickness of the workpiece. Harder materials, such as sapphire, typically require slower feed rates compared to more forgiving materials, such as silicon.

[0019] The wafer is positioned on a porous ceramic rotating vacuum chuck with the back side of the wafer facing up (towards the grinding wheel). Both the grinding wheel and the wafer chuck rotate during the grinding process. Deionized water is sprayed onto the workpiece to provide cooling and to wash away material particles generated during the grinding process. A grinding tape is applied to the front side of the wafer to protect the device from damage during the thinning process.

[0020] In conventional grinding, thinning is a two-step process. The first step is the coarse grinding, which performs the majority of the material removal. The second step is the fine grinding.

[0021] Polishing is the final step that produces a distortion-free surface that is flat, scratch-free, and mirror-like in appearance. Mechanical polishing requires separate processes and equipment from conventional grinding. Mechanical polishing is simply a minimal removal process of 2-3 μm of material and is typically only performed on silicon.

[0022] CMP uses an abrasive chemical slurry along with a polishing pad to effect material removal. CMP achieves more planarization compared to mechanical grinding, but is considered a "dirtier" and more expensive process. The wafer is attached to a backside film, such as a wax mount, that can be difficult to remove or leave residue on the front side of the wafer.

[0023] CMP has the advantage of being more forgiving when processing hard or exotic materials, such as tungsten.

[0024] Unfortunately, such processes still require improved precision in wafer thinning.

[0025] Embodiments of the present disclosure provide a means for improving the precision of substrate thinning. Embodiments of a precision substrate thinning process and an apparatus thereof are discussed below.

[0026] In one embodiment, the apparatus can be used for one or more of the following processes: (i) thinning (or average thickness reduction); (ii) surface planarization; (iii) total thickness variation (TTV) minimization. TTV as used herein refers to the difference between the maximum and minimum thickness values ​​that occur during a measurement period of one or more adjacent or non-adjacent substrates. Precision substrate thinning (PST) is a combination of the above processes. In one embodiment, PST is used to thin a substrate to less than one of the following: 50 μm, 10 μm, 5 μm, and 1 μm. In one embodiment, PST is used to minimize TTV to less than one of the following: 200 nm, 100 nm, 50 nm, 25 nm, and 10 nm.

[0027] In one embodiment, the apparatus consists of a process chamber into which an etching gas is introduced and turned into a plasma to etch the substrate. A metrology system is described below that measures thickness and thickness variation across the substrate. A process for correcting TTV and flatness errors is also described below. In one embodiment, such correction is achieved using a subsystem that generates a desired spatially variable etch rate. The spatially variable etch rate along with the metrology subsystem allows for the implementation of a closed-loop control scheme to precisely reach the thin thickness and low thickness variation required for precision substrate thinning (PST). In one embodiment, the spatially variable etch rate is determined using an algorithm executed in one or more of the following locations: a local computer, a remote computer, and a cloud-based computer.

[0028] In another embodiment of the correction process, the TTV across the substrate is corrected using a nanoscale precision programmable profiling (nP3) process. A discussion of the nP3 process is provided in International Patent Application No. PCT / US2021 / 019732, which is incorporated herein by reference in its entirety. In one embodiment, the TTV across the substrate is measured and recorded using a metrology subsystem. nP3 is then used to coat the substrate with a nanometer-precision film of polymer on the uneven substrate. The planarized profile is then etched back to the original substrate. A discussion of such an apparatus is provided below with respect to FIG. 1.

[0029] Reference is now made to FIG. 1, which illustrates an architecture for a PST device according to an embodiment of the present disclosure.

[0030] 1, a substrate 101 to be etched is placed inside a vacuum chamber 102 (also called an etching chamber) on a substrate clamp 103. In one embodiment, the vacuum pressure is controlled by implementing a closed loop control scheme between a pressure sensor 104 and a vacuum pump 105. The output of the vacuum pump 105 is an exhaust 106.

[0031] In one embodiment, the plasma is generated through a remote plasma source, although other sources may be used as discussed further below. In one embodiment, mass flow controllers (MFCs) 107A-107C (identified as "MFC-1," "MFC-2," and "MFC-3," respectively) are used to control the amount of etchant gases 108A-108C (identified as "ETCH GAS-1," "ETCH GAS-2," and "ETCH GAS-3," respectively) injected into plasma generator 109, which creates the plasma. MFCs 107A-107C may each be referred to collectively or individually as MFC 107. Etchant gases 108A-108C may each be referred to collectively or individually as etchant gases 108. While FIG. 1 illustrates three MFCs 107 and three etchant gases 108, any number of MFCs 107 and etchant gases 108 may be utilized.

[0032] In one embodiment, a subassembly 110 for uniform substrate heating may be present below the substrate clamp 103. In one embodiment, the substrate clamp 103 is connected to an RF power source 111 to generate a DC bias on the substrate 101 to effect physical etching if desired.

[0033] In one embodiment, there may be an optical metrology system above the etch chamber 102. In this case, a single point metrology sensor 112 (such as a coupled color imaging (LCI) sensor) is used to measure the substrate thickness. In one embodiment, a thermal actuation subsystem 113, as described further below, is present on top as shown in FIG. 1. The optical metrology subsystem, consisting of the metrology sensor 112 and the thermal actuation subsystem 113, illuminates the substrate 101 through a viewport 114. In one embodiment, the viewport 114 is made of a material that is transparent to light from both subsystems.

[0034] In alternative embodiments, these subsystems are inside the etch chamber 102 itself. In one embodiment, the instrument has a temperature camera 115 to monitor the temperature across the substrate 101. In one embodiment, a closed loop control scheme is implemented in which the metrology sensor 112 and the temperature camera 115 (e.g., an IR camera) are used as feedback to control the thermal actuation subsystem 113, resulting in a spatially variable etch rate to reduce spatially variable temperature and therefore thickness variations.

[0035] In one embodiment, the PST apparatus consists of the following subsystems: etch chamber 102, plasma generator 109, DC biased cathode, thermal actuation subsystem 113, an array of nozzles to implement a spatially varying etch rate, metrology sensor 112, a substrate scale metrology system using a large aperture, and a substrate scale metrology system using a single spot measurement sensor.

[0036] In one embodiment, the etching chamber 102 is the process chamber in which etching takes place. In one embodiment, an etching gas 108 is introduced into the etching chamber 102 where the flow rate of the etching gas 108 is controlled through a mass flow controller 107. In one embodiment, the etching gas 108 includes, but is not limited to, CF4, CHF3, SF6, NF3, Ar, O2, Cl2, N2, and H2.

[0037] In one embodiment, the etch chamber 102 is connected to a vacuum pump 105 through a needle valve to control the vacuum pressure. In one embodiment, the etch chamber 102 has a viewport 114 that is transparent to light from the metrology subsystem and thermal actuation subsystems, such as thermal actuation subsystem 113.

[0038] In one embodiment, the plasma generator 109 is configured to generate plasma using various techniques, such as conductively coupled plasma (CCP), inductively coupled plasma (ICP), electron cyclotron resonance (ECR), and remote plasma source (RPS).

[0039] In one embodiment, the PST apparatus includes a DC biased cathode along with the plasma generation source described above to produce a physical etch on the substrate 101. In one embodiment, the ratio of power between the DC biased cathode and the plasma generator 109 is adjusted to control the amount of physical etch versus chemical etch.

[0040] In one embodiment, the PST apparatus includes a thermal actuation subsystem 113. In one embodiment, such subsystem 113 includes various subsystems for creating a desired temperature profile on the substrate 101, such as a subsystem for uniform thermal actuation, a subsystem for spatially variable thermal actuation, and a subsystem for spatially variable thermal actuation using a digital micromirror device (DMD).

[0041] In one embodiment, the PST device includes a subsystem 113 for uniform thermal actuation. In one embodiment, such a subsystem has a thermal actuator for uniform heating of the substrate 101 to increase the etch rate. In one embodiment, such a subsystem includes a resistive heating element (see element 103) mounted inside the etching chamber 102 below the substrate 101, preferably below the plate on which the substrate 101 rests. In another embodiment, radiative heating lamps, such as quartz halogen lamps, are present inside the etching chamber 102.

[0042] As also discussed above, in one embodiment, the thermal actuation subsystem 113 includes a subsystem for spatially variable thermal actuation. In one embodiment, such a subsystem includes high power laser diodes (LDs) or light emitting diodes (LEDs) as sources of illumination assembled in a two-dimensional matrix on a printed circuit board (PCB). In one embodiment, such a subsystem includes a suitable heat sink to remove heat from the PCB and the LDs / LEDs. In one embodiment, such a subsystem includes a stack of optical components including, but not limited to, aspheric lenses, cylindrical lenses, reflectors, and apertures to focus divergent light from each of the illumination sources onto the substrate 101.

[0043] Additionally, as discussed above, in one embodiment, the thermal actuation subsystem 113 includes spatially variable thermal actuation using a DMD (referred to herein as a "DMD" subsystem). In one embodiment, the DMD subsystem includes a high power laser diode used as a source of radiation. Additionally, in one embodiment, the DMD subsystem directs a high power laser onto the substrate 101 to generate a spatial temperature profile. In one embodiment, the DMD subsystem includes an aspheric lens, a cylindrical lens, and a heat sink to mount and collimate the laser diode. In one embodiment, the DMD subsystem includes one or more of the above subsystems mounted on a fixed platform or a movable XY stage that can be used to illuminate the entire substrate 101.

[0044] In one embodiment, the PST device includes a nozzle array for spatially varying the etch rate. In one embodiment, such a subsystem consists of an array of nozzles for injecting an etching gas 108 inside the process chamber 102. The mass flow rate through each of the nozzles can be varied to obtain a spatially variable etch rate.

[0045] In one embodiment, the PST apparatus includes a metrology sensor 112. In one embodiment, the metrology sensor 112 in the apparatus provides information about the thickness and thickness variations across the substrate 101. In one embodiment, the substrate thickness information is provided using sensing techniques such as laser interferometry, low coherence interferometry, ellipsometry, phase shifting interferometry, moire interferometry, and spectral interface wafer thickness metrology.

[0046] In one embodiment, the PST device includes a substrate-scale metrology using a large aperture. In one embodiment, such a substrate-scale metrology is configured to measure across the entire substrate 101 using a large aperture, such that the entire substrate 101 is illuminated and measured. In one embodiment, the technique utilized to perform such illumination and measurement includes linked color imaging (LCI) with hyperspectral imaging, which utilizes (1) a low-coherence illumination source, such as a superluminescent diode (SLD), that illuminates the entire substrate 101, (2) a reference surface from which light can reflect for interferometry, (3) a hyperspectral camera, which is equivalent to having a two-dimensional array of single-point spectrometers, where each pixel or each single-point spectrometer corresponds to a specific location on the wafer, and (4) software algorithms that analyze the resulting spectrogram to assess thickness and / or thickness variation.

[0047] In one embodiment, a metrology sensor 112 in the apparatus provides information about the top profile of the substrate. In one embodiment, the top profile is measured using sensing techniques such as laser interferometry, optical emission interferometry, and Fizeau interferometry.

[0048] In one embodiment, the PST apparatus includes a substrate-scale metrology system that uses a single spot measurement sensor. In one embodiment, where the sensing area is smaller than the substrate 101, sampling of the entire substrate 101 is performed using a sensor mounted on an XY stage. In one embodiment, such a sensor is mounted on an XY stage to scan the entire substrate 101. In one embodiment, instead of a single sensor, an array of sensors is used at different orientations for high throughput. In one embodiment, sampling of the entire substrate 101 is performed using a variable pitch mechanism (VPM). In one embodiment, one or more sensors discussed above with respect to metrology sensor 112 are mounted on a VPM to scan the entire substrate 101.

[0049] An overview of how the process is carried out is given below.

[0050] In one embodiment, substrate thinning is performed using a dry etching process, described below with respect to Figure 2. Figure 2 is a flow chart of a method 200 for performing substrate thinning using a dry etching process, according to an embodiment of the present disclosure.

[0051] Referring to FIG. 2 in conjunction with FIG. 1, in step 201 , a substrate 101 is placed inside an etching chamber 102 .

[0052] In step 202 , a suitable etching gas chemistry is introduced inside the etching chamber 102 .

[0053] In step 203, a plasma is generated for use in etching using one of the following techniques discussed above, such as CCP, ICP, ECR, or RPS.

[0054] In step 204, the etch rate is increased by heating the substrate 101 using the techniques discussed above, such as uniform thermal actuation, spatially variable thermal actuation, and spatially variable thermal actuation using a DMD subsystem.

[0055] In one embodiment, because materials with high bond strength are difficult to etch, including but not limited to silicon dioxide, diamond, and gallium nitride, the etch rate can also be increased by introducing a physical sputtering component using a DC biased cathode as discussed above.

[0056] In step 205, etching is stopped once the substrate reaches a desired thickness. In one embodiment, a metrology system using metrology sensor 112 discussed above and / or a substrate scale metrology system using a large aperture and / or a substrate scale metrology system using a single spot measurement sensor provides information about the substrate thickness, including the average thickness. In one embodiment, the process discussed above is stopped once the substrate 101 reaches a desired thickness. In one embodiment, the thickness information is obtained in real time (e.g., >10 Hz). In another embodiment, the measurements obtained are performed intermittently. For example, the etching process is stopped, followed by a measurement, and the etching process is restarted. Such cycles continue until the desired thickness is reached.

[0057] A method for substrate planarization using nP3 is discussed below with respect to FIG.

[0058] FIG. 3 is a flow chart of a method 300 for performing substrate planarization using nP3 according to an embodiment of the present disclosure.

[0059] Referring to FIG. 3 in conjunction with FIG. 1, in step 301 flatness information across the substrate 101 is obtained using the metrology sensor 112 discussed above, and / or a substrate scale metrology system using a large aperture, and / or a substrate scale metrology system using a single spot measurement sensor.

[0060] In step 302, a nanometer-precise film thickness of polymer is inkjetted onto the uneven substrate 101, resulting in a nearly flat top surface using the nP3 process.

[0061] In step 303, the hardened resist is etched back into the substrate 101 using a dry etching process, such as method 200. In one embodiment, one or a series of intermediate films are between the polymer and the substrate 101. For example, the intermediate film may correspond to silicon dioxide on a diamond substrate. In such an embodiment, the polymer profile is first transferred into the silicon dioxide using fluorine chemistry at a temperature low enough to ensure the stability of the polymer, for example 150° C. The profile can now be etched into the diamond using oxygen dominated chemistry at a fast etch rate, either by heating the substrate 101 or by DC bias, or both.

[0062] In one embodiment, the etchback is performed using open loop control or spatial etch rate control, as discussed above with respect to the thermal actuation subsystem 113 and the nozzle array for spatially varying the etch rate.

[0063] In one embodiment, steps 301-303 may be repeated multiple times until flatness within a desired range is achieved.

[0064] A substrate planarization process using spatial etch rate control is now discussed below with respect to FIG.

[0065] FIG. 4 is a flow chart of a method 400 for performing substrate planarization using spatial etch rate control in accordance with an embodiment of the present disclosure.

[0066] Referring to FIG. 4 in conjunction with FIG. 1, in step 401, optical metrology is performed continuously, or intermittently, or once at the beginning and once at the end, to measure the variation in the top surface profile across the substrate 101.

[0067] In step 402, a control scheme is implemented in which metrology information is used as feedback to control spatial etch rate actuators.

[0068] In step 403, the substrate is etched with a spatially variable etch rate using the techniques discussed above, such as uniform thermal actuation, spatially variable thermal actuation, or spatially variable thermal actuation using a DMD system.

[0069] A process for minimizing TTV using nP3 is now discussed below with respect to FIG.

[0070] FIG. 5 is a flow chart of a method 500 for minimizing TTV using nP3 according to an embodiment of the present disclosure.

[0071] Referring to FIG. 5 in conjunction with FIG. 1, in step 501, substrate thickness and thickness variation across the substrate 101 are measured using the techniques discussed above with respect to the metrology sensor 112, the substrate scale metrology system using a large aperture, and the substrate scale metrology system using a single spot measurement sensor.

[0072] In step 502 , the difference between the current profile and the desired profile is calculated and provided as input to the nP3 process, which then inkjet a nanometer-precise film thickness of polymer onto the substrate 101 .

[0073] In step 503, the hardened resist is etched back into the substrate 101 using a dry etching process, such as method 200. In one embodiment, one or a series of intermediate films are between the polymer and the substrate 101. For example, the intermediate film may correspond to silicon dioxide on a diamond substrate. In such an embodiment, the polymer profile is first transferred into the silicon dioxide using fluorine chemistry at a temperature low enough to ensure the stability of the polymer, for example 150° C. The profile can now be etched into the diamond using oxygen dominated chemistry at a fast etch rate, either by heating the substrate or by DC bias, or both.

[0074] In one embodiment, the etchback is performed using open loop control or spatial etch rate control, as discussed above with respect to the thermal actuation subsystem 113 and the nozzle array for spatially varying the etch rate.

[0075] Steps 501-503 can be repeated multiple times until flatness within a desired range is obtained.

[0076] A discussion of minimizing TTV using spatial etch rate control is provided below with respect to FIG.

[0077] FIG. 6 is a flow chart of a method 600 for minimizing TTV using spatial etch rate control according to an embodiment of the present disclosure.

[0078] Referring to FIG. 6 in conjunction with FIG. 1, in step 601, optical metrology is performed continuously, or intermittently, or once at the beginning and once at the end, to measure thickness and thickness variation across the substrate 101.

[0079] In step 602, a control scheme is implemented in which the metrology information is used as feedback to control the spatial etch rate actuators by calculating the spatial etch rate across the substrate 101 using the metrology information.

[0080] In step 603, the die is etched using a spatially variable etch rate using the techniques discussed above, such as uniform thermal actuation, spatially variable thermal actuation, or spatially variable thermal actuation using a DMD system.

[0081] Reference is now made to FIG. 7, which illustrates an alternative architecture for a PST device compared to the architecture presented in FIG. 1, in accordance with an embodiment of the present disclosure.

[0082] As shown in FIG. 7, a mirror 701 is used to direct light from the thermal actuation subsystem 113 onto the substrate 101. In one embodiment, the mirror 701 is located on a movable stage. In one embodiment, a dichroic mirror or beam splitter is used to enable the same optical path for metrology and thermal actuation. In another embodiment, the position and orientation of the metrology assembly including the metrology sensor 112 and / or the substrate scale metrology system using a large aperture and / or the substrate scale metrology system using a single point measurement sensor and the thermal actuation subsystem 113 as discussed above are swapped. In one embodiment, the metrology sensor 112 is mounted on the metrology assembly to scan the substrate 101.

[0083] 7, a mirror 701 is used to direct light from the thermal actuation subsystem 113 onto the substrate 101. In one embodiment, the mirror 701 is located on a movable stage. In one embodiment, a dichroic mirror or beam splitter is used to enable the same optical path for metrology and thermal actuation. In another embodiment, the position and orientation of the metrology assembly including the metrology sensor 112 and the thermal actuation subsystem 113 are swapped. In one embodiment, the metrology sensor 112 is mounted on the metrology assembly to scan the substrate 101.

[0084] Reference is now made to FIG. 8, which illustrates a further alternative architecture for a PST device according to an embodiment of the present disclosure.

[0085] As shown in Figure 8, the thermal actuation subsystem 113 is located below the process chamber 102. Additionally, as shown in Figure 8, a substrate clamp 103 is used that is transparent to light from the thermal actuation subsystem 113. In another embodiment, either or both of the metrology subsystem using the metrology sensor 112 and the thermal actuation subsystem 113 are located inside the vacuum chamber 102.

[0086] In one embodiment, there may be an intermediate film between the die and the base (see 1602 in FIG. 16) so that this film absorbs light from the thermal actuation subsystem 113. In one embodiment, this intermediate layer is carbon tape.

[0087] FIG. 9 is a flow chart of a method 900 for performing precision substrate thinning using spatial etch rate control in accordance with an embodiment of the present disclosure.

[0088] 9 in conjunction with FIGS. 1, 7 and 8, in step 901, a substrate 101 is placed into an etch chamber 102. In one embodiment, the substrate 101 is diced. In another embodiment, the substrate 101 is not diced. In one embodiment, the process time is reduced by reducing the thickness of the input substrate 101 using a process such as wafer grinding and polishing.

[0089] Once the substrate 101 is positioned inside the etching chamber 102, in step 902, the chamber 102 is pumped down to create a vacuum.

[0090] In step 903, a plasma of the etching gas 108 is generated. For example, in one embodiment, a gas 108 suitable for etching a particular substrate material is injected inside the chamber 102. In one embodiment, an MFC 107 is used to control the mass flow rate of the input gas 108. In one embodiment, a plasma is ignited and then the substrate 101 is etched.

[0091] At step 904, the thickness and / or thickness variation across the substrate 101 is measured. In one embodiment, a metrology system including metrology sensor 112 is used to measure the thickness and / or thickness variation of the substrate 101. In one embodiment, the measurements are taken continuously or intermittently. In one embodiment, a measurement is taken once at the beginning and once at the end.

[0092] It should be noted that the etch rate may vary with temperature, as shown in Figure 10. Figure 10 illustrates the change in etch rate as a function of temperature for silicon, according to an embodiment of the present disclosure.

[0093] 9 in conjunction with Figures 1, 7, 8, and 10, in step 905 a determination is made as to whether the substrate 101 has reached a desired specification. In one embodiment, the desired specification refers to one or more of the following: a desired thickness of the substrate, a desired TTV, and a desired top surface flatness.

[0094] If the desired specifications have not been reached, then in step 906 the required spatial heat load for the substrate 101 is calculated.

[0095] In one embodiment, a spatially varying etch rate can be produced by generating a spatially varying temperature profile on the substrate 101. In one embodiment, thickness variations obtained from a metrology subsystem are used to calculate the spatial temperature profile (heat load on the substrate 101). In one embodiment, the desired temperature profile is generated by varying the heat input from an illumination source to different portions of the substrate 101. Techniques such as pulse width modulation (PWM) can be used for such purposes.

[0096] In step 907, the thermal actuation subsystem 113 is used to apply the calculated spatial heat load to etch the substrate 101 at a spatially variable etch rate.

[0097] In one embodiment, a spatially variable etch rate is generated by varying the concentration of etching gas 108 or the power of the plasma across the surface of the substrate 101. In one embodiment, the substrate 101 is cooled by injecting gas 108, such as N2 or Ar, into the process chamber 102 and the plasma generator 109 is turned off. In one embodiment, the substrate 101 is cooled using backside He cooling. The process of measurement and thermal actuation is repeated until the thickness and TTV of the substrate 101 are within specifications.

[0098] After applying the calculated spatial heat load using the thermal actuation subsystem 113 , the thickness and / or thickness variation across the substrate 101 is measured in step 904 .

[0099] Returning to step 905, however, if the desired specifications have been reached, then in step 908, the precision substrate thinning process is complete.

[0100] FIG. 11 illustrates an embodiment of a thermal actuation subsystem 113 of the present disclosure.

[0101] As shown in Figure 11, the thermal actuation subsystem 113 includes multiple high power illumination sources, including but not limited to laser diodes 1101 (LDs) or LEDs assembled in a two-dimensional matrix configuration. In one embodiment, the LDs 1101 are mounted on a printed circuit board (PCB) 1102. In one embodiment, a heat sink is used to remove heat from these LDs 1101. As shown in Figure 11, a water-cooled metal plate 1103 is used as the heat sink.

[0102] In one embodiment, the PCB 1102 has thermal vias to provide a thermal path from the laser diode 1101 to the heat sink 1103. In one embodiment, the PCB 1102 is made of standard PCB materials such as, but not limited to, epoxy resin. In one embodiment, an insulated metal substrate (IMS) PCB 1102 is used to improve thermal conduction between the heat sink 1103 and the LD 1101.

[0103] In one embodiment, a stack of optical components including, but not limited to, lenses 1104A-1104C (identified as "Lens 1", "Lens 2", "Lens 3", and "Lens 4", respectively), apertures, and reflectors are used to capture light from the illumination source and focus them onto the substrate 101. One such case is depicted in FIG. 11, where a stack of four lenses 1104A-1104D is used for each laser diode 1101. The lenses 1104A-1104D may each be referred to collectively or individually as lenses 1104. In one embodiment, the positions of these optical components are varied to reach the desired focal length. In one embodiment, the entire assembly is mounted on an XY stage 1105 to prevent any blind spots due to the pitch of the LDs 1101.

[0104] 11 illustrates four lenses 1104, it should be noted that the thermal actuation subsystem 113 may include any number of lenses 1104. Additionally, it should be noted that the thermal actuation subsystem 113 may include any number of laser diodes 1101.

[0105] 12A-12E in conjunction with FIG. 11, which illustrate thermal simulation results for quantifying the temperature across a die for a given heat input, in accordance with an embodiment of the present disclosure.

[0106] In particular, FIG. 12A illustrates the results of a transient thermal simulation used to calculate temperature versus time, where PTS is performed on a diced Si wafer, so that each die has dimensions of 10 mm×10 mm with a thickness of 0.75 mm. In one embodiment, the heat load from the laser diode 1101 is simulated by applying 0.45 W of directional radiation from a 2 mm diameter source. The input radiation on the die is shown in FIG. 12B. As shown in FIG. 12A, the temperature at the center of the die reaches about 200° C. in 100 seconds. FIG. 12C illustrates the two-dimensional temperature profile on the die at steady state. FIG. 12E illustrates the steady state temperature across the cross-sectional line of FIG. 12C. FIG. 12D illustrates the temperature difference between the center of the die and the periphery of the die versus time. As shown in FIG. 12D, it can be concluded that the temperature variation within the die is always less than 2.5° C.

[0107] 1 and 7-8, FIG. 13 is a methodology for PWM control of an illumination source used in one example of a thermal actuation subsystem 113 according to an embodiment of the present disclosure. PWM is used in the illumination source to modulate the thermal load to generate a desired temperature profile on the substrate 101. A power supply 1301 is connected to a buck controller 1302, which outputs constant current to the LDs 1101A-1101N and the LEDs, where N is a positive integer. The laser diodes 1101A-1101N may each be collectively or individually referred to as laser diodes 1101. In one embodiment, the LDs 1101 are connected to a matrix manager 1303, which can be individually programmed by a microcontroller 1305 to bypass the LDs 1101 across a switch ("SW A , …, S.W.N ", where N is a positive integer. Each of the switches 1304A-1304N may be collectively or individually referred to as a switch 1304. In one embodiment, the LD 1101 can be fully on, fully off, or dimmed using PWM.

[0108] Reference is now made to FIGS. 14A and 14B, which illustrate simulation and experimental results of an optical lens stack for focusing diverging light from a laser diode, in accordance with an embodiment of the present disclosure.

[0109] Illumination sources such as LD 1101 and LEDs typically emit divergent light. In one embodiment, optical components are used to capture this divergent light and focus it as a small spot on the substrate 101. In one embodiment, optical components including, but not limited to, aspheric lenses, concave lenses, convex lenses, plano-concave lenses, plano-convex lenses, freeform lenses, parabolic reflectors, elliptical reflectors, optical fibers, and combinations thereof are used for this purpose. In one embodiment, the optical components have suitable coatings to improve light transmission. FIG. 14B illustrates simulation results for a case such as the optical assembly 1401 presented in FIG. 14A, where light from a laser diode is focused on a substrate such as the substrate 101 of FIG. 1, which is 400 mm away. The spacing between the lenses 1104 can be changed to adjust the focal length. In one embodiment, the optical assembly 1401 as shown in FIG. 14A consists of an illumination source such as a 1.6 W, 447 nm laser diode with a diverging beam angle of 56°, a first lens (lens 1) 1104A (an aspheric lens), a second lens (lens 2) 1104B (a plano-convex lens with a radius of curvature of 20.67 mm), a third lens (lens 3) 1104C (a plano-convex lens with a radius of curvature of 21.19 mm), and a fourth lens (lens 4) 1104D (a plano-convex lens with a radius of curvature of 25.48 mm).

[0110] In one embodiment, the lens 1104 of the optical assembly 1401 has a MgF2 anti-reflective coating. Figure 14B depicts the resulting illumination profile on a 4 mm x 4 mm die. As shown in Figure 14B, Figure 14B suggests that the die receives 1.39 W of power, thereby indicating an efficiency of about 87%.

[0111] 15A-15C, which illustrate a substrate-scale metrology method using a single-point sensor according to an embodiment of the present disclosure.

[0112] When the sensing area is smaller than the substrate 101, various techniques can be used to scan the entire substrate 101, as illustrated in FIGS. 15A-15C. As illustrated in FIG. 15A, a single sensor 1501 is mounted on an XY stage. As illustrated in FIG. 15B, an array of sensors 1502 is mounted on an XY stage to reduce measurement time. In another embodiment, the array of sensors 1502 is mounted on a linear or rotary stage. FIG. 15C illustrates a configuration in which the array of sensors 1502 is placed at an angle to the direction of motion, thereby helping to reach a lower effective pitch. In such an embodiment, the measurement can potentially be reduced to one scan in one direction. Other configurations can also be used, including but not limited to VPMs, rotary stages, and the like.

[0113] Reference is now made to FIG. 16, which illustrates an inter die feature to address edge non-uniformity according to an embodiment of the present disclosure.

[0114] Substrates that are diced can have thickness variations and non-uniformities around the edges of the die due to lateral etching. In one embodiment, the principles of the present disclosure address these edge non-uniformities by having features between the dies as shown in FIG. 16. As shown in FIG. 16, the substrate is made of individual dies 1601, which may be from a variety of electronic or optical materials. The base 1602 on which these individual dies 1601 are placed may be a polymer base, tape frame, glass carrier, sapphire carrier, transparent carrier, silicon carrier, silicon carbide carrier, etc. By adjusting the geometry of the inter-die features 1603, it is possible to affect the amount of etching species in the kerf and tune the process from fast edge to slow edge. In one embodiment, the inter-die features 1603 are made of materials including, but not limited to, polymer, silicon dioxide, silicon carbide, silicon nitride, alumina, copper, titanium, and titanium oxide.

[0115] Figure 17 is a flowchart of a method 1700 for creating inter-die features 1603 according to an embodiment of the present disclosure. Figures 18A-18F depict cross-sectional views for creating inter-die features 1603 using steps described in Figure 17 according to an embodiment of the present disclosure.

[0116] 17 along with FIGS. 18A-18F, in step 1701, a conformal sacrificial layer 1801 is coated on the substrate die 1601 and exposed portions of the substrate 101 as shown in FIGS. 18A-18B. In one embodiment, the coating process includes, but is not limited to, chemical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, flowable chemical vapor deposition, and atomic layer deposition. In one embodiment, the conformal sacrificial film 1801 is one or more of the following: oxide, silicon oxide, aluminum oxide, silicon carbide, silicon nitride, fluoropolymer, polymer, photoresist, carbon, and adhesive.

[0117] In step 1702, anisotropic etching of the sacrificial film 1801 is performed using a process including, but not limited to, reactive ion etching as shown in Figure 18C. For example, as shown in Figure 18C, an upper portion of the sacrificial film 1801 that overlies the upper surface of the substrate die 1601 and an upper portion of the sacrificial film 1801 that overlies the upper surface of the substrate 101 are etched away.

[0118] In step 1703, a gap fill material is deposited on the exposed portion of the substrate 101 (as well as the top surface of the substrate die 1601), as shown in FIG. 18D. In one embodiment, a photoresist 1802 (e.g., a polymer) is deposited using a process such as spin coating or inkjet. In another embodiment, the gap fill material is comprised of one or more of the following: oxide, silicon oxide, aluminum oxide, silicon carbide, silicon nitride, fluoropolymer, polymer, photoresist, carbon, and adhesive.

[0119] In step 1704, the top layer of gap fill material 1802 (which overlies the top surface of substrate die 1601) is removed, as shown in FIG. 18E.

[0120] In step 1705, the remaining conformal sacrificial layer 1801 is removed by an etching process, thereby forming inter-die features 1803, as shown in FIG. 18F.

[0121] In one embodiment, the desired width of the inter-die features 1803 is obtained by adjusting the thickness of the conformal sacrificial film (SiO 2 ) 1801 in step 1701.

[0122] 19A-B, which illustrate an exemplary process for profile correction using nP3, according to an embodiment of the present disclosure.

[0123] As shown in Figure 19A, an original substrate 1901 is coated with a polymer film 1902. In one embodiment, the material of the original substrate 1901 is silicon. In one embodiment, the top surface profile of the substrate 1901 is measured using a metrology system. The nP3 process uses this information to inkjet a polymer nanometer-precision planarizing film 1902 onto the uneven substrate 1901. This planarized profile is now transferred to the original substrate 1901 through etch-back, as shown in Figure 19B.

[0124] 20A-20C, which illustrate a process for profile correction using an intermediate film, according to an embodiment of the present disclosure.

[0125] As shown in Fig. 20A, a substrate (original substrate) 2001 is coated with an intermediate film 2002 and a polymer film 2003. As further shown in Fig. 20A, an intermediate film 2002 is used between the substrate 2001 and the polymer film 2003. In such an embodiment, a profile is first transferred onto the intermediate film 2002, as shown in Fig. 20B, at a temperature low enough to ensure the stability of the polymer. Fig. 20C illustrates the profile transferred from the intermediate film 2002 onto the substrate 2001. In particular, this profile can be etched into the material of the substrate 2001 using high temperature or DC bias to enhance the etch rate, as seen in Fig. 20C.

[0126]

[0071] Referring now to FIG. 21 in conjunction with FIGS. 1, 7 and 8, FIG. 21 is a flowchart of a method 2100 for PST using nP3 according to an embodiment of the present disclosure.

[0127] In step 2101, the thickness and thickness variation across the substrate 101 is measured.

[0128] Based on such measurements, a spatial thickness profile of the polymer to be used as a coating to minimize the TTV is calculated in step 2102. In one embodiment, the required thickness of the polymer depends on the etch selectivity of the polymer to the substrate 101.

[0129] In step 2103, a polymer film of the calculated thickness (profile) is then coated onto the substrate 101 using the nP3 process, such as by inkjet.

[0130] In step 2104, the profile is then etched back into the original substrate.

[0131] In one embodiment, there may be an intermediate layer, such as that shown in Figures 20A and 20B. In one embodiment, the process discussed above (steps 2101-2104) is repeated until the thickness variation of the substrate 101 is within specifications.

[0132] Reference is now made to FIG. 22, which illustrates a substrate having dies of different thicknesses according to an embodiment of the present disclosure.

[0133] PST can also be used for substrate thinning when the desired thickness may be different for each or group of substrate dies 1601. As shown in FIG. 22, FIG. 22 depicts such a scenario where the desired thicknesses of the substrate dies 1601 are different. In one embodiment, the desired thicknesses of the substrate dies 1601 are varied using method 900, such that a variable heat load is applied on the dies 1601 to reach the different desired die thicknesses. In another embodiment, method 2100 can be used, such that the thickness profile of the coated polymer film accounts for the different thicknesses on each substrate die 1601.

[0134]

[00103] Referring now to FIG. 23, FIG. 23 illustrates an example method 2300 for three-dimensional (3D) integration, one of the use cases for PST, in accordance with an embodiment of the present disclosure.

[0135] 23, method 2300 includes a feed wafer 2301 from which material on a surface of the feed wafer 2301 is mechanically removed using chemical mechanical polishing 2302. The feed wafer may then be ground to a desired thickness using grinding 2303. The feed wafer may then be cut or diced into dies using dicing 2304, followed by a step of picking and placing the die for bonding 2305. After the step of picking and placing the die for bonding 2305, an annealing step 2306 is performed, thereby forming a three-dimensional (3D) integrated circuit (IC) 2307.

[0136] 23, PST (precision substrate thinning) 2308 can occur at different stages of the method 2300. PST can be performed before or after dicing step 2304, after pick and place step 2305, or after annealing step 2306. In one embodiment, the input substrate to PST can have variations based on where in the method 2300 PST occurs. The variations include not only whether the substrate is diced or not diced, but also that the base film is of a different material, among other things.

[0137] In one embodiment, PST using process 900 is performed after the dicing step and after pick-and-place assembly onto the product substrate 101. In such an embodiment, PST is used to improve the TTV of the die to less than one of the following: 1 μm, 500 nm, 200 nm, 100 nm, 50 nm, 25 nm, and 10 nm. Furthermore, in such an embodiment, PST is performed on the die to reach a final average thickness of less than one of the following: 100 μm, 50 μm, 10 μm, 5 μm, and 1 μm.

[0138] In another embodiment, PST using process 900 is performed after die cutting and before pick and place assembly. In such an embodiment, PST is performed on one or more of the following carrier substrates: tape frame, glass, sapphire, and silicon carbide. In such an embodiment, PST is used to improve the TTV of the die to less than one of the following: 1 μm, 500 nm, 200 nm, 100 nm, 50 nm, 25 nm, and 10 nm. Furthermore, in such an embodiment, PST is performed on die with thicknesses of less than one of the following: 100 μm, 50 μm, 10 μm, 5 μm, and 1 μm.

[0139] In another embodiment, PST using process 2100 is performed prior to dicing. In such an embodiment, PST is performed on one or more of the following carrier substrates: tape frame, glass, sapphire, and silicon carbide. In such an embodiment, PST is used to improve the TTV of the substrate to less than one of the following: 1 μm, 500 nm, 200 nm, 100 nm, 50 nm, 25 nm, and 10 nm. In one embodiment, a multi-step approach is utilized, where a first step process is performed at a faster etch rate and one or more subsequent processes are performed at a slower etch rate.

[0140] In one embodiment, one or more substrate thinning steps using process 2100 are performed prior to dicing, and then one or more substrate thinning steps using process 900 are performed after dicing.

[0141] Table 1, shown below, lists various potential options for etching gases and process conditions that can be utilized for a particular substrate material according to an embodiment of the present disclosure.

[0142] [Table 1]

[0143] Figure 24 is a flowchart of an alternative method 2400 for generating inter-die features according to an embodiment of the present disclosure. Figures 25A-25C depict cross-sectional views for generating inter-die features using the steps described in Figure 24 according to an embodiment of the present disclosure.

[0144] Referring to Figure 24 together with Figures 25A-25C, in step 2401, deposition of photoresist 1802 (e.g., a polymer) is performed on the substrate die 1601 and substrate 101 using a process such as spin coating or inkjet, as shown in Figures 25A and 25B.

[0145] In step 2402, alignment and photolithography are performed to create inter-die features 1803, as shown in FIG. 25C.

[0146] As a result of the above, the principles of the present disclosure provide a means for improved accuracy in substrate thinning.

[0147] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification are selected to best explain the principles, practical applications, or technical improvements of the present embodiments beyond the technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method for thinning a group of two or more dies, comprising: introducing an etching gas chemistry into a plasma generator; generating a plasma using the etching gas chemistry with the plasma generator; using the plasma to etch the two or more dies disposed in an etching chamber to thin the two or more dies until the two or more dies reach a desired thickness; and performing spatially varying closed-loop control of an etch rate of the etch to provide a spatially varying etch rate during thinning of the two or more dies.

2. The method of claim 1 , wherein the plasma is generated inside an etch chamber.

3. The method of claim 1 , wherein the plasma is generated by a remote source.

4. The method of claim 1 , wherein the two or more dies are disposed on a base.

5. The method of claim 4 , wherein the base is a tape frame.

6. The method of claim 4 , wherein the base is a carrier wafer.

7. 10. The method of claim 1, further comprising using a metrology module for spatially variable closed-loop control of an etch rate of said etch.

8. 8. The method of claim 7, wherein the metrology module is used to measure die thickness and thickness variation using one or more of low coherence interferometry, ellipsometry, phase shifting interferometry, and moire interferometry.

9. The method of claim 7 , wherein the metrology module is used to measure topography using one or more of laser interferometry, optical emission interferometry, and Fizeau interferometry.

10. The method of claim 7 , wherein the metrology module moves relative to the two or more dies by using one or more of a linear stage, a rotational stage, and a variable pitch mechanism.

11. 10. The method of claim 1, wherein the spatially variable etch rate is provided using a thermal actuation module comprising one or more of a resistive heating element, a radiative heating element, an illumination source, and a digital micromirror array.

12. The method of claim 11 , wherein the thermal actuation module comprises an optical component that focuses light from the illumination source onto the two or more dies.

13. The method of claim 12 , wherein the thermal actuation module moves relative to the two or more dies by using one or more of a linear stage, a rotational stage, and a variable pitch mechanism.

14. The method of claim 1 , wherein the two or more dies are placed on a direct current (DC) biased electrode to enhance the etch rate.

15. The method of claim 1 , further comprising correcting flatness or total thickness variation (TTV) errors of the two or more dies.

16. 16. The method of claim 15, wherein a final total thickness variation (TTV) of the two or more dies is less than one of the following values: 200 nm, 100 nm, 50 nm, 25 nm, and 10 nm.

17. 16. The method of claim 15, wherein a final total thickness variation (TTV) across the two or more dies is less than one of the following values: 200 nm, 100 nm, 50 nm, 25 nm, and 10 nm.

18. The method of claim 1 , wherein the final average thickness of the two or more dies is less than one of the following values: 50 μm, 10 μm, 5 μm, and 1 μm.

19. The method of claim 1 , wherein the two or more dies have inter-die features to address edge unevenness.

20. 20. The method of claim 19, wherein the height and width of the inter-die features are adjusted to adjust the etch rate around the die edges.

21. 10. The method of claim 1, wherein the spatially variable etch rate is determined using an algorithm executed on one or more of a local computer, a remote computer, and a cloud-based computer.

22. 10. The method of claim 1, further comprising performing nP3 to perform total thickness variation (TTV) reduction and planarization on the two or more dies.

23. A system for thinning a group of two or more die using the method of claim 1.

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